SP8854DKGHCAR [ZARLINK]
1.7GHz PARALLEL LOAD PROFESSIONAL SYNTHESISER; 1.7GHz的并行加载专业合成器
| 型号： | SP8854DKGHCAR |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | 1.7GHz PARALLEL LOAD PROFESSIONAL SYNTHESISER |
| 文件： | 总14页 (文件大小：559K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink’s obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
SP8854D
PACKAGE DETAILS
Dimensions are shown thus: mm (in). For further package information please contact your local Customer Service Centre.
17.27/17.78
(0.680/0.700)
12.45/12.95
(0.490/0.510)
16.33/16.81
(0.643/0.662)
0.51 (0.02) NOM
INDEX CORNER
AT 45°
1.02MM/(0.040
45° AT 3 PLACES
)NOM
0.89(0.035)
03.05/3.43
(0.120/0.135)
HC44 MULTILAYER CERAMIC J LEADED CHIP CARRIER
CUSTOMER SERVICE CENTRES
HEADQUARTERS OPERATIONS
FRANCE & BENELUX Les Ulis Cedex Tel: (1) 64 46 23 45
Fax: (1) 69 18 90 00
GEC PLESSEY SEMICONDUCTORS
Cheney Manor, Swindon,
GERMANY Munich Tel: (089) 3609 06 0 Fax: (089) 3609 06 55
ITALY Milan Tel: (02) 66040867 Fax: (02) 66040993
JAPAN Tokyo Tel: (03) 5276–5501 Fax: (03) 5276–5510
NORTH AMERICA Scotts Valley, USA
Wiltshire United Kingdom SN2 2QW.
Tel: (01793) 518000
Fax: (01793) 518411
Tel: (408) 438 2900 Fax: (408) 438 7023
SOUTH EAST ASIA Singapore Tel: (65) 3827708 Fax: (65) 3828872
SWEDEN Stockholm Tel: 46 8 7029770 Fax: 46 8 6404736
TAIWAN, ROC Taipei Tel: 886 2 5461260 Fax: 886 2 7190260
UK, EIRE, DENMARK, FINLAND & NORWAY
Swindon Tel: (01793) 518527/518566 Fax: (01793) 518582
These are supported by Agents and Distributors in major countries world–wide.
GEC PLESSEY SEMICONDUCTORS
P.O. Box 660017 1500 Green Hills Road,
Scotts Valley, California 95067–0017,
United States of America. Tel: (408) 438 2900
Fax: (408) 438 5576
GEC Plessey Semiconductors 1995 Publication No. D.S. 3701 Issue No. 2.6 October 1995
TECHNICAL DOCUMENTATION – NOT FOR RESALE. PRINTED IN UNITED KINGDOM
This publication is issued to provide information only, which (unless agreed by the Company in writing) may not be used, applied or reproduced for any purpose nor form part of any
order or contract nor to be regarded as a representation relating to the products or services concerned. No warranty or guarantee express or implied is made regarding the capability,
performance or suitability of any product or service. The Company reserves the right to alter without prior notice the specification, design, or price of any product or service. Information
concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It
is the user’s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and
has not been superseded. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and
materials are sold and services provided subject to the Company’s conditions of sale, which are available on request.
SP8854D
C
C
2
1
From equation 3:
tan 45°
1
cos 45°
2
FROM
CHARGE
PUMP
0 . 4142
628319
3
100kHz
R
2
–
+
OUTPUT
TO
VCO
9
FROM
CHARGE
PUMP
659 10
From equation 2:
REFERENCE
1
2
(100kHz 2 )2 659 10
9
6
Fig. 8. Third order loop filter circuit diagram
3 . 844 10
2
Using these values in equation 1:
3
1 x 10
2
10MHz V
[A]
1
100 (2
100kHz)2
Loop Filter Design
Generally the third order filter configuration shown in Fig.8
gives better results than the more commonly used second
order because the reference sidebands are reduced. Three
equations are required to determine values for the three
constants where;
Where A is :
2
2
2
n
6
1
1
(
)
(
)
2
100k
100k
3 . 844 x 10
2
n
2
2
9
(
2
)
(
659 x 10
)
1
1 = C1
2 = R2 (C1 + C2)
3 = C2 R2
1
The equations are;
9
1 . 59
3 . 84 10
C1 C1
10
x 2 . 415
1
1
1
2
3
2
2
K
N
K0
1
9
n
2
1
2
1
2
2
2
2
1
n
n
3
Now
3 . 84nF
1
R2 (C1 C2)
C2 R2
2
3
n
1
tan
0
cos
0
3
3
n
Substituting for C2
Where;
K
is the phase detector gain factor in mA/radian
K0 is the VCO gain factor in radian/second/Volt
R2 C1
2
2
3
N
is the total division ratio from VCO to reference
frequency
is the natural loop bandwidth
is the phase margin normally set to 45°
n
0
Since the phase detector is linear over a range of 2 radian,
K can be calculated from
829
K = Phase comparator current setting/2
mA/radian
These values can now be substituted in equation 1 to obtain
a value for C1 and equation 2 and 3 used to determine values
for C2 and R2
0 . 794
EXAMPLE
Calculate values for a loop with the following parameters
Frequency to be synthesised: 1000MHz
Reference frequency
Division ratio
n natural loop frequency
K0 VCO gain factor
0 phase margin
10MHz
1000MHz/10MHz = 100
100kHz
2 x 10MHz/Volt
45°
Phase comparator current
6.3mA
The phase detector gain factor K
= 6.3mA /2 = 1mA/radian
SP8854D
gain can be modified when new frequency data is entered to
compensate for change in the VCO gain characteristic over its
frequency band. The charge pump pulse current is
determined by the current fed into pin 19 and is approximately
equal to pin 19 current when the programmed multiplication
ratio is one. The circuit diagram Fig. 7e shows the internal
components on pin 19 which mirror the input current into the
charge pump. The voltage at pin 19 will be approximately 1.6V
above ground due to two Vbe drops in the current mirror. This
voltage will exhibit a negative temperature coefficient, causing
the charge pump current to change with chip temperature by
up to 10% over the full military temperature range if the current
programming resistor is connected to VCC as shown in the
application diagram Fig. 5. In critical applications where this
change in charge pump current would be too large the resistor
to pin 19 could be increased in value and connected to a
higher supply to reduce the effect of Vbe variation on the
current level. A suitable resistor connected to a 30V supply
would reduce the variation in pin 19 current due to
temperature to less than 1.5%. Alternatively a stable current
source could be used to set pin 19 current.
The charge pump output on pin 20 will only produce
symmetricalupanddowncurrentsifthevoltageisequaltothat
on the voltage reference pin 21. In order to ensure that this
voltage relationship is maintained, an operational amplifier
must be used as shown in the typical application Fig. 5. Using
this configuration pin 20 voltage will be forced to be equal to
that on pin 21 since the operational amplifier differential input
voltage will be no more than a few millivolts (the input offset
voltageoftheamplifier). Whenthesynthesiserisfirstswitched
onorwhenafrequencyoutsidetheVCOrangeisprogrammed
the amplifier output will limit, allowing pin 20 voltage to differ
from that on pin 21. As soon as an achievable frequency value
is programmed and the amplifier output starts to slew the
correct voltage relationship between pin 20 and 21 will be
restored. Because of the importance of voltage equality
between the charge pump reference and output pins, a
resistor should never be connected in series with the
operational amplifier inverting input and pin 20 as is the case
with a phase detector giving voltage outputs. Any current
drawn from the charge pump reference pin should be limited
to the few micro amps input current of a typical operational
amplifier. A resistor between the charge pump reference and
the non inverting input could be added to provide isolation but
the value should not be so high that more than a few millivolts
drop are produced by the amplifier input current.
When selecting a suitable amplifer for the loop filter, a
number of parameters are important; input offset voltage in
most designs is only a few milivolts and an offset of 5mV will
produce a mismatch in the up and down currents of about 4%
with the charge pump multiplication factor set at 1. The
mismatch in up down currents caused by input offset voltage
will be reduced in proportion to the charge pump multiplication
factor in use. If the linearity of the phase detector about the
normal phase locked operating point is critical, the input offset
voltage of most amplifiers can be adjusted to near zero by
means of a potentiometer.
The charge pump reference voltage on pin 21 is about 1.3V
below the positive supply and will change with temperature
and with the programmed charge pump multiplication factor.
In many cases it is convenient to operate the amplifier with the
negative power supply pin connected to 0V as this removes
theneedforanadditionalpowersupply. Theamplifierselected
must have a common mode range to within 3.4V (minimum
charge pump reference voltage) of the negative supply pin to
operate correctly without a negative supply. Most popular
amplifiers can be operated from a 30V positive supply to give
a wide VCO voltage drive range and have adequate common
mode range to operate with inputs at +3.4V with respect to the
negative supply. Input bias and offset current levels to most
operational amplifiers are unlikely to be high enough to
significantly affect the accuracy of the charge pump circuit
currents but the bias current can be important in reducing
referencesidebandsandlocaloscillatordriftduringfrequency
changes. When the loop is locked, the charge pump produces
only very narrow pulses of sufficient width to make up for any
charge lost from the loop filter components during the
reference cycle. The charge lost will be due to leakage from
the charge pump output pin and to the amplifier input bias
current, the latter usually being more significant. The result of
the lost charge is a sawtooth ripple on the VCO control line
which frequency modulates the phase locked oscillator at the
reference frequency and its harmonics. A similar effect will
occur whenever the strobe input is taken high during a
programming sequence. In this case the charge pump is
disabledwhenthestrobeinputishighandanyleakagecurrent
will cause the oscillator to drift off frequency. To reduce this
effect, the duration of the strobe pulse should be minimised.
F
and F outputs
ref
These outputs provide access to the outputs from the RF
pd
and reference dividers and are provided for monitoring
purposes during product development or test, and for
connection of an external phase detector if required. the
output circuit is of ECL type, the circuit diagram being shown
in Fig. 7g. The outputs can be enabled or disabled under
software control by the address 0 control word but are best left
in the disabled state when not required as the fast edge
speeds on the output can increase the level of reference
sidebands on the synthesised oscillator.
The emitter follower outputs have no internal down resistor
to save current and if the outputs are required an external pull
down resistor should be fitted.The value should be kept as
high as possible to reduce supply current, about 2.2k being
suitable for monitoring with a high impedance oscilloscope
probe or for driving an AC coupled 50ohm load. A minimum
value for the pull down resistor is 330ohms. When the Fpd and
Fref outputs are disabled the output level will be at the logic low
level of about 3.5V so that the additional supply current due to
the load resistors will be present even when the outputs are
disabled.
Reference input
The reference input circuit functions as an input amplifier or
crystal oscillator. When an external reference signal is used
thisissimplyACcoupledtopin28, thebaseoftheinputemitter
follower. When a low phase noise synthesiser is required the
reference signal is critical since any noise present here will be
multiplied by the loop. To obtain the lowest possible phase
noise from the SP8854D it is best to use the highest possible
reference input frequency and to divide this down internally to
obtain the required frequency at the phase detector. The
amplitude of the reference input is also important, and a level
close to the maximum will give the lowest noise. When the use
of a low reference input frequency say 4–10MHz is essential
some advantage may be gained by using a limiting amplifier
such as a CMOS gate to square up the reference input.
In cases where a suitable reference signal is not available,
it may be more convenient to use the input buffer as a crystal
oscillator in this case the emitter follower input transistor is
connected as a colpitts oscillator with the crystal connected
from the base to ground and with the feedback necessary for
oscillation provided by a capacitor tap at the emitter. The
arrangement is shown inset in Fig. 5
.
SP8854D
V
CC
V
CC
3k
3k
296
296
296
40k
40k
24,25
28
27
F
F
pd ref
OUTPUTS
60k
60k
3.3mA
50 A
50 A
100 A
0V
0V
100 A
100 A
Fig. 7g Fpd and F outputs
Fig. 7h Reference oscillator
ref
Fig. 7 Interface circuit diagrams (cont)
using a chip capacitor. The remaining input should be
decoupled to ground, again using a chip capacitor. The inputs
can be driven differentially but the input circuit should not
provide a DC path between inputs or to ground.
APPLICATIONS
RF layout
The SP8854D can operate with input frequencies up to
1.7GHz but to obtain optimum performance, good RF layout
practices should be used. A suitable layout technique is to use
double sided printed circuit board with through plated holes.
Wherever possible the top surface on which the SP8854D is
mountedshouldbeleftasacontinuoussheetofcoppertoform
a low impedance earth plane. The ground pins 12 and 16
should be connected directly to the earth plane. Pins such as
VCC and the unused RF input should be decoupled with chip
capacitors mounted as close to the device pin as possible with
a direct connection to the earth plane, suitable values are
10nF for the power supplies and <1nF for the RF input pin.(a
lower value should be used sufficient to give good
decoupleing at the RF frequnecy of operation). A larger
decoupling capacitor mounted as close as possible to pin 26
should be used to prevent modulation of VCC by the charge
pump pulses. The Rset resistor should also be mounted close
to the Rset pin to prevent noise pickup, and the capacitor
connected from the charge pump output should be a chip
component with short connections to the SP8854D.
When the reference is derived from a crystal connected to
pins 27 and 28 as shown in Fig. 5 the oscillator components
are best mounted close to the SP8854D.
All signals such as the programming inputs, RF in,
referenceinandtheconnectionstotheop–amparebesttaken
through the pc board adjacent to the SP8854D with through
plated holes allowing connections to remote points without
fragmenting the earth plane.
Lock detect circuit
The lock detect circuit uses the up and down correction
pulses from the phase detector to determine whether the loop
is in or out of lock. When the loop is locked, both up and down
pulses are very narrow compared to the reference frequency,
but the pulse width in the out of lock condition continuously
varies, depending on the phase difference between the
outputs of the reference and RF counters. The logical AND of
the up and down pulses is used to switch a 20mA current sink
to pin 18 and a 50k resistor provides a load to VCC. The circuit
is shown in Fig. 7c. When lock is established, the narrow
pulses from the phase detector ensure that the current source
isoffforthemajorityofthetimeandsopin18willbepulledhigh
by the 50k resistor. A voltage comparator with a switching
threshold at about 4.7V monitors the voltage at pin 18 and
switches pin 17 low when pin 18 is more positive than the 4.7V
threshold. When the loop is unlocked, the frequency
difference at the counter outputs will produce a cyclic change
in pulse width from the phase detector outputs with a
frequency equal to the difference in frequency at the reference
and RF counter outputs. A small capacitor connected to pin 18
prevents the indication of false phase lock conditions at pin 17
for momentary phase coincidence. Because of the variable
width pulse nature of the signal at pin 18 the calculation of a
suitable capacitor value is complex, but if an indication with a
delay amounting to several times the expected lock up time is
acceptable, the delay will be approximately equal to the time
constant of the capacitor on pin 18 and the internal 50k
resistor. If a faster indication is required, comparable with the
loop lock up time, the capacitor will need to be 2–3 times
smaller than the time constant calculation suggests. The time
torespondtoanoutoflockconditionis2–3timeslessthanthat
required to indicate lock.
Programming bus
The input pins are designed to be compatible with TTL or
CMOS logic with a switching threshold set at about 2.4V by
three forward biased base emitter diodes. The inputs will be
taken high by an internal pull up resistor if left open circuit but
for best noise immunity it is better to connect unused inputs
directly to VCC or ground.
Charge pump circuit
RF inputs
The charge pump circuit converts the variable width up and
down pulses from the phase detector into adjustable current
pulses which can be directly connected to the loop amplifer.
Themagnitudeofthecurrentandthereforethephasedetector
The prescaler has a differential input amplifer to improve
input sensitivity. Generally the input drive will be single ended
and the RF signal should be AC coupled to either of the inputs
SP8854D
V
CC
V
CC
4k
325
325
40k
40k
5k
5k
RF
INPUT
13
500
500
INPUT
RF
INPUT
14
50 A
3mA
0V
3k
0V
Fig.7a 16 bit input bus, Fpd/F enable, control direction,
Fig. 7b RF inputs
ref
reference divider inputs and strobe
C–LOCK DETECT (HIGH WHEN LOCKED)
18
V
CC
V
CC
2k5
2k5
50k
3k
3k
17
LOW
WHEN
LOCK
DETECT
OUTPUT
LOCKED
V
REF
4.7V
3k
3k
400 A
100 A
20 A
100
100
1k
11
0V
0V
Fig. 7c Lock detect decouple
Fig. 7d Lock detect output
CHARGE PUMP
OUTPUT
REFERENCE
R
V
CC
set
20 21
19
450
450
V
CC
CHARGE PUMP
CURRENT SOURCES
UP
83
83
V
CC
DOWN
130
2mA
Fig. 7e Rset pin.
Fig. 7f Charge pump circuit
Fig. 7 Interface circuit diagrams
SP8854D
The Fpd and Fref signals to the phase detector are available
on pin 24 and 25 and may be used to monitor the frequency
input to the phase detector or used in conjunction with an
external phase detector. The outputs are disabled by taking
pin 22 low. When the Fpd and Fref outputs are to be used at
high frequencies, an external pull down resistor of minimum
value330 maybeconnectedtogroundtoreducethefalltime
of the output pulse.
The charge pump connections to the loop amplifier consist
of the charge pump output and the charge pump reference.
The matching of the charge pump up and down currents will
only be maintained if the charge pump output is held at a
voltage equal to the charge pump reference using an
operational amplifier to produce a virtual earth condition at pin
20.
The lock detect circuit can drive an LED to give visual
indication of phase lock or provide an indication to the control
system if a pull up resistor is used in place of the LED. A small
capacitor connected from the c–lock detector pin to ground
may be used to delay lock detect indication and remove
glitches produced by momentary phase coincidence during
lock up.
Bit 15
Bit 14
Current Multiplication
Factor
0
0
1
1
0
1
0
1
1.0
1.5
2.5
4.0
Table 1
Vcc 1 . 6V
Rset
Pin 19 current
Phase detector gain
Ipin 19(mA) multiplication factor
2
mA radian
To allow for control direction changes introduced by the
design of the PLL, pin 23 is used to reverse the sense of the
phase detector by transposing the Fpd and Fref connections.
In order that any external phase detector will also be reversed,
the Fpd/Fref outputs are interchanged by pin 23 as shown in
Table 2.
4
5
6
7
PIN
11
40 41 42 43
1
44
2
3
8
9
10
13
12
11
10
9
8
7
6
5
4
3
2
1
0
2
2
2
2
2
2
2
2
2
2
2
2
2
2
M COUNTER
3 BIT A
COUNTER
PHASE
DETECTOR
GAIN
CONTROL
See Table 1
Output for RF Phase Lag
Fig. 6 Programming pin allocation
Control direction pin 23
Pin 20
1
0
Current Source
Current Sink
Table 2
SP8854D
+5V
STROBE
CONTROL
MICRO
1k
7
8
39
38
37
36
35
34
33
32
31
30
29
9
* VALUES DEPEND
ON APPLICATION
10
11
12
13
14
15
16
17
SP8854D
VCO
1n
LOOP
FILTER
*
APPLICATION USING
CRYSTAL REFERENCE
*
*
2k2
SP8854
+30V
100n
27
28
Fpd Fref
–
+
OP27
ETC
33p
1n
10n
* 100p
1n
in
10MHz
CRYSTAL
1
10n
100p
R
ef
Fig. 5 Typical application diagram
DESCRIPTION
when frequency changes are made, the strobe input disables
the charge pump outputs when high. During this period the
VCO control voltage will be maintained by the loop filter
components around the loop amplifier, but due to the
combined effects of the amplifier input current and charge
pump leakage a gradual change will occur. In order to reduce
the change, the duration of the strobe pulse should be
minimised. Selection of a loop amplifer with low input current
will reduce the VCO voltage droop during the strobe pulse and
result in minimum reference sidebands from the synthesiser.
Prescaler and AM counter
The programmable divider chain is of A M counter
construction and therefore contains a dual modulus front end
prescaler, an A counter which controls the dual modulus ratio
and an M counter which performs the bulk multi–modulus
division. A programmable divider of this construction has a
division ratio of MN+A and a minimum integer steppable
division ratio of N(N–1), where N is the prescaler ratio.
Data entry and storage
Data is loaded from the 16 bit bus by applying a positive
pulse to the strobe input. The input bus can be driven from TTL
or CMOS logic levels. When the strobe input is low, the bus
inputs are isolated and the data can be changed without
affecting the programmed state. When the strobe input is
taken high, the A and M and counters are reset and the input
dataisappliedtotheinternalstorageregister. Whenthestrobe
input is again taken low, the data on the input bus is stored in
the internal register and the A and M counters released. The
strobe input is level triggered so that if the data is changed
whilst the input is high, the final value before the strobe goes
low will be stored.
Reference input
The reference source can be either driven from an external
sine or square wave source of up to 100MHz or a crystal can
be connected as shown in Fig. 5.
Phase Comparator and Charge pump
The SP8854D has a digital phase/frequency comparator
driving a charge pump with programmable current output. The
charge pump current level at the minimum gain setting is
approximately equal to the current fed into the Rset input pin
19 and can be increased by programming the bus according
to Table 1 by up to 4 times.
InordertopreventdisturbancesontheVCOcontrolvoltage
SP8854D
TYPICAL OVERLOAD
+20
+10
+7
GUARANTEED
OPERATING
WINDOW
INPUT TO
PIN13
(dBm)
–5
–10
–20
–30
1.7GHz
2GHz
100MHz
1GHz
10GHz
TYPICAL SENSITIVITY
INPUT DRIVE REQUIREMENTS
Fig. 5 SP8854D
+j1
+j0.5
+j2
Zo=50
+j0.2
+j5
0
0.2
0.5
1
2
5
50MHz
1.1GHz
2.5GHz
–j5
–j0.2
–j2
–j0.5
–j1
Fig. 4 R.F. input impedance
SP8854D
ELECTRICAL CHARACTERISTICS
Guaranteed over the full temperature and supply voltage range (unless otherwise stated)
Temperature Tamb for KG parts –55°C and +100 °C
Temperature Tamb for IG parts –40°C and +85°C
Supply Voltage VCC = 4.75V and 5.25V
Value
Characteristics
Supply current
Pin
Units
Conditions
Min
Typ
Max
240
15, 26
13, 14
13,14,24
28, 25
28,24,25
28
180
mA
RF input sensitivity
–5.0
56
1
+7.0
16383
1023
50
dBm
100MHz to 1.7GHz See Fig. 3
RF division ratio
Reference division ratio
Comparison frequency
Reference input frequency
MHz
MHz
10
0
100
Reference division ratio ≥ 2 See
Note 1
Reference input voltage
Fref/Fpd output voltage high
Fref/Fpd output voltage low
Lock detect output voltage
28
24, 25
24, 25
17
+6
+10
dBm
–0.8
–1.4
300
Vwrt VCC 2.2K to 0V
Vwrt VCC 2.2K to 0V
2
500
1.7
mV
mA
Iout = 3mA
Charge pump current at
multiplication factor =1
19,20,21
Vpin 20 = Vpin 21
,
1.4
1.5
I
pin 19 = 1.6mA
Charge pump current at
multiplication factor =1.5
19,20,21
19,20,21
19,20,21
mA
mA
mA
V
Vpin 20 = Vpin 21
,
,
,
2.0
3.4
2.3
3.8
6.1
2.5
4.1
6.5
Ipin 19 = 1.6mA
Charge pump current at
multiplication factor = 2.5
Vpin 20 = Vpin 21
Ipin 19 = 1.6mA
Charge pump current at
multiplication factor = 4.0
Vpin 20 = Vpin 21
pin 19 = 1.6mA
5.4
3.5
I
Input bus high logic level
Input bus low logic level
Input bus current source
Input bus current sink
1–11,22
23,29,44
1–11,22,
23,29–44
1
V
A
1–11,22,
23,29–44
–200
VIN = 0V
1–11,22,
23,29–44
10
5
A
VIN = VCC
Up down current matching
20
%
Vpin 20 = Vpin 21,
Ipin 19 = 1.6mA
Charge pump reference
voltage
21
21
VCC – 0.5
V
V
I
pin 19 = 1.6mA
current multiplication factor =1
pin 19 = 1.6mA
Charge pump reference
voltage
VCC–1.6
0.5
I
current multiplication factor = 4
Rset current
19
19
18
2
mA
V
See Note 2
Rset Voltage
1.6
Ipin 19 = 1.6 mA
C–lock detect current
Strobe pulse width
Data set up time
+10
A
Vpin18=4.7V
Note 3
50
nS
nS
100
Note 3
Notes: 1. Lower reference frequencies may be used if slew rates are maintained.
2. Pin 19 current x multiplication factor must be less than 5mA if charge pump current accuracy is to be maintained.
3. Guaranteed but not tested.
SP8854D
PIN DESCRIPTION
PIN
DESCRIPTION
1,2,3,4,5,6,7,8,9,10,11,42,43,44
These pins are the data inputs used to set the RF divider ratio (M.N+A). Open
circuit=1 (high) on these pins. Data is transparent from pins to RF buffer when Pin
39 (strobe) is HI and frozen in RF buffer when Pin 39 is LO.
13, 14 (RF INPUT)
Balanced inputs to the RF pre–amplifier. For single ended operation the signal is
AC coupled into pin 13 with pin 14 AC decoupled to ground (or vice–versa.) Pins
13 and 14 are internally DC biased.
17 (LOCK DETECT INPUT)
18 (C–LOCK DETECT)
A current sink into this pin is enabled when the lock detect circuit indicates lock.
Used to give an external indication of phase lock.
A capacitor connected to this point determines the lock detect integrator time
constant and can be used to vary the sensitivity of the phase lock indicator.
19 (Rset)
An external resistor from Pin 19 to VCC sets the charge pump output current.
20 (CP OUTPUT)
The phase detector output is a single ended charge pump sourcing or sinking
current to the inverting input of an external loop filter.
21 (CP REF)
Connected to the non–inverting input of the loop filter to set the optimum DC bias.
22 (Fref/Fpd ENABLE)
Part of the input bus. When this pin is logic HI the Fref and Fpd outputs are en-
abled. Open circuit=HI.
23 (CONTROL DIRECTION)
This pin controls charge pump output direction. For Pin 23 HI the output sinks
current when Fpd > Fref or when the RF phase leads Ref phase. for Pin 23 LO the
relationship is reversed. (see table 2).
24
25
=Fpd if Pin 23 is HI
=Fref if Pin 23 is LO
RF divider output pulses. Fpd=RF input frequency/(M.N+A). Pulse width=8
RF input cycles (1 cycle of the divide by 8 prescaler output).
=Fref if Pin 23 is HI
=Fpd if pin 23 is LO
Reference divider output pulses. Fref=Reference input frequency/R. Pulse width
=high period of Ref input.
27 (Reference Oscillator Capacitor)
28 (Ref IN/XTAL)
Leave open circuit if an external reference is used. See Fig. 5 for typical
connection for use as an onboard crystal oscillator.
This pin is the input buffer amplifier for an external reference signal. This amplifier
provides the active element if an onboard crystal oscillator is used.
29,30,31,32,33,34,35,36,37,38
39 (Strobe)
These pins set the Reference divider ratio R. Open circuit =HI.
When Pin 39 is HI the A, M, and R counters are held in the reset state and the
charge pump output is disabled. When Pin 39 is low the data on the RF data and
PD Gain data inputs is fixed in the buffers, the buffers are loaded into the RF
counters and the PD Gain control, all the counters are active, and the charge
pump is enabled. Open circuit =HI.
40, 41 (PD Gain)
These pins set the charge pump current multiplication factor (see table 1). The
data is transparent into the buffers when Pin 39 is HI and frozen when Pin 39 is
LO. Open circuit =HI.
SP8854D
F.2SP854Dblockdigram
OCTOBER 1995
PRELIMINARY INFORMATION
D.S. 3701 2.6
SP8854D
1.7GHz PARALLEL LOAD PROFESSIONAL SYNTHESISER
The SP8854D is one of a family of parallel load
synthesisers containing all the elements apart from the loop
amplifier to fabricate a PLL synthesis loop. Other parts in the
series are the SP8852D which is fully programmable requiring
INDEX CORNER
two 16 word bit words to set the RF and reference counters,
and the SP8855D which is programmed by hard wired links or
switches.
1 44
The SP8854D is programmed using a 16 bit parallel data
bus. This Data is stored in an internal buffer. The 10 bit
programmable reference divider is programmed by
connecting the 10 programming pins either to ground or +5V.
The device can therefore be programmed with a single
transfer from the control microprocessor. Hard wired inputs
can also control the Fpd and Fref outputs and the control sense
of the loop.
FEATURES
1.7GHz Operating Frequency
HC44
Single 5V Supply Operation
Low Power Consumption <1.3W
High Comparison Frequency 20MHz
High Gain Phase Detector 1mA/rad
Zero ‘‘Dead Band” Phase Detector
Wide Range of RF and Reference Divide Ratios
Programming by Single Word Data Transfer
Pin
Description
Pin
Description
1
Input bus bit 10
Input bus bit 9
Input bus bit 8
Input bus bit 7
Input bus bit 6
Input bus bit 5
Input bus bit 4
Input bus bit 3
Input bus bit 2
Input bus bit 1
Input bus bit 0
0V (prescaler)
RF input
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Control direction
2
F
F
pd*
ref*
3
4
+5V
5
Ref. osc capacitor
Ref in/XTAL
6
ABSOLUTE MAXIMUM RATINGS
7
Ref divider bit 9
Ref divider bit 8
Ref divider bit 7
Ref divider bit 6
Ref divider bit 5
Ref divider bit 4
Ref divider bit 3
Ref divider bit 2
Ref divider bit 1
Ref divider bit 0
Strobe
Input bus bit 15
Input bus bit 14
Input bus bit 13
Input bus bit 12
Input bus bit 11
8
Supply Voltage
Storage Temperature
Operating Temperature
–0.3V to 6V
–65°C to +150°C
–55°C to +100°C
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Prescaler & reference Input Voltage
Data inputs
2.5V p–p
VCC +0.3V
VEE –0.3V
+175°C
RF input
V
V
+5V (prescaler)
0V
CC
EE
Junction temperature
Lock detect output
C–lock detect
ORDERING INFORMATION
R
set
SP8854D KG HCAR (non standard temperature range
–55°C to +100°C standard product screening)
Charge pump output
Charge pump ref.
F
/F enable
pd ref
SP8854D IG HCAR (Industrial temperature range
–40°C to +85°C standard product screening)
*F andF outputsarereversedusingthecontroldirectioninput.The
pd
ref
table above is correct when pin 23 is high.
Thermal Data
ESD:
JC=5°C/W
JC=53°C/W
1000V, Human body model
Fig. 1 Pin connections – top view
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