PDSP16510A_技术文档

PDSP16256/A

Programmable FIR Filter

DS3709

ISSUE 7.1

June 1999

Features

Ordering Information

Commercial (0°C to +70°C)

PDSP16256A/C0/AC 25MHz, PGA package

Industrial (-40°C to +85°C)

PDSP16256 B0/AC 20MHz, PGA package

PDSP16256 B0/GC 20MHz, QFP package

Military (-55°C to +125°C)

● Sixteen MACs in a Single Device

● Basic Mode is 16-Tap Filter at up to 25MHz

Sample Rates

● Programmable to give up to 128 Taps with

Sampling Rates Proportionally Reducing to

3·125MHz

PDSP16256 MC/AC1R 20MHz, MIL-STD-883*

● 16-bit Data and 32-bit Accumulators

● Can be configured as One Long Filter or Two

Half-Length Filters

(latest revision), PGA package

PDSP16256 MC/GC1R 20MHz, MIL-STD-883*

(latest revision), QFP package

● Decimate-by-two Option will Double the Filter

Length

● Coefficients supplied from Host System or local

EPROM

*See notes following Electrical Characteristics for further

information on MIL-STD-883 screening

Associated Products

Applications

PDSP16350 I/Q Splitter/NCO

PDSP16510A FFT Processor

● High Performance Digital Filters

Description

The device can be configured as either one long

filter or two separate filters with half the number of

taps in each. Both networks can have independent

inputs and outputs.

The PDSP16256 contains sixteen multiplier -

accumulators, which can be multi cycled to provide

from 16 to 128 stages of digital filtering. Input data

and coefficients are both represented by 16-bit

two’s complement numbers with coefficients

converted internally to 12 bits and the results being

accumulated up to 32 bits.

Both single and cascaded devices can be operated

in decimate-by-two mode. The output rate is then

half the input rate, but twice the number of stages

are possible at a given sample rate. A single device

with a 20MHz clock would then, for example,

provide a 128-stage low pass filter, with a 5MHz

input rate and 2·5MHz output rate.

In 16-tap mode the device samples data at the

system clock rate of up to 25MHz. If a lower sample

rate is acceptable then the number of stages can be

increased in powers of two up to a maximum of 128.

Each time the number of stages is doubled, the

sampleclockratemustbehalvedwithrespecttothe

system clock. With 128 stages the sample clock is

therefore one eighth of the system clock.

Coefficients are stored internally and can be down

loaded from a host system or an EPROM. The latter

requires no additional support, and is used in stand

alone applications. A full set of coefficients is then

automatically loaded at power on, or at the request

of the system. A single EPROM can be used to

provide coefficients for up to 16 devices.

In all speed modes devices can be cascaded to

provide filters of any length, only limited by the

possibility of accumulator overflow. The 32-bit

results are passed between cascaded devices

without any intermediate scaling and subsequent

loss of precision.

PDSP16256/A

CHANGE

COEFF

POWER-ON

RESET

EPROM

ADDR DATA

RES

PDSP

16256

INPUT

DATA

OUTPUT

DATA

EPROM

GND

SCLK

Figure. 1 A dual filter application

CHANGE

EPROM

COEFF

ADDR DATA

POWER-ON

RESET

RES

COEFFICIENTS

PDSP

16256

ANALOG

INPUT

OUTPUT

DATA

ADC

EPROM

GND

CLKOP

SCLK

Figure. 2 Typical system application

2

PDSP16256/A

Signal

Description

DA15:0

DB15:0

16-bit data input bus to Network A.

Delayed data output bus in the single filter mode. Connected to the data input bus of the next device in a

cascaded chain. Input to Network B in the dual filter modes.

X31:0

Expansion input bus in the single filter mode. Connected to the previous filter output in a cascaded chain.

The inputs are not used on a single device system or on the Termination device in a cascaded chain. The

X bus provides the output from Network B in both dual modes.

F31:0

FEN

In single filter mode this bus holds the main device output. In dual mode it holds the output from Network A.

Filterenable.ThefirsthighpresentonanSCLKrisingedgedefinesthefirstdatasample.Thecontrolregister

and coefficient memory must be configured befor FEN is enabled.The signal must stay active whilst valid

data is being received and must be low if FRUN is high.

DFEN

SWAP

Delayed filter enable. This output is connected to the Filter Enable input of the next device in a cascaded

chain when moving towards the termination device and with multiple stand-alone EPROM-loaded

configurations. It is used to coordinate the control logic within each device.

Selects either the upper or lower set of coefficients for Bank Swap. A low selects the lower bank, a high the

upper bank.

FRUN

DCLR

In EPROM load mode, when high this signal allows continuous filter operations to occur without the need for

the initial FEN edge. If the device is not a single, interface or master device then this pin must be tied low.

A low on this signal on the SCLK rising edge will clear all the internal accumulators.

need only remain

DCLR

low for a single cycle, signal BUSY will indicate when the internal clearing is complete. After a clear the

device must be re-synchronised to the data stream using FEN. It is recommended that FEN is taken low

at the same time as clear. FEN may then be taken high to synchronise the data stream once BUSY has

returned low.

C15:0

A7:0

16-bit coefficient input bus. In the Byte mode of operation, C15:8 have alternative uses as explained in the

text.

Coefficient address bus. In the EPROM mode A7:0 are address outputs for an EPROM. In the remote host

mode they are inputs from the host. A7 is not used when coefficients are loaded as 16-bit words.

CCS

WEN

This pin is similar in operation to A7:0 and provides a higher order address bit. When low the coefficients

are loaded, when high the control register is loaded.

In the remote mode this pin is an input which when low enables the load operation. In the EPROM mode

it is an output which provides the write enable for other slave devices.

CS

This pin is always an input and must also be low for the internal write operation to occur.

BYTE

When this pin is tied low, coefficients are loaded as two 8-bit bytes. When the pin is high they are loaded

as 16-bit words. In the EPROM mode this pin is ignored.

EPROM

When this pin is tied low coefficients are loaded as bytes from an external EPROM. The device outputs an

address on A7:0. When the pin is high coefficients must be loaded from a remote master. They can then

be transferred individually rather than as a complete set.

SCLK

The main system clock; all operations are synchronous with this clock. The clock rate must be either 1, 2,

4, or 8 times the required data sampling rate. The factor used depends on the required filter length.

CLKOP

OEN

This output, when used to enable SCLK, can provide a data sampling clock. It has the effect of dividing the

SCLK rate by 1, 2, 4 or 8 depending on the filter mode selected.

OEN

Tri-state enable for the F bus. When high the outputs will be high impedance.

device and does not therefore take effect until the first SCLK rising edge

is registered onto the

BUSY

RES

A high on this signal indicates that the device is completing internal operations and is not yet able to accept

new data. The signal is used during automatic EPROM loading, reset and accumulator clearing.

When this pin is low the control logic and accumulators are reset. In the EPROM mode it will initiate a load

sequence when it goes high.

NOTES

1. Unused buses (e.g. X31:0 when the device is configured in single or termination mode) can be set to any value. They should however be

maintained at a valid logic level to avoid an increase in power consumption.

2. To ensure correct input voltage thresholds are maintained all the V_DDand GND pins must be connected to adequate power and ground planes.

Table 1 Pin descriptions

3

PDSP16256/A

R

P

N

M

L

K

J

H

G

F

EXTRA PIN D4,

CONNECTED TO D3

E

D

C

B

A

AC144

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

Fig. 3a Pin connections for 144 pin PGA package (bottom view)

PIN 1 INDEX

PIN 1

PIN 172

GC172

Fig. 3b Pin connections for 172 pin QFP (top view)

Figure. 3 Pin connection diagrams (not to scale). See Table 1 for signal descriptions and Table 2 for

pinouts.

4

PDSP16256/A

Signal

GG

AC

Signal

AC

GG

AC

Signal

GG

Signal

GG

AC

SWAP

GND

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

P1

-

C15

GND

A15

B15

D13

C14

G15

C15

D14

J15

E13

D15

E14

E15

F13

F14

F15

-

G14

G13

H14

-

H15

H13

J14

K15

-

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

-

GND

BUSY

X0

V_DD

X1

X2

X3

X4

X5

X6

GND

X7

X8

V_DD

X9

X10

X11

X12

X13

X14

GND

X15

X16

X17

X18

X19

X20

X21

X22

GND

X23

X24

X25

V_DD

X26

X27

X28

X29

X30

GND

X31

V_DD

FRUN

1

2

3

4

5

6

7

8

F0

F1

F2

F3

V_DD

F4

F5

GND

F6

F7

F8

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

R14

-

N12

P13

-

A1

A2

-

C4

B3

A3

B4

C5

A4

-

B5

A5

A7

C6

B6

A6

B7

C7

B8

A9

A8

C8

B9

A10

C9

B10

A11

C10

-

OEN

CLKOP

N2

N1

M2

-

L3

M1

M3

-

L2

L1

K3

K2

K1

J2

J3

G1

H2

H1

J1

H3

G2

F1

G3

-

F2

E1

F3

E2

D1

-

E3

D2

C1

C2

D3

B1

B2

-

WEN

CCS

V_DD

DA0

DA1

DA2

DA3

DA4

DA5

GND

DA6

DA7

DA8

DA9

V_DD

DA10

DA11

DA12

DA13

DA14

DA15

GND

C0

R13

P12

N11

R12

P11

R11

R9

N10

P10

R10

P9

R7

N9

P8

R8

N8

P7

R6

-

N7

P6

R5

N6

P5

R4

-

N5

P4

R3

P3

N4

-

CS

V_DD

RES

SLCK

GND

V_DD

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

F9

BYTE

F10

F11

F12

GND

F13

F14

F15

V_DD

F16

F17

F18

F19

V_DD

F20

F21

GND

F22

F23

F24

F25

F26

F27

F28

GND

F29

F30

F31

V_DD

FEN

DFEN

EPROM

A0

A1

A2

A3

A4

V_DD

A5

A6

GND

A7

DB0

DB1

DB2

GND

DB3

DB4

DB5

DB6

DB7

V_DD

DB8

DB9

DB10

DB11

DB12

DB13

DB14

GND

DB15

V_DD

C1

C2

C3

C4

C5

V_DD

C6

C7

J13

K14

-

L15

K13

L14

M15

L13

M14

N15

-

N14

M13

P15

-

B11

A12

C11

-

B12

A13

B13

C12

A14

-

C8

C9

C10

GND

C11

C12

C13

V_DD

R2

P2

N3

-

R1

P14

N13

R15

B14

-

C13

GND

C14

C3

-

DCLR

NOTE. All GND and V_DDpins must be used

Table 2 Pin connections for AC144 and GC172 packages

5

PDSP16256/A

DA15:0

F31:0

OEN

SCLK

FRUN

SWAP

A7:0

NETWORK

A

C15:0

CCS

WEN

CS

DUAL

MODE

COEFFICIENT

STORAGE

AND

MUX

BYTE

EPROM

FEN

CONTROL

NETWORK

B

DFEN

DCLR

RES

SINGLE

MODE

CLKOP

BUSY

DB15:0

X31:0

Figure. 4 Block Diagram

Operational Overview

The PDSP16256 is an application specific FIR filter for

use in high performance digital signal processing

systems. Sampling rates can be up to 25MHz. The

device provides the filter function without any software

development, and the options are simply selected by

loading a control register. The device can be user

configured as either a single filter, or as two separate

filters. The latter can provide two independent filters for

the in-phase and quadrature channels after IQ splitting,

or can provide two filters in cascade for greater stop

band rejection.

through’ are not permissible in the system.

Coefficients can be loaded from a host system using a

conventional peripheral interface and separate data

bus. Alternatively, they can be loaded as a complete set

from a byte wide EPROM. The device produces

addresses for the EPROM and a BUSY output indicates

that the transfer is occurring. Up to sixteen devices can

have their coefficients supplied from a single EPROM.

These devices need not necessarily be part of the same

filter network.

Each of the filter networks shown in Fig. 4 contains eight

systolic multiplier accumulator stages; an example with

four stages is shown in Fig. 5. Input data flows through

thedelaylinesandispresentedformultiplicationwiththe

requiredcoefficient. Thisisaddedtoeitherthelastresult

from this accumulator or the result from the previous

accumulator.Thefilterresultsprogressalongtheadders

at the data sample rate. If the sample rate equals SCLK

dividedbyfour,forexample,thentheaccumulatedresult

is passed onto the next stage every fourth cycle. The

structure described is highly efficient when used to

calculate filtered results from continuous input data.

A comprehensive digital filter design program is

availableforPCcompatiblemachines. Thiswilloptimise

the filter coefficients for the filter type required and

number of taps available at the selected sample rate

within the PDSP16256 device. An EPROM file can be

automatically generated in Motorola S-record format.

The device operates from a system clock, with rates up

to 25MHz. This clock must be 1, 2, 4, or 8 times the

required sampling frequency, with the higher

multiplication rates producing longer filter networks at

the expense of lower sampling rates. Devices can be

connected in cascade to produce longer filter lengths.

This can be accomplished without the need for any

additional external data delays, and all the single device

options remain available.

Continuous inputs are accepted, and continuous results

produced after the internal pipeline delay. Connection

can be made directly to an A-D converter. The filter

operation can be synchronised to a Filter Enable signal

(FEN) whose positive going edge marks the first data

sample. Theinternalmultiplieraccumulatorarraycanbe

cleared with a dedicated input. This is necessary if

erroneous results obtained during the normal data ‘flush

6

PDSP16256/A

DATA

OUT

DATA

IN

DATA

DELAY LINE

DATA

DELAY LINE

DATA

DELAY LINE

DATA

DELAY LINE

COEFF

RAM

COEFF

RAM

COEFF

RAM

COEFF

RAM

ACCUMULATE

EXPANSION

IN

RESULT

OUT

ADDER

21

Z

Figure. 5 Filter network diagram

Single Filter Options

the higher frequency components present in the input.

The Nyquist criterion, specifying that the sampling rate

must be at least double the highest frequency compo-

nent, can still then be satisfied even though the sampling

rate has been halved.

When operating as a single filter the device accepts data

on the 16-bit DA bus at the selected sample rate, see

Figs. 5 and 6. Results are presented on the 32-bit F bus,

whichmaybetristatedusingthe OEN input.Signal OEN is

registered onto the device and does not therefore take

effect until the first SCLK rising edge. Devices may be

cascaded this allows filters with more taps than available

from a single device. To accomplish this two further

buses are utilised. The DB bus presents the input data to

the next device in cascade after the appropriate delay,

while, partial results are accepted on the X bus.

The system clock latency for a single device is shown in

Table3.Thisisdefinedasthedelayfromaparticulardata

sample being available on the input pins to the first result

including that input appearing on the output pins. It does

not include the delay needed to gather N samples, for an

N tap filter, before a mathematically correct result is

obtained.

Singlefiltermodeisselectedbysettingcontrolregisterbit

15 to a one. The required filter length is then selected

using control register bits 14 and 13 as summarised in

Table 3. The options define the number of times each

multiplier accumulator is used per sample clock period.

This can be once, twice, four times, or eight times.

DA15:0

F31:0

OEN

NETWORK

A

In addition a normal/decimate bit (CR12) allows the filter

length to be doubled at any sample rate. This is possible

when the filter coefficients are selected to produce a low

passfilter,sincethefilteredoutputwouldthennotcontain

DUAL

MODE

MUX

CR

Input

Output

Rate

Filter

Length

Setup

Latency

14 13 12 Rate

NETWORK

B

0

1

0

1

0

1

0

1

0

1

0

1

0

SCLK

16 Taps

32 Taps

64 Taps

128 Taps

16

17

16

18

20

24

SCLK/2

SCLK/4

SCLK/8

SCLK/2

SCLK/4

SCLK/8

SINGLE

MODE

DB15:0

X31:0

Table 3 Single Filter options

Figure. 6 Single Filter bus utilisation

7

PDSP16256/A

SPEED MODE 0 (Data input and output at f ) CR14:13 = 00, CR12 = 0. CLKOP held high.

SCLK

31

32

33

1

2

3

16

17

18

34

35

FEN

DA15:0

A

B

C

F31:0

A′′

B′′

C′′

D′′

E′′

A′

B′

C′

CLKOP

First data point (A)

is read on edge 1

First valid result

including data point (A)

available after edge 16

Valid result contains

the first 16 data points

available after edge 31

SPEED MODE 1 (Data input and output at half f ) CR14:13 = 01, CR12 = 0

SCLK

78

79

80

1

2

3

16

17

18

81

82

FEN

DA15:0

A

B

F31:0

A′′

B′′

C′′

A′

B′

CLKOP

First data point (A)

is read on edge 1

First valid result

including data point (A)

available after edge 16

Valid result contains

the first 32 data points

available after edge 78

SPEED MODE 2 (Data input and output at a quarter f ) CR14:13 = 10, CR12 = 0

SCLK

272 273 274 275 276

1

2

3

4

5

20

21 22

23 24

FEN

DA15:0

A

B

F31:0

A′

B′

A′′

B′′

CLKOP

First data point (A)

is read on edge 1

First valid result

including data point (A)

available after edge 20

Valid result contains

the first 64 data points

available after edge 272

SPEED MODE 3 (Data input and output at an eighth f ) CR14:13 = 11, CR12 = 0

SCLK

1040 1041 1042 1043

1

2

3

4

5

6

7

8

9

24

25 26

27 28 29 30

31 32

FEN

A

B

DA15:0

F31:0

A′

B′

A′′

CLKOP

First data point (A)

is read on edge 1

First valid result

including data point (A)

available after edge 24

Valid result contains

the first 128 data points

available after edge 1040

SPEED MODE 1 Decimating (Datainputathalf f

andoutputataquarterf )CR14:13=01,CR12=1.

SCLK

142

143

144

1

2

3

18

19

20

21

22

145

FEN

DA15:0

A

B

F31:0

B′

B′′

CLKOP

First data point (A)

is read on edge 1

First valid result

including data point (A)

available after edge 18

Valid result contains

the first 64 data points

available after edge 142

Figure. 7 Single Filter timing diagrams

8

PDSP16256/A

Dual Indipendant Filter Options

length is selected using control register bits 14 and 13 as

summarised in Table 4, which also shows the resulting

latency. As in single filter mode normal or decimate-by-

two operation can be selected using control register bit

12.

When operating as two independent filters the device

accepts 16 bit data on both the DA and DB buses at the

selected sample rate, see Fig. 8. Results are available

from both the F and X buses. The F bus may be tristated

using the OEN input. Signal OEN is registered onto the

device and does not therefore take effect until the first

SCLK rising edge

Dual Cascaded Filter Options

When operating as two cascaded filters the device ac-

cepts 16 bit data on the DA bus at the selected sample

rate. Results are presented on the 32-bit X bus, see Fig.

9. Each filter must be configured in the same manner.

Multiple device expansion is not possible in this mode.

Each filter must be configured in the same manner, and

multiple device expansion is not possible due to the pin

re-organization. The latter requirement can, of course,

still be satisfied by several devices configured as single

filters.

Dual cascaded filter mode is selected by setting control

register bit 15 to a zero and bit 4 to a one. The required

filter length is selected using control register bits 14 and

13 as summarised in Table 4, which also shows the

resulting latency. The decimate-by-two option is not

available in this mode.

The data for the second filter network is extracted as the

middle16bitsfromthefirstnetworksaccumulatedresult.

Forsuccessfuloperationthefirstfilternetworkmusthave

unity gain. See the section on filter accuracy for more

details.

Dual independent filter mode is selected by setting

control register bits 15 and 4 to a zero. The required filter

CR

Input

Output

Rate

Filter

Length

Setup

Latency

1413 12 Rate

Ind Cas

0 0 0 SCLK

0 0 1 SCLK

0 1 0 SCLK/2

0 1 1 SCLK/2

1 0 0 SCLK/4

1 0 1 SCLK/4

1 1 0 SCLK/8

SCLK

8 Taps

16 Taps

32 Taps

64 Taps

16

17

16

18

20

24

27

-

28

-

SCLK/2

SCLK/4

SCLK/8

36

The cascade option is used to increase the stop band

rejection in a practical filter application. Theoretically,

increasingthenumberoftapsinanFIRfilterwillincrease

the stop band rejection, but this assumes floating point

calculationswithnoaccuracylimitations.Inpractice,with

fixed point arithmetic, better performance is achieved

with two smaller filters in series.

-

40

Table 4. Dual Filter options

DA15:0

F31:0

OEN

DA15:0

F31:0

OEN

NETWORK

A

NETWORK

A

DUAL

MODE

DUAL

MODE

MUX

NETWORK

B

NETWORK

B

SINGLE

MODE

SINGLE

MODE

DB15:0

X31:0

DB15:0

X31:0

Figure. 8 Dual independent filter bus utilisation

Figure. 9 Dual cascaded filter bus utilisation

9

PDSP16256/A

Filter Accuary

Input data and coefficients are both represented by 16-

bit two’s complement numbers. The coefficients are

converted to twelve bits by rounding towards zero. This

is achieved as follows. If the coefficient is positive then

theleastsignificant4bitsarediscarded. Ifthecoefficient

is negative then the logical ‘OR’ of the least significant 4

bits are added to the remainder of the word. Twelve bit

coefficients can be used directly provided the least

significant four bits are set to zero.

INPUT DATA

COEFFICIENT

ADDER

The FIR filter results are calculated using a multiplier

accumulator structure as shown in Fig. 10. The trunca-

tion and word growth allowed for in the data path are

explained in Fig. 10. The 16-bit data and 12-bit coeffi-

cient inputs (each with one sign bit before the binary

point), are presented to the multiplier. This produces a

28-bitresultwithtwobitsbeforethebinarypoint.Produc-

ing the full 28-bit result ensures that if both the data and

coefficients are set to logic 1 a valid result is generated.

Prior to entering the accumulator the least significant 4

bitsofthemultiplierresultaretruncatedandtheresulting

24 bits sign extended to 32 bits. The final accumulator

result is 32 bits with 10 bits before the binary point. Thus

9bitsofwordgrowthareallowedwithintheaccumulator.

All accumulator bits are made available on the output

pins.

ACCUMULATOR

RESULT

Figure. 10 Multiplier Accumulator

In cascade mode the middle 16 bits from the network A

accumulator are fed round to the network B data inputs,

see Fig. 11.

INPUT DATA

COEFFICIENT

S

-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 -15

-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11

Multiplication producing a 28-bit result

MULTIPLIER RESULT

0

-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14

-22 -23 -24 -25 -26

Sign extended to 32 bits, least significant 4 bits truncated

ACCUMULATOR RESULT

S

3

S

2

S

1

0

-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14

-22

ACCUMULATOR RESULT

S

8

7

6

5

4

These bits are passed to filter network B during cascade mode

Figure. 11 Filter accuracy

10

PDSP16256/A

Cascading Devices

When the filter requirements are beyond the capabilities

of a single device, it is possible to connect several

devices in cascade increasing the number of taps avail-

able at the required sample rate. Within each device all

filter length, decimate, and bank swap options are still

possible, but each device in the chain must be similarly

programmed and configured as a single filter.

to the Filter Enable input (FEN) of the next device in the

chain. The Interface device, itself, needs a FEN signal

producedbythesystem,unlessinEPROMmode,where

FRUN may be pulled high. Even when the latter is true,

theFENconnectionmustbemadebetweentheremain-

ing devices in the chain. By effectively extending the

filter length, the cascade latency is therefore the same

as for the single device in the same mode. Once the

pipeline is initially flushed the latency is as given in

Table 3.

The number of devices which can be cascaded is only

limitedbythepossibilityofoverflowinthe32-bitinterme-

diate accumulations. If more than sixteen devices are

cascaded in auto EPROM load mode, then an additional

EPROM will be needed.

When devices are cascaded such that the data sample

rate equals the clock rate, (Control register bits 14:13 =

00), then a different cascade configuration must be

used. This is shown in Fig. 13. The number of devices

that can be cascaded is, again, only limited by the 32-bit

accumulators.

In modes where the data sample rate does not equal the

clock rate. Then the cascade arrangement shown in Fig.

12isused. Delayeddataispassedfromdevicetodevice

in one direction, while intermediate results flow in the

oppositedirection.Theinterfacedevicebothacceptsthe

input data and produces the final result. It is not neces-

sary for each device to know its exact position in the

chain, but the device which receives the input data and

produces the final result must be identified, as must the

device which terminates the chain. The former is known

as the Interface device and the latter as the Termination

device, all others are Intermediate devices. Control

RegisterbitsCR11:10areusedtodefinethesepositions

as shown in Table 6.

In this mode the delayed data is passed from device to

device in the same direction as the intermediate results.

The device which accepts the input data is now at the

opposite end of the chain to the device which produces

the final result. The control logic in each of the devices

must be synchronised this is achieved by connecting all

the device FEN inputs to the global FEN. The cascade

latency for the complete filter is built up from the 12

delays from the termination device, 8 delays from the

interface device and additional intermediate devices

each adding 4 delays.

Thecontrollogicineachofthedevicesmustbesynchro-

nisedwithrespecttotheInterfacedevice.Thisisachieved

by connecting the Delayed Filter Enable output (DFEN)

Avalable Options

No more than 128 coefficients can be stored internally.

Thislimitsthefilterlength/decimate/bankswapoptions

to those which do not require more than that number of

coefficients. Thus when a filter with 128 taps is to be

implemented in a single device, it is not possible to

decimate or bank swap. When a filter with 64 taps is

implemented, decimate or bank swap are possible, but

not both. With all other filter lengths, all decimate and

bank swap configurations are possible.

RESULTS

DATA IN FEN

OUT

DA15:0

FEN

F31:0

INTERFACE

DEVICE

DB15:0 DFEN X31:0

DA15:0

FEN

F31:0

INTERMEDIATE

DEVICE

DB15:0 DFEN X31:0

DA15:0

FEN

F31:0

TERMINATION

DEVICE

DB15:0 DFEN X31:0

Figure. 12 Three-device cascaded system

11

PDSP16256/A

RESULTS

OUT

FEN

DB15:0

FEN

F31:0

INTERFACE

DEVICE

DA15:0 DFEN X31:0

DB15:0

FEN

F31:0

INTERMEDIATE

DEVICE

DA15:0 DFEN X31:0

DB15:0

FEN

F31:0

TERMINATION

DEVICE

DA15:0 DFEN X31:0

DATA IN

Figure. 13 Full speed cascaded system

128 TAP

127

64 TAP

32 TAP

16 TAP

127

UPPER

BANK

NOT USED

64

63

64

63

NO SWAP

POSSIBLE

UPPER

BANK

LOWER

BANK

32

31

32

31

UPPER

BANK

LOWER

BANK

16

15

LOWER

BANK

0

(a) Single Filters

64 TAP

127

32 TAP

16 TAP

8 TAP

127

B UPPER

BANK

FILTER B

NO SWAP

POSSIBLE

96

95

NOT USED

A UPPER

BANK

NOT USED

64

63

64

63

64

63

B UPPER

A UPPER

48

47

B LOWER

BANK

FILTER A

NO SWAP

POSSIBLE

32

31

32

31

32

31

B UPPER

A UPPER

B LOWER

A LOWER

B LOWER

A LOWER

BANK

16

15

0

(b) Dual Filters

Figure. 14 Coefficient memory map

12

PDSP16256/A

Loading Coefficients

Filter Control

Two control modes are available selected by input

signal FRUN. In EPROM load mode, when FRUN is

tied high the device will commence operation once the

coefficients have been loaded. The CLKOP signal

indicateswhennewinputdataisrequiredandthatnew

results are available, see Fig. 7. In both EPROM and

remote master load modes, when FRUN is tied low

filteroperationwillnotcommenceuntilahighhasbeen

detected on signal FEN. This mode allows synchroni-

sationtoanexistingdatastream. FENshouldbetaken

high when the first valid data sample is available so

that both are read into the device on the next SCLK

rising edge. Proper device operation requires FEN to

be low during control register and coefficient loading

bothinEPROMmodeandRemoteMastermode.After

loading coefficients, filter operation is determined by

FRUN and FEN as described above.

When the device is to operate in a stand alone

application then the coefficients can be down loaded

as a complete set from a previously programmed

EPROM. Alternatively if the system contains a micro-

processor they can be individually transferred from a

remote master under software control. In any mode

the system clock must be present and stable during

the transfer, and the addressing scheme is such that

the least significant address specifies the coefficient

applied to the first multiplier seen by incoming data.

The addresses used during the load operation are

those illustrated in Fig. 15. The Control Register is

loaded when CCS is high. In byte mode address A0 is

used to select the portion of control register loaded,

otherwise the address bits are redundant. When an

EPROM is used to provide coefficients, this redun-

dancy causes the number of locations needed for any

device to be double that for the coefficients alone.

During device reset

must be held low for a mini-

RES

mum of 16 SCLK cycles. After a reset the control

register returns to its default state of 8C80 _HEX. This

places the device into the following mode :

Auto EPROM LOAD

EPROM

When

is tied low, the PDSP16256 assumes

the role of a master device in the system and controls

the loading of coefficients from an external EPROM,

see Fig.15. A load sequence commences when

●

Single filter

Sample rate equal to the clock rate

Non-decimating

A single device (Not in a cascade chain)

●

RES

the

input goes high, and will continue until every

●

coefficient has been loaded. BUSY goes high to

indicate that a load sequence is occurring and the

filter output is invalid. The device will not commence

a filter operation until the FEN edge is received after

BUSYhasgonelow.Thisrequirementcanbeavoided

if FRUN is tied high.

●

Bank swap selected by bit in the control register

Coeficient Bank Swap

A Bank Swap feature is provided which allows all

coefficients to be simultaneously replaced with a dif-

ferent set. A bit in the Control Register (CR7) allows

the swap to be controlled by either input signal SWAP

or Control Register bit (CR6). The latter is useful if the

device is controlled by a microprocessor, when driving

a separate pin would entail additional address decod-

ing logic and an external latch.

The address bus pins become outputs on the Master

device,andproduceanewaddresseveryfoursystem

clock periods. This four clock interval, minus output

delays and the data set up time, defines the available

EPROM access time.

The coefficients are always loaded as bytes. The

state ofb the

pin on the master device is ig-

BYTE

If SWAP or bit CR6 is low, the coefficients used will be

those loaded into the lower banks illustrated in Fig. 14.

When the SWAP or CR6 is high, the upper banks are

used.

nored. This arrangement also allows the eight most

significant coefficient bus pins (C15:8) to be used for

other purposes as described later. Since the 16-bit

coefficients are loaded in two bytes the A0 pin speci-

fies the required byte. The maximum number of

stored coefficients is 128, eight address outputs are

therefore provided for the EPROM. These eight out-

puts from the Master must also drive the address

inputs on the slave devices.

The actual swap will occur when the next sampling

clock active going transition occurs. This can be up to

seven system clocks later than the swap transition,

and is filter length dependent. The first valid filtered

output will then occur after the pipeline latencies given

in Tables 3 and 4.

13

PDSP16256/A

SCLK

00

01

00

01

VALID ADDR

00

A7:0

LOAD MASTER CONTROL LOAD FIRST COEFFICIENT

REGISTER

LOAD LAST COEFFICIENT

CCS

RES

BUSY

Fig. 15a EPROM load sequence

SCLK

A7:0

CCS

FE

FF

00

01

00

01

FE

FF

00

01

00

01

0000

0001

0010

C15:12

LOAD LAST

MASTER

COEFFICIENT

LOAD SLAVE 1

CONTROL

REGISTER

LOAD SLAVE 1

COEFFICIENTS

LOAD LAST

SLAVE 1

COEFFICIENT

LOAD SLAVE 2

CONTROL

REGISTER

LOAD SLAVE 2

COEFFICIENTS

Fig. 15b EPROM load sequence for a cascaded system

Figure. 15 EPROM load sequence timing diagrams

(2 SLAVES)

PDSP16256

0010

GND

C11:8

CS

EPROM

LSB

A7:0

ADDRESS

CCS

MASTER

EPROM

BYTE

WEN

MSB

C15:12

C7:0

DATA

PDSP16256

SLAVE 1

0001

GND

C11:8

CS

A7:0

CCS

V

EPROM

BYTE

WEN

DD

C15:12

C7:0

GND

PDSP16256

SLAVE 2

0010

GND

C11:8

CS

A7:0

CCS

V

EPROM

BYTE

WEN

DD

C15:12

C7:0

GND

Figure. 16 Three device auto EPROM load

14

PDSP16256/A

When the filter length is less than the maximum, the

PDSP16256 will only transfer the correct number of

coefficients, and one or more significant address bits

willremainlow.Sufficientcoefficientsarealwaysloaded

to allow for a possible Bank Swap to occur, and the

EPROM allocation must allow for this even if the

feature is not to be used. Table 5 shows the number of

coefficients loaded for each of the modes.

These coded inputs always correspond to the block

address used for the segment of EPROM allocated to

thatdevice. Code‘allzeros’mustnotbeusedsincethe

Master device has implied use of the bottom segment.

This is necessary since the C11:8 pins are alterna-

tively used on the Master device to define the number

of devices supported by the EPROM.

In addition to providing the most significant addresses

to the EPROM, the C15:12 address outputs from the

masterdevicemustalsodrivetheC15:12inputsonthe

slave devices. These C15:12 inputs are internally

compared to the C11:8 inputs to decide if that device

is currently to be loaded. This approach avoids the

If several devices are cascaded, only one device

assumestheroleoftheMasterbyhavingits

EPROM

grounded. It produces a

signal for the other de-

WEN

vices,plusfourhigherorderaddressoutputsonC15:12,

see Fig. 16. The extra address bits on C15:12 define

separate areas of EPROM, containing coefficients for

up to fifteen additional devices. The least significant

block of memory must always be allocated to the

Master device. The additional devices need not in

practice be all part of the same cascaded chain, but

can consist of several independent filters. They must,

CS

need for external decoders and makes the

input

redundant. This input, however, must be tied low on

every device in an EPROM supported system.

The Control Coefficient pin (CCS) is used to define

whenthecontrolregisteristobeloaded.Itbecomesan

outputontheMasterdevicewhichprovidesanEPROM

address bit next in significance above A7:0, and also

drivestheCCSinputsontheslavedevices.Thisoutput

is high for the first two EPROM transfers in order to

access the control information, and then remains low

whilstthecoefficientsareloaded. Thiscontrolinforma-

tionisthusnotstoredadjacenttothecoefficientswithin

the EPROM, and in fact the EPROM must provide

twice the storage necessary to contain the coefficients

alone. All but two of the bytes in the additional half are

redundant. See Fig.17 for the EPROM memory map.

however, all havetheir

pins tied low. FRUN can

BYTE

still be used to start these independent filters after all

the devices have been loaded. In this case, however,

eachslaveFENpinshouldbedrivenbyDFENfromthe

master device.

WhenoneEPROMissupplyinginformationforseveral

devices, some means of selectively enabling each

additional device must be provided. This is achieved

by using the C11:8 pins on the slave devices as binary

coded inputs to define one to fifteen extra devices.

COEFFICIENTS

PER DEVICE

Control

Register

Number of

Coefficients

Loaded

32

64

128

14 13 12

255

511

1023

NOT USED

0

1

0

1

0

1

0

1

0

1

0

1

0

1

32

64

128

194

193

192

191

386

385

384

383

770

769

768

767

CONTROL REG

DEVICE 2

FILTER

COEFFICIENTS

128

127

256

255

512

511

Invalid Mode

NOT USED

Table 5. Number of coefficients loaded

66

65

64

63

130

129

128

127

258

257

256

255

NOTE:

The EPROM memory map assumes that, for the 32 and 64

coefficient per device options, the unused address pins are

unconnected. If all address pins are connected as shown in

Fig. 16 then the 128 coefficients per device memory map

columnshouldbeused.Onlythosecoefficientsrequiredwillbe

read,hencetheupperportionsofthecoefficientaddressspace

will be ignored.

CONTROL REG

DEVICE 1

FILTER

COEFFICIENTS

0

Figure. 17 EPROM Memory Map

15

PDSP16256/A

Using a Remote Master

When a remote master is used to load

The address and coefficient buses plus

the and signals must all meet the specified

coefficients,

must be tied high and a

EPROM

WEN

CS

conventional peripheral interface is then provided. It

is not possible, however, to read coefficients already

stored. The master supplies an address and data

bus, and writes to the PDSP16256 occur under the

set up and hold times with respect to the system

clock, see Fig 20 and Switching Characteristics.

This synchronous interface is optimum for the

majority of high end applications, when individual

coefficients must be updated at sample clock rates.

However, if the coefficients are to be loaded under

software control from a general purpose

control of synchronous

and

inputs. The

WEN

CS

CoefficientControlRegisterpin(CCS)mustbedriven

by a master address line higher in significance than

A7:0. Both the

and

signals must be low for

CS

WEN

microprocessor, the processor’s

will

WRITE STROBE

the load operation to occur. When loading the control

register the signal must be held low for a further 2

cycles, see Fig. 20. Since the internal write operation

is actually performed with the system clock, it is

necessary for the clock to be present during the

transfer.

probably be asynchronous with the SCLK clock

used by the PDSP16256. In this case external

synchronising logic is needed, as shown in Fig.18.

CS

Fig. 19 shows the recommended loading sequence

andfilteroperationinitiation.Thesimplesttechnique

is to reset the device prior to loading a set of

coefficients.CoefficientsmaybeloadedonceBUSY

The

input defines whether coefficients are

BYTE

loaded as a single 16 bit word or two 8-bit bytes. The

latter saves on connections to the remote master.

Address bits A7:0 are used in byte mode. 16-bit word

mode uses bits A6:0, A7 being redundant. When

writing in byte mode the least significant byte (A0 = 0)

must be written first followed by the most significant

byte (A0 = 1).

returns low or 22 cycles after

is taken high.

RES

When loading a device from a remote master the

control register must be loaded first followed by the

filtercoefficients. Fig. 19showstherequiredloading

sequence, two examples are given one for byte

mode the other for word mode. A gap of at least one

cycle must be left after loading the control register

before loading the first coefficient.

InbytemodetheinternalcomparisonbetweenC15:12

andC11:8ismade,regardlessofthestateof

.

EPROM

ForthisreasonpinsC15:8shouldallbetiedlowwhen

a remote master is used with byte transfers. This

ensures that the internal comparison gives equality

and allows the load operation to occur.

Filter operations are started by presenting the first

data word at the same time as raising signal FEN;

FRUN should always be low.

16

PDSP16256/A

SCLK

COEFFICIENT

LOAD

STATE MACHINE

D

Q

WEN

PROCESSOR WRITE STROBE

PDSP

16256

HOLD

CIRCUIT

A7:0

C15:0

ADDRESS

DATA

STROBE

REGISTERED

INTO STATE

MACHINE

COEFFICIENT

REGISTERED INTO

SYNCHRONISATION

REGISTER

INPUT CLOCKED

TO PDSP16256 ON

THIS EDGE

SCLK

PROCESSOR WRITE STROBE

REGISTERED STROBE

PDSP16256 WEN

ADDRESS/DATA

A7:0/C15:0

ADDRESS AND DATA VALID

A7:0 AND C15:0 HELD AFTER FALLING EDGE OF WRITE STROBE

Figure. 18 Remote Master synchronisation

17

PDSP16256/A

DEVICE RESET

1

2

3

4

5

6

7

16 17

37

38

39

SCLK

RES

BUSY

RES must be held low

for 16 cycles

BUSY goes active

Coefficient loading may start

once BUSY has returned low

BYTE WIDE COEFFICIENT LOAD

1

2

3

4

5

6

7

8

67

68

69

70

71

SCLK

CCS

A7:0

00

01

00

10

01

00

02

20

03

00

3E

3F

AC

00

02

C15:0

CS

WEN

Control register loaded Blank cycles Coefficients loaded into the required address location. CS must be maintained

with CCS high This example uses byte wide loading (BYTE held low). for two cycles

WORD WIDE COEFFICIENT LOAD

1

2

3

4

5

6

7

8

34

35

36

37

38

SCLK

CCS

A7:0

00

01

02

03

04

1E

1F

AC00

0010 0020 0030 0040 0050

001F 0200

C15:0

CS

WEN

Control register loaded Blank cycles Coefficients loaded into the required address location.

with CCS high This example uses word wide loading (BYTE held high).

START OF FILTER OPERATION

1

2

3

4

5

6

7

8

9

16

17

18

19

SCLK

FEN

DA15:0

0010

0020

0030

0040

0050

0090

00A0

0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

0001 0001 0004 0004

F31:0

CLKOP

The first data sample

is read as FEN goes high

The first result available. CLKOP

indicates the first active result cycle

Figure. 19 Device startup timing diagrams

18

PDSP16256/A

Control Register

The control register is double buffered. This allows

the writing of a new control word without affecting the

current operation of the device. To activate the new

control register after it has been written to the device

the bank swap signal must be toggled. After a reset

the active control register is loaded directly and bank

swap need not be used.

The internal operation of the PDSP16256 is

controlled by the status of a 16-bit control register. In

the dual filter modes both networks are controlled by

the same register. The significance of the various

bits are shown in Table 6. Tables 7 and 8 define the

control register bit interdependence for the filter and

bank swapping modes.

Control

Register

Function

Bits

15

4

0

1

0

1

X

Two independent filters

Two filters in cascade

Single Filter

Bits Decode

Function

Dual filter mode

15

0

Table 7 Control register filter mode bits

15

1

Single filter mode

14:13

00

01

10

Sample rate is the system clock

Sample rate is half the system clock

Sample rate is quarter the system

clock

Control

Register

Function

Bits

14:13

12

11

0

Sample rate is eighth the system clock

Output rate equals the input rate

Decimate-by-two

7

6

5

12

1

0

1

X

0

1

X

0

1

Control by input pin

11:10

9:8

7

00

01

10

11

00

0

Intermediate device

Lower bank selected

Upper bank selected

Swap on every sample clock

Interface device

Termination device

Single device

Table 8 Control register bank swap bits

These bits MUST be at logical zero

Bank swap is controlled by input pin

Bank swap is controlled by Bit 6

Lower bank if bit 7 is set

Upper bank if bit 7 is set

This bit must be at logical zero

Two independent filters

7

1

6

0

6

1

5

4

0

1

4

Two filters in cascade

3:0

These bits MUST be at logical zero

Table 6 Control register bit allocation

19

PDSP16256/A

SCLK

t_HS

t_HH

t_HS

t_HH

t_CL

t_CH

t_HH

CCS

CS

CCS

CS

WEN

C15:0

A7:0

WEN

C15:0

A7:0

VALID DATA

VALID ADDRESS

VALID DATA

VALID ADDRESS

(a) Coefficient Write

(b) Control Register Write

Figure. 20 Remote Master setup and hold timings

CLK 1

CLK 2

CLK 9

SCLK

t_CD

VALID ADDRESS

A7:0

VALID ADDRESS

C15:12

CCS

C7:0

t_HSt_HH

Figure. 21 EPROM load timings

SCLK

t_OSt_OH

t_CL

t_CH

t_CD

OEN

t_CZF

t_CVF

HIGH Z

VALID DATA

F31:0

VALID DATA

OUTPUT PINS

t_HSt_HH

INPUT PINS

Figure. 22 Operating timings

20

PDSP16256/A

Electrical Characteristics

The Electrical Characteristics are guaranteed over the following range of operating conditions, unless

otherwise stated:

Commercial: T_AMB= 0°C to+70°C, V_DD= +5V±5%, GND = 0V

IndustriaL: T_AMB= -40°C to +85°C, V_DD= +5V±10%, GND = 0V

Military: T_AMB= -55°C to +125°C, V_DD= +5V±10%, GND = 0V

Static Characteristics

Characteristic

Value

Units

Symbol

Conditions

Min. Typ. Max.

Output high voltage

Output low voltage

V_OH

V_OL

V_IH

V_IL

V_IH

V_IL

I_IN

C_IN

I_OZ

I_OS

2·4

-

3·5

-

2·0

-

210

-

0·4

-

1·0

-

V

I_OH= 4mA

_OH= 4mA

I

Input high voltage (CMOS)

Input low voltage (CMOS)

Input high voltage (TTL)

Input low voltage (TTL)

Input leakage current

Input capacitance

SCLK input only

All other inputs

GND < V_IN< V_DD

0·8

110

V

µA

pF

µA

mA

10

Output leakage current

Output short circuit current

250

10

150

300

GND < V_OUT< V_DD

V_DD= 15·5V

Switching Characteristics (see Figs. 20, 21 and 22)

Commercial Industrial

Military

Units

Characteristic

Symbol

Conditions

Min. Max.

Max.

Min.

Input signal setup to clock rising edge

Input signal hold after clock rising edge

t_HS

t_HH

8

4

-

8

4

-

ns

8

4

-

OEN

t_OS

-

26

25

-

20

4

5

-

28

20

-

set up to clock rising edge

hold after clock rising edge

20

4

5

20

4

5

-

28

20

-

ns

MHz

ns

mA

t_OH

t_CD

f_SCLK

t_CH

Clock rising edge to output signal valid

Clock frequency

Clock high time

Clock low time

Clock to data valid F bus from high impedance

Clock to data high impedance F bus

30pF

-

20

12

-

18

11

-

20

12

-

t_CL

-

t_CVF

t_CZF

I_DD

30

400

30

380

30

380

See Fig. 23

See Note 1

-

V_DDcurrent

NOTE 1. V_DD= 15·5V, outputs unloaded, clock frequency = Max.

21

PDSP16256/A

Test

Waveform measurement level

Delay from

output high

to output

V

H

0·5V

I

OL

high impedance

Delay from

output low

0·5V

to output

V

L

high impedance

1·5V

DUT

30pF

Delay from

output high

impedance to

output low

1·5V

Delay from

output high

impedance to

output high

I

OH

0·5V

1·5V

Three state delay measurement load

V_His the voltage reached when the output is driven high

VL is the voltage reached when the output is driven low

Figure. 23 Three state delay measurement

Absolute Maximum Ratings (Note 1)

PDSP16256 MC AC1R and PDSP16256 MC GC1R

(MIL-STD-883 PARTS)

20·5V to 17·0V

Supply voltage, V_DD

Polyimide is used as an inter-layer dielectric as

glassification. Polymeric material meeting the

requirements of MIL-STD-883 test method 5011 is used

for die attach.

20·5V to V_DD10·5V

Input voltage, V_IN

Output voltage, V_OUT

18mA

500V

265°C to1150°C

Clamp diode current per pin, I_K(see note 2)

Static discharge voltage (HBM)

Storage temperature, T_S

Maximum junction temperature, T_JMAX

Commercial grade

Life tesst/burn-in connections are given in Tables 9 and

10 on the following pages.

1100°C

1110°C

1150°C

3000mW

Industrial grade

Military grade

Change Notification

Package power dissipation

Thermal resistance, Junction-to-Case, θ_JC

5°C/W

ThechangenotificationrequirementsofMIL-PRF-38535

will be implemented on MIL-STD-883 grade devices.

Known customers will be notified of any changes since

the last buy when ordering further parts if significant

changes have been made.

NOTES

1. Exceeding these ratings may cause permanent

damage. Functional operation under these conditions

is not implied.

2. Maximum dissipation should not be exceeded for

more than 1 second, only one output to be tested at

any one time.

Rev.

Date

A

B

C

D

MAR 1993 SEPT 1995 JAN 1998 AUG 1998

3. Exposure to absolute maximum ratings for extended

periods may affect device reliablity.

4. Current is defined as negative into the device.

5. The θ_JCdata assumes that heat is extracted from the

top of the package.

6. Maximum junction temperature, T_JMAX, is specified

with power applied.

22

PDSP16256/A

Voltage

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

C1

C2

C3

C4

C5

C6

C7

N/C

0V/180k

15·0V

C8

C9

15·0V/180k

0V

H14

H15

J1

J2

J3

J13

J14

J15

K1

K2

K3

K13

K14

K15

L1

L2

L3

L13

L14

L15

M1

M2

M3

M13

M14

M15

N1

N/C

0V

0V/180k

N/C

0V

0V/180k

N/C

15·0V

RESET

N/C

CLOCK

15·0V

0V

N12

N13

N14

N15

P1

P2

P3

P4

P5

P6

P7

P8

P9

P10

P11

P12

P13

P14

P15

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

15·0V

N/C

C10

C11

C12

C13

C14

C15

D1

D2

D3

D4

D13

D14

D15

E1

E2

E3

E13

E14

E15

F1

F2

F3

F13

F14

F15

G1

G2

G3

G13

G14

G15

H1

H2

H3

N/C

15·0V/180k

15·0V

0V

N/C

15·0V

N/C

0V/180k

0V

15·0V/180k

N/C

0V

15·0V

0V

N/C

0V

N/C

0V/180k

15·0V

0V

N/C

0V/180k

15·0V/180k

N/C

0V/180k

N/C

0V

15·0V

0V

15·0V

0V

15·0V

N/C

N2

N3

N4

N5

N6

N7

N8

N9

15·0V

15·0V/180k

15·0V

0V

N/C

15·0V

15·0V/180k

N/C

0V

15·0V

0V

N10

N11

H13

0V

Table 9 Life test/burn-in connections for PDSP16256 MC AC1R (PGA). NOTE: PDA is 5% and based on

groups 1 and 7

23

PDSP16256/A

Voltage

1

2

3

4

5

6

7

8

N/C

15·0V

N/C

0V

N/C

0V

N/C

15·0V

N/C

15·0V

N/C

0V

N/C

0V

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

15·0V

0V

15·0V

N/C

15·0V

0V

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

15·0V/180k

0V

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

158

159

160

161

162

163

164

165

166

167

168

169

170

171

172

0V

N/C

0V/180k

15·0V

0V

15·0V

0V

0V/180k

0V

0V/180k

15·0V

0V/180k

0V

0V/180k

15·0V/180k

0V

15·0V

RESET

CLOCK

0V

15·0V

0V/180k

15·0V

15·0V/180k

0V

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

0V

15·0V

0V

15·0V

0V

15·0V/180k

N/C

0V

N/C

15·0V

N/C

0V

15·0V/180k

15·0V

15·0V/180k

0V

N/C

15·0V

0V

15·0V

15·0V/180k

15·0V

0V

15·0V/180k

15·0V

N/C

15·0V

0V/180k

0V

Table 10 Life test/burn-in connections for PDSP16256 MC GC1R (QFP). NOTE: PDA is 5% and based on

groups 1 and 7

24


型号：	PDSP16510A
厂家：	ZARLINK SEMICONDUCTOR INC
描述：	Programmable FIR Filter 可编程FIR滤波器
文件：	总25页 (文件大小：205K)
中文：	中文翻译
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PDSP16510A [ZARLINK]

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