MT9172AN [ZARLINK]
ISO2-CMOS ST-BUS FAMILY; ISO2 -CMOS ST- BUS系列
| 型号： | MT9172AN |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | ISO2-CMOS ST-BUS FAMILY |
| 文件： | 总25页 (文件大小：403K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO2-CMOS ST-BUS FAMILY MT9171/72
Digital Subscriber Interface Circuit
Digital Network Interface Circuit
DS5130
ISSUE 3
February 1999
Features
Ordering Information
•
Full duplex transmission over a single twisted
pair
MT9171AE
MT9171AN
MT9171AP
MT9172AE
MT9172AN
MT9172AP
22 Pin Plastic DIP (400 mil)
24 Pin SSOP
28 Pin PLCC
22 Pin Plastic DIP (400 mil)
24 Pin SSOP
28 Pin PLCC
•
•
•
•
•
•
•
•
Selectable 80 or 160 kbit/s line rate
Adaptive echo cancellation
Up to 3km (9171) and 4 km (9172)
ISDN compatible (2B+D) data format
Transparent modem capability
Frame synchronization and clock extraction
Zarlink ST-BUS compatible
-40°C to +85°C
Description
The MT9171 (DSIC) and MT9172 (DNIC) are pin for
pin compatible replacements for the MT8971 and
MT8972, respectively. They are multi-function
devices capable of providing high speed, full duplex
digital transmission up to 160 kbit/s over a twisted
Low power (typically 50 mW), single 5V supply
Applications
wire pair.
They use adaptive echo-cancelling
techniques and transfer data in (2B+D) format
compatible to the ISDN basic rate. Several modes of
operation allow an easy interface to digital
telecommunication networks including use as a high
speed limited distance modem with data rates up to
160 kbit/s. Both devices function identically but with
the DSIC having a shorter maximum loop reach
specification. The generic "DNIC" will be used to
reference both devices unless otherwise noted.
•
•
Digital subscriber lines
High speed data transmission over twisted
wires
•
•
Digital PABX line cards and telephone sets
80 or 160 kbit/s single chip modem
2
The MT9171/72 is fabricated in Zarlink’s ISO -
CMOS process.
DSTi/Di
L
Differentially
Encoded Biphase
Transmitter
Transmit
Filter &
Line Driver
OUT
Transmit
Interface
Prescrambler
Scrambler
CDSTi/
CDi
L
OUT
DIS
V
Bias
Control
Transmit
Address
Echo Canceller
Error
Signal
Register
Timing
F0/CLD
MUX
Master Clock
Phase Locked
Precan
C4/TCK
F0o/RCK
MS0
Echo Estimate
Transmit/
Clock
Receive
Timing &
Control
—
+
-1
Receive
Filter
DPLL
∑
MS1
+2
L
IN
MS2
Sync Detect
Receive
RegC
Status
OSC2
OSC1
DSTo/Do
Differentially
Encoded Biphase
Receiver
De-
Prescrambler
Receive
Interface
Descrambler
CDSTo/
CDo
V
V
V
V
DD
SS
Bias Ref
Figure 1 - Functional Block Diagram
9-115
MT9171/72
Advance Information
22
21
20
19
18
17
16
15
14
13
12
1
2
3
4
5
6
7
8
LOUT
VBias
VRef
MS2
MS1
MS0
VDD
LIN
TEST
LOUT DIS
Precan
OSC1
OSC2
C4/TCK
F0o/RCK
DSTi/Di
•
NC
5
25
24
23
22
21
20
19
MS2
NC
MS1
MS0
RegC
LOUT DIS
Precan
OSC1
OSC2
NC
6
7
RegC
8
9
F0/CLD
CDSTi/CDi
CDSTo/CDo
VSS
10
11
9
10
11
F0/CLD
NC
C4/TCK
DSTo/Do
22 PIN PDIP
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
LOUT
VDD
LIN
TEST
LOUT DIS
Precan
OSC1
NC
VBias
VRef
MS2
MS1
MS0
RegC
NC
28 PIN PLCC
OSC2
9
C4/TCK
F0o/RCK
DSTi/Di
F0/CLD
CDSTi/CDi
CDSTo/CDo
VSS
10
11
12
DSTo/Do
24 PIN SSOP
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
Line Out. Transmit Signal output (Analog). Referenced to VBias.
22
24
28
1
2
3
1
2
3
2
3
4
LOUT
VBias
VRef
Internal Bias Voltage output. Connect via 0.33 µF decoupling capacitor to VDD.
Internal Reference Voltage output. Connect via 0.33 µF decoupling capacitor to
VDD.
4,5, 4,5,
5,7, MS2-MS0 Mode Select inputs (Digital). The logic levels present on these pins select the
6
7
8
6
7
9
8
various operating modes for a particular application. See Table 1 for the
operating modes.
9
RegC
Regulator Control output (Digital). A 512 kHz clock used for switch mode power
supplies. Unused in MAS/MOD mode and should be left open circuit.
10
F0/CLD Frame Pulse/C-Channel Load (Digital). In DN mode a 244 ns wide negative
pulse input for the MASTER indicating the start of the active channel times of the
device. Output for the SLAVE indicating the start of the active channel times of
the device. Output in MOD mode providing a pulse indicating the start of the C-
channel.
9
10
11
12
13
CDSTi/ Control/Data ST-BUS In/Control/Data In (Digital). A 2.048 Mbit/s serial control
CDi
& signalling input in DN mode. In MOD mode this is a continuous bit stream at
the bit rate selected.
10
CDSTo/ Control/Data ST-BUS Out/Control/Data Out (Digital). A 2.048 Mbit/s serial
CDo
control & signalling output in DN mode. In MOD mode this is a continuous bit
stream at the bit rate selected.
11
12
12
13
14
15
VSS
Negative Power Supply (0V).
DSTo/Do Data ST-BUS Out/Data Out (Digital). A 2.048 Mbit/s serial PCM/data output in
DN mode. In MOD mode this is a continuous bit stream at the bit rate selected.
9-116
Advance Information
MT9171/72
Pin Description (continued)
Pin #
Name
Description
22
24
28
13
14
16
DSTi/Di Data ST-BUS In/Data In (Digital). A 2.048 Mbit/s serial PCM/data input in DN
mode. In MOD mode this is a continuous bit stream at the bit rate selected.
14
15
15
16
17
19
F0o/RCK Frame Pulse Out/Receive Bit Rate Clock output (Digital). In DN mode a 244 ns
wide negative pulse indicating the end of the active channel times of the device to
allow daisy chaining. In MOD mode provides the receive bit rate clock to the
system.
C4/TCK Data Clock/Transmit Baud Rate Clock (Digital). A 4.096 MHz TTL compatible
clock input for the MASTER and output for the SLAVE in DN mode. For MOD
mode this pin provides the transmit bit rate clock to the system.
16
17
17
19
21
22
OSC2 Oscillator Output. CMOS Output.
OSC1 Oscillator Input. CMOS Input. D.C. couple signals to this pin. Refer to D.C.
Electrical Characteristics for OSC1 input requirements.
18
20
23
Precan Precanceller Disable. When held to Logic ’1’, the internal path from LOUT to the
precanceller is forced to VBias thus bypassing the precanceller section. When
logic ’0’, the LOUT to the precanceller path is enabled and functions normally. An
internal pulldown (50 kΩ) is provided on this pin.
8,
18
1,6,
11,
18,
20,
25
NC
No Connection. Leave open circuit
19
21
24
LOUT DIS LOUT Disable. When held to logic “1”, LOUT is disabled (i.e., output = VBias). When
logic “0”, LOUT functions normally. An internal pulldown (50 kΩ) is provided on this
pin.
20
21
22
22
23
24
26
27
28
TEST
LIN
Test Pin. Connect to VSS.
Receive Signal input (Analog).
VDD
Positive Power Supply (+5V) input.
9-117
MT9171/72
Advance Information
F0
C4
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
B1
DSTi
DSTo
F0o
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
7
B1
7
Channel Time 0
Figure 3 - DV Port - 80 kbit/s (Modes 2, 3, 6)
F0
C4
B1
B1
DSTi
B1 B1 B1 B1 B1 B1 B1 B1
B2 B2 B2 B2 B2 B2 B2 B2
7 6 5 4 3 2 1
7
7
6
5
4
3
2
1
0
0
0
0
DSTo
F0o
B1 B1 B1 B1 B1 B1 B1 B1
B2 B2 B2 B2 B2 B2 B2 B2
7 6 5 4 3 2 1
7
7
6
5
4
3
2
1
Channel Time 0
Channel Time 16
Figure 4 - DV Port - 160 kbit/s (Modes 2, 3, 6)
9-118
Advance Information
MT9171/72
transmission is made possible through on board
adaptive echo cancellation.
Functional Description
The MT9171/72 is a device which may be used in
practically any application that requires high speed
data transmission over two wires, including smart
telephone sets, workstations, data terminals and
computers. The device supports the 2B+D channel
format (two 64 kbit/s B-channels and one 16 kbit/s D-
channel) over two wires as recommended by the
CCITT. The line data is converted to and from the ST-
BUS format on the system side of the network to
allow for easy interfacing with other components
such as the S-interface device in an NT1
arrangement, or to digital PABX components.
The DNIC has various modes of operation which are
selected through the mode select pins MS0-2. The
two major modes of operation are the MODEM
(MOD) and DIGITAL NETWORK (DN) modes. MOD
mode is a transparent 80 or 160 kbit/s modem. In
DN mode the line carries the B and D channels
formatted for the ISDN at either 80 or 160 kbit/s. In
the DN mode the DV and CD ports are standard ST-
BUS and in MOD mode they are transparent serial
data streams at 80 or 160 kbit/s. Other modes
include: MASTER (MAS) or SLAVE (SLV) mode,
where the timebase and frame synchronization are
provided externally or are extracted from the line and
DUAL or SINGLE (SINGL) port modes, where both
the DV and CD ports are active or where the CD port
is inactive and all information is passed through the
DV port. For a detailed description of the modes see
“Operating Modes” section.
Smart telephone sets with data and voice capability
can be easily implemented using the MT9171/72 as
a line interface. The device’s high bandwidth and
long loop length capability allows its use in a wide
variety of sets. This can be extended to provide full
data and voice capability to the private subscriber by
the installation of equipment in both the home and
central office or remote concentration equipment.
Within the subscriber equipment the MT9171/72
would terminate the line and encode/ decode the
data and voice for transmission while additional
electronics could provide interfaces for a standard
telephone set and any number of data ports
supporting standard data rates for such things as
computer communications and telemetry for remote
meter reading. Digital workstations with a high
degree of networking capability can be designed
using the DNIC for the line interface, offering up to
160 kbit/s data transmission over existing telephone
lines. The MT9171/72 could also be valuable within
existing computer networks for connecting a large
In DIGITAL NETWORK (DN) mode there are three
channels transferred by the DV and CD ports. They
are the B, C and D channels. The B1 and B2
channels each have a bandwidth of 64 kbit/s and are
used for carrying PCM encoded voice or data. These
channels are always transmitted and received
through the DV port (Figures 3, 4, 5, 6). The C-
channel, having a bandwidth of 64 kbit/s, provides a
means for the system to control the DNIC and for the
DNIC to pass status information back to the system.
The C-channel has a Housekeeping (HK) bit which is
the only bit of the C-channel transmitted and
received on the line. The 2B+D channel bits and the
HK bit are double-buffered. The D-channel can be
transmitted or received on the line with either an 8,
16 or 64 kbit/s bandwidth depending on the DNIC’s
mode of operation. Both the HK bit and the D-
channel can be used for end-to-end signalling or low
speed data transfer. In DUAL port mode the C and D
channels are accessed via the CD port (Figure 7)
while in SINGL port mode they are transferred
through the DV port (Figures 5, 6) along with the B1
and B2 channels.
number of terminals to
a
computer or for
intercomputer links. With the DNIC, this can be
accomplished at up to 160 kbit/s at a very low cost
per line for terminal to computer links and in many
cases this bandwidth would be sufficient for
computer to computer links.
Figure 1 shows the block diagram of the MT9171/72.
The DNIC provides a bidirectional interface between
the DV (data/voice) port and a full duplex line
operating at 80 or 160 kbit/s over a single pair of
twisted wires. The DNIC has three serial ports. The
DV port (DSTi/Di, DSTo/Do), the CD (control/data)
port (CDSTi/CDi, CDSTo/CDo) and a line port (LIN,
LOUT). The data on the line is made up of information
from the DV and CD ports. The DNIC must combine
information received from both the DV and CD ports
and put it onto the line. At the same time, the data
received from the line must be split into the various
channels and directed to the proper ports. The
usable data rates are 72 and 144 kbit/s as required
for the basic rate interface in ISDN. Full duplex
9-119
MT9171/72
Advance Information
9-120
Advance Information
MT9171/72
In DIGITAL NETWORK (DN) mode, upon entering
the DNIC from the DV and CD ports, the B-channel
data, D-channel D0 (and D1 for 160 kbit/s), the HK
bit of the C-channel (160kbit/s only) and a SYNC bit
are combined in a serial format to be sent out on the
line by the Transmit Interface (Figures 11, 12). The
SYNC bit produces an alternating 1-0 pattern each
frame in order for the remote end to extract the frame
alignment from the line. It is possible for the remote
end to lock on to a data bit pattern which simulates
this alternating 1-0 pattern that is not the true
SYNC. To decrease the probability of this happening
the DNIC may be programmed to put the data
through a prescrambler that scrambles the data
according to a predetermined polynomial with
respect to the SYNC bit. This greatly decreases the
probability that the SYNC pattern can be reproduced
by any data on the line. In order for the echo
canceller to function correctly, a dedicated scrambler
is used with a scrambling algorithm which is different
for the SLV and MAS modes. These algorithms are
calculated in such a way as to provide orthogonality
between the near and far end data streams such that
the correlation between the two signals is very low.
For any two DNICs on a link, one must be in SLV
mode with the other in MAS mode. The scrambled
data is differentially encoded which serves to make
the data on the line polarity-independent. It is then
biphase encoded as shown in Figure 10. See “Line
Interface” section for more details on the encoding.
Before leaving the DNIC the differentially encoded
biphase data is passed through a pulse-shaping
bandpass transmit filter that filters out the high and
low frequency components and conditions the signal
for transmission on the line.
The composite transmit and receive signal is
received at LIN. On entering the DNIC this signal
passes through a Precanceller which is a summing
amplifier and lowpass filter that partially cancels the
near-end signal and provides first order antialiasing
for the received signal. Internal, partial cancellation
F0
C4
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
C
C
CDSTo
0
1
2
2
3
4
5
5
6
7
0
1
2
3
3
4
5
6
6
7
0
0
CDSTi
F0o
0
1
3
4
6
7
0
1
2
4
5
7
3.9 µsec
62.5 µsec
125 µsec
Channel Time 0
Channel Time 16
Figure 7 - CD Port (Modes 2,6)
CLD
TCK
CDi
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
6
6
7
7
0
0
1
2
3
3
4
4
5
6
7
0
0
1
C
C
CDo
1
2
5
6
7
1
Figure 8 - CD Port (Modes 1,5)
9-121
MT9171/72
Advance Information
of the near end signal may be disabled by holding
the Precan pin high. This mode simplifies the design
of external line transceivers used for loop extension
applications. The Precan pin features an internal
pull-down which allows this pin to be left
unconnected in applications where this function is
not required. The resultant signal passes through
a receive filter to bandlimit and equalize it. At this
point, the echo estimate from the echo canceller is
subtracted from the precancelled received signal.
This difference signal is then input to the echo
canceller as an error signal and also squared up by a
comparator and passed to the biphase receiver.
Within the echo canceller, the sign of this error signal
is determined. Depending on the sign, the echo
estimate is either incremented or decremented and
this new estimate is stored back in RAM.
DNIC in the chain receives the system F0 with
the following devices receiving its predecessor’s F0o.
In MOD mode, all the ports have a different format.
The line port again operates at 80 or 160 kbit/s,
however, there is no synchronization overhead, only
transparent data. The DV and CD ports carry serial
data at 80 or 160 kbit/s with the DV port transferring
all the data for the line and the CD port carrying the
C-channel only. In this mode the transfer of data at
both ports is synchronized to the TCK and RCK
clocks for transmit and receive data, respectively.
The CLD signal goes low to indicate the start of the
C-channel data on the CD port. It is used to load
and latch the input and output C-channel but has no
relationship to the data on the DV port.
The timebase in both SLV and MAS modes
(generated internally in SLV mode and externally in
MAS mode) is phase-locked to the received data
Operating Modes (MS0-2)
stream.
This phase-locked clock operates the
The logic levels present on the mode select pins
MS0, MS1 and MS2 program the DNIC for different
operating modes and configure the DV and CD ports
Biphase Decoder, Descrambler and Deprescrambler
in MAS mode and the entire chip in SLV mode. The
Biphase Decoder decodes the received encoded bit
stream resulting in the original NRZ data which is
passed onto the Descrambler and Deprescrambler
where the data is restored to its original content by
performing the reverse polynomials. The SYNC bits
are extracted and the Receive Interface separates
the channels and outputs them to the proper ports in
the proper channel times. The destination of the
various channels is the same as that received on the
input DV and CD ports.
accordingly.
Table
1
shows the modes
corresponding to the state of MS0-2. These pins
select the DNIC to operate as a MASTER or SLAVE,
in DUAL or SINGLE port operation, in MODEM or
DIGITAL NETWORK mode and the order of the C
and D channels on the CD port. Table 2 provides a
description of each mode and Table 3 gives a pin
configuration according to the mode selected for all
pins that have variable functions. These functions
vary depending on whether it is in MAS or SLV, and
whether DN or MOD mode is used.
The Transmit/Receive Timing and Control block
generates all the clocks for the transmit and receive
functions and controls the entire chip according to
the control register. In order that more than one
DNIC may be connected to the same DV and
CD ports an F0o signal is generated which signals
the next device in a daisy chain that its channel times
are now active. In this arrangement only the first
The overall mode of operation of the DNIC can be
programmed to be either a baseband modem
(MOD mode) or a digital network transceiver (DN
mode). As a baseband modem, transmit/receive
data is passed transparently through the device at 80
or 160 kbit/s by the DV port. The CD port transfers
Mode Select Pins
Mode
Operating Mode
MS2 MS1
MS0
SLV
MAS
E
DUAL SINGL MOD
DN
D-C
E
C-D
ODE
E
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
E
E
E
E
E
E
E
E
X
X
E
E
E
E
E
E
E
E
E
E
X
E
E
E
E
E
E
E
E
E
X
E
E
E
E
E
E
E
Table 1. Mode Select Pins
E=Enabled
X=Not Applicable
Blanks are disabled
9-122
Advance Information
MT9171/72
the C-channel and D-Channel also at 80 or 160
kbit/s.
on the line. Due to jitter and end to end delay, one
end must be the master to generate all the timing for
the link and the other must extract the timing from
the receive data and synchronize itself to this timing
in order to recover the synchronous data. DUAL port
mode allows the user to use two separate serial
busses: the DV port for PCM/data (B channels) and
the CD port for control and signalling information (C
and D channels). In the SINGL port mode, all four
channels are concatenated into one serial stream
and input to the DNIC via the DV port. The order of
the C and D channels may be changed only in DN/
DUAL mode. The DNIC may be configured to transfer
the D-channel in channel 0 and the C-channel in
In DN mode, both the DV and CD ports operate as
ST-BUS streams at 2.048 Mbit/s. The DV port
transfers data over pins DSTi and DSTo while on the
CD port, the CDSTi and CDSTo pins are used. The
SINGL port option only exists in DN mode.
In MOD mode, DUAL port operation must be used
and the D, B1 and B2 channel designations no
longer exist. The selection of SLV or MAS will
determine which of the DNICs is using the externally
supplied clock and which is phase locking to the data
Mode
Function
SLAVE - The chip timebase is extracted from the received line data and the external 10.24 MHz
crystal is phase locked to it to provide clocks for the entire device and are output for the external
system to synchronize to.
SLV
MASTER - The timebase is derived from the externally supplied data clocks and 10.24 MHz clock
which must be frequency locked. The transmit data is synchronized to the system timing with the
receive data recovered by a clock extracted from the receive data and resynchronized to the system
timing.
MAS
DUAL PORT - Both the CD and DV ports are active with the CD port transferring the C&D channels
and the DV port transferring the B1& B2 channels.
DUAL
SINGLE PORT - The B1& B2, C and D channels are all transferred through the DV port. The CD
port is disabled and CDSTi should be pulled high.
SINGL
MODEM - Baseband operation at 80 or 160 kbits/s. The line data is received and transmitted
through the DV port at the baud rate selected. The C-channel is transferred through the CD port
also at the baud rate and is synchronized to the CLD output.
MOD
DN
DIGITAL NETWORK - Intended for use in the digital network with the DV and CD ports operating at
2.048 Mbits/s and the line at 80 or 160 kbits/s configured according to the applicable ISDN
recommendation.
D-C
C-D
D BEFORE C-CHANNEL - The D-channel is transferred before the C-channel following F0.
C BEFORE D-CHANNEL - The C-channel is transferred before the D-channel following F0.
OUTPUT DATA ENABLE - When mode 7 is selected, the DV and CD ports are put in high
impedance state. This is intended for power-up reset to avoid bus contention and possible damage
to the device during the initial random state in a daisy chain configuration of DNICs. In all the other
modes of operation DV and CD ports are enabled during the appropriate channel times.
ODE
Table 2. Mode Definitions
F0/CLD
Input/Output
F0o/RCK
Input/Output
C4/TCK
Input/Output
Mode
#
Name
Name
Name
0
1
2
3
4
5
6
7
F0
CLD
F0
Input
Output
Input
F0o
RCK
F0o
F0o
F0o
RCK
F0o
F0o
Output
Output
Output
Output
Output
Output
Output
Output
C4
TCK
C4
Input
Output
Input
F0
Input
C4
Input
F0
Output
Output
Output
Input
C4
Output
Output
Output
Input
CLD
F0
TCK
C4
F0
C4
Table 3. Pin Configurations
9-123
MT9171/72
Advance Information
channel 16 or vice versa. One other feature exists;
ODE, where both the DV and CD ports are tristated
in order that no devices are damaged due to
excessive loading while all DNICs are in a random
state on power up in a daisy chain arrangement.
In order for more than one DNIC to be connected to
any one DV and CD port, making more efficient use
of the busses, the DSTo and CDSTo outputs are put
into high impedance during the inactive channel
times of the DNIC. This allows additional DNICs to
be cascaded onto the same DV and CD ports. When
used in this way a signal called F0o is used as an
indication to the next DNIC in a daisy chain that its
channel time is now active. Only the first DNIC in the
chain receives the system frame pulse and all
others receive the F0o from its predecessor in
DV Port (DSTi/Di, DSTo/Do)
The DV port transfers data or PCM encoded voice to
and from the line according to the particular mode
selected by the mode select pins. The modes
affecting the configuration of the DV port are MOD or
DN and DUAL or SINGL. In DN mode the DV port
operates as an ST-BUS at 2.048 Mbit/s with 32, 8 bit
channels per frame as shown in Figure 9. In this
mode the DV port channel configuration depends
upon whether DUAL or SINGL port is selected.
When DUAL port mode is used, the C and D
channels are passed through the CD port and the B1
and B2 channels are passed through the DV port. At
80 kbit/s only one channel of the available 32 at the
DV port is utilized, this being channel 0 which carries
the B1-channel. This is shown in Figure 3. At 160
kbit/s, two channels are used, these being 0 and 16
carrying the B1 and B2 channels, respectively. This
is shown in Figure 4. When SINGL port mode is
used, channels B1, B2, C and D are all passed via
the DV port and the CD port is disabled. See CD port
description for an explanation of the C and D
channels.
the chain.
cascaded.
This allows up to 16 DNICs to be
CD Port (CDSTi/CDi, CDSTo/CDo)
The CD port is a serial bidirectional port used only in
DUAL port mode. It is a means by which the DNIC
receives its control information for things such as
setting the bit rate, enabling internal loopback tests,
sending status information back to the system and
transferring low speed signalling data to and from the
line.
The CD port is composed of the C and D-Channels.
The C-channel is used for transferring control and
status information between the DNIC and the
system. The D-channel is used for sending and
receiving signalling information and lower speed
data between the line and the system. In DN/DUAL
mode the DNIC receives a C-channel on CDSTi
while transmitting a C-channel on CDSTo. Fifteen
channel times later (halfway through the frame) a D-
channel is received on CDSTi while a D-channel is
transmitted on CDSTo. This is shown in Figure 7. The
order of the C and D bytes in DUAL port mode can
be reversed by the mode select pins. See Table 1 for
a listing of the byte orientations.
The D-channel is always passed during channel time
0 followed by the C and B1 channels in channel
times 1 and 2, respectively for 80 kbit/s. See Figure
5. For 160 kbit/s the B2 channel is added and
occupies channel time 3 of the DV port. See Figure
6. For all of the various configurations the bit orders
are shown by the respective diagram. In MOD mode
the DV and CD ports no longer operate at 2.048
Mbits/s but are continuous serial bit streams
operating at the bit rate selected of 80 or 160 kbit/s.
The D-channel exists only in DN mode and may be
used for transferring low speed data or signalling
information over the line at 8, 16 or 64 kbit/s (by
using the DINB feature). The information passes
While in the MOD mode only DUAL port operation
can be used.
F0
125 µsec
Channel Channel
31
Channel
1
Channel
2
Channel Channel
29 30
Channel
31
Channel
0
ST-BUS
• • • • • • • •
0
Most
Significant
Bit (First)
Least
Significant
Bit (Last)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
3.9 µsec
Figure 9 - ST-BUS Format
9-124
Advance Information
MT9171/72
transparently through the DNIC and is transmitted to
or received from the line at the bit rate selected in the
Control Register.
Register (Table 4). If they are 0, 1 the C-channel is
written to the Diagnostics Register (Table 5).
The Diagnostics Register Reset bit (bit 2) of the
Control Register determines the reset state of the
Diagnostics Register. If, on writing to the Control
Register, this bit is set to logic “0”, the Diagnostics
Register will be reset coincident with the frame
pulse. When this bit is logic “1”, the Diagnostics
If the bit rate is 80 kbit/s, only D0 is transmitted and
received. At 160 kbit/s, D0 and D1 are transmitted
and received. When the DINB bit is set in the Control
Register the entire D-channel is transmitted and
received in the B1-channel timeslot.
Register will not be reset.
In order to use the
diagnostic features, the Diagnostics Register must
be continuously written to. The output C-channel
sends status information from the Status Register to
the system along with the received HK bit as shown
in Table 6.
The C-channel is used for transferring control and
status information between the DNIC and the
system. The Control and Diagnostics Registers are
accessed through the C-channel. They contain
information to control the DNIC and carry out the
diagnostics as well as the HK bit to be transmitted on
the line as described in Tables 4 and 5. Bits 0 and 1
of the C-channel select between the Control and
Diagnostics Register. If these bits are 0, 0 then the
C-channel information is written to the Control
In MOD mode, the CD port is no longer an ST-BUS
but is a serial bit stream operating at the bit rate
selected. It continues to transfer the C-channel but
the D-channel and the HK bit no longer exist. DUAL
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Reg Sel-1
Reg Sel-2
DRR
BRS
DINB
PSEN
ATTACK
TxHK
Default Mode Selection (Refer to Table 4a)
Bit
Name
Description
0
1
2
Reg Sel-1
Reg Sel-2
DRR
Register Select-1. Must be set to ’0’ to select the Control Register.
Register Select-2. Must be set to ’0’ to select the Control Register.
Diagnostics Register Reset. Writing a "0" to this bit will cause a diagnostics register reset
to occur coincident with the next frame pulse as in the MT8972A. When this bit is a logic
"1", the Diagnostics Register will not be reset.
3
4
BRS
Bit Rate Select. When set to ’0’ selects 80 kbit/s. When set to ’1’, selects 160 kbit/s.
➀
DINB
D-Channel in B Timeslot. When ’0’, the D-channel bits (D0 or D0 and D1) corresponding
to the selected bit rate (80 or 160 kbit/s) are transmitted during the normal D-channel bit
times. When set to ’1’, the entire D-channel (D0-D7) is transmitted during the B1-channel
timeslot on the line providing a 64 kbit/s D-channel link.
➀
5
6
7
PSEN
Prescrambler/Deprescrambler Enable. When set to ’1’, the data prescrambler and
deprescrambler are enabled. When set to ’0’, the data prescrambler and deprescrambler
are disabled.
➀
ATTACK
Convergence Speedup. When set to ’1’, the echo canceller will converge to the reflection
➀
coefficient much faster. Used on power-up for fast convergence. When ’0’, the echo
canceller will require the normal amount of time to converge to a reflection coefficient.
➀
TxHK
Transmit Housekeeping. When set to ’0’, logic zero is transmitted over the line as
Housekeeping Bit.When set to ’1’, logic one is transmitted over the line as Housekeeping
Bit.
Table 4. Control Register
Notes:
➀
Suggested use of ATTACK:
-At 160 kbit/s full convergence requires 850 ms with ATTACK held high for the first 240 frames or 30 ms.
-At 80 kbit/s full convergence requires 1.75 s with ATTACK held high for the first 480 frames or 60 ms.
When bits 4-7 of the Control Register are all set to one, the DNIC operates in one of the default modes as defined in Table 4a,
depending upon the status of bit-3.
➀
9-125
MT9171/72
Advance Information
C-Channel
(Bit 0-7)
Internal Control Internal Diagnostic
Description
Register
Register
➀
XXX01111
00000000
01000000
Default Mode-1 : Bit rate is 80 kbit/s. ATTACK,
PSEN, DINB, DRR and all diagnostics are disabled.
TxHK=0.
➀
XXX11111
00010000
01000000
Default Mode-2 Bit rate is 160 kbit/s. ATTACK,
PSEN, DINB, DRR and all diagnostics are disabled.
TxHK=0.
Table 4a. Default Mode Selection
Notes:
➀
Default Mode 1 can also be selected by tying CDSTi/CDi pin low when DNIC is operating in dual mode.
Default Mode 2 can also be selected by tying CDSTi/CDi pin high when DNIC is operating in dual mode.
➀
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
Reg Sel-1
Reg Sel-2
Loopback
FUN
PSWAP
DLO
Not Used
Default Mode Selection
(Refer to Table 4a)
Bit
Name
Description
0
1
Reg Sel-1
Reg Sel-2
Loopback
Register Select-1. Must be set to ’0’ to select the Diagnostic Register.
Register Select-2. Must be set to ’1’ to select the Diagnostic Register.
Bit 2 Bit 3
2,3
0
0
1
1
0
1
0
1
All loopback testing functions disabled. Normal operation.
DSTi internally looped back into DSTo for system diagnostics.
➀
LOUT is internally looped back into LIN for system diagnostics.
➀
DSTo is internally looped back into DSTi for end-to-end testing.
➀
4
5
FUN
Force Unsync. When set to ’1’, the DNIC is forced out-of-sync to test the SYNC
recovery circuitry. When set to ’0’, the operation continues in synchronization.
➀
PSWAP
Polynomial Swap.When set to ’1’, the scrambling and descrambling polynomials are
interchanged (use for MAS mode only). When set to ’0’, the polynomials retain their
normal designations.
➀
6
7
DLO
Disable Line Out. When set to ’1’, the signal on LOUT is set set to VBias. When set to
’0’, LOUT pin functions normally.
Not Used
Must be set to ’0’ for normal operation.
Table 5. Diagnostic Register
Notes:
When bits 4-7 of the Diagnostic Register are all set to one, the DNIC operates in one of the default modes as defined in Table 4a,
depending upon the status of bit-3.
➀
➀
➀
Do not use LOUT to LIN loopback in DN/SLV mode.
Do not use DSTo to DSTi loopback in MOD/MAS mode.
port operation must be used in MOD mode. The C-
channel is clocked in and out of the CD port by TCK
and CLD with TCK defining the bits and CLD the
channel boundaries of the data stream as shown in
Figure 8.
The line interface is made up of LOUT and LIN with
LOUT driving the transmit signal onto the line and LIN
receiving the composite transmit and receive signal
from the line. The line code used in the DNIC is
Biphase and is shown in Figure 10. The scrambled
NRZ data is differentially encoded meaning the
previous differential encoded output is XOR’d with
the current data bit which produces the current
output. This is then biphase encoded where
transitions occur midway through the bit cell with a
Line Port (LIN, LOUT
)
9-126
Advance Information
MT9171/72
0
1
2
3
4
5
6
7
SYNC
CHQual
Rx HK
Future Functionality
ID
Status
Name
Function
Register
0
SYNC
Synchronization - When set this bit indicates that synchronization to the received
line data sync pattern has been acquired. For DN mode only.
1-2
CHQual Channel Quality - These bits provide an estimate of the receiver’s margin against
noise. The farther this 2 bit value is from 0 the better the SNR.
3
4-6
7
Rx HK Housekeeping - This bit is the received housekeeping (HK) bit from the far end.
Future Future Functionality. These bits return Logic 1 when read.
ID
This bit provides a hardware identifier for the DNIC revision. The MT9171/72 will
return a logic “0” for this bit. (Logic “1” returned for MT8972A.)
Table 6. Status Register
negative going transition indicating a logic "0" and a
positive going transition indicating a logic "1".
The frame format of the transmit data on the line is
shown in Figures 11 and 12 for the DN mode at 80
and 160 kbit/s. At 80 kbit/s a SYNC bit for frame
recovery, one bit of the D-channel and the B1-
channel are transmitted. At 160 kbit/s a SYNC bit,
the HK bit, two bits of the D-channel and both B1 and
B2 channels are transmitted.
There are some major reasons for using a biphase
line code. The power density is concentrated in a
spectral region that minimizes dispersion and
differential attenuation. This can shorten the line
response and reduce the intersymbol interference
which are critical for adaptive echo cancellation.
There are regular zero crossings halfway through
every bit cell or baud which allows simple clock
extraction at the receiving end. There is no D.C.
content in the code so that phantom power feed may
be applied to the line and simple transformer
coupling may be used with no effect on the data. It is
bipolar, making data reception simple and providing
a high signal to noise ratio. The signal is then passed
through a bandpass filter which conditions the signal
for the line by limiting the spectral content from
0.2fBaud to 1.6fBaud and on to a line driver where it is
If the DINB bit of the Control Register is set, the
entire D-channel is transmitted during the B1-
channel timeslot. In MOD mode the SYNC, HK and
D-channel bits are not transmitted or received but
rather a continuous data stream at 80 or 160 kbit/s is
present. No frame recovery information is present on
the line in MOD mode.
made available to be put onto the line biased at VBias
.
The resulting transmit signal will have a distributed
spectrum with a peak at 3/4fBaud. The transmit signal
(LOUT) may be disabled by holding the LOUT DIS pin
high or by writing DLO (bit 6) of the Diagnostics
Register to logic “1”. When disabled, LOUT is forced to
the VBias level. LOUT DIS has an internal pull-down to
allow this pin to be left not connected in applications
where this function is not required. The receive
signal is the above transmit signal superimposed on
the signal from the remote end and any reflections or
delayed symbols of the near end signal.
9-127
MT9171/72
Advance Information
Bits
Bit 7
1
Bit 6
1
Bit 5
1
Bit 4
0
Bit 3
0
Bit 2
1
Bit 1
0
Bit 0
0
Data
NRZ Data
Differential
Encoded
Differential
Encoded
Biphase
Transmit
Line Signal
V
Bias
Note: Last bit sent was a logic 0
Figure 10 - Data & Line Encoding
F0
B1
SYNC
D
B1
B1
B1
B1
B1
B1
B1
B1
7
SYNC
L
7
0
0
1
2
3
4
5
6
OUT
Figure 11 - Frame Format - 80 kbit/s (Modes 0, 2, 3, 4, 6)
F0
SYNC HK0
D
D
B1 B1 B1 B1 B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2 SYNC
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1
0
L
OUT
Figure 12 - Frame Format - 160 kbit/s (Modes 0, 2, 3, 4, 6)
9-128
Advance Information
MT9171/72
If the scramblers power up with all zeros in them,
they are not capable of randomizing all-zeros data
sequence. This increases the correlation between
the transmit and receive data which may cause loss
of convergence in the echo canceller and high bit
error rates.
Applications
Typical connection diagrams are shown in Figures 13
and 14 for the DN mode as a MASTER and SLAVE,
respectively. LOUT is connected to the coupling
transformer through a resistor R2 and capacitors C2
and C2’ to match the line characteristic impedance.
Suggested values of R2, C2 and C2’ for 80 and 160
kbit/s operation are provided in Figures 13 and 14.
Overvoltage protection is provided by R1, D1 and
D2. C1 is present to properly bias the received line
signal for the LIN input. A 2:1 coupling transformer is
used to couple to the line with a secondary center
tap for optional phantom power feed. Varistors have
been shown for surge protection against such things
as lightning strikes.
In DN mode the insertion of the SYNC pattern will
provide enough pseudo-random activity to maintain
convergence. In MOD mode the SYNC pattern is not
inserted. For this reason, at least on ”1” must be fed
into the DNIC on power up to ensure that the
scramblers will randomize any subsequent all-zeros
sequence.
C2’ = 1.5 nF
For 80 kbit/s: C2’ = 3.3 nF
+5V
MT9171/72
C2 = 22 nF
DSTi
D1 = D2 = MUR405
DV Port ST-BUS
{
DSTo
L
OUT
CDSTi
CDSTo
F0
2 : 1
D2
CD Port ST-BUS
Master Clocks
{
{
R2 = 390Ω
R1 = 47Ω
Line Feed
Voltage
68 Volts
(Typ)
C4
L
IN
1.0 µF
2.5 Joules
0.02 Watt
MS0
MS1
MS2
Mode Select
Lines
OSC1
D.C. coupled,
Frequency locked
10.24 MHz clock.
Refer to AC Electrical
Characteristics
Clock Timing
0.33 µF
OSC2
F0o
NC
+5V
V
Ref
C1 = 0.33 µF
V
DN Mode.
Bias
0.33 µF
Note: Low leakage diodes (1 & 2) are required so
that the DC voltage at L ≈ V
To Next DNIC
IN
Bias
Figure 13 - Typical Connection Diagram - MAS/DN Mode, 160 kbit/s
C2’ = 1.5 nF
For 80 kbit/s: C2’ = 3.3 nF
+5V
MT9171/72
DSTi
C2 = 22 nF
D1 = D2 = MUR405
DV Port ST-BUS
{
{
{
DSTo
L
OUT
CDSTi
CDSTo
F0
2:1
D2
CD Port ST-BUS
Master Clocks
R2 = 390Ω
R1 = 47Ω
C4
L
IN
1.0 µF
68 Volts
(Typ)
Supply
MS0
MS1
MS2
Mode Select
Lines
2.5 Joules
0.02 Watt
OSC1
OSC2
10.24 MHz XTAL
C3=33pF=C4
0.33 µF
+5V
V
Ref
V
C1 = 0.33 µF
Bias
0.33 µF
Note: Low leakage diodes (1 & 2) are required so
that the DC voltage at L ≈ V
IN
Bias
Figure 14 - Typical Connection Diagram - SLV/DN Mode, 160 kbit/s
9-129
MT9171/72
Advance Information
Absolute Maximum Ratings** - Voltages are with respect to ground (V ) unless otherwise stated.
SS
Parameter
Symbol
Min
Max
Units
1
2
3
4
5
Supply Voltage
VDD
VMax
IMax
-0.3
-0.3
7
VDD+0.3
40
V
V
Voltage on any pin (other than supply)
Current on any pin (other than supply)
Storage Temperature
mA
°C
TST
-65
+150
750
Package Power Dissipation (Derate 16mW/°C above 75°C)
PDiss
mW
** Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions† - Voltages are with respect to ground (V ) unless otherwise stated.
SS
Characteristics
Sym
Min
Typ*
Max
Units
Test Conditions
1
2
3
4
Operating Supply Voltage
VDD
TOP
VIH
VIL
4.75
-40
2.4
0
5.00
5.25
+85
VDD
0.4
V
°C
V
Operating Temperature
Input High Voltage (except OSC1)
Input Low Voltage (except OSC1)
for 400 mV noise margin
for 400 mV noise margin
V
* Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
† Parameters over recommended temperature & power supply voltage ranges.
DC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated.
SS
Characteristics
Sym Min
Typ*
Max Units
Test Conditions
1
2
3
Operating Supply Current
IDD
10
mA
V
Output High Voltage (ex OSC2) VOH
2.4
10
IOH=10mA
Output High Current
(except OSC2)
IOH
mA
Source current. VOH=2.4V
O
U
T
P
U
T
4
5
6
Output High Current - OSC2
Output Low Voltage (ex OSC2)
IOH
VOL
IOL
10
µA
Source current VOH=3.5V
IOL=5mA
0.4
10
V
Output Low Current
(except OSC2)
5
7.5
mA
Sink current. VOL=0.4V
S
7
Output Low Current - OSC2
High Imped. Output Leakage
IOL
IOZ
VO
10
µA
µA
Sink current. VOL=1.5V
VIN=VSS to VDD
8
9
Output Voltage
(VRef
)
V
Bias-1.8
VDD/2
V
V
(VBias
)
10
11
12
13
14
15
16
Input High Voltage (ex OSC1)
Input Low Voltage (ex OSC1)
Input High Voltage (OSC1)
Input Low Voltage (OSC1)
Input Leakage Current
VIH
VIL
2.0
4.0
V
V
0.8
VIHo
VILo
IIL
V
I
N
P
U
T
S
1.0
10
V
µA
kΩ
VIN=VSS to VDD
Input Pulldown Impedance
LOUT DIS and Precan
ZPD
50
20
17
Input Leakage Current for
OSC1 Input
IIOSC
µA
* Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
† Parameters over recommended temperature & power supply voltage ranges.
9-130
Advance Information
MT9171/72
AC Electrical Characteristics† - Voltages are with respect to ground (V ) unless otherwise stated.
SS
Characteristics
Input Voltage
Sym
Min Typ* Max Units
Test Conditions
1
2
(LIN)
(LIN)
VIN
ZIN
5.0
Vpp
kΩ
Input Impedance
20
fBaud=160 kHz
I
N
3
Crystal/Clock Frequency
fC
10.24
0
MHz
ppm
%
4
P Crystal/Clock Tolerance
U
T
S
TC
-100
40
+100
60
➀
5a
5b
Crystal/Clock Duty Cycle
Crystal/Clock Duty Cycle
DCC
DCC
50
Normal temp. & VDD
➀
45
50
55
%
Recommended at max./
min. temp. & VDD
6
7
8
Crystal/Clock Loading
CL
Co
33
8
50
pF
pF
From OSC1 & OSC2 to VSS.
Output Capacitance
(LOUT
)
O
U
T
P
U
T
Load Resistance
(LOUT
)
RLout
500
100
Ω
kΩ
(VBias, VRef
)
9
Load Capacitance
Output Voltage
(LOUT
)
CLout
Vo
20
pF
µF
Capacitance to VBias.
(VBias, VRef
)
0.1
3.2
S
10
(LOUT
)
4.3
4.6
Vpp RLout = 500Ω, CLout = 20pF
† Timing is over recommended temperature & power supply voltages.
* Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
➀ Duty cycle is measured at V /2 volts.
DD
.
AC Electrical Characteristics† - Clock Timing - DN Mode (Figures 16 & 17)
Characteristics
C4 Clock Period
Sym
Min
Typ*
Max
Units
Test Conditions
1
2
3
4
5
6
tC4P
tC4W
tF0S
tF0H
tF0W
JC
244
122
ns
ns
ns
ns
ns
ns
C4 Clock Width High or Low
Frame Pulse Setup Time
Frame Pulse Hold Time
Frame Pulse Width
In Master Mode - Note 1
50
50
244
10.24 MHz Clock Jitter (wrt C4)
±15
Note 2
† Timing is over recommended temperature & power supply voltages.
* Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
Notes: 1)
2)
When operating as a SLAVE the C4 clock has a 40% duty cycle.
When operating in MAS/DN Mode, the C4 and Oscillator clocks must be externally frequency-locked (i.e.,
F =2.5xf ). The relative phase between these two clocks (Φ in Fig. 17) is not critical and may vary from
C
C4
0 ns to t
. However, the relative jitter must be less than J (see Figure 17).
C4P
C
F0
C4
ST-BUS
Channel 31 Channel 0 Channel 0
BIT CELLS
Bit 0
Bit 7
Bit 6
Figure 15 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams
9-131
MT9171/72
Advance Information
t
t
C4W
C4P
2.0V
C4
0.8V
t
t
F0H
t
F0S
C4W
t
F0W
2.0V
F0
0.8V
Figure 16 - C4 Clock & Frame Pulse Alignment for ST-BUS Streams in DN Mode
2.0V
0.8V
C4
Φ
J
C
3.0V
2.0V
OSC1
Figure 17 - Frequency Locking for the C4 and OSC1 Clocks in MAS/DN Mode
AC Electrical Characteristics† - Clock Timing - MOD Mode (Figure 18)
80 kbit/s
160 kbit/s
Test
Conditions
Characteristics
Sym
Units
Min Typ* Max Min Typ* Max
1 TCK/RCK Clock Period
tCP
tCW
12.5
6.25
20
6.25
3.125
20
µs
µs
ns
µs
µs
µs
µs
2
3
TCK/RCK Clock Width
tCT
CL=40pF
TCK/RCK Clock Transition Time
tCLDS
tCLDH
tCLDW
tCLDP
3.125
3.125
6.05
8xtCP
1.56
1.56
2.925
8xtCP
4 CLD to TCK Setup Time
5 CLD to TCK Hold Time
6 CLD Width Low
7 CLD Period
† Timing is over recommended temperature & power supply voltage ranges.
* Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing.
t
CP
t
CT
t
CW
2.4V
0.4V
RCK
TCK
t
CP
2.4V
0.4V
t
t
CLDH
CLDS
t
CW
t
CT
t
CLDW
2.4V
0.4V
CLD
Note 1: TCK and CLD are generated on chip and provide the data clocks for the CD port and the transmit section of the
DV port. RCK, also generated on chip, is extracted from the receive data and only clocks out the data at the D output
o
and may be skewed with respect to TCK due to end-to-end delay.
Note 2: At the slave end TCK is phase locked to RCK.
o
The rising edge of TCK will lead the rising edge of RCK by approximately 90 .
Figure 18 - RCK, TCK & CLD Timing For MOD Mode
9-132
Advance Information
MT9171/72
AC Electrical Characteristics† - Data Timing - DN Mode (Figure 19)
Characteristics
DSTi/CDSTi Data Setup Time
DSTi/CDSTi Data Hold Time
Sym
tRS
Min
30
Typ* Max
Units
ns
Test Conditions
1
2
tRH
50
ns
3a DSTo/CDSTo Data Delay
tTD
120
140
ns
CL=40pF
CL=40pF
3b DSTo/CDSTo High Z to Data Delay
tZTD
ns
† Timing is over recommended temperature & power supply voltage ranges.
Bit
Stream
Bit Cell
2.0V
0.8V
C4
2.0V
0.8V
DSTi
CDSTi
t
TD
t
t
t
t
TD
RH
ZTD
RS
2.4V
0.4V
DSTo
CDSTo
Figure 19 - Data Timing For DN Mode
AC Electrical Characteristics† - Data Timing - MOD Mode (Figure 20)
80 kbit/s
160 kbit/s
Test
Conditions
Characteristics
Sym
Units
Min Typ* Max Min Typ* Max
1 Di/CDi Data Setup Time
2 Di/CDi Data Hold Time
3 Do Data Delay Time
4 CDo Data Delay Time
tDS
tDH
tRD
tTD
150
4.5
150
2.5
ns
µs
70
70
70
70
ns CL=40pF
ns CL=40pF
† Timing is over recommended temperature & power supply voltage ranges.
* Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing.
Performance Characteristics of the MT9171 DSIC
Characteristics
Sym Min Typ*
Max
Units
Test Conditions
SNR≥16.5dB (300kHz
bandlimited noise)
1
2
3
Allowable Attenuation for Bit Error
Afb
0
30
25
dB
-6
Rate of 10 (Note 1)
Line Length at 80 kbit/s -24 AWG
-26 AWG
L80
3.0
2.2
km
km
attenuation - 6.9 dB/km
attenuation - 10.0 dB/km
Line Length at 160 kbit/s -24 AWG
-26 AWG
L160
3.0
2.2
attenuation - 8.0 dB/km
attenuation - 11.5 dB/km
Performance Characteristics of the MT9172 DNIC
Characteristics
Sym Min Typ*
Max
Units
Test Conditions
1
2
3
Allowable Attenuation for Bit Error
Rate of 10 (Note 1)
Afb
0
40
33
dB
SNR≥16.5dB
bandlimited noise)
(300kHz
-6
Line Length at 80 kbit/s -24 AWG
-26 AWG
L80
5.0
3.4
km
km
attenuation - 6.9 dB/km
attenuation - 10.0 dB/km
Line Length at 160 kbit/s -24 AWG
-26 AWG
L160
4.0
3.0
attenuation - 8.0 dB/km
attenuation - 11.5 dB/km
Note 1: Attenuation measured from Master L
to Slave L at 3/4baud frequency.
OUT
IN
* Typical figures are at 25°C, for design aid only: not guaranteed and not subject to production testing.
9-133
MT9171/72
Advance Information
Tx Bit
Stream
Bit Cell
2.4V
TCK
0.4V
t
t
DS
DH
2.0V
0.8V
Di
CDI
t
t
TD
TD
2.4V
0.4V
CDo
Rx Bit
Stream
Bit Cell
t
t
RD
RD
RCK
2.4V
0.4V
Do
Figure 20 - Data Timing for Master Modem Mode
9-134
Advance Information
MT9171/72
2.4V
TCK
0.4V
t
t
DS
DH
π t
CP
2.0V
0.8V
Di
CDI
t
t
TD
TD
2.4V
0.4V
CDo
RCK
2.4V
0.4V
Do
Figure 21 - Data Timing for Slave Modem Mode
9-135
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