MT8963ASR [ZARLINK]
Integrated PCM Filter Codec; 综合PCM编解码器过滤
| 型号： | MT8963ASR |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Integrated PCM Filter Codec |
| 文件： | 总32页 (文件大小：609K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO2-CMOS MT8960/61/62/63/64/65/66/67
Integrated PCM Filter Codec
Data Sheet
February 2005
Features
•
•
•
•
•
•
ST-BUS compatible
Ordering Information
MT8960/61/64/65AE
MT8962/63AE
MT8962/63/66/67AS
MT8963ASR
18 Pin PDIP
20 Pin PDIP
20 Pin SOIC
20 Pin SOIC
18 Pin PDIP*
20 Pin PDIP*
20 Pin SOIC*
20 Pin SOIC*
Tubes
Transmit/Receive filters & PCM Codec in one I.C
Meets AT&T D3/D4 and CCITT G711 and G712
µ-Law: MT8960/62/64/67
Tubes
Tubes
Tape & Reel
Tubes
MT8960AE1
MT8962/63AE1
MT8962AS1
Tubes
Tubes
A-Law: MT8961/63/65/67
MT8963AS1
Tubes
Low power consumption:
*Pb Free Matte Tin
-40°C to +85°C
Op.: 30 mW typ.
Stby.: 2.5 mW typ.
•
Digital Coding Options:
Description
MT8964/65/66/67 CCITT Code
Manufactured in ISO2-CMOS, these integrated
filter/codecs are designed to meet the demanding
performance needs of the digital telecommunications
industry, e.g., PABX, Central Office, Digital telephones.
MT8960/61/62/63 Alternative Code
•
•
•
Digitally controlled gain adjust of both filters
Analog and digital loopback
Filters and codec independently user accessible
for testing
•
•
•
•
Powerdown mode available
2.048 MHz master clock input
Up to six uncommitted control outputs
±5 V ±5% power supply
ANUL
Analog to
Transmit
Output
V
X
Digital PCM
Encoder
DSTo
Register
Filter
SD0
SD1
SD2
SD3
SD4
SD5
CSTi
CA
F1i
C2i
A Register
8-Bits
Output
Control
Logic
Register
B-Register
8-Bits
PCM Digital
to Analog
Decoder
Input
Receive
Filter
DSTi
V
R
Register
V
GNDA GNDD
V
V
EE
Ref
DD
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2005, Zarlink Semiconductor Inc. All Rights Reserved.
MT8960/61/62/63/64/65/66/67
Data Sheet
MT8962/63/66/67
MT8960/61/64/65
20
19
18
17
16
15
14
13
12
11
1
2
CSTi
DSTi
C2i
GNDD
VRef
GNDA
VR
18
17
16
15
14
13
12
11
10
1
2
3
4
5
6
7
8
9
CSTi
DSTi
C2i
GNDD
VRef
GNDA
VR
3
4
5
DSTo
VDD
SD5
SD4
F1i
DSTo
VDD
F1i
ANUL
VX
ANUL
VX
6
7
VEE
SD0
SD1
SD2
CA
VEE
SD0
8
SD3
SD2
CA
9
SD1
SD3
10
18 PIN PDIP
20 PIN PDIP/SOIC
Figure 2 - Pin Connections
Pin Description
Pin Name
Description
CSTi
Control ST-BUS In is a TTL-compatible digital input used to control the function of the filter/codec.
Three modes of operation may be effected by applying to this input a logic high (VDD), logic low
(GNDD), or an 8-bit serial word, depending on the logic states of CA and F1i.
Functions controlled are: powerdown, filter gain adjust, loopback, chip testing, SD outputs.
DSTi
C2i
Data ST-BUS In accepts the incoming 8-bit PCM word. Input is TTL-compatible.
Clock Input is a TTL-compatible 2.048 MHz clock.
DSTo Data ST-BUS Out is a three-state digital output driving the PCM bus with the outgoing 8-bit PCM
word.
VDD
F1i
Positive power Supply (+5 V).
Synchronization Input is an active low digital input enabling (in conjunction with CA) the PCM input,
PCM output and digital control input. It is internally sampled on every positive edge of the clock, C2i,
and provides frame and channel synchronization.
CA
Control Address is a three-level digital input which enables PCM input and output and determines
into which control register (A or B) the serial data, presented to CSTi, is stored.
SD3
System Drive Output is an open drain output of an N-channel transistor which has its source tied to
GNDA. Inactive state is open circuit.
SD4-5 System Drive Outputs are open drain outputs of N-channel transistors which have their source tied
to GNDD. Inactive state is open circuit.
SD0-2 System Drive Outputs are “Totempole“ CMOS outputs switching between GNDD and VDD. Inactive
state is logic low.
VEE
VX
Negative power supply (-5 V).
Voice Transmit is the analog input to the transmit filter.
ANUL Auto Null is used to integrate an internal auto-null signal. A 0.1 µF capacitor must be connected
between this pin and GNDA.
VR
Voice Receive is the analog output of the receive filter.
GNDA Analog ground (0 V).
VRef
Voltage Reference input to D to A converter.
GNDD Digital ground (0 V).
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Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
MT8960/62
MT8964/66
Digital Output
Digital Output
11111111
11110000
11100000
11010000
11000000
10110000
10100000
10000000
10001111
10011111
10101111
10111111
11001111
11011111
10010000
10000000
00000000
00010000
11101111
11111111
01111111
01101111
00100000
00110000
01000000
01010000
01100000
01110000
01111111
01011111
01001111
00111111
00101111
00011111
00001111
00000000
-2.415V -1.207V
0V
+1.207V +2.415V
Analog Input Voltage (V
)
Bit 7...
MSB
0
IN
LSB
Figure 3 - µ-Law Encoder Transfer Characteristic
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Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
MT8961/63
MT8965/67
Digital Output
Digital Output
11111111
11110000
11100000
11010000
11000000
10110000
10100000
10101010
10100101
10110101
10000101
10010101
11100101
11110101
10010000
10000000
00000000
00010000
11000101
11010101
01010101
01000101
00100000
00110000
01000000
01010000
01100000
01110000
01111111
01110101
01100101
00010101
00000101
00110101
00100101
00101010
-2.5V
-1.25V
0V
+2.5V
+1.25V
Analog Input Voltage (V
)
Bit 7...
MSB
0
IN
LSB
Figure 4 - A-Law Encoder Transfer Characteristic
Functional Description
Figure 1 shows the functional block diagram of the MT8960-67. These devices provide the conversion interface
between the voiceband analog signals of a telephone subscriber loop and the digital signals required in a digital
PCM (pulse code modulation) switching system. Analog (voiceband) signals in the transmit path enter the chip at
VX, are sampled at 8 kHz, and the samples quantized and assigned 8-bit digital values defined by logarithmic PCM
encoding laws. Analog signals in the receive path leave the chip at VR after reconstruction from digital 8-bit words.
Separate switched capacitor filter sections are used for bandlimiting prior to digital encoding in the transmit path
and after digital decoding in the receive path. All filter clocks are derived from the 2.048 MHz master clock input,
C2i. Chip size is minimized by the use of common circuitry performing the A to D and D to A conversion. A
successive approximation technique is used with capacitor arrays to define the 16 steps and 8 chords in the signal
conversion process. Eight-bit PCM encoded digital data enters and leaves the chip serially on DSTi and DSTo
pins, respectively.
Transmit Path
Analog signals at the input (Vx) are firstly bandlimited to 508 kHz by an RC lowpass filter section. This performs the
necessary anti-aliasing for the following first-order sampled data lowpass pre-filter which is clocked at 512 kHz.
This further bandlimits the signal to 124 kHz before a fifth-order elliptic lowpass filter, clocked at 128 kHz, provides
the 3.4 kHz bandwidth required by the encoder section. A 50/60 Hz third-order highpass notch filter clocked at
8 kHz completes the transmit filter path. Accumulated DC offset is cancelled in this last section by a switched-
capacitor auto-zero loop which integrates the sign bit of the encoded PCM word, fed back from the codec and
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Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
injects this voltage level into the non-inverting input of the comparator. An integrating capacitor (of value between
0.1 and 1 µF) must be externally connected from this point (ANUL) to the Analog Ground (GNDA).
The absolute gain of the transmit filter (nominally 0 dB at 1 kHz) can be adjusted from 0 dB to 7 dB in 1 dB steps by
means of three binary controlled gain pads.
The resulting bandpass characteristics with the limits shown in Figure 10 meet the CCITT and AT&T recommended
specifications. Typical attenuations are 30 dB for 0-60 Hz and 35 dB for 4.6 kHz and above.
The filter output signal is an 8 kHz staircase waveform which is fed into the codec capacitor array, or alternatively,
into an external capacitive load of 250 pF when the chip is in the test mode. The digital encoder generates an eight-
bit digital word representation of the 8 kHz sampled analog signal. The first bit of serial data stream is bit 7 (MSB)
and represents the sign of the analog signal. Bits 4-6 represent the chord which contains the analog sample value.
Bits 0-3 represent the step value of the analog sample within the selected chord. The MT8960-63 provide a sign
plus magnitude PCM output code format. The MT8964/66 PCM output code conforms to the AT &T D3
specification, i.e., true sign bit and inverted magnitude bits. The MT8965/67 PCM output code conforms to the
CCITT specifications with alternate digit inversion (even bits inverted). See Figs. 3 and 4 for the digital output code
corresponding to the analog voltage, VIN, at VX input.
The eight-bit digital word is output at DSTo at a nominal rate of 2.048 MHz, via the output buffer as the first 8-bits of
the 125 µs sampling frame.
Receive Path
An eight-bit PCM encoded digital word is received on DSTi input once during the 125 µs period and is loaded into
the input register. A charge proportional to the received PCM word appears on the capacitor array and an 8 kHz
sample and hold circuit integrates this charge and holds it for the rest of the sampling period.
The receive (D/A) filter provides interpolation filtering on the 8 kHz sample and hold signal from the codec. The filter
consists of a 3.4 kHz lowpass fifth-order elliptic section clocked at 128 kHz and performs bandlimiting and
smoothing of the 8 kHz "staircase" waveform. In addition, sinx/x gain correction is applied to the signal to
compensate for the attenuation of higher frequencies caused by the capacitive sample and hold circuit. The
absolute gain of the receive filter can be adjusted from 0 dB to -7 dB in 1 dB steps by means of three binary
controlled gain pads. The resulting lowpass characteristics, with the limits shown in Figure 11, meet the CCITT and
AT & T recommended specifications.
Typical attenuation at 4.6 kHz and above is 30 dB. The filter is followed by a buffer amplifier which will drive 5V
peak/peak into a 10k ohm load, suitable for driving electronic 2-4 wire circuits.
VRef
An external voltage must be supplied to the VRef pin which provides the reference voltage for the digital encoding
and decoding of the analog signal. For VRef = 2.5 V, the digital encode decision value for overload (maximum
analog signal detect level) is equal to an analog input VIN = 2.415 V (µ-Law version) or 2.5 V (A-Law version) and is
equivalent to a signal level of 3.17 dBm0 or 3.14 dBm0 respectively, at the codec.
The analog output voltage from the decoder at VR is defined as:
µ-Law:
-0.5
2C
16.5 + S
VRef
X
V
±
+
[( 128 ) (128 )( 33 )]
OFFSET
A-Law:
VRef
2C+1
0.5 + S
X
V
[(128 )( 32 )]
±
OFFSETC=0
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Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
2C
16.5 + S
VRef
X
V
[(128 )( 32 )]
±
OFFSETC≠0
where C = chord number (0-7)
S = step number (0-15)
VRef is a high impedance input with a varying capacitive load of up to 40 pF.
The recommended reference voltage for the MT8960 series of codecs is 2.5 V ±0.5%. The output voltage from the
reference source should have a maximum temperature coefficient of 100 ppm/C°. This voltage should have a total
regulation tolerance of ±0.5% both for changes in the input voltage and output loading of the voltage reference
source. A voltage reference circuit capable of meeting these specifications is shown in Figure 5. Analog
Devices’AD1403A voltage reference circuit is capable of driving a large number of codecs due to the high input
impedance of the VRef input. Normal precautions should be taken in PCB layout design to minimize noise coupling
to this pin. A 0.1 µF capacitor connected from VRef to ground and located as close as possible to the codec is
recommended to minimize noise entering through VRef. This capacitor should have good high frequency
characteristics.
NC
8
NC
7
NC
6
NC
5
V
Ref
0.1 µF
AD1403A
MT8960-67
FILTER/CODEC
1
2
3
4
NC
+5 V
2.5 V
Figure 5 - Typical Voltage Reference Circuit
Timing
The codec operates in a synchronous manner (see Figure 9a). The codec is activated on the first positive edge of
C2i after F1i has gone low. The digital output at DSTo (which is a three-state output driver) will then change from
a high impedance state to the sign bit of the encoded PCM word to be output. This will remain valid until the next
positive edge, when the next most significant bit will be output.
On the first negative clock edge (after F1i signal has been internally synchronized and CA is at GNDD or VEE) the
logic signal present at DSTi will be clocked into the input shift register as the sign bit of the incoming PCM word.
The eight-bit word is thus input at DSTi on negative edges of C2i and output at DSTo on positive edges of C2i.
F1i must return to a high level after the eighth clock pulse causing DSTo to enter high impedance and
preventing further input data to DSTi. F1i will continue to be sampled on every positive edge of C2i. (Note: F1i may
subsequently be taken low during the same sampling frame to enable entry of serial data into CSTi. This occurs
usually mid-frame, in conjunction with CA=VDD, in order to enter an 8-bit control word into Register B. In this case,
PCM input and output are inhibited by CA at VDD.)
Internally the codec will then perform a decode cycle on the newly input PCM word. The sampled and held analog
signal thus decoded will be updated 25 µs from the start of the cycle. After this the analog input from the filter is
sampled for 18 µs, after which digital conversion takes place during the remaining 82 µs of the sampling cycle.
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Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
Since a single clock frequency of 2.048 MHz is required, all digital data is input and output at this rate. DSTo,
therefore, assumes a high impedance state for all but 3.9 µs of the 125 µs frame. Similarly, DSTi input data is valid
for only 3.9 µs.
Digital Control Functions
CSTi is a digital input (levels GNDD to VDD) which is used to control the function of the filter/codec. It operates in
three different modes depending on the logic levels applied to the Control Address input (CA) and chip enable input
(F1i) (see Table 1).
Mode 1
CA=-5V (VEE); CSTi=0V (GNDD)
The filter/codec is in normal operation with nominal transmit and receive gain of 0dB. The SD outputs are in their
active states and the test modes cannot be entered.
CA = -5V (VEE); CSTi = +5V (VDD
)
A state of powerdown is forced upon the chip whereby DSTo becomes high impedance, VR is connected to GNDA
and all analog sections have power removed.
Mode 2
CA= -5V (VEE); CSTi receives an eight-bit control word
CSTi accepts a serial data stream synchronously with DSTi (i.e., it accepts an eight-bit serial word in a 3.9 µs
timeslot, updated every 125 µs, and is specified identically to DSTi for timing considerations). This eight-bit control
word is entered into Control Register A and enables programming of the following functions: transmit and receive
gain, powerdown, loopback. Register B is reset to zero and the SD outputs assume their inactive state. Test modes
cannot be entered.
Mode 3
CA=0V (GNDD); CSTi receives an eight-bit control word
As in Mode 2, the control word enters Register A and the aforementioned functions are controlled. In this mode,
however, Register B is not reset, thus not affecting the states of the SD outputs.
CA=+5V (VDD); CSTi receives an 8-bit control word
In this case the control word is transferred into Register B. Register A is unaffected. The input and output of PCM
data is inhibited.
The contents of Register B controls the six uncommitted outputs SD0-SD5 (four outputs, SD0-SD3, on
MT8960/61/64/65 versions of chip) and also provide entry into one of the three test modes of the chip.
Note: For Modes 1 and 2, F1i must be at logic low for one period of 3.9 µs, in each 125 µs cycle, when PCM data
is being input and output, and the control word at CSTi enters Register A. For Mode 3, F1i must be at a logic low for
two periods of 3.9 µs, in each 125 µs cycle. In the first period, CA must be at GNDD or VEE, and in the second
period CA must be high (VDD)
.
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Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
Mode
CA
CSTi
Function
1
VEE
GNDD
VDD
Normal chip operation.
Powerdown.
(Note 1)
2
VEE
GNDD
VDD
Serial
Data
Eight-bit control word into Register A. Register B is reset.
Eight-bit control word into register A. Register B is unaffected.
Eight-bit control word into register A. Register B is unaffected.
3
Serial
Data
(Note 2)
Serial
Data
Note 1:
Note 2:
When operating in Mode 1, there should be only one frame pulse (F1i) per 125 µs frame
When operating in Mode 3, PCM input and output is inhibited by CA=VDD
.
Table 1 - Digital Control Modes
TRANSMIT (A/D)
BIT 2
BIT 1
BIT 0
FILTER GAIN (dB)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
+ 1
+ 2
+ 3
+ 4
+ 5
+ 6
+ 7
RECEIVE (D/A)
BIT 5
BIT 4
BIT 3
FILTER GAIN (dB)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
- 1
- 2
- 3
- 4
- 5
- 6
- 7
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Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
TRANSMIT (A/D)
BIT 2
BIT 7
BIT 1
BIT 6
BIT 0
FILTER GAIN (dB)
FUNCTION CONTROL
0
0
1
1
0
1
0
1
Normal operation
Digital Loopback
Analog Loopback
Powerdown
Table 2 - Control States - Register A
Control Registers A, B
The contents of these registers control the filter/codec functions as described in Tables 2 and 3.
Bit 7 of the registers is the MSB and is defined as the first bit of the serial data stream input (corresponding to the
sign bit of the PCM word).
On initial power-up these registers are set to the powerdown condition for a maximum of 25 clock cycles. During
this time it is impossible to change the data in these registers.
Chip Testing
By enabling Register B with valid data (eight-bit control word input to CSTi when F1i=GNDD and CA= VCC) the chip
testing mode can be entered. Bits 6 and 7 (most sign bits) define states for testing the transmit filter, receive filter
and the codec function. The input in each case is VX input and the output in each case is VR output. (See Table 3 for
details.)
Loopback
Loopback of the filter/codec is controlled by the control word entered into Register A. Bits 6 and 7 (most sign bits)
provide either a digital or analog loopback condition. Digital loopback is defined as follows:
•
PCM input data at DSTi is latched into the PCM input register and the output of this register is connected to
the input of the 3-state PCM output register.
•
•
The digital input to the PCM digital-to-analog decoder is disconnected, forced to zero (0).
The output of the PCM encoder is disabled and thus the encoded data is lost. The PCM output at DSTo is
determined by the PCM input data.
Analog loopback is defined as follows:
•
•
•
•
PCM input data is latched, decoded and filtered as normal but not output at VR.
Analog output buffer at VR has its input shorted to GNDA and disconnected from the receive filter output.
Analog input at VX is disconnected from the transmit filter input.
The receive filter output is connected to the transmit filter input. Thus the decode signal is fed back through
the receive path and encoded in the normal way. The analog output buffer at VR is not tested by this
configuration.
In both cases of loopback, DSTi is the input and DSTo is the output.
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Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
Logic Control Outputs SD0-5
These outputs are directly controlled by the logic states of bits 0-5 in Register B. A logic low (GNDD) in Register B
causes the SD outputs to assume an inactive state. A logic high (VDD) in Register B causes the SD outputs to
assume an active state (see Table 3). SD0-2 switch between GNDD and VDD and may be used to control
external logic or transistor circuitry, for example, that employed on the line card for performing such functions
as relay drive for application of ringing to line, message waiting indication, etc.
SD3-5 are used primarily to drive external analog circuitry. Examples may include the switching in or out of gain
sections or filter sections (e.g., ring trip filter) (Figure 7).
MT8962/63/66/67 provides all six SD outputs.
MT8960/61/64/65 each packaged in an 18-pin DIP provide only four control outputs, SD0-3.
Telephone Set
2 Wire
Analog
PCM Highway
Supervision
Protection
MT8960/61
Battery
Feed
MT8962/63
2W/4W
Converter
MT8964/65
MT8966/67
Ringing
Figure 6 - Typical Line Termination
LOGIC CONTROL OUTPUTS SD0-SD2
BITS 0-2
0
1
Inactive state - logic low (GNDD).
Active state - logic high (VDD).
BIT 3
LOGIC CONTROL OUTPUT SD3
0
1
Inactive state - High Impedance.
Active state - GNDA.
BITS 4,5
LOGIC CONTROL OUTPUTS SD4, SD5
0
1
Inactive state - High Impedance.
Active state - GNDD.
BIT 7 BIT 6
CHIP TESTING CONTROLS
0
0
Normal operation.
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Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
BITS 0-2
LOGIC CONTROL OUTPUTS SD0-SD2
0
1
1
1
0
1
Transmit filter testing, i.e.:
Transmit filter input connected to VX input
Receive filter and Buffer disconnected from VR
Receive filter testing, i.e.:
Receive filter input connected to VX input
Receive filter input disconnected from codec
Codec testing i.e.:
Codec analog input connected to VX
Codec analog input disconnected from transmit filter output
Codec analog output connected to VR
VR disconnected from receive filter output
Table 3 - Control States - Register B
Powerdown
Powerdown of the chip is achieved in several ways:
Internal Control:
1)
2)
Initial Power-up. Initial application of VDD and VEE causes powerdown for a period of 25 clock cycles and
during this period the chip will accept input only from C2i. The B-register is reset to zero forcing SD0-5 to
be inactive. Bits 0-5 of Register A (gain adjust bits) are forced to zero and bits 6 and 7 of Register A
become logic high thus reinforcing the powerdown.
Loss of C2i. Powerdown is entered 10 to 40 µs after C2i has assumed a continuous logic high (VDD). In
this condition the chip will be in the same state as in (1) above.
Note: If C2i stops at a continuous logic low (GNDD), the digital data and status is indeterminate.
External Control:
1)
Register A. Powerdown is controlled by bits 6 and 7 (when both at logic high) of Register A which in turn
receives its control word input via CSTi, when F1i is low and CA input is either at VEE or GNDD. Power is
removed from the filters and analog sections of the chip. The analog output buffer at VR will be connected
to GNDA. DSTo becomes high impedance and the clocks to the majority of the logic are stopped. SD
outputs are unaffected and may be updated as normal.
2)
CSTi Input. With CA at VEE and CSTi held at continuous logic high the chip assumes the same state as
described in External Control (1) above.
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Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
Message
Waiting
-100 V DC
MT8960/61/64/65
(With Relay
Drive)
From ST-BUS
From ST-BUS
Master Clock
to ST-BUS
5 V
CSTi
DSTi
C2i
GNDD
V
2.5 V
Ref
GNDA
DSTo
V
R
2/4 Wire
Telephone
Line
0.1µF
Ring Trip
Filter
Converter
V
F1i
ANUL
DD
Gain
Section
Alignment
V
X
(With Relay
Drive)
Register Select
CA
SD3
SD2
V
SD0
-5 V
EE
SD1
Ring Feed
-48 V DC
-48 V DC
(With Relay
Drive)
90 V
RMS
Figure 7 - Typical Use of the Special Drive Outputs
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Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
DSTi
DSTo
CDTi
V
V
SD0
X
R
Line
Interface
&
.
.
.
•
Monitoring
Circuitry
•
•
SDn
Line 1
Speech
Switch
-
MT8960-67
8980
8
8
•
•
•
•
•
•
Repeated for Lines
2 to 255
Repeated for Lines
2 to 255
Controlling
Micro-
Processor
8
8
Control &
Signalling
-
8980
DSTi
DSTo
CDTi
V
V
SD0
X
R
Line
Interface
&
.
.
.
•
Monitoring
Circuitry
•
•
SDn
Line 256
MT8960-67
Figure 8 - Example Architecture of a Simple Digital Switching System using the MT8960-67
13
Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
1
DC Supply Voltages
V
DD-GNDD
-0.3
-6.0
+6.0
+0.3
VDD
VDD
V
V
V
V
V
EE-GNDD
VRef
2
3
4
Reference Voltage
Analog Input
GNDA
VEE
VX
Digital Inputs
Except CA
CA
GNDD-0.3
V
DD+0.3
V
V
V
V
EE-0.3
GNDD-0.3
VEE-0.3
VDD+0.3
VDD+0.3
VDD+0.3
VDD+0.3
20
5
Output Voltage
SD0-2
SD3
V
SD4-5
II
VEE-0.3
V
6
7
8
Current On Any Pin
mA
°C
mW
Storage Temperature
TS
-55
+125
Power Dissipation at 25°C (Derate 16 mW/°C above 75°C)
PDiss
500
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions - Voltages are with respect to GNDD unless otherwise stated
Characteristics
Supply Voltage
Sym.
Min.
Typ.* Max.
Units
Comments
1
2
VDD
VEE
4.75
5.0
-5.0
2.5
0.0
0.0
5.25
V
V
-5.25
-4.75
VRef
VGNDD
V
Vdc
Vac
See Note 1
Ref. to GNDA
Voltage On Digital Ground
Operating Temperature
-0.1
-0.4
+0.1
+0.4
Ref. to GNDA 400 ns max.
duration in 125 µs cycle
3
4
TO
0
+70
°C
Operating Current
VDD
VEE
IDD
IEE
3.0
3.0
4.0
4.0
mA
mA
All digital inputs at VDD
or GNDD (or VEE for CA)
VRef
IRef
2.0
µA
Mean current
5
Standby Current
VDD
IDDO
0.25
1.0
1.0
mA
mA
All digital inputs at VDD
or GNDD (or VEE for CA)
VEE
IEEO
0.25
Note 1: Temperature coefficient of VRef should be better than 100 ppm/°C.
14
Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
DC Electrical Characteristics - Voltages are with respect to GNDD unless otherwise stated.
T =0 to 70°C, V =5V±5%, V =-5V±5%, V =2.5V±0.5%, GNDA=GNDD=0V,Clock Frequency =2.048MHz. Outputs unloaded unless
A
DD
EE
Ref
otherwise specified.
Characteristics
Sym. Min. Typ.*
Max.
Units
Test Conditions
1
2
Input Current
Except CA
CA
II
10.0
10.0
0.8
µA
µA
V
VIN = GNDD to VDD
VIN = VEE to VDD
IIC
D
I
Input Low
Except CA
CA
VIL
VILC
VIH
VIIC
0.0
VEE
2.4
0.0
V
+1.2
G Voltage
I
V
EE
3
4
Input High Voltage All Inputs
5.0
V
T
A
L
Input Intermediate CA
Voltage
0.8
V
5
6
Output Leakage
DSTo
I0Z
±0.1
µA
µA
Output High Impedance
Current (Tristate) SD3-5
10.0
0.4
1.0
Output Low
Voltage
DSTo
VOL
VOL
VOH
VOH
ROUT
COUT
IIN
V
V
IOUT =1.6 mA
IOUT =1 mA
D
I
SD0-2
DSTo
SD0-2
SD3-5
G
I
7
Output High
Voltage
Output Resistance
4.0
4.0
V
IOUT =-100µA
IOUT =-1mA
VOUT =+1V
V
T
A
L
8
9
1.0
4.0
2.0
KΩ
pF
µA
Output Capacitance DSTo
Output High Impedance
1
0
Input Current
VX
VX
VX
10.0
VEE ≤ VIN ≤ VCC
1
1
Input Resistance
Input Capacitance
RIN
CIN
10.0
30.0
+1.0
MΩ
pF
A
N
A
L
1
2
fIN = 0 - 4 kHz
See Note 2
1
3
1
4
Input Offset Voltage VX
VOSIN
ROUT
mV
Ω
O
G
Output Resistance
VR
100
100
1
5
Output Offset Voltage VR
VOSO
UT
mV
Digital Input= +0
* Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing.
Note 2:
V
OSIN specifies the DC component of the digitally encoded PCM word.
15
Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
AC Electrical Characteristics - Voltages are with respect to GNDD unless otherwise stated.
TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency=2.048 MHz. Outputs unloaded unless
otherwise specified.
Characteristics
Clock Frequency
Sym.
Min.
Typ.*
Max
Units
Test Conditions
1
2
C2i
C2i
C2i
C2i
fC
2.046 2.048
2.05
50
MHz
ns
ns
%
See Note 3
Clock Rise Time
Clock Fall Time
Clock Duty Cycle
tCR
tCF
3
50
4
40
50
60
5
Chip Enable Rise Time F1i
Chip Enable Fall Time F1i
Chip Enable Setup Time F1i
Chip Enable Hold Time F1i
tER
tEF
tES
tEH
tOR
tOF
100
100
ns
ns
ns
ns
ns
ns
6
7
50
25
See Note 4
See Note 4
8
D
I
G
I
T
A
L
9
Output Rise Time
Output Fall Time
DSTo
DSTo
100
100
10
11
Propagation Delay Clock DSTo
to Output Enable
tPZL
tPZH
122
122
ns
ns
RL=10 KΩ to VCC
12
13
14
15
16
17
Propagation Delay
Clock to Output
DSTo
tPLH
tPHL
100
100
ns
ns
CL=100 pF
Input Rise Time
Input Fall Time
Input Setup Time
Input Hold Time
CSTi
DSTi
tIR
100
100
ns
ns
CSTi
DSTi
tIF
100
100
ns
ns
CSTi
DSTi
tISH
tISL
25
0
ns
ns
CSTi
DSTi
tIH
60
60
ns
ns
Propagation Delay
Clock to SD Output
SD
tPCS
400
ns
CL = 100 pF
CL = 20 pF
D
I
G
I
18
19
20
SD Output Fall Time
SD Output Rise Time
SD
SD
tSF
tSR
tDL
200
400
122
ns
ns
ns
T
A
L
Digital Loopback
Time DSTi to DSTo
(See Figures 9a, 9b, 9c)
* Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing.
Note 3:
Note 4:
The filter characteristics are totally dependent upon the accuracy of the clock frequency providing F1i is synchronized to
C2i. The A/D and D/A functions are unaffected by changes in clock frequency.
This gives a 75 ns period, 50 ns before and 25 ns after the 50% point of C2i rising edge, when change in F1i will give an
undetermined state to the internally synchronized enable signal.
16
Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
AC Electrical Characteristics - Transmit (A/D) Path - Voltages are with respect to GNDD unless otherwise stated.
TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz,
Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified.
Typ.
Characteristics
Sym.
Min.
Max.
Units
Test Conditions
*
1
Analog Input at VX equivalent to
the overload decision level at the
codec
VIN
Level at codec:
µ-Law: 3.17 dBm0
A-Law: 3.14 dBm0
See Note 6
4.82
9
VPP
VPP
5.00
0
2
3
Absolute Gain (0dB setting)
GAX
-0.25
-0.35
+0.25
+0.35
dB
dB
0 dBm0 @ 1004 Hz
Absolute Gain (+1dB to +7dB
settings)
from nominal,
@ 1004 Hz
4
5
Gain Variation
With Temp
GAXT
GAXS
GTX1
0.01
0.04
dB
TA=0°C to 70°C
With Supplies
dB/V
A
N
A
L
Gain Tracking
Sinusoidal Level:
+3 to -20 dBm0
Noise Signal Level:
-10 to -55 dBm0
-55 to -60 dBm0
(See Figure 12) CCITT G712
(Method 1)
-0.25
+0.25
dB
O
G
-0.25
-0.50
+0.25
+0.50
dB
dB
CCITT G712
(Method 2)
AT&T
GTX2
DQX1
Sinusoidal Level:
+3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
-0.25
-0.50
-1.50
+0.25
+0.50
+1.50
dB
dB
dB
6
Quantization
Noise Signal Level:
-3 dBm0
Distortion
28.00
35.60
33.90
29.30
14.20
dB
dB
dB
dB
dB
(See Figure 13) CCITT G712
(Method 1)
-6 to -27 dBm0
-34 dBm0
-40 dBm0
-55 dBm0
CCITT G712
(Method 2)
AT&T
DQX2
Sinusoidal Input Level:
0 to -30 dBm0
-40 dBm0
35.30
29.30
24.30
dB
dB
dB
-45 dBm0
7
Idle Channel
Noise
C-message
NCX
NPX
NSFX
18
-67
-56
-46
dBrnC0 µ-Law Only
Psophometric
dBm0p CCITT G712
8
9
Single Frequency Noise
dBm0
dB
CCITT G712
Harmonic Distortion
Input Signal:
(2nd or 3rd Harmonic)
0 dBm0 @ 1.02 kHz
10
11
Envelope Delay
DAX
DDX
270
µs
@ 1004 Hz
Envelope Delay 1000-2600 Hz
60
µs
µs
µs
Input Signal:
400-3200 Hz
Sinewave
Variation With
Frequency
600-3000 Hz
400-3200 Hz
150
250
at 0 dBm0
17
Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
AC Electrical Characteristics - Transmit (A/D) Path - Voltages are with respect to GNDD unless otherwise stated.
TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz,
Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified.
A
N
A
L
Quantization
Distortion
CCITT G712
(Method 2)
AT&T
DQX2
Sinusoidal Input Level:
0 to -30 dBm0
-40 dBm0
35.30
29.30
24.30
dB
dB
dB
(cont’d)
(See Figure 13)
-45 dBm0
O
G
12
Intermodulation CCITT G712
IMDX
1
-55
-41
dB
dB
50/60 Hz @ -23 dBm0
and any signal within
300-3400 Hz at -9
dBm0
Distortion
50/60 Hz
CCITT G712
2 tone
IMDX
2
740 Hz and 1255 Hz
@ -4 to -21 dBm0.
Equal Input Levels
AT&T
IMDX
3
-47
-49
dB
dB
2nd order products
3rd order products
0 dBm0 Input Signal
4 tone
IMDX
4
13
Gain Relative to ≤50 Hz
Gain @ 1004 Hz 60 Hz
(See Figure 10) 200 Hz
GRX
-25
-30
dB
dB
dB
dB
dB
dB
dB
dB
dB
-1.8
-
0.00
0.125
0.125
0.030
-
Transmit
Filter
300-3000 Hz
3200 Hz
3300 Hz
3400 Hz
4000 Hz
≥4600 Hz
0.125
-
Response
0.275
-
0.100
-14
0.350
-0.80
-32
14
15
Crosstalk D/A to A/D
CTRT
-70
dB
0 dBm0 @ 1.02 kHz
in D/A
Power Supply
Rejection
VDD
VEE
PSS
R1
33
35
dB
dB
Input 50 mVRMS at
1.02 kHz
PSS
R2
16
Overload
Fig.15)
Distortion
(See
Input
frequency=1.02kHz
* Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing
Note 6:
0dBm0=1.185 VRMS for the µ-Law codec.
0dBm0=1.231 VRMS for the A-Law codec.
18
Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
AC Electrical Characteristics - Receive (D/A) Path - Voltages are with respect to GNDD unless otherwise stated.
TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz,
Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified.
Characteristics
Sym.
Min.
Typ.* Max.
Units
Test Conditions
1
Analog output at VR
VOUT
Level at codec:
µ-Law: 3.17 dBm0
A-Law: 3.14 dBm0
RL=10 KΩ
equivalent to the overload
decision level at codec
4.829
5.000
Vpp
Vpp
See Note 7
2
3
Absolute Gain (0dB setting)
GAR
-0.25
-0.35
+0.25
+0.35
dB
dB
0 dBm0 @ 1004Hz
Absolute Attenuation (-1dB
to -7dB settings)
From nominal,
@ 1004Hz
4
5
Gain Variation
With Temp.
GART
GARS
GTR1
0.01
0.04
dB
TA=0°C to 70°C
With Supplies
CCITT G712
dB/V
Gain Tracking
Sinusoidal Level:
+3 to -10 dBm0
Noise Signal Level:
-10 to -55 dBm0
-55 to -60 dBm0
(See Figure 12) (Method 1)
-0.25
+0.25
dB
-0.25
-0.50
+0.25
+0.50
dB
dB
CCITT G712
(Method 2)
AT & T
GTR2
DQR1
Sinusoidal Level:
+3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0
-0.25
-0.50
-1.50
+0.25
+0.50
+1.50
dB
dB
dB
A
N
A
L
6
Quantization
Distortion
CCITT G712
(Method 1)
Noise Signal Level:
-3 dBm0
28.00
35.60
33.90
29.30
14.30
dB
dB
dB
dB
dB
O
G
(See Fig. 13)
-6 to -27 dBm0
-34 dBm0
-40 dBm0
-55 dBm0
DQR2
Sinusoidal Input Level:
0 to -30 dBm0
-40 dBm0
CCITT G712
(Method 2)
AT & T
36.40
30.40
25.40
dB
dB
dB
-45 dBm0
7
Idle Channel
Noise
C-message
NCR
NPR
12
-75
-56
-46
dBrnC0 µ-Law Only
dBm0p CCITT G712
dBm0 CCITT G712
Psophometric
8
9
Single Frequency Noise
NSFR
Harmonic Distortion
dB
Input Signal 0 dBm0
(2nd or 3rd Harmonic)
at 1.02 kHz
10
Intermodulation CCITT G712
IMDR2
-41
dB
Distortion
2 tone
AT & T
4 tone
IMDR3
IMDR4
-47
-49
dB
dB
2nd order products
3rd order products
19
Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
AC Electrical Characteristics - Receive (D/A) Path - Voltages are with respect to GNDD unless otherwise stated.
TA=0 to 70°C, VDD=5V±5%, VEE=-5V±5%, VRef=2.5V±0.5%, GNDA=GNDD=0V, Clock Frequency = 2.048MHz,
Filter Gain Setting = 0dB. Outputs unloaded unless otherwise specified.
11
12
Envelope Delay
DAR
DDR
210
µs
@ 1004 Hz
Envelope Delay 1000-2600 Hz
Variation with 600-3000 Hz
90
µs
µs
µs
Input Signal:
170
265
400 - 3200 Hz digital
sinewave at 0 dBm0
Frequency
400-3200 Hz
13
Gain Relative to <200 Hz
GRR
0.125
0.125
0.125
0.030
-0.100
-14.0
dB
dB
dB
dB
dB
dB
dB
0 dBm0 Input Signal
Gain @ 1004 Hz 200 Hz
-0.5
A
N
A
L
(See Figure 11)
300-3000 Hz
-0.125
-0.350
-0.80
Receive
Filter
3300 Hz
3400 Hz
4000 Hz
≥4600 Hz
Response
O
G
-28.0
14
15
16
Crosstalk A/D to D/A
CTTR
-70
dB
0 dBm0 @ 1.02 kHz
in A/D
Power Supply
Rejection
VDD
VEE
PSRR3
PSRR4
33
35
dB
dB
Input 50 mVRMS at
1.02 kHz
Overload Distortion
(See Fig. 15)
Input frequency=1.02
kHz
* Typical figures are at 25°C with nominal ±5V supplies. For design aid only: not guaranteed and not subject to production testing.
Note 7: 0dBm0=1.185 VRMS for µ-Law codec and 0dBm0=1.231 VRMS for A-Law codec.
20
Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
125 µs
C2i
INPUT
F1i
INTERNAL
ENABLE
DSTo
HIGH IMPEDANCE
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
7
OUTPUT
DSTi
INPUT
7
7
6
6
5 V
CA
(Mode 3)
0 V
CSTi
INPUT
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
LOAD
A-REGISTER
LOAD
B-REGISTER
Figure 9a - Timing Diagram - 125 µs Frame Period
21
Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
8 CLOCK CYCLES
(See Note)
90%
50%
10%
C2i
Input
t
t
CF
CR
t
t
EF
ER
90%
10%
F1i
Input
t
t
t
t
t
t
EH
ES
EH
ES
EH
ES
DSTo
high
impedance
high-Z
Output
t
t
PZL
PZH
t
PZL
PZH
t
Figure 9b - Timing Diagram - Output Enable
Note:
In typical applications, F1i will remain low for 8 cycles of C2i. However, the device will function normally as long as t
and
ES
t
are met at each positive edge of C2i.
EH
90%
C2i
50%
10%
Input
t
t
CF
CR
90%
50%
10%
DSTo
Output
t
OR
t
OF
t
PLH
t
PLH
90%
50%
10%
DSTi, CSTi
Input
t
IF
t
IR
t
IH
t
ISL
t
ISH
Figure 9c - Timing Diagram - Input/Output
22
Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
SCALE B
SCALE A
PASSBAND ATTENUATION
SCALE A SCALE B
-0.125
STOPBAND ATTENUATION
0
-0.125
0.35
0.125
0.35
∏(4000-F)
SIN
-14
- 1
1200
1
10
14
10
1
∏(4000-F)
-18 SIN
Attenuation
Relative To
Attenuation
At 1 kHz (dB)
-7/9
1200
20
Note: Above function
crossover occurs
at 4000Hz.
20
25
30
2
2
3
4
30
32
3
4
40
40
0
5060100
200
300
3000
3200 3300 3400
4000
4600
5000
10000
FREQUENCY (Hz)
Figure 10 - Attenuation vs Frequency for Transmit (A/D) Filter
23
Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
SCALE A
-0.125
SCALE B
SCALE A
PASSBAND ATTENUATION
STOPBAND ATTENUATION
0
1
0.125
0.35
∏(4000-F)
SIN
-14
- 1
1200
10
14
1
2
3
4
Attenuation
Relative To
Attenuation
At 1 kHz (dB)
20
2
3
4
28
30
40
0
100
200
300
3000
3200 3300 3400
4000
4600
5000 10000
FREQUENCY (Hz)
Figure 11 - Attenuation vs Frequency for Receive (D/A) Filter
24
Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
5a. CCITT Method 1
CCITT End-To-End Spec
+1.0
+1.0
+0.5
+0.25
0
+0.5
+0.25
0
1
2
Channel Spec
Input Level
(dBm0)
-60 -55 -50
-40
-30
-20
-10
-10
0 -3
-0.25
-0.5
-0.25
-0.5
-1.0
-1.0
Bandlimited White Noise Test Signal
5b. CCITT Method 2
Sinusiodal Test Signal
+1.5
+1.0
+0.5
CCITT End-To-End Spec
1
Channel Spec
2
+0.25
0
Input Level
(dBm0)
-60
-50
-40
-30
-20
-10
0 +3
-0.25
-0.5
-1.0
-1.5
Sinusoidal Test Signal
Figure 12 - Variation of Gain With Input Level
25
Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
6a. CCITT Method 1
40
30
20
10
1
2
Channel Spec
35.6
33.9
33.9
32.2
29.3
28.0
27.6
26.3
CCITT End-To-End
Spec
14.3
12.6
0
-20
-10
-6
-3
0
+3
-60
-55
-50
-40
-34
-30 -27
Input Level (dBm0)
6b. CCITT Method 2
40
1
2
Channel Spec
D/A
36.4
36.4
35.3
33.0
1
Channel Spec
2
35.3
A/D
33.0
30.4
30
20
10
0
CCITT
29.3
27.0
End-To-End
Spec
25.4
24.3
22.0
-60
-50
-40
-30
-20
-10
0
Input Level (dBm0)
Figure 13 - Signal to Total Distortion Ratio vs Input Level
26
Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
1000
750
CCITT
½
Channel Spec
(2800Hz)
500
370
250
125
0
(600Hz)
(2600Hz)
2500
500
1000
1500
2000
3000
Figure 14 - Envelope Delay Variation Frequency
27
Zarlink Semiconductor Inc.
MT8960/61/62/63/64/65/66/67
Data Sheet
5
4.5
4
3
3
4
5
6
7
8
9
Input Level (dBm0)
*Relative to Fundamental Output power level with +3 dBm0 input signal level at a frequency of 1.02 kHz.
Figure 15 - Overload Distortion (End-to-End)
28
Zarlink Semiconductor Inc.
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相关型号：
MT8963ASR1
PCM Codec, A-Law, 1-Func, CMOS, PDSO20, 0.300 INCH, LEAD FREE, MS-013AC, SOIC-20
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