MT88E45ASR [ZARLINK]

Telephone Calling No Identification Circuit, CMOS, PDSO20, 0.300 INCH, SOIC-20;
MT88E45ASR
型号: MT88E45ASR
厂家: ZARLINK SEMICONDUCTOR INC    ZARLINK SEMICONDUCTOR INC
描述:

Telephone Calling No Identification Circuit, CMOS, PDSO20, 0.300 INCH, SOIC-20

文件: 总30页 (文件大小:525K)
中文:  中文翻译
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MT88E45  
4-Wire Calling Number Identification  
Circuit 2 (4-Wire CNIC2)  
Data Sheet  
August 2005  
Features  
Compatible with:  
Ordering Information  
Bellcore GR-30-CORE, SR-TSV-002476,  
ANSI/TIA/EIA-716, TIA/EIA-777;  
MT88E45BN  
MT88E45BS  
MT88E45BSR  
MT88EBNR  
20 Pin SSOP Tubes  
20 Pin SOIC  
20 Pin SOIC  
Tubes  
Tape & Reel  
ETSI ETS 300 778-1 (FSK only variant) & -2;  
BT (British Telecom) SIN227 & SIN242  
20 Pin SSOP Tape & Reel  
20 Pin SSOP* Tubes  
MT88E45BN1  
MT88E45BNR1 20 Pin SSOP* Tape & Reel  
*Pb Free Matte Tin  
Bellcore ‘CPE Alerting Signal’ (CAS), ETSI ‘Dual  
Tone Alerting Signal’ (DT-AS), BT Idle State and  
Loop State ‘Tone Alert Signal’ detection  
1200 baud Bell 202 and CCITT V.23 FSK  
demodulation  
-40°C to +85°C  
Applications  
Separate differential input amplifiers with  
adjustable gain for Tip/Ring and telephone hybrid  
or speech IC connections  
Bellcore CID (Calling Identity Delivery) and  
CIDCW (Calling Identity Delivery on Call Waiting)  
telephones and adjuncts  
Selectable 3-wire FSK data interface (bit stream  
or 1 byte buffer)  
Facility to monitor the stop bit for framing error  
check  
ETSI, BT CLIP (Calling Line Identity Presentation)  
and CLIP with Call Waiting telephones and  
adjuncts  
Fax and answering machines  
Computer Telephony Integration (CTI) systems  
FSK Carrier detect status output  
3 to 5V +/- 10% supply voltage  
Uses 3.579545 MHz crystal or ceramic resonator  
Low power CMOS with power down  
MODE  
FSKen+Tip/Ring CASen  
+
DATA  
IN1+  
IN1-  
GS1  
IN2+  
IN2-  
Anti-Alias  
Filter  
FSK  
FSK  
Data Timing  
Recovery  
Bandpass  
Demodulator  
-
DCLK  
PWDN  
PWDN  
PWDN  
FSKen  
CASen  
CD  
Carrier  
Detector  
+
-
DR  
DR/STD  
Hybrid CASen  
STD  
2130Hz  
Bandpass  
GS2  
PWDN  
CASen  
MODE  
FSKen  
Guard  
Time  
Tone  
Detection  
Algorithm  
ST/GT  
EST  
Bias  
Generator  
VREF  
2750Hz  
Bandpass  
Control Bit  
Decode  
PWDN  
Oscillator  
Vdd  
Vss  
CASen  
OSC1  
OSC2  
CB2  
CB0 CB1  
Figure 1 - Functional Block Diagram  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 2001-2005, Zarlink Semiconductor Inc. All Rights Reserved.  
MT88E45  
Data Sheet  
Description  
The MT88E45B is a low power CMOS integrated circuit suitable for receiving the physical layer signals used in  
North American (Bellcore) Calling Identity Delivery on Call Waiting (CIDCW) and Calling Identity Delivery (CID)  
services. It is also suitable for ETSI and BT Calling Line Identity Presentation (CLIP) and CLIP with Call Waiting  
services.  
The MT88E45B contains a 1200 baud Bell 202/CCITT V.23 FSK demodulator and a CAS/DT-AS detector. Two  
input op-amps allow the MT88E45B to be connected to both Tip/Ring and the telephone hybrid or speech IC  
receive pair for optimal CIDCW telephone architectural implementation. FSK demodulation is always on Tip/Ring,  
while CAS detection can be on Tip/Ring or Hybrid Receive. Tip/Ring CAS detection is required for the Bellcore/TIA  
Multiple Extension Interworking (MEI) and BT’s on-hook CLIP. A selectable FSK data interface allows the data to be  
processed as a bit stream or extracted from a 1 byte on chip buffer. Power management has been incorporated to  
power down the FSK or CAS section when not required. Full chip power down is also available. The MT88E45B is  
suitable for applications using a fixed power source (with a +/-10% variation) between 3 and 5 V.  
2
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
1
2
3
4
5
6
7
8
9
10  
20  
IN2+  
IN2-  
GS2  
CB2  
VREF  
IN1+  
MT88E45B  
19  
18  
17  
16  
15  
14  
13  
12  
11  
IN1-  
GS1  
Vss  
OSC1  
OSC2  
CB0  
CB1  
Vdd  
CD  
ST/GT  
EST  
DCLK  
DATA  
DR/STD  
Figure 2 - Pin Connections  
Pin Description  
Pin # Name  
Description  
1
VREF Voltage Reference (Output). Nominally Vdd/2. It is used to bias the Tip/Ring and Hybrid input op-  
amps.  
2
3
4
IN1+ Tip/Ring Op-amp Non-inverting (Input).  
IN1- Tip/Ring Op-amp Inverting (Input).  
GS1 Tip/Ring Gain Select (Output). This is the output of the Tip/Ring connection op-amp. The op-  
amp should be used to connect the MT88E45B to Tip and Ring. The Tip/Ring signal can be  
amplified or attenuated at GS1 via selection of the feedback resistor between GS1 and IN1-. FSK  
demodulation (which is always on Tip/Ring) or CAS detection (for MEI or BT on-hook CLIP) of the  
GS1 signal is enabled via the CB1 and CB2 pins. See Tables 1 and 2.  
5
6
Vss Power supply ground.  
OSC1 Oscillator (Input). Crystal connection. This pin can also be driven directly from an external clock  
source.  
7
8
OSC2 Oscillator (Output). Crystal connection. When OSC1 is driven by an external clock, this pin  
should be left open.  
CB0 Control Bit 0 (CMOS Input). This pin is used primarily to select the 3-wire FSK data interface  
mode. When it is low, interface mode 0 is selected where the FSK bit stream is output directly.  
When it is high, interface mode 1 is selected where the FSK byte is stored in a 1 byte buffer which  
can be read serially by the application’s microcontroller.  
The FSK interface is consisted of the DATA, DCLK and DR/STD pins. See the 3 pin descriptions  
to understand how CB0 affects the FSK interface.  
When CB0 is high and CB1, CB2 are both low the MT88E45B is put into a power down state  
consuming minimal power supply current. See Tables 1 and 2.  
9
DCLK 3-wire FSK Interface Data Clock (Schmitt Input/CMOS Output). In mode 0 (when the CB0 pin  
is logic low) this is a CMOS output which denotes the nominal mid-point of a FSK data bit.  
In mode 1 (when the CB0 pin is logic high) this is a Schmitt trigger input used to shift the FSK data  
byte out to the DATA pin.  
3
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
Pin Description  
Pin # Name  
Description  
10  
DATA 3-wire FSK Interface Data (CMOS Output). Mark frequency corresponds to logical 1. Space  
frequency corresponds to logical 0.  
In mode 0 (when the CB0 pin is logic low) the FSK serial bit stream is output to the DATA pin  
directly.  
In mode 1 (when the CB0 pin is logic high) the start bit is stripped off, the data byte and the trailing  
stop bit are stored in a 9 bit buffer. At the end of each word signalled by the DR/STD pin, the  
microcontroller should shift the byte out onto the DATA pin by applying 8 read pulses to the DCLK  
pin. A 9th DCLK pulse will shift out the stop bit for framing error checking.  
11 DR/STD 3-wire FSK Interface Data Ready/CAS Detection Delayed Steering (CMOS Output). Active  
low.  
When FSK demodulation is enabled via the CB1 and CB2 pins this pin is the Data Ready output.  
It denotes the end of a word. In both FSK interface modes 0 and 1, it is normally hi and goes low  
for half a bit time at the end of a word. But in mode 1 if DCLK starts during DR low, the first rising  
edge of the DCLK input will return DR to high. This feature allows an interrupt requested by a low  
going DR to be cleared upon reading the first DATA bit.  
When CAS detection is enabled via the CB1 and CB2 pins this pin is the Delayed Steering output.  
It goes low to indicate that a time qualified CAS has been detected.  
12  
EST CAS Detection Early Steering (CMOS Output). Active high. This pin is the raw CAS detection  
output. It goes high to indicate the presence of a signal meeting the CAS accept frequencies and  
signal level. It is used in conjunction with the ST/GT pin and external components to time qualify  
the detection to determine whether the signal is a real CAS.  
13 ST/GT CAS Detection Steering/Guard Time (CMOS Output/Analog Input). It is used in conjunction  
with the EST pin and external components to time qualify the detection to determine whether the  
signal is a real CAS.  
A voltage greater than VTGt at this pin causes the MT88E45B to indicate that a CAS has been  
detected by asserting the DR/STD pin low. A voltage less than VTGt frees up the MT88E45B to  
accept a new CAS and returns DR/STD to high.  
14  
CD  
Carrier Detect (CMOS Output). Active low.  
A logic low indicates that an FSK signal is present. A time hysteresis is provided to allow for  
momentary signal discontinuity. The demodulated FSK data is ignored by the MT88E45B until  
carrier detect has been activated.  
15  
16  
Vdd Positive power supply.  
CB1 Control Bit 1 (CMOS Input). Together with CB2 this pin selects the MT88E45B’s functionality  
between FSK demodulation, Tip/Ring CAS detection and Hybrid CAS detection.  
When CB0 is high and CB1, CB2 are both low the MT88E45B is put into a power down state  
consuming minimal power supply current. See Tables 1 and 2.  
17  
18  
CB2 Control Bit 2 (CMOS Input). Together with CB1 this pin selects the MT88E45B’s functionality  
between FSK demodulation, Tip/Ring CAS detection and Hybrid CAS detection.  
When CB0 is high and CB1, CB2 are both low the MT88E45B is put into a power down state  
consuming minimal power supply current. See Tables 1 and 2.  
GS2 Hybrid Gain Select (Output). This is the output of the hybrid receive connection op-amp. The op-  
amp should be used to connect the MT88E45B to the telephone hybrid or speech IC receive pair.  
The hybrid receive signal can be amplified or attenuated at GS2 via selection of the feedback  
resistor between GS2 and IN2-. When the CPE is off-hook CAS detection of the GS2 signal  
should be enabled via the CB1 and CB2 pins. See Tables 1 and 2.  
19  
20  
IN2- Hybrid Op-amp Inverting (Input).  
IN2+ Hybrid Op-amp Non-Inverting (Input).  
4
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
FSK  
CB0 CB1 CB2  
Function  
Interface  
0/1  
0/1  
0/1  
1
1
0
1
0
1
Set by CB0 FSK Demodulation. Tip/Ring input (GS1) selected. DR/STD is DR.  
Set by CB0 Hybrid CAS Detection. Hybrid Receive input (GS2) selected. DR/STD is STD.  
Set by CB0 Tip/Ring CAS Detection. Tip/Ring input (GS1) selected. DR/STD is STD.  
When the line is off-hook, a Bellcore/TIA Multiple Extension Interworking (MEI)  
compatible Type 2 CPE should be able to detect CAS from Tip/Ring while the  
CPE is on-hook because it may be the ACK sender. Tip/Ring CAS detection is  
also required for BT’s on-hook CLIP.  
1
0
0
0
0
0
Mode 1 Power Down. The MT88E45B is disabled and draws virtually no power supply  
current.  
Mode 0 Reserved for factory testing.  
Table 1 - CB0/1/2 Functionality  
The number of control bits (CB) required to interface the MT88E45B with the microcontroller depends on the  
functionality of the application, as shown in Table 2.  
Functionality Group  
Controls  
Description  
FSK (mode 0 or 1) and  
CB2  
CB0 is hardwired to Vdd or Vss to select the FSK  
Hybrid CAS only  
interface.  
(Non MEI compatible)  
CB1 hardwired to Vdd.  
The microcontroller uses CB2 to select between the 2  
functions.  
FSK (mode 0 or 1),  
Hybrid CAS,  
CB1  
CB2  
CB0 is hardwired to Vdd or Vss to select the FSK  
interface.  
Tip/Ring CAS  
The microcontroller uses CB1 and CB2 to select between  
the 3 functions.  
(MEI compatible or BT on-hook CLIP)  
FSK (mode 1),  
CB1  
CB2  
CB0 is hardwired to Vdd to select FSK interface mode 1.  
The microcontroller uses CB1 and CB2 to select between  
the 4 functions.  
Hybrid CAS,  
Tip/Ring CAS,  
Power Down  
(MEI compatible or BT on-hook CLIP)  
FSK (mode 0), Hybrid CAS,  
CB0  
CB1  
CB2  
All 3 pins are required.  
Tip/Ring CAS, Power Down  
(MEI compatible or BT on-hook CLIP)  
Table 2 - Control Bit Functionality Groups  
Functional Overview  
The MT88E45B is compatible with FSK and FSK plus CAS (CPE Alerting Signal) based Caller ID services around  
the world. Caller ID is the generic name for a group of services offered by telephone operating companies whereby  
information about the calling party is delivered to the subscriber. In Europe and some other countries Caller ID is  
known as Calling Line Identity Presentation (CLIP). ETSI calls CAS ‘Dual Tone Alerting Signal’ (DT-AS), BT calls it  
Tone Alert Signal’.  
Depending on the service, data delivery can occur when the line is in the on-hook or off-hook state. In most  
countries the data is modulated in either Bell 202 or CCITT V.23 FSK format and transmitted at 1200 baud from the  
serving end office to the subscriber’s terminal. Additionally in off-hook signalling, the special dual tone CAS is used  
5
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
to alert the terminal before FSK data transmission. BT uses CAS to alert the terminal prior to FSK in both on-hook  
(Idle State) and off-hook (Loop State) signalling.  
In North America, Caller ID uses the voiceband data transmission interface defined in the Bellcore document GR-  
30-CORE. The terminal or CPE (Customer Premises Equipment) requirements are defined in Bellcore document  
SR-TSV-002476. Typical services are CND (Calling Number Delivery), CNAM (Calling Name Delivery), VMWI  
(Visual Message Waiting Indicator) and CIDCW (Calling Identity Delivery on Call Waiting).  
In Europe, Caller ID requirements are defined by ETSI. The CPE documents are ETS 300 778-1 for on-hook, ETS  
300 778-2 for off-hook. The end office requirements are ETS 300 659-1 (on-hook) and ETS 300 659-2 (off-hook).  
ETSI has defined services such as CLIP and CLIP with Call Waiting which are similar to those of Bellcore. Some  
European countries produce their own national specifications. For example, in the UK BT’s standards are SIN227  
and SIN242, the UK CCA (Cable Communications Association) standard is TW/P&E/312.  
In on-hook Caller ID, such as CND, CNAM and CLIP, the information is typically transmitted (in FSK) from the end  
office before the subscriber picks up the phone. There are various methods such as between the first and second  
rings (North America), between an abbreviated ring and the first true ring (Japan, France and Germany). On-hook  
Caller ID can also occur without ringing for services such as VMWI. In BT’s on-hook CLIP, the signalling begins with  
a line polarity reversal, followed by CAS and then FSK. Bellcore calls an on-hook capable Caller ID CPE a ‘Type 1  
CPE’.  
In off-hook Caller ID, such as CIDCW and CLIP with Call Waiting, information about a new calling party is sent to  
the subscriber who is already engaged in a call. Bellcore’s method uses CAS to alert the CPE. When the CPE  
detects CAS and there are no off-hook extensions, the CPE should mute its transmission path and send an  
acknowledgment to the end office via a DTMF digit called ACK. Upon receiving ACK, the end office will send the  
FSK data. Bellcore calls an off-hook capable CPE a ‘Type 2 CPE’. A Type 2 CPE is capable of off-hook and Type 1  
functionalities and should ACK with a DTMF ‘D’. The ETSI and BT off-hook signalling protocols are similar to  
Bellcore’s but with timing and signal parametric differences. ETSI has no requirement for off-hook extension  
checking before ACK.  
One factor affecting the quality of the CIDCW service is the CPE’s CAS speech immunity. Although the end office  
has muted the far end party before and after it sends CAS, the near end (the end which is to receive the  
information) user may be still talking. Therefore the CPE must be able to detect CAS successfully in the presence  
of near end speech. This is called the talkdown immunity. The CPE must also be immune to imitation of CAS by  
speech from both ends of the connection because the CAS detector is continuously exposed to speech throughout  
the call. This is called the talkoff immunity.  
If the CPE is a telephone, one way to achieve good CAS speech immunity is to put CAS detection on the telephone  
hybrid or speech IC receive pair instead of on Tip and Ring. Talkdown immunity improves because the near end  
speech has been attenuated while the CAS level is the same as on Tip/Ring, resulting in improved signal to speech  
ratio. Talkoff immunity is also improved because the near end speech has been attenuated.  
In the Bellcore SR-TSV-002476 Issue 1 off-hook protocol, the CPE should not ACK if it detected an off-hook  
extension. The FSK will not be sent and the customer will not receive the Call Waiting ID. Bellcore, together with the  
TIA (Telecommunications Industry Association) TR41.3.1 working group, has defined a CPE capability called  
Multiple Extension Interworking (MEI) which overcomes this problem.  
In the MEI scheme, all MEI compatible CPEs must be capable of detecting CAS when the line is off-hook, even  
though the CPE itself may be on-hook. This is because under some conditions an on-hook CPE may become the  
ACK sender. Another reason for the on-hook CPE to detect CAS is to maintain synchronous call logs between on  
and off-hook CPEs. When CAS is received and all off-hook CPEs are MEI compatible, one of the CPEs will ACK  
and all compatible CPEs will receive FSK.  
A problem arises in a CPE where the CAS detector is connected only to the hybrid or speech IC receive pair: it  
cannot detect CAS when it is on-hook. The reason is that when the CPE is on-hook either the hybrid/speech IC is  
non functional or the signal level is severely attenuated. Therefore an on-hook Type 2 CPE must be capable of  
6
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
detecting CAS from Tip/Ring, in addition to detecting CAS from the hybrid/speech IC receive signal when it is off-  
hook.  
The MT88E45B offers an optimal solution which combines good speech immunity and MEI compatibility. Two input  
op-amps allow the MT88E45B to be connected both to Tip/Ring and to the hybrid/speech IC receive pair. Both  
connections can be differential or single ended. FSK demodulation is always on the Tip/Ring signal. CAS detection  
can be from the Tip/Ring or hybrid/speech IC receive signal. Being able to detect CAS on Tip/Ring also makes the  
MT88E45B suitable for BT on-hook CLIP applications.  
For applications such as those in most European countries where Tip/Ring CAS detection is not needed, then the  
Tip/Ring and Hybrid op-amp gains can be tailored independently to meet country specific FSK and CAS signal level  
requirements respectively. Note that since the Hybrid op-amp is for CAS detection only, its gain can always be  
tailored specifically for the CAS signal level.  
The FSK demodulator is compatible with Bellcore, ETSI and BT standards. The demodulated FSK data is either  
output directly (bit stream mode) or stored in a one byte buffer (buffer mode). In the buffer mode, the stop bit  
immediately following a byte is also stored and can be shifted out after the data byte. This facility allows for framing  
error checking required in Type 2 CPEs. In the bit stream mode, two timing signals are provided. One indicates the  
bit sampling instants of the data byte, the other the end of byte. A carrier detector indicates presence of signal and  
shuts off the data stream when there is no signal.  
The entire chip can be put into a virtually zero current power down mode. The input op-amps, FSK demodulator,  
CAS detector and the oscillator are all shut off. Furthermore, power management has been incorporated to  
minimize operating current. When FSK is selected the CAS detector is powered down. When CAS is selected the  
FSK demodulator is powered down.  
Functional Description  
3 to 5 V Operation  
The MT88E45B’s FSK and CAS reject levels are proportional to Vdd. When operated at Vdd equal 3 V +/- 10%, to  
keep the FSK and CAS reject levels as at 5 V (nominal) the Tip/Ring and Hybrid op-amp gains should be reduced  
from those of 5 V. Gains for nominal Vdd (with a +/- 10% variation) other than 3 or 5 V can be chosen as  
interpolation between the 3 and 5 V settings.  
Input Configuration  
The MT88E45B provides an input arrangement comprised of two op-amps and a bias source (VREF). VREF is a low  
impedance voltage source which is used to bias the op-amp inputs at Vdd/2. The Tip/Ring op-amp (IN1+, IN1-, GS1  
pins) is for connecting to Tip and Ring. The Hybrid op-amp (IN2+, IN2-, GS2 pins) is for connecting to the telephone  
hybrid or speech IC receive pair.  
Either FSK or CAS detection can be selected for the Tip/Ring connection, while the hybrid connection is for CAS  
detection only. Phrased in another way, FSK demodulation is always on Tip/Ring, while CAS detection can be on  
Tip/Ring or Hybrid Receive. Tip/Ring CAS detection is required for MEI and BT on-hook CLIP, while Hybrid CAS  
detection is needed for optimal CAS speech immunity.  
The feedback resistor connected between GS1 and IN1- can be used to adjust the Tip/Ring signal gain. The  
feedback resistor connected between GS2 and IN2- can be used to adjust the hybrid receive signal gain. When the  
Tip/Ring op-amp is selected, the GS2 signal is ignored. When the Hybrid op-amp is selected, the GS1 signal is  
ignored.  
Either or both op-amps can be configured in the single ended input configuration shown in Figure 33, or in the  
differential input configuration shown in Figure 44.  
7
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
IN+  
IN-  
R
C
IN  
GS  
R
F
Voltage Gain  
(AV) = RF / RIN  
VREF  
Highpass Corner Frequency  
f-3dB = 1/(2πRINC)  
Figure 3 - Single Ended Input Configuration  
R1  
R4  
IN+  
IN-  
C1  
C2  
R5  
GS  
R2  
R3  
VREF  
Differential Input Amplifier  
C1 = C2  
R1 = R4 (For unity gain R5= R4)  
R3 = (R2R5) / (R2 + R5)  
Voltage Gain  
Highpass Corner Frequency  
(A diff) = R5/R1  
V
f
-3dB = 1/(2πR1C1)  
Input Impedance  
R12 + (1/ωC)2  
(Z diff) = 2  
IN  
Figure 4 - Differential Input Configuration  
CAS Detection  
In North America, CAS is used in off-hook signalling only. In Europe (ETSI) it is used in off-hook signalling, and by  
BT in both on and off-hook signalling. ETSI calls it the Dual Tone Alerting Signal (DT-AS). Although the ETSI on-  
hook standard contains a DT-AS specification, BT is the only administration known to employ CAS in on-hook  
signalling. (BT calls it Tone Alert Signal.) The CAS/DT-AS characteristics are summarized in Table 3.  
BTc  
2130 Hz and 2750 Hz  
Bellcorea  
ETSIb  
(Off-hook = ‘Loop State’)  
(On-hook = ‘Idle State’)  
CAS/DT-AS Characteristics  
(Off-hook only)  
(Off-hook)  
Frequency Tolerance  
Signal Level (per tone)  
Reject Level (per tone)  
+/-0.5%  
-14 to -32 dBmd  
-45 dBm  
+/-0.5%  
Off-hook: +/-0.6%  
On-hook: +/-1.1%  
+0.22 to -37.78 dBm  
(-2 to -40 dBV)  
On-hook: -43.78 dBm  
(-46 dBV)  
-9.78 to -32.78 dBm  
(-12 to -35 dBVe)  
Maximum Twist (V2130Hz/V2750Hz  
)
+/-6 dB  
+/-6 dB  
+/-7 dB  
8
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
BTc  
2130 Hz and 2750 Hz  
Bellcorea  
ETSIb  
(Off-hook = ‘Loop State’)  
(On-hook = ‘Idle State’)  
CAS/DT-AS Characteristics  
(Off-hook only)  
(Off-hook)  
Duration  
75 to 85 ms  
75 to 85 ms  
Off-hook: 80 to 85 ms  
On-hook: 88 to 110 ms  
Reject Duration  
Signal to Noise Ratio  
Off-hook: <=70 ms  
On-hook: <=20 ms  
Off-hook: Speech  
On-hook: >= 20 dB  
(300-3400 Hz)  
Speech  
Speech  
Hybrid Op-amp (GS2) Gain  
Vdd = 5V +/- 10%  
0 to -5 dB  
0 to -5 dB  
0 dB  
Hybrid Op-amp (GS2) Gain  
-3.5 to -8.5 dB  
-3.5 to -8.5 dB  
-3.5 dB  
Vdd = 3V +/- 10%  
a. SR-TSV-002476, Issue 1 Dec 1992  
b. ETS 300 778-2 Jan 98. The DT-AS plus FSK variant of ETSI on-hook signalling described in ETS 300 778-1 is not supported  
because on-hook DT-AS uses the GS1 op-amp. With the GS1 gain in Table 4, the DT-AS minimum level will be below the  
MT88E45B’s minimum accept level.  
c. SIN227 Issue 3 Nov 97, SIN242 Issue 2 Nov 96  
d. dBm - Decibels above or below a reference power of 1 mW into 600 ohms. 0 dBm = 0.7746 Vrms.  
e. dBV - Decibels above or below a reference voltage of 1 Vrms. 0 dBV = 1 Vrms  
Table 3 - CAS/DT-AS Characteristics  
Table 3 shows the Hybrid op-amp (GS2) gain for operation at 3 V and 5 V nominal Vdd, with a ± 10% Vdd variation.  
For 3 V operation, the Hybrid op-amp gain should be reduced from the 5 V setting to maintain the CAS reject level  
and to maintain the talkoff immunity: the CAS threshold is directly proportional to Vdd, when Vdd is reduced the  
threshold becomes lower, hence lower level CAS are accepted. If the gain is not reduced, the MT88E45B will be  
more talkoff prone. In Table 3, the GS2 gain is shown as a range. By adopting the lower gain, talkoff immunity can  
be improved.  
When CAS detection is selected, the dual purpose output pin DR/STD is STD. STD goes low when CAS has been  
detected, and returns high after CAS has ended.  
CAS Guard Time  
The guard time circuit shown in Figure 55 implements a timing algorithm which determines whether the signal is a  
CAS. Proper selection of the guard time(s) is key to good speech immunity. The first indication that there might be a  
CAS is when EST goes high. EST high indicates that both tones are present. EST low indicates that one or both  
tones is not present. STD low indicates that CAS has been detected. When STD returns high it indicates that CAS  
has ended.  
The timing algorithm consists of 2 components: a tone present guard time (tGP) and a tone absent guard time (tGA).  
tGP sets the minimum accept duration for CAS. That is, both tones must be detected continuously for tGP for STD to  
go low to indicate that CAS has been detected. For STD to return high to indicate that CAS has ended, one or both  
tones must have disappeared for tGA. The purpose of tGA is to bridge over momentary EST dropouts once EST has  
met the minimum tone duration so as to decrease the likelihood of a long talkoff being broken up into several  
talkoffs. Usually tGA is set very short or removed altogether because there is another way to deal with the problem  
(by ignoring further detections for 2 seconds after every detection).  
9
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
MT88E45B  
Vdd  
Both Tones Present  
P
N
Q1  
C
+
ST/GT  
R1  
-
VTGt  
Vdiode  
R2  
Comparator  
Q2  
= Vss  
Rp=R1 || R2  
EST  
DR/STD  
Indicates STD in CAS  
detection mode  
CAS  
tDP  
tDA  
tABS  
tGP=R1C ln [Vdd / (Vdd-VTGt)]  
EST  
tREC  
tGA=RpC ln Vdd - Vdiode (Rp/R2)  
VTGt - Vdiode (Rp/R2)  
Rp=R1 || R2  
tGP  
tGA  
ST/GT  
STD  
tGA=0 if R2=0  
Figure 5 - CAS Guard Time Circuit Operation  
Tone present guard time (tGP) operation: In Figure 5 5 initially there is no CAS, EST is low so Q1 is off. C has been  
fully charged applying 0 V to ST/GT so Q2 is on. When both tones are detected EST goes high and turns off Q2.  
Because C has been fully charged (ST/GT=0V), the comparator output is low and Q1 stays off. With both Q1 and  
Q2 off the high at EST discharges C through R1 and the ST/GT voltage increases from 0 V. When the voltage  
exceeds the comparator threshold VTGt, which is typically 0.5 Vdd, the comparator output goes high; Q1 turns on  
and accelerates the discharge of C (ST/GT goes quickly to Vdd); STD goes low to indicate that a valid CAS has  
been received. If one or both tones disappeared before tGP has been reached (i.e. when ST/GT voltage is still below  
VTGt), Q2 turns back on and charges C quickly to bring the ST/GT voltage back to 0 V. Then if EST goes high again  
the tGP duration must start over.  
Tone absent guard time (tGA) operation: In Figure 5 5 initially both tones have been detected for tGP so C is fully  
discharged and ST/GT is at Vdd. While both tones continue to be detected EST stays high; ST/GT is at Vdd (the  
comparator output is high); so Q1 is on and Q2 is off. When one or both tones stop EST goes low and turns off Q1.  
Because C is fully discharged (ST/GT=Vdd), the comparator output is high and Q2 stays off. With both Q1 and Q2  
off the low at EST charges C through Rp=(R1 || R2) and the ST/GT voltage falls towards 0V. When the voltage has  
fallen below VTGt, the comparator output goes low. Since EST is also low Q2 turns on and accelerates the  
charging of C so that ST/GT goes quickly to 0V. STD goes high to indicate that the CAS has ended. If EST goes  
back to high before tGA has been reached (i.e. when ST/GT voltage is still above VTGt), Q1 turns back on and  
discharges C quickly to bring the ST/GT voltage back to Vdd. Then if EST goes low again the tGA duration must start  
over. To set tGA=0, set R2 to 0.  
10  
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
In Figure 55, tDP is the delay from the start of CAS to EST responding, tDA is the delay from the end of CAS to EST  
responding. The total delay from the start of CAS to STD responding is tREC=tDP+tGP. The total delay from the end of  
CAS to STD responding is tABS=tDA+tGA.  
Parameter  
North America: Bellcorea  
Europe: ETSIb  
1300 Hz +/- 1.5%  
2100 Hz +/- 1.5%  
UK: BTc  
Mark (Logical 1) Frequency  
Space (Logical 0) Frequency  
Received Signal Level  
1200 Hz +/- 1%  
2200 Hz +/- 1%  
-4.23 to -36.20 dBm  
(476 to 12 mVrms)d  
-5.78 to -33.78 dBme  
-5.78 to -37.78 dBm  
(-8 to -40 dBV)  
(-8 to -36 dBV)f,g  
Signal Reject Level  
-48.24 dBm (3mVrms) for  
On-hook No Ring Signalling  
such as VMWI  
On-hook only:  
-47.78 dBm  
(-50dBV)  
Transmission Rate  
1200 baud +/- 1%  
-6 to +10 dB  
1200 baud +/- 1%  
-6 to +6 dB  
Twist (VMARK/VSPACE  
)
Signal to Noise Ratio  
Single Tone (f):  
-18 dB (f<=60Hz)  
>= 25 dB  
>= 20 dB  
(300 to 3400 Hz)  
(300 to 3400 Hz)  
-12 dB (60<f<=120Hz)  
-6 dB (120<f<=200Hz)  
+25 dB (200<f<3200Hz)  
+6 dB (f>=3200Hz)  
Tip/Ring Op-Amp (GS1) Gain  
Vdd = 5V +/- 10%  
0 dB  
-2 dBh  
0 dB  
Tip/Ring Op-Amp (GS1) Gain  
Vdd = 3V +/- 10%  
-3.5 dB  
-5.5 dBi  
-3.5 dB  
a. ANSI/TIA/EIA-716 and TIA/EIA-777. Bellcore has agreed to the values and will synchronize its requirements.  
b. ETS 300 778-1 (On-hook) Sep 97, ETS 300 778-2 (Off-hook) Jan 98.  
c. SIN 227 Issue 3 Nov 97, SIN242 Issue 2 Nov 96.  
d. North American on-hook signalling range. The off-hook range is inside the on-hook range: 190mVrms to 12mVrms.  
e. dBm - Decibels above or below a reference power of 1 mW into 600 ohms. 0 dBm = 0.7746 Vrms  
f. dBV - Decibels above or below a reference voltage of 1 Vrms. 0 dBV = 1 Vrms.  
g. ETSI on-hook signalling range. The off-Hook signalling levels are inside this range: -8.78 to -30.78 dBm (-11 to -33 dBV).  
h. The 5V ETSI Tip/Ring op-amp gain can be 0 dB if there is no FSK reject level requirement.  
i. The 3V ETSI Tip/Ring op-amp gain can be -3.5dB if there is no FSK reject level requirement.  
Table 4 - FSK Signal Characteristics  
FSK Demodulation  
The FSK characteristics are shown in Table 4. In North America, TIA (Telecommunications Industry Association)  
also sets standards. The Type 1 Caller ID CPE standard is ANSI/TIA/EIA-716. The Type 2 standard is TIA/EIA-777.  
The North American FSK characteristics in Table 4 are from ANSI/TIA/EIA-716. They differ from those Bellcore  
published in SR-TSV-002476 and SR-3004. Bellcore is represented in TR41.3.1 and will synchronize to the TIA  
requirements in its future documents.  
The TIA Type 1 standard includes an FSK reject level:  
if data is not preceded by ringing (e.g., VMWI), FSK signals below 3mVrms (-48.24 dBm) shall be rejected  
if data is preceded by ringing, FSK detection may be extended below 3mVrms  
The MT88E45B is compliant with the Bellcore/TIA, ETSI and BT requirements with the Tip/Ring op-amp gains in  
Table 4. In Europe if the country specific FSK requirements do not incorporate ETSI’s FSK reject level then the  
Tip/Ring op-amp gain can also be 0 dB at 5 V and -3.5 dB at 3 V to meet the ETSI minimum CAS level for on-hook  
signalling (-40 dBV).  
11  
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
For 3 V operation, the FSK receiver becomes more sensitive and lower level signals will be accepted than at 5 V. To  
maintain the FSK reject level, the Tip/Ring input op-amp gain should be reduced. Note that since the Tip/Ring op-  
amp is also used for Tip/Ring CAS detection, the CAS level will also be reduced for on-hook detection.  
FSK Data Interface  
The MT88E45B provides a powerful dual mode 3-wire interface so that the data bytes in the demodulated FSK bit  
stream can be extracted without the need either for an external UART or for the CPE’s microcontroller to perform  
the function in software. The interface is specifically designed for the 1200 baud rate and is consisted of 3 pins:  
DATA, DCLK (Data Clock) and DR (Data Ready). DR/STD is a dual purpose output pin. When FSK is selected it is  
DR.  
Two modes (modes 0 and 1) are selectable via the CB0 pin. In mode 0, the FSK bit stream is output directly. In  
mode 1, the data byte and the trailing stop bit are stored in a 9 bit buffer. If mode 1 is desired, the CB0 pin can be  
hardwired to Vdd. If mode 0 is desired and full chip power down is not required, the CB0 pin can be hardwired to  
Vss.  
In Bellcore’s off-hook protocol, a Type 2 CPE should restore the voicepath within 50 ms after the end of the FSK  
signal. Due to noise, end of carrier detection is not always reliable. The TIA Type 2 standard stipulates that the CPE  
must detect the end of FSK when any one of the following occurs:  
absence of carrier signal or,  
more than five framing errors (trailing stop bit a 0 instead of a 1) have been detected in the FSK message or,  
more than 150 ms of continuous mark signal or space signal has been detected.  
Mode 0 - Bit Stream Mode  
This mode is selected when the CB0 pin is low. In this mode the FSK data is output directly to the DATA pin. DCLK  
and DR pins are timing signal outputs (see Figure 13.  
For each received stop and start bit sequence, the MT88E45B outputs a fixed frequency clock string of 8 pulses at  
the DCLK pin. Each DCLK rising edge occurs in the middle of a DATA bit cell. DCLK is not generated for the start  
and stop bits. Consequently, DCLK will clock only valid data into a peripheral device such as a serial to parallel shift  
register or a microcontroller. The MT88E45B also outputs an end of word pulse (Data Ready) at the DR pin. DR  
goes low for half a nominal bit time at the beginning of the trailing stop bit. It can be used to interrupt a  
microcontroller or cause a serial to parallel converter to parallel load its data into the microcontroller. Since the DR  
rising edge occurs in the middle of the stop bit, it can also be used to read the stop bit to check for framing error.  
Alternatively, DCLK and DATA may occupy 2 bits of a microcontroller’s input port. The microcontroller polls the  
input port and saves the DATA bit whenever DCLK changes from low to high. When DR goes low, the word may  
then be assembled from the last 8 saved bits.  
DATA may also be connected to a personal computer’s serial communication port after conversion from CMOS to  
RS-232 voltage levels.  
Mode 1 - Buffer Mode  
This mode is selected when the CB0 pin is high. In this mode the received byte is stored on chip. At the end of a  
byte DR goes low to indicate that a new byte has become available. The microcontroller applies DCLK pulses to  
read the register contents serially out of the DATA pin (see Figure 1414).  
Internal to the MT88E45B, the start bit is stripped off, the data bits and the trailing stop bit are sampled and stored.  
Midway through the stop bit, the 8 data bits and the stop bit are parallel loaded into a 9 bit shift register and DR  
goes low. The register’s contents are shifted out to the DATA pin on the supplied DCLK’s rising edges in the order  
they were received. The last bit must be shifted out and DCLK returned to low before the next DR. DCLK must be  
low for tDDS before DR goes low and must remain low for tDDH after DR has gone low (see Figure 14).  
12  
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
If DCLK begins while DR is low, DR will return to high upon the first DCLK rising edge. If DR interrupts a  
microcontroller then this feature allows the interrupt to be cleared by the first read pulse. Otherwise DR is low for  
half a nominal bit time (1/2400 sec).  
Reading the stop bit allows the software to check for framing errors. When framing error is not checked the  
microcontroller only needs to send 8 DCLK pulses to shift the data byte out.  
Carrier Detect  
The carrier detector provides an indication of the presence of a signal in the FSK frequency band. It detects the  
presence of a signal of sufficient amplitude at the output of the FSK bandpass filter. The signal is qualified by a  
frequency aware digital algorithm before the CD output is set low to indicate carrier detection. A 10 ms hysteresis is  
provided to allow for momentary signal dropout once CD has been activated. CD is released when there is no  
activity at the FSK bandpass filter output for 10 ms.  
When CD is inactive (high), the raw output of the FSK demodulator is ignored by the internal data timing recovery  
circuit. In mode 0 the DATA, DCLK and DR pins are forced high. In mode 1 the output shift register is not updated  
and DR is high; if DCLK is clocked, DATA is undefined.  
Note that signals such as speech, CAS and DTMF tones also lie in the FSK frequency band and the carrier detector  
may be activated by these signals. They will be demodulated and presented as data. To avoid the false data, the  
MT88E45B should be put into CAS or power down mode when FSK is not expected. Ringing, on the other hand,  
does not pose a problem as it is ignored by the carrier detector.  
Interrupt  
The DR/STD output can be used to interrupt a microcontroller. When the MT88E45B is the only interrupt source,  
DR/STD can be connected directly to the microcontroller’s interrupt input. Figure 9 shows the necessary  
connections when the MT88E45B is one of many interrupt sources. The diodes and resistors implement a wired-or  
so that the microcontroller is interrupted (INT low active or falling edge triggered) when one or more of INT1, INT2  
or DR/STD is low. The microcontroller can determine which one of DR/STD, INT1 or INT2 caused the interrupt by  
reading them into an input port.  
When system power is first applied and CB0/1/2 have already been configured to select CAS detection, DR/STD  
will power up as logic low. This is because there is no charge across the ST/GT capacitor in Figure 55, hence  
ST/GT is at Vdd which causes STD to be low. If DR/STD is used to interrupt a microcontroller the interrupt will not  
clear until the capacitor has charged up. Therefore upon initial power up the microcontroller should ignore this  
interrupt source until there is sufficient time to charge the capacitor. Alternatively, the MT88E45B can be put into  
power down mode: DR/STD goes high and clears the interrupt, ST/GT goes low and the capacitor will charge up  
quickly.  
Power Down  
The MT88E45B can be powered down to consume virtually no power supply current via a state of the CB0/1/2 pins.  
Momentary transition of CB0/1/2 into the power down code will not activate power down.  
In power down mode both input op-amps, VREF and the oscillator are non functional. DCLK becomes an input  
because to select the power down state CB0 is 1 which will select FSK interface mode 1. If the application uses  
FSK interface mode 0 and the MT88E45B needs to be powered down then a pull down resistor should be added  
at the DCLK pin to define its state during power down (R15 in Figure 7). When the MT88E45B is powered down  
DATA, DR/STD, CD are high; EST and ST/GT are low.  
To reduce the operating current an Intelligent Power Down feature has been incorporated. When FSK is selected,  
the CAS detector is powered down. When CAS is selected the FSK demodulator is powered down. The two input  
op-amps are not affected and both will remain operational.  
13  
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
Oscillator  
The MT88E45B requires a 3.579545 MHz crystal or ceramic resonator to generate its oscillator clock. To meet the  
CAS detection frequency tolerance specifications the crystal or resonator must have a 0.1% frequency tolerance.  
The crystal specification is as follows: (e.g., CTS MP036S)  
Frequency:  
3.579545 MHz  
± 0.1% (over temperature  
range of the application)  
Parallel  
Frequency Tolerance:  
Resonance Mode:  
Load Capacitance:  
Maximum Series  
Resistance:  
18 pF  
150 Ω  
Maximum Drive Level:  
2 mW  
Alternatively an external clock source can be used. In which case the OSC1 pin should be driven directly from a  
CMOS buffer and the OSC2 pin left open.  
For 5V+/-10% applications any number of MT88E45B’s can be connected as shown in Figure 6 6 so that only one  
crystal is required.  
MT88E45B  
MT88E45B  
MT88E45B  
OSC1 OSC2  
OSC1 OSC2  
OSC1 OSC2  
to the  
next MT88E45B  
(For 5V+/-10% applications only)  
3.579545 MHz  
Figure 6 - Common Crystal Connection  
14  
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
Application Circuits  
Tx+  
Tx-  
Microphone  
Speaker  
Telephone  
TIP  
TIP  
Hybrid  
or  
Speech IC  
(Symbolic)  
RING  
RING  
Rx+  
Rx-  
R5  
R3  
R6  
R11  
R10  
MT88E45B  
VREF  
D1  
R1  
C1  
R8 C3  
IN2+  
IN2-  
D2  
IN1+  
IN1-  
R9 C4  
R12  
GS2  
D3  
R7  
GS1  
CB2  
R4  
C2 R2  
= To Microcontroller  
= From Microcontroller  
D4  
Vss  
CB1  
Vdd  
C5  
OSC1  
OSC2  
CB0  
Vdd  
Xtal  
Vss  
CD  
C6  
(FSK Interface Mode 1 selected)  
ST/GT  
EST  
R13  
R14  
DCLK  
DATA  
R15  
R15 is required only if both FSK  
interface mode 0 and power  
down features are used.  
C6 should be  
connected directly  
across Vdd and Vss  
pins  
DR/STD  
D5  
Unless stated otherwise, resistors are 1%, 0.1Watt; capacitors are 5%, 6.3V.  
For 1000Vrms, 60Hz isolation from Tip to Earth and Ring to Earth:  
R1,R2  
430K, 0.5W, 5%, 475V min. C1,C2  
(e.g. IRC type GS-3)  
2n2, 1332V min.  
If the 1000Vrms is handled by other methods then this circuit has to meet the FCC Part 68 Type B Ringer requirements:  
R1,R2  
432K, 0.1W, 1%, 56V min. C1,C2  
2n2, 212V min.  
Common to both sets of R1,R2:  
5V, 0dB gain 3V, -3.5dB gain  
R3,R4  
R8,R9  
R13  
34K  
C3,C4  
C5  
2n2  
R5,R10  
R6,R11  
R7,R12  
53K6  
60K4  
464K  
35K7  
40K2  
309K  
464K  
100n  
825K  
C6  
100n, 20%  
R14  
226K or 26K1  
100K, 20%  
D1-D4  
D5  
Xtal  
Diodes. 1N4148 or equivalent  
Diode. 1N4148 or equivalent  
3.579545MHz, 0.1% crystal  
or ceramic resonator  
R15  
Figure 7 - Application Circuit: Bellcore MEI Compatible Type 2 Telephone  
15  
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
1.00  
0.95  
0.90  
0.85  
0.80  
0.75  
0.70  
0.65  
0.60  
0.55  
0.50  
Gain ratio for  
Bellcore GS1, GS2  
ETSI GS2 op amps  
0.794  
Gain ratio for ETSI  
GS1 op amp  
0.668  
0.531  
3.0  
3.5  
4.0  
Nominal Vdd (Volts)  
4.5  
5.0  
Figure 8 - Gain Ratio as a Function of Nominal Vdd  
Gain Setting Resistor Calculation Example for Figure 8:  
For the desired nominal Vdd, use Figure 8 to determine approximate Av.  
For the GS1 op-amp, start with the 0 dB gain setting resistor values of R50dB, R60dB and R70dB. In Figure 7  
these values are 53K7, 60K4 and 464 K respectively. Keep C1,C2,R1,R2,R3,R4 as in Figure 7 to maintain  
the highpass corner frequency constant for all gain settings.  
For the desired gain setting of Av:  
R7Av= R70dB x AV  
R5Av= R50dB x AV  
Scaled for desired gain. Choose  
the closest standard resistor value as R7Av.  
Actual Av from now on is R7Av/R70db  
Scaled for good common mode range. Choose  
the closest standard resistor value as R5Av.  
1/R6Av = 1/R5Av - 1/R7Av  
Calculate R6Av so that R5Av=R6Av || R7Av. Choose  
the closest standard resistor value as R6Av.  
Repeat for R10, R11, R12 for the GS2 op-amp.  
16  
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
Example:  
For a gain of -3.5 dB, Av=10-3.5/20 = 0.668  
R7-3.5dB= 464 K x 0.668 = 309K9, the closest standard resistor value is 309 K.  
Av is now 309 K/464 K = 0.666  
R5-3.5dB= 53K6 x 0.666 = 35K7, the closest standard resistor value is 35K7.  
Therefore R6-3.5dB is calculated to be 40K4, the closest standard resistor value is 40K2.  
Vdd  
Vdd  
Microcontroller  
Interrupt Source 1  
Resistor (R2)  
Resistor (R1)  
INT1  
D1  
(Open Drain)  
R1 can be opened and  
D1 shorted if the  
microcontroller does not  
read the INT1 pin.  
Interrupt Source 2  
INT2  
(CMOS)  
INT(input)  
MT88E45B  
DR/STD  
(CMOS)  
Input Port Bit  
Figure 9 - Application Circuit: Multiple Interrupt Source  
17  
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
Absolute Maximum Ratings* - Voltages are with respect to VSS unless otherwise stated  
Parameter  
Symbol  
Min.  
Max.  
Units  
1
2
3
4
Supply voltage with respect to Vss  
Voltage on any pin other than supplies **  
Current at any pin other than supplies  
Storage Temperature  
VDD  
VPIN  
IPIN  
-0.3  
6
V
Vss-0.3  
VDD+0.3  
10  
V
mA  
oC  
TST  
-65  
150  
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.  
**  
Under normal operating conditions voltage on any pin except supplies can be minimum VSS-1V to maximum VDD+1V for an input current  
limited to less than 200 µΑ  
Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated.  
Characteristics  
Sym.  
Min.  
Typ.‡  
Max.  
Units  
1
2
3
4
Power Supplies  
VDD  
fOSC  
2.7  
5.5  
V
MHz  
%
Clock Frequency  
3.579545  
Tolerance on Clock Frequency  
Operating Temperature  
fOSC  
TOP  
-0.1  
-40  
+0.1  
85  
oC  
‡ Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing.  
DC Electrical Characteristics†  
Characteristics  
Sym.  
Min.  
Typ.‡  
Max.  
Units  
Test Conditions  
1
2
Standby Supply  
Current  
IDDQ  
0.1  
15  
µA  
All inputs are  
VDD/VSS except  
for oscillator pins.  
No analog input.  
outputs unloaded.  
CB0/1/2 = 1/0/0  
S
U
P
P
L
Operating Supply  
Current  
IDD  
All inputs are  
V
DD/VSS except  
V
DD = 5V ±10%  
DD = 3V ±10%  
2.8  
1.5  
8
mA  
mA  
for oscillator pins.  
No analog input.  
outputs unloaded.  
Y
V
4.5  
3
4
Power  
PO  
VT+  
VT-  
44  
mW  
V
Consumption  
Schmitt Input High  
Threshold  
Schmitt Input Low  
Threshold  
0.44*VDD  
0.27*VDD  
0.64*VDD  
0.47*VDD  
DCLK  
V
5
6
Schmitt Hysteresis  
CMOS Input High  
Voltage  
CMOS Input Low  
Voltage  
Output High Source  
Current  
VHYS  
VIH  
0.2  
0.7*VDD  
V
V
VDD  
CB0  
CB1  
CB2  
VIL  
IOH  
VSS  
0.8  
0.3*VDD  
V
DCLK  
DATA  
DR/STD  
CD, EST  
ST/GT  
7
mA  
VOH=0.9*VDD  
18  
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
DC Electrical Characteristics(continued)  
Characteristics  
Sym.  
Min.  
Typ.‡  
Max.  
Units  
Test Conditions  
DCLK  
DATA  
8
9
Output Low Sink  
Current  
IOL  
2
mA  
VOL=0.1*VDD  
DR/STD  
CD, EST  
ST/GT  
IN1+  
IN1-  
IN2+  
IN2-  
Input Current  
Iin1  
Iin2  
Ioz1  
1
10  
5
µA  
µA  
µA  
Vin=VDD to VSS  
Vin=VDD to VSS  
DCLK  
CB0  
CB1  
CB2  
ST/GT  
10  
Output High-  
Vout =VDD to VSS  
No Load  
Impedance Current  
VREF  
11  
12  
13  
Output Voltage  
Output Resistance  
VREF 0.5VDD -0.1  
RREF  
VTGt  
0.5VDD+0.1  
2
0.5VDD+0.05  
V
kΩ  
V
ST/GT  
Comparator  
0.5VDD  
0.05  
-
Threshold Voltage  
† DC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.  
‡ Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing.  
AC Electrical Characteristics- CAS Detection  
Characteristic  
Sym.  
Min.  
Typ.‡  
Max.  
Unit  
Notes*  
1
2
Lower Tone Frequency  
Upper Tone Frequency  
fL  
2130  
2750  
Hz  
Hz  
fH  
range within which  
tones are  
3
4
Frequency Deviation: Accept  
Frequency Deviation: Reject  
1.1%  
3.5%  
accepted  
range outside of  
which tones are  
rejected  
Accept Signal Level (per  
tone)  
-40  
-2  
dBV  
dBm  
5
6
7
1, 5, 6  
2, 5, 6  
1, 5, 6  
-37.78  
0.22  
Reject Signal Level (per tone)  
Vdd=5V +/-10% only  
-46  
dBV  
dBm  
-43.78  
Reject Signal Level (per tone)  
Vdd=3V+/-10% or 5V+/-10%  
-47.22  
-45  
dBV  
dBm  
8
9
Twist: 20 log (V2130Hz/V2750Hz  
)
-7  
+7  
dB  
dB  
Signal to Noise Ratio  
† AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.  
SNRCAS  
20  
3,4  
‡ Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing  
*Notes:  
1. Tip/Ring signal level. Input op-amp configured to 0dB gain at Vdd=5V+/-10%, -3.5dB at Vdd=3V+/-10%.  
2. Tip/Ring signal level. Input op-amp configured to 0dB gain at Vdd=5V+/-10%.  
3. Both tones have the same amplitude.  
4. Band limited random noise 300-3400Hz. Measurement valid only when tone is present.  
5. dBV - Decibels above or below a reference voltage of 1 Vrms. 0 dBV = 1 Vrms. Signal level is per tone.  
6. dBm - Decibels above or below a reference power of 1 mW into 600 ohms. 0 dBm = 0.7746 Vrms. Signal level is per tone.  
19  
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
AC Electrical Characteristics- FSK Demodulation  
Characteristics  
Sym.  
Min.  
Typ.‡  
Max.  
Units  
Notes*  
-40  
-37.78  
10.0  
-6.45  
-4.23  
476  
dBV  
dBm  
1
2
Accept Signal Level Range  
1, 2, 4, 5  
mVrms  
-48.24  
-50.46  
3
dBm  
dBV  
Bell 202 Format Reject Signal Level  
Transmission Rate  
1, 2, 4, 5  
mVrms  
3
4
1188  
1200  
1212  
baud  
Mark and Space Frequencies  
Bell 202 1 (Mark)  
1188  
2178  
1200  
2200  
1212  
2222  
Hz  
Hz  
Bell 202 0 (Space)  
CCITT V.23 1 (Mark)  
CCITT V.23 0 (Space)  
1280.5  
2068.5  
1300  
2100  
1319.5  
2131.5  
Hz  
Hz  
5
6
Twist: 20 log (VMARK/VSPACE  
)
-6  
+10  
dB  
dB  
Signal to Noise Ratio  
† AC Electrical Characteristics are over recommended operating conditions, unless otherwise stated.  
SNRFSK  
20  
1,3  
‡ Typical figures are nominal values and are for design aid only: not guaranteed and not subject to production testing.  
*Notes:  
1. Both mark and space have the same amplitude.  
2. Tip/Ring signal level. Input op-amp configured to 0dB gain at Vdd=5V+/-10%, -3.5dB at Vdd=3V+/-10%.  
3. Band limited random noise (200-3400Hz). Present when FSK signal is present. Note that the BT band is 300-3400Hz, the Bellcore  
band is 0-4kHz.  
4. dBV - Decibels above or below a reference voltage of 1 Vrms. 0 dBV = 1 Vrms.  
5. dBm - Decibels above or below a reference power of 1 mW into 600 ohms. 0 dBm = 0.7746 Vrms.  
Electrical Characteristics- Gain Setting Amplifiers  
Characteristics  
Input Leakage Current  
Sym.  
Min.  
Max.  
Units  
Test Conditions  
1
2
3
4
5
6
7
8
9
IIN  
Rin  
1
µA  
MΩ  
mV  
dB  
dB  
dB  
MHz  
V
V
SS VIN VDD  
Input Resistance  
10  
Input Offset Voltage  
VOS  
PSRR  
CMRR  
AVOL  
fC  
25  
Power Supply Rejection Ratio  
Common Mode Rejection Ratio  
DC Open Loop Voltage Gain  
Unity Gain Bandwidth  
30  
40  
1kHz ripple on VDD  
CMmin VIN VCMmax  
V
40  
0.3  
0.5  
V
V
DD-0.5  
50  
Output Voltage Swing  
VO  
Load 100kΩ  
Capacitive Load (GS1,GS2)  
CL  
pF  
10 Resistive Load (GS1,GS2)  
RL  
100  
1.0  
kΩ  
V
DD-1.0  
11 Common Mode Range Voltage  
VCM  
† Electrical characteristics are over recommended operating conditions, unless otherwise stated.  
20  
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
AC Electrical Characteristics- CAS Detection Timing  
Characteristics  
Sym.  
Min.  
Max.  
Units  
Notes  
1
2
Tone present detect time  
Tone absent detect time  
tDP  
tDA  
0.5  
0.1  
10  
8
ms  
ms  
See Figures16 16, 1717  
See Figures16 16, 1717  
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.  
AC Electrical Characteristics- Oscillator and Carrier Detect Timing  
Characteristics  
Power-up time  
Sym.  
Min.  
Max.  
Units  
Notes  
1
2
3
4
5
tPU  
tPD  
tCP  
tCA  
50  
10  
25  
ms  
ms  
ms  
ms  
ms  
OSC2  
CD  
Power-down time  
Input FSK to CD low delay  
Input FSK to CD high delay  
Hysteresis  
10  
10  
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.  
AC Electrical Characteristics- 3-Wire FSK Data Interface Timing (Mode 0)  
Characteristics  
Rise time  
Sym.  
Min.  
Typ.‡  
Max. Units  
Notes*  
1
2
3
4
5
tRR  
tRF  
tRL  
200  
200  
417  
1212  
5
ns  
ns  
into 50 pF Load  
DR/STD  
DATA  
Fall time  
Low time  
Rate  
into 50 pF Load  
415  
416  
1200  
1
µs  
2
1
1188  
baud  
ms  
Input FSK to DATA  
delay  
tIDD  
6
7
Rise time  
tR  
tF  
200  
200  
ns  
ns  
µs  
µs  
Hz  
µs  
µs  
µs  
into 50 pF Load  
Fall time  
into 50 pF Load  
DATA  
DCLK  
8
DATA to DCLK delay  
DCLK to DATA delay  
Frequency  
tDCD  
tCDD  
fDCLK0  
tCH  
6
6
416  
416  
1, 2, 3  
9
1, 2, 3  
10  
11  
12  
13  
1201.6  
415  
415  
415  
1202.8  
416  
1204  
417  
417  
417  
2
2
2
2
DCLK  
High time  
Low time  
tCL  
416  
DCLK  
DR/STD  
DCLK to DR delay  
tCRD  
416  
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.  
‡ Typical figures are at 25oC and are for design aid only: not guaranteed and not subject to production testing.  
*Notes:  
1. FSK input data at 1200 ±12 baud.  
2. OSC1 at 3.579545 MHz ±0.1%.  
3. Function of signal condition.  
21  
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
AC Electrical Characteristics- 3-Wire FSK Data Interface Timing (Mode 1)  
Characteristics  
Frequency  
Sym.  
Min.  
Max.  
Units  
Notes  
1
2
3
4
5
fDCLK1  
1
MHz  
%
DCLK  
Duty cycle  
30  
70  
Rise time  
tR1  
100  
ns  
DCLK low set up before DR  
tDDS  
500  
500  
ns  
DCLK  
DR/STD  
DCLK low hold time after DR  
† AC Electrical Characteristics are over recommended operating conditions unless otherwise stated.  
tDDH  
ns  
AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels  
Characteristics  
Sym.  
Level  
Units  
Notes  
1
2
3
CMOS Threshold Voltage  
VCT  
VHM  
VLM  
0.5*VDD  
0.7*VDD  
0.3*VDD  
V
V
V
Rise/Fall Threshold Voltage High  
Rise/Fall Threshold Voltage Low  
t
t
CDD  
DCD  
VHM  
VCT  
VLM  
DATA  
DCLK  
t
F
t
R
VHM  
VCT  
VLM  
t
t
CH  
CL  
t
t
R
F
Figure 10 - DATA and DCLK Mode 0 Output Timing  
t
t
RR  
RF  
VHM  
VCT  
VLM  
DR  
t
RL  
Figure 11 - DR Output Timing  
22  
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
VHM  
VLM  
DCLK  
t
R1  
Figure 12 - DCLK Mode 1 Input Timing  
start  
start  
start  
TIP/RING  
b7  
stop  
b0 b1 b2 b3 b4 b5 b6 b7  
b0 b1 b2 b3 b4 b5 b6 b7  
start  
b0 b1 b2 b3 b4 b5  
(A/B) WIRES  
stop  
stop  
tIDD  
start  
start  
b0 b1 b2 b3 b4 b5 b6 b7  
DATA  
b6 b7  
b0 b1 b2 b3 b4 b5 b6 b7  
b0 b1 b2 b3  
(Output)  
stop  
stop  
stop  
DCLK  
(Output)  
tCL  
tCH  
tCRD  
1/fDCLK0  
DR  
(Output)  
tRL  
Figure 13 - 3-Wire FSK Data Interface Timing (Mode 0)  
23  
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
Word N+1  
Word N  
7
Demodulated Data  
(Internal Signal)  
1
5
stop  
0
3
2
3
4
6
7
stop  
tRL  
start  
Note 1  
DR (Data Ready)  
(Output)  
Note 2  
>tDDS  
>tDDH  
1/fDCLK1  
DCLK (Data Clock)  
(Schmitt Input)  
DATA  
(Output)  
7
stop  
0
1
2
4
5
6
7
stop  
0
Word N-1  
Word N  
The DCLK input must be low before and after DR falling edge.  
Note 1: DCLK occurs during DR low and returns DR to high.  
Note 2: DCLK occurs after DR, so DR is low for half a nominal bit time.  
Figure 14 - 3-Wire FSK Data Interface Timing (Mode 1)  
1st Ring  
A
Ch. seizure  
C
Data  
E
2nd Ring  
Note 2  
Mark  
D
TIP/RING  
B
F
PWDN  
Note 1  
Note 2  
tPU  
Note 4  
Note 3  
tPD  
OSC2  
FSKen  
Note 1  
tCA  
tCP  
CD  
DR  
Note 5  
A = 2sec typical  
B = 250-500ms  
C = 250ms  
DCLK  
DATA  
D = 150ms  
E = feature specific  
..101010..  
Data  
Max C+D+E = 2.9 to 3.7sec  
F 200ms  
Figure 15 - Application Timing for Bellcore On-hook Data Transmission Associated with Ringing,  
e.g., CID  
Notes:  
This on-hook case application is included because a CIDCW (off-hook) CPE must be also capable of receiving on-hook data  
transmission (with ringing) from the end office.  
1) PWDN and FSKen are internal signals decoded from CB0/1/2.  
2) The CPE designer may choose to enable the MT88E45B only after the end of ringing to conserve power in a battery operated CPE.  
CD is not activated by ringing.  
3) The microcontroller in the CPE powers down the MT88E45B after CD has become inactive.  
4) The microcontroller times out if CD is not activated.  
5) This signal represents the mode of the DR/STD pin.  
24  
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
CPE unmutes handset  
and enables keypad  
CPE goes off-hook  
CPE mutes handset & disables keypad  
CPE sends  
TIP/RING  
Note 5  
Mark  
Data  
F
CAS  
ACK  
C
Note 1  
A
E
G
B
D
PWDN  
Note 8  
Hybrid CASen  
Note 8  
Note 2  
Note 3  
Note 4  
FSKen  
Note 8  
tPU  
OSC2  
EST  
tDP  
tDA  
tGA  
VTGt  
tGP  
ST/GT  
tREC  
tABS  
STD  
Note 9  
tCP  
tCA  
Note 6  
Note 7  
CD  
A = 75-85 ms  
B = 0-100 ms  
C = 55-65 ms  
D = 0-500 ms  
E = 58-75 ms  
F = feature specific  
G 50 ms  
DR  
Note 9  
DCLK  
DATA  
Data  
Figure 16 - Application Timing for Bellcore Off-hook Data Transmission, e.g., CIDCW  
Notes:  
1) In a CPE where AC power is not available, the designer may choose to switch over to line power when the CPE goes off-hook and  
use battery power while on-hook. The CPE must also be CID (on-hook) capable because a CIDCW CPE includes CID functionality.  
2) Non-FSK signals such as CAS, speech and DTMF tones are in the same frequency band as FSK. They will be demodulated and  
give false data. Therefore the MT88E45B should be taken out of FSK mode when FSK is not expected.  
3) The MT88E45B may be put into FSK mode as soon as the CPE has finished sending the acknowledgment signal ACK. TR-NWT-  
000575 specifies that ACK = DTMF ‘D’ for non-ADSI CPE, ‘A’ for ADSI CPE.  
4) The MT88E45B should be taken out of FSK mode when CD has become inactive, or after 5 framing errors have been detected, or  
after 150ms of continuous mark signal or space signal has been received. The framing errors need not be consecutive.  
5) In an unsuccessful attempt where the end office does not send the FSK signal, the CPE should unmute the handset and enable the  
keypad after interval D has expired.  
6) The total recognition time is tREC = tGP + tDP , where tGP is the tone present guard time and tDP is the tone present detect time. VTGt  
is the comparator threshold (refer to Figure 55 for details).  
7) The total tone absent time is tABS = tGA + tDA , where tGA is the tone absent guard time and tDA is the tone absent detect time. VTGt  
is the comparator threshold (refer to Figure5 5 for details).  
8) PWDN, Hybrid CASen and FSKen are internal signals decoded from CB0/1/2.  
9) This signal represents the mode of the DR/STD pin.  
25  
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
Line Reversal  
‘Idle State Tone Alert Signal’  
DT-AS  
B
Ch. seizure  
Mark  
E
Data  
F
Ring  
A/B Wires  
A
C
D
G
Note 4  
PWDN  
Note 6  
50-150ms  
Tip/Ring  
CASen  
Note 6  
tDP  
tDA  
tGA  
EST  
tGP  
Note 1  
Note 2  
VTGt  
ST/GT  
tREC  
tABS Note 3  
STD  
Note 7  
15±1ms  
< 0.5mA (optional)  
TE DC load  
TE AC load  
<120µAµ  
20±5ms  
Current wetting pulse (see SIN227)  
Zss (Refer to SIN227)  
Note 4  
Note 5  
FSKen  
Note 6  
tCP  
tCA  
A 100 ms  
B = 88-110 ms  
C 45 ms (up to 5sec)  
D = 80-262 ms  
CD  
DR  
Note 7  
E = 45-75 ms  
F 2.5sec (typ. 500 ms)  
G > 200 ms  
DCLK  
DATA  
OSC2  
..101010..  
Data  
Note:  
All  
values  
tPU  
tPD  
obtained from SIN227  
Issue 1  
Figure 17 - Application Timing for BT Caller Display Service (CDS), e.g., CLIP  
Notes:  
1) The total recognition time is tREC = tGP + tDP , where tGP is the tone present guard time and tDP is the tone present detect time. VTGt  
is the comparator threshold (refer to Figure 55 for details).  
2) The total tone absent time is tABS = tGA + tDA , where tGA is the tone absent guard time and tDA is the tone absent detect time. VTGt  
is the comparator threshold (refer to Figure 55 for details).  
3) By choosing tGA=15ms, tABS will be 15-25ms so that the current wetting pulse and AC load can be applied right after the STD rising  
edge.  
4) SIN227 specifies that the AC and DC loads should be removed between 50-150ms after the end of the FSK signal, indicated by CD  
returning to high. The MT88E45B may also be powered down at this time.  
5) The MT88E45B should be taken out of FSK mode when FSK is not expected to prevent the FSK demodulator from reacting to other  
in-band signals such as speech, DT-AS/CAS and DTMF tones.  
6) PWDN, Tip/Ring CASen, FSKen are internal signals decoded from CB0/1/2.  
7) This signal represents the mode of the DR/STD pin.  
26  
Zarlink Semiconductor Inc.  
MT88E45  
Data Sheet  
Line Reversal (Optionally sent)  
Ring Burst  
First Complete  
Ring Cycle  
Mark  
D
Ch. seizure  
C
Data  
E
A/B Wires  
A
B
F
Note 2  
Note 1  
50-150ms  
250-400ms  
PWDN  
Note 3  
TE DC load  
TE AC load  
FSKen  
Note 3  
tCP  
tCA  
CD  
A = 200-450 ms  
B 500 ms  
C = 80-262 ms  
D = 45-262 ms  
E 2.5s (typ. 500 ms)  
F >200 ms  
Note: Parameter  
from "CCA Exceptions  
Document Issue 3"  
DR  
Note 4  
DCLK  
DATA  
OSC2  
F
..101010..  
Data  
tPU  
tPD  
Figure 18 - Application Timing for UK’s CCA Caller Display Service (CDS), e.g., CLIP  
Notes:  
1) From TW/P&E/312. Start time: The CPE should enter the signalling state by applying the DC and AC terminations within this time  
after the end of the ring burst.  
2) End time: The CPE should leave the signalling state by removing the DC and AC terminations within this time after the end of Data,  
indicated by CD returning to high. The MT88E45B should also be taken out of FSK mode at this time to prevent the FSK  
demodulator from reacting to other in-band signals such as speech, and DTMF tones.  
3) PWDN and FSKen are internal signals decoded from CB0/1/2.  
4) This signal represents the mode of the DR/STD pin.  
27  
Zarlink Semiconductor Inc.  
For more information about all Zarlink products  
visit our Web Site at  
www.zarlink.com  
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.  
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such  
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or  
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual  
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in  
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.  
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part  
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other  
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the  
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute  
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and  
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does  
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in  
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.  
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system  
conforms to the I2C Standard Specification as defined by Philips.  
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Copyright Zarlink Semiconductor Inc. All Rights Reserved.  
TECHNICAL DOCUMENTATION - NOT FOR RESALE  

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