MGCT04LH1T [ZARLINK]
Transmit Circuit for TDMA/AMPS and CDMA/AMPS; 发射电路用于TDMA / AMPS和CDMA / AMPS
| 型号： | MGCT04LH1T |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Transmit Circuit for TDMA/AMPS and CDMA/AMPS |
| 文件： | 总12页 (文件大小：346K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
This product is obsolete.
This information is available for your
convenience only.
For more information on
Zarlink’s obsolete products and
replacement product lists, please visit
http://products.zarlink.com/obsolete_products/
MGCT04
Transmit Circuit for TDMA/AMPS and CDMA/AMPS
Preliminary Information
DS5424
ISSUE 1.1
March 2001
Features
Ordering Information
•
•
Dual RF Ports for 900MHz and 1900MHz
MGCT04/KG/LH1S
MGCT04/KG/LH1T
AGC Amplifier with 90dB of Variable Gain, Fully
Compensated for Temperature
•
•
On-chip Active Filter. Removes the
Requirement for External IF SAW Filter
High Power 900MHz and 1900MHz Output
Stages
•
•
Quadrature Modulator
mobile phones. It can be used for both TDMA/AMPS
or CDMA/AMPS systems. The MGCT04 is
compatible with baseband and mixed signal interface
circuits from Zarlink Semiconductor and other
manufacturers.
Small Scale MLF Package
Applications
•
•
Transmit Modulator and Up-converter in TDMA/
AMPS Mobile Phones
System costs have been kept to a minimum by
removing the requirement for an additional SAW filter
in the transmit IF path. The AGC has been split
between RF and IF sections to reduce noise and a
low pass filter has been included before the IF
variable gain amplifier to remove spurious products
produced in the modulator.
Transmit Up-converter in CDMA/AMPS Mobile
Phones
The MGCT04 circuit is designed for use in dual
band, dual mode cellular 900MHz/PCS1900MHz
CP2
CP1
CP0
LO 2GHz
LO 1GHz
8
23
5
19
21
UHF
OSCILLATOR
INPUT SELECT
CONTROL LOGIC
1900 MHz
OUTPUT DRIVER
27
26
RF190
RF190
13
14
POWER CONTROL
IF VGA
Q IN
Q IN
ALL PASS
PHASE
RF VGA
28
1
÷
2/4 AND
PHASE
RFDEG1
RFDEG2
SHIFT
NETWORK
SHIFT
15
16
I IN
I IN
3
2
RF900
RF900
SSB MIXER
900 MHz
OUTPUT DRIVER
7
VGA CONTROL
DIV
OUT
÷
8
V
REF
VCO
BUFFER
OSC
BUFFER
BIAS
BUFFER
9
10
22
VHF OSC IN
VHF OSC BIAS
AGC
Figure 1 - MGCT04 Block Diagram
1
MGCT04 Preliminary Information
21
15
22
14
28
8
Note:
Corner Pads are connected
to ground
1
7
Figure 2 - Pin Connections - top view
Function
Pin
Signal Name
RF DEG2
1
Connection to external inductor to control gain of power amplifiers
Inverse output from 900MHz differential output driver
Output from 900MHz differential output driver
Ground to RF circuits
2
RF 900B
RF 900
3
4
RF GND
CP0
5
Control pin 0. See tables 2 & 3 for function
Ground for VHF oscillator
6
VCO GND
DIV OUT
CP2
7
Output from VHF oscillator divided by 8
Control pin 2. See tables 2 & 3 for function
Input from external VHF oscillator
Switched bias voltage for external VHF oscillator
Positive supply to VHF oscillator
Ground
8
9
VHF OSC IN
VHF OSC BIAS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VCO V
GND
Q IN
CC
Q +input
Q INB
I IN
Q -input
I +input
I INB
I -input
V
Positive supply
CC
UHF V
Positive supply to UHF LO input buffers
2GHz local oscillator input
CC
LO 2GHZ
GND UHF
LO 1GHZ
AGC
Ground to UHF oscillator input buffers
1GHz local oscillator input
Control voltage for IF and RF variable gain amplifiers
Control pin 1. See tables 2 & 3 for function
Positive supply to RF circuits
CP1
RF V
CC
RF GND
RF 1900B
RF 1900
RF DEG1
Ground to RF circuits
Inverse output from 1900MHz differential output driver
Output from 1900MHz differential output driver
Connection to external inductor to control gain of power amplifiers
Table 1 - Pin Assignments
2
Preliminary Information MGCT04
Absolute Maximum Ratings
Supply voltage (V
)
4V
Operating temperature
-40˚C to 100˚C
150˚C
CC
Control input voltage
-0.6V to V + 0.6V
Max Junction Temperature (T )
CC
J
Storage temperature, T
-55˚C to +125˚C
STG
Electrical Characteristics
Test conditions (unless otherwise stated): Tamb = -30°C to +70°C, V = 2·7V to 3·6V. UHF LO level = -15dBm
CC
(both bands), I, Q input = 1.4 volts p.p, test frequency = 849MHz (900 output) and 1910MHz (1900
output).These characteristics are guaranteed by either production test or design. They apply within the
specified ambient temperature and supply voltage ranges unless otherwise stated.
Value
Characteristics
Supply current
Units
Conditions
Min.
Typ.
Max.
Sleep current
Standby mode
75
10
µA
mA
mA
All circuits off
8
4
See Tables 4 and 5
Pin 7 connected to V
Standby Mode - Prescaler
disabled
CC
Total supply current
Standby to operating mode
switching time
118
160
10
mA
µs
Maximum power PCS mode
Logic inputs
Logic high voltage
Logic low voltage
V
-0.6
V
V
V
CC
CC
0
0·8
Table 2 - DC Characteristics
Value
Units
Characteristics
Conditions
Min.
Typ.
Max.
I and Q modulator
I and Q input voltage level
I and Q common mode voltage
1.0
1.4
1.2
2.0
Vpp
V
Differential
I and Q differential input
resistance
13.5
kΩ
I and Q input bandwidth
IF Vector offset
2.5
25
30
MHz
dB
Pout = +8dBm
Pout = + 8dBm
SSB rejection
dB
VHF oscillator input and divider
Input drive level
22
40
70
mVrms From external VHF osc. via
matching network
VHF oscillator bias voltage
Output level from prescaler
Prescaler divide ratio
1.2
V
400
mVpp
6pF load
8
Drive output for synthesiser
Table 3 - AC Characteristics
3
MGCT04 Preliminary Information
Value
Characteristics
Units
Conditions
Min.
Typ.
Max.
Variable gain amplifiers
IF amp. operating frequency range
50
200
MHz
MHz
RF amp. operating frequency
range
750
2000
Overall gain control range
84
90
dB
V
Voltage gain
Control voltage for minimum gain
Control voltage for maximum gain
AGC control voltage slope
0.1
2.6
60
V
33
dB/V
SSB mixer and UHF oscillator
inputs
Cellular band LO input level
-15
-15
850
-10
-10
-5
-5
dBm
dBm
MHz
From external UHF osc. via
matching network
PCS band LO input level
From external UHF osc. via
matching network
Cellular band local oscillator input
frequency. (LO 1GHz)
1100
PCS band local oscillator input
frequency (LO 2GHz)
1500
2150
MHz
900MHz RF output stage
Specifications assume 50 ohm
load driven via a matching network
(Fig. 6)
RF amplifier operating frequency
824
849
MHz
range
Output power
ACPR (CDMA)
ACPR (TDMA)
+8
-66
-45
+19
-52
-30
dBm
dBc
dBc
Note 1
Pout = +3dBm Vcc = 3V
Pout = +8dBm, Offset = 30kHz
Vcc = 3V
-90
-60
dBc
Pout = +8dBm, Offset = 60kHz
Vcc = 3V
Output power AMPS
Receive band noise
+10
+14
+19
dBm
Note 2
-128
dBm/
Hz
At duplex frequency, offset 45MHz
Pout = +3dBm
Receive band noise
(869 - 894MHz)
-123
121
dBm/
Hz
ftx = 849 MHz Pout = +8dBm
Spurious Outputs
LO Leakage
-30
-30
-20
-20
-20
dBc
dBc
dBm
Pout = +8dBm
Pout = +8dBm
Note 3
Image Rejection
Other Spurii
Table 3 - AC Characteristics (continued)
4
Preliminary Information MGCT04
Value
Typ.
Characteristics
Units
Conditions
Min.
Max.
1900MHz RF output stage (PCS)
Specifications assume 50 ohm
load driven via a matching network
(Fig. 5)
RF amplifier operating frequency
1850
1910
MHz
range
Output power
ACPR (CDMA)
ACPR (TDMA)
+8
-66
-45
+18
-52
-30
dBm
dBc
dBc
Note 1
Pout = +3dBm Vcc = 3V
Pout = +8dBm, Offset = 30kHz
Vcc = 3V
-90
-60
dBc
Pout = +8dBm, Offset = 60kHz
Vcc = 3V
Receive band noise
-128
-123
dBm/
Hz
At duplex frequency, offset 80MHz
Pout = +3dBm
Receive band noise
(1930 - 1990 MHz)
-121
dBm/
Hz
ftx = 1910MHz, Pout = +8dBm
Spurious Outputs
LO Leakage
-30
-30
-20
-20
-20
dBc
dBc
dBm
Pout = +8dBm
Pout = +8dBm
Note 3
Image Rejection
Other Spurii
Table 3 - AC Characteristics (continued)
Notes:
1. V (I/Q) = 1.4V differential, VHF LO = 22mV rms, UHF LO = -15dBm, VGA = 2.6volts
2. V (I/Q) = 1.4 V dc differential, VHF LO = 22mV rms, UHF LO = -15dBm, VGA = 2.6 volts
3. Frequency range 10MHz to 10*ftx except Rx and Tx bands
is applied to the I and Q inputs of the quadrature
Circuit Description
General
The MGCT04 circuit is designed to provide the
transmit function in dual band dual mode CDMA/
AMPS IS136/AMPS mobile phones. The circuit
contains the following blocks:
modulator to produce the intermediate frequency by
mixing with the local oscillator frequency from the
VHF VCO. The control inputs can select either a
divide by two or divide by four function between the
VHF VCO and the quadrature modulator giving a
choice of possible intermediate frequencies.
VHF Oscillator Input Oscillator Bias and
Divider
1. Quadrature modulator
2. VHF voltage controlled oscillator buffer and
divide by 8 prescaler
An external VHF oscillator circuit is AC coupled to
the VHF oscillator input. The oscillator drives the
quadrature modulator and an internal divide by eight
circuit to reduce the frequency of the output signal to
be sent off chip to the frequency synthesiser. This
reduces the power required in the output buffer
circuit and also allows a low frequency low power
CMOS synthesiser to be used. The divider can be
disabled if not required by connecting the output pin
(DIV OUT - pin 7) to the positive power supply. This
reduces the total supply current by typically 4mA. An
oscillator bias circuit is included on the chip so that
the external VHF oscillator transistor can be switched
off using the control inputs. The bias voltage is
3. Active IF low pass filter
4. IF variable gain amplifier
5. Single sideband mixer with external UHF
oscillator inputs
6. RF variable gain amplifier
7. 900MHz and 1900MHz high power output driver
stages
8. Power and mode control logic
Quadrature Modulator
I and Q data from a baseband circuit such as the
Zarlink Semiconductor MGCM02 or MGCM03 circuit
5
MGCT04 Preliminary Information
switched off in either of the sleep conditions shown
in Tables 4 and 5.
filter to be used for both 900MHz and 1900MHz
bands.
RF Variable Gain Amplifier
Active Low Pass Filter
The SSB mixer is followed by the RF variable gain
amplifier stage which provides about 23dB of the
total gain variation. An additional SAW filter in the
transmit path is avoided by providing the gain
variation after the mixer.
The output from the quadrature modulator is passed
to the active low pass filter which attenuates wide
band noise and spurious outputs.
IF Variable Gain Amplifier
The filtered IF signal is passed to the IF variable gain
amplifier which in turn drives the single sideband
mixer. An externally applied AGC control voltage
allows the total circuit gain to be varied over a
minimum 84dB range.
The variable gain amplifier control circuit ensures
that the attenuation from maximum power is initially
controlled by the RF variable gain stage thus
reducing the noise contribution from the RF mixer.
Output Drivers
The AGC action is split between the IF and RF
portions of the circuit and an internal AGC control
circuit processes the external AGC control voltage to
drive both IF and RF variable gain amplifiers and
provides a near linear control characteristic over the
entire AGC range.
Separate output drive stages are provided for
900MHz and 1900MHz operation. A differential
design is used for both amplifiers to improve power
efficiency and to ease power supply decoupling
problems. The 900MHz output stage provides a
linear output of 3 to 5 dBm for CDMA and 8 dBm for
TDMA operation, but is over-driven in AMPS mode to
obtain a typical output of 11dBm. In both power
driver stages the DC current is backed off as the RF
and IF gain is reduced, improving efficiency when
less than maximum output power is required.
Single Sideband Mixer
The modulated IF signal is fed to the single sideband
mixer which up-converts the IF to the RF frequency
to be transmitted by mixing with an RF signal from
one of two external UHF oscillator input pins,
seiected by an on chip multiplexer. When 1900MHz
mode is programmed with the VHF oscillator in
divide by four mode (Tables 4 and 5), the polarity of
the quadrature oscillator drive signals to the single
sideband mixer are reversed, thus selecting a low
side LO for 1900MHz PCS and high side for
900MHz. This technique allows a common IF and
Control Inputs
Three control inputs are provided to select different
operating modes for the chip; the various modes
selected by the control pins are shown in Tables 4
and 5.
CP2 CP1 CP0
Function
0
0
0
0
0
0
1
1
0
1
0
1
Sleep mode. All circuits powered down
Quadrature modulator on. 1900MHz mode. Low side UHF LO. IF = VHF VCO ÷ 4
Quadrature modulator on. 900MHz mode. high side UHF LO. IF = VHF VCO ÷ 4
Standby mode. VHF oscillator input buffer, oscillator bias and divider on. All other
circuits powered down
Table 4 - Control pin functions;VHF LO in divide-by-four mode
CP2 CP1 CP0
Function
Sleep mode. All circuits powered down
1
1
1
1
0
0
1
1
0
1
0
1
Quadrature modulator on. 1900MHz mode. High side UHF LO. IF = VHF VCO ÷ 2
Quadrature modulator on. 900MHz mode. high side UHF LO. IF = VHF VCO ÷ 2
Standby mode. VHF oscillator input buffer, oscillator bias and divider on. All other
circuits powered down
Table 5 - Control pin functions;VHF LO in divide-by-two mode
6
Preliminary Information MGCT04
V
CC
V
CC
V
CC
1.85k
1.85k
INPUT
400k
600
OSC
BIAS
800k
DIV
OUT
V
REF
1.2V
2.5mA
0.5mA
Figure 3a - Control inputs CP0,
CP1 and CP2
Figure 3b - Oscillator bias
buffer
Figure 3c - Divider ouput
circuit
V
CC
V
CC
550
550
2.7k
2.7k
V
V
V
−
+
OUT
OUT
V
BIAS
BIAS
10k
10k
4k5
4k5
VHF OSC
INPUT
LO2GHz
LO1GHz
100
100
1.6mA
4p
540µA
Figure 3d - VHF oscillator input buffer
Figure 3e - LO2GHz and LO1GHz oscillator
inputs
RF900
RF900
RF1900
RF1900
V
V
CC
CC
V
V
BIAS
BIAS
RFDEG2
RFDEG1
Figure 3f - 900MHz and 1900MHz outputs
10k
80k
V
CC
I IN/Q IN
I IN/Q IN
TO
QUAD
MOD
V
CC
27k
27k
AGC IN
V
1
2
BIAS
BIAS
44k
2.0p
V
80k
TO
QUAD
MOD
10k
Figure 3g - I and Q inputs
Figure 3h - AGC input
7
MGCT04 Preliminary Information
1GHz LO
2GHz LO
1900MHz
power amplifier
1900MHz
SAW filter
Vcc
CONTROL
MICROPROCESSOR
1900MHz
matching
network
1900MHz
diplexer
AGC
900MHz
matching
network
900MHz
diplexer
28
1
22
21
900MHz
power amplifier
900MHz
SAW filter
External
VHF oscillator
MGCT04
Oscillator
control
7
15
MIXED SIGNAL
INTERFACE
CIRCUIT
8
14
VHF SYNTHESISER
Oscillator
out
Oscillator
bias
Vee
Figure 4 - Typical application circuit
V
V
CC
CC
50Ω SAW
FILTER
50Ω SAW
FILTER
C3
C1
L1
15n
L2
15n
C3
C1
L1
L2
68n
1.2p 1.2p
1.5p 100p 68n
PIN 27
PIN 26
PIN 3
L4
L3
3.9n
L4
L3
22n
5.6n
22n
L5
L5
5.6n
22n
PIN 2
C4
1.2p
C4
1.5p
C2
1.2p
C2
100p
NOTE
NOTE
L1 and L2 are required to provide a DC feed to the output pins
and do not form part of the matching network
L1 and L2 are required to provide a DC feed to the output pins
and do not form part of the matching network
Figure 5 - Typical 1900MHz output matching
network
Figure 6 - Typical 900MHz output matching
network
8
Preliminary Information MGCT04
MGCT04
VCO control
voltage
VHF OSC IN (9)
Frequency
Synthesizer
VHF OSC BIAS (10)
DIV OUT (7)
Vee
Figure 7 - Typical circuit showing connection of external VHF oscillator
3n3 5p6
10n 68p
Pin 19
Pin 21
2p
2n2
b) UHF LO 2GHz
a) UHF LO 1GHz
4n7
39n
Pin 9
Note:
Test signal generator impedance
is 50 ohms in each case
8P
c) VHF LO
Figure 8 - LO Input Test Circuits
9
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
相关型号：
©2020 ICPDF网 联系我们和版权申明