LE7920-1JCT [ZARLINK]
Analog Transmission Interface;
| 型号： | LE7920-1JCT |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Analog Transmission Interface |
| 文件： | 总19页 (文件大小：630K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
™
Le7920
Subscriber Line Interface Circuit
VE580 Series
The Le7920 Subscriber Line Interface Circuit implements the
basic telephone line interface functions, and enables the
design of low cost, high performance, POTS line interface
cards.
DISTINCTIVE CHARACTERISTICS
Control states: Active, Ringing, Standby,
Programmable loop-detect threshold
Programmable ring-trip detect threshold
No –5 V supply required
Current Gain = 500
On-chip Thermal Management (TMG) feature
and Disconnect
Low standby power (35 mW)
–19 V to –58 V battery operation
On-hook transmission
Two-wire impedance set by single external
Four on-chip relay drivers and relay snubbers, 1
impedance
ringing and 3 general purpose (32 PLCC)
Programmable constant-current feed
BLOCK DIAGRAM
TMG
Relay
RYOUT3
Driver
Relay
RYOUT2
Driver
Relay
RYOUT1
Driver
Ring Relay
Driver
RINGOUT
A(TIP)
D1
D2
D3
C1
C2
HPA
Input Decoder
and Control
Two-Wire
DET
Interface
HPB
VTX
RSN
Signal
B(RING)
Transmission
Off-Hook
Detector
RD
RDC
CAS
Power-Feed
Controller
DA
DB
Ring-Trip
Detector
VBAT
BGND
VCC VBREF AGND/DGND
Document ID# 080146 Date:
Sep 19, 2007
2
Rev:
J
Version:
Distribution:
Public Document
Le7920
Data Sheet
TABLE OF CONTENTS
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Standard Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Electrical Characteristics (continued). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Electrical Characteristics (continued). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Relay Driver Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
DC Feed Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Test Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
Test Circuits (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Test Circuits (continued) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
Physical Dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
32-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision C to Revision D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision D to Revision E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision E to Revision F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision F to Revision G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision G to Revision H. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision H to Revision I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision I1 to Revision J1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Revision J1 to Revision J2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
2
Zarlink Semiconductor Inc.
Le7920
Data Sheet
ORDERING INFORMATION
Standard Products
Zarlink standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
Le7920
J
C
C = Commercial (0°C to 70°C)*
PLCC package
PACKAGING MATERIAL
Blank= Standard package
D= Green package (see note)
PERFORMANCE GRADE
Blank = Standard specification
–1 = 53 dB Longitudinal Balance
–2 = 63 dB Longitudinal Balance
DEVICE NUMBER/DESCRIPTION
Le7920
Subscriber Line Interface Circuit
Note: Green package meets RoHS Directive 2002/95/EC of the European
Council to minimize the environmental impact of electrical equipment.
Valid Combinations
Valid Combinations list configurations planned to
be supported in volume for this device. Consult
the local Zarlink sales office to confirm availabil-
ity of specific valid combinations, to check on
newly released combinations, and to obtain addi-
tional data on Zarlink’s standard military–grade
products.
Valid Combinations
–1
JC
Le7920*
–2
DJC
*Zarlink reserves the right to fulfill all orders for this device with parts marked with the "Am" part number prefix, until such time
as all inventory bearing this mark has been depleted. It should be noted that parts marked with either the "Am" or the "Le" part
number prefix are equivalent devices in terms of form, fit, and function. The only difference between the two is in the part number
prefix appearing on the topside mark.
3
Zarlink Semiconductor Inc.
Le7920
Data Sheet
CONNECTION DIAGRAM
Top View
4
3
2
1
32 31 30
RYOUT2
RYOUT3
TMG
VBAT
D2
DA
29
28
27
26
25
24
23
22
21
5
6
RD
32-Pin
PLCC
HPB
HPA
NC
7
8
9
VTX
VBREF
RSN
AGND
D1
10
11
12
13
NC
NC
DET
14 15 16 17 18 19 20
Notes:
1. Pin 1 is marked for orientation.
2. NC = No Connect
4
Zarlink Semiconductor Inc.
Le7920
Data Sheet
PIN DESCRIPTIONS
Pin Name
AGND/DGND
A(TIP)
Type
Description
Ground
Output
Ground
Output
Inputs
Analog and Digital ground.
Output of A(TIP) power amplifier.
Battery (power) ground.
BGND
B(RING)
C2–C1
Output of B(RING) power amplifier.
Decoder. TTL compatible. C2 is MSB and C1 is LSB.
Anti-Saturation pin for capacitor to filter reference voltage when operating in anti-
saturation region.
CAS
Capacitor
Relay Driver Control. D3–D1 control the relay drivers RYOUT1, RYOUT2, and RYOUT3.
Logic Low on D1 activates the RYOUT1 relay driver. Logic Low on D2 activates the
RYOUT2 relay driver. Logic Low on D3 activates the RYOUT3 relay driver. TTL
compatible.
D3–D1
Input
DA
DB
Input
Input
Ring-trip negative. Negative input to ring-trip comparator.
Ring-trip positive. Positive input to ring-trip comparator.
Switchhook detector. Logic Low indicates that selected detector is tripped. Logic inputs
C2–C1, E1, and E0 select the detector. Open-collector with a built-in 15 kΩ pull-up
resistor.
DET
Output
HPA
HPB
NC
Capacitor
Capacitor
—
High-Pass Filter Capacitor. A(TIP) side of high-pass filter capacitor.
High-Pass Filter Capacitor. B(RING) side of high-pass filter capacitor.
No Connect. Pin not internally connected.
RD
Resistor
Detect resistor. Detector threshold set and filter pin.
DC feed resistor. Connection point for the DC feed current programming network. The
other end of the network connects to the receiver summing node (RSN).
RDC
Resistor
Output
RINGOUT
Ring Relay Driver. Open-collector driver with emitter internally connected to BGND.
Receive Summing Node. The metallic current (both AC and DC) between A(TIP) and
B(RING) is equal to 500 times the current into this pin. The networks that program
receive gain, two-wire impedance, and feed resistance all connect to this node.
RSN
Input
RYOUT1
RYOUT2
Output
Output
Relay/Switch Driver. Open-collector driver with emitter internally connected to BGND.
Relay/Switch Driver. Open-collector driver with emitter internally connected to BGND
(PLCC only).
Relay/Switch Driver. Open-collector driver with emitter internally connected to BGND
(PLCC only).
RYOUT3
TMG
Output
—
Thermal Management. External resistor connects between this pin and VBAT to offload
power from SLIC.
VBAT
VBREF
VCC
Battery
—
Battery supply and connection to substrate.
This is an Zarlink reserved pin and must always be connected to the VBAT pin.
+5 V power supply.
Power
Transmit Audio. This output is a 0.50 gain version of the A(TIP) and B(RING) metallic
voltage. VTX also sources the two-wire input impedance programming network.
VTX
Output
5
Zarlink Semiconductor Inc.
Le7920
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Storage temperature......................... –55°C to +150°C
V
with respect to AGND/DGND ..... –0.4 V to +7.0 V
CC
V
with respect to AGND/DGND:
BAT
Continuous..................................... +0.4 V to –70 V
10 ms ............................................. +0.4 V to –75 V
BGND with respect to AGND/DGND........ +3 V to –3 V
A(TIP) or B(RING) to BGND:
Continuous ........................................ V
to +1 V
BAT
10 ms (f = 0.1 Hz) ............................. –70 V to +5 V
1 µs (f = 0.1 Hz) ................................ –80 V to +8 V
250 ns (f = 0.1 Hz) .......................... –90 V to +12 V
Current from A(TIP) or B(RING).....................±150 mA
RINGOUT/RYOUT1,2,3 current.........................50 mA
RINGOUT/RYOUT1,2,3 voltage ........... BGND to +7 V
RINGOUT/RYOUT1,2,3 transient....... BGND to +10 V
DA and DB inputs
Voltage on ring-trip inputs.....................V
to 0 V
BAT
Current into ring-trip inputs .........................±10 mA
C2–C1 and D3–D1
Input voltage .........................–0.4 V to V + 0.4 V
CC
Maximum power dissipation, continuous,
T = 70°C, No heat sink (See note)
A
In 32-pin PLCC package................................1.7 W
Thermal Data:................................................................θ
JA
In 32-pin PLCC package.......................43°C/W typ
ESD immunity/pin (HBM) ..................................1500 V
Note: Thermal limiting circuitry on chip will shut down the circuit at a junction temperature of about 165°C. Continuous operation
above 145°C junction temperature may degrade device reliability.
Stresses above those listed under "Absolute Maximum Ratings" can cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
6
Zarlink Semiconductor Inc.
Le7920
Data Sheet
OPERATING RANGES
The operating ranges define those limits between which the functionality of the device is guaranteed.
Commercial (C) Devices
Ambient temperature .............................0°C to +70°C*
V
..................................................... 4.75 V to 5.25 V
CC
V
..................................................... –19 V to –58 V
BAT
AGND/DGND ..........................................................0 V
BGND with respect to
AGND/DGND ....................... –100 mV to +100 mV
Load resistance on VTX to ground ..............20 kΩ min
* Zarlink guarantees the performance of this device over commercial (0 to 70º C) and industrial (-40 to 85ºC) temperature ranges
by conducting electrical characterization over each range and by conducting a production test with single insertion coupled to
periodic sampling. These characterization and test procedures comply with section 4.6.2 of Bellcore GR-357-CORE Component
Reliability Assurance Requirements for Telecommunications Equipment.
Package Assembly
The standard (non-green) package devices are assembled with industry-standard mold compounds, and the leads possess a tin/
lead (Sn/Pb) plating. These packages are compatible with conventional SnPb eutectic solder board assembly processes. The
peak soldering temperature should not exceed 225°C during printed circuit board assembly.
The green package devices are assembled with enhanced environmental compatible lead (Pb), halogen, and antimony-free
materials. The leads possess a matte-tin plating which is compatible with conventional board assembly processes or newer lead-
free board assembly processes. The peak soldering temperature should not exceed 245°C during printed circuit board assembly.
Refer to IPC/JEDEC J-Std-020B Table 5-2 for the recommended solder reflow temperature profile
7
Zarlink Semiconductor Inc.
Le7920
Data Sheet
ELECTRICAL CHARACTERISTICS
Description
Transmission Performance
2-wire return loss
Analog output (VTX) impedance
Analog (VTX) output offset voltage
Overload level, 2-wire and 4-wire
Overload level
Test Conditions (See Note 1)
Min
Typ
Max
Unit
Note
200 Hz to 3.4 kHz
26
dB
Ω
1, 4
4
3
20
+50
–50
2.5
0.77
mV
Vpk
Vrms
Active state
On hook, RLAC = 600 Ω
2a
2b
THD, Total Harmonic Distortion
0 dBm
+7 dBm
–64
–55
–50
–40
dB
5
THD, On hook
0 dBm, RLAC = 600 Ω
–36
Longitudinal Capability (See Test Circuit D)
Longitudinal to
metallic L-T, L-4
balance
200 Hz to 1 kHz
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–1*
–2
–1
–2
52
63
50
58
4
4
dB
1 kHz to 3.4 kHz
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–1*
–2
–1
–2
52
58
50
53
4
4
Longitudinal signal generation 4-L
Longitudinal current per pin (A or B)
Longitudinal impedance at A or B
Idle Channel Noise
200 Hz to 3.4 kHz
Active state
0 to 100 Hz
40
20
27
25
35
mArms
Ω/pin
8
C-message weighted noise
RL = 600 Ω
0°C to +70°C
7
+10
+12
–80
–78
dBrnc
dBmp
RL = 600 Ω
–40°C to +85°C
4
Psophometric weighted noise
RL = 600 Ω
RL = 600 Ω
0°C to +70°C
–40°C to +85°C
–83
Insertion Loss and Balance Return Signal (See Test Circuits A and B)
Gain accuracy
4- to 2-wire
Gain accuracy
2- to 4-wire, 4- to 4-wire
Gain accuracy, 4- to 2-wire
Gain accuracy, 2- to 4-wire, 4- to 4-wire On hook
Gain accuracy over frequency
0 dBm, 1 kHz
0 dBm, 1 kHz
On hook
–0.20
–6.22
0
+0.20
–5.82
–6.02
–0.35
–6.37
–0.15
+0.35
–5.67
+0.15
4
–6.02
dB
µs
300 to 3.4 kHz
relative to 1 kHz
Gain tracking
+3 dBm to –55 dBm
relative to 0 dBm
0 dBm to –37 dBm
+3 dBm to 0 dBm
–0.15
+0.15
Gain tracking
On hook
–0.15
–0.35
+0.15
+0.35
Group delay
0 dBm, 1 kHz
4
4, 7
Note:
* Performance Grade
8
Zarlink Semiconductor Inc.
Le7920
Data Sheet
ELECTRICAL CHARACTERISTICS (continued)
Description
Line Characteristics
Test Conditions (See Note 1)
Min
Typ
Max
Unit
Note
IL, Short Loops, Active state
IL, Long Loops, Active state
RLDC = 600 Ω
RLDC = 1930 Ω, BAT = –42.75 V,
TA = 25°C
20
18
23
19
26
mA
IL, Accuracy, Standby state
0.7IL
18
IL
1.3IL
BAT – 3 V
------------------------------
RL + 400
IL=
TA= 25°C
Constant-current region
RL = 0
Active, A and B to ground
VBAT = –52 V
30
IL, Loop current, Disconnect state
ILLIM
VAB, Open Circuit voltage
100
120
µA
mA
V
85
–44
–42.75
Power Supply Rejection Ratio (VRIPPLE = 100 mVrms), Active Normal State
VCC
VBAT
50 Hz to 3.4 kHz
50 Hz to 3.4 kHz
CAS pin to VBAT
30
28
85
40
50
170
dB
5
4
Effective internal resistance
Power Dissipation
On hook, Disconnect state
On hook, Standby state
On hook, Active state
Off hook, Standby state
Off hook, Active state
Supply Currents, Battery = –48V
255
kΩ
25
35
125
860
450
70
100
270
1200
800
mW
RL = 600 Ω
RL = 300 Ω, RTMG = 2350 Ω
ICC
,
Disconnect state
1.7
2.2
6.3
4.0
4.0
8.5
On-hook VCC supply current
Standby state
Active state, BAT = –48 V
mA
IBAT
,
Disconnect state
0.25
0.55
2.8
1.0
1.5
4.8
On-hook VBAT supply current
Standby state
Active state, BAT = –48 V
RFI Rejection
RFI rejection
Receive Summing Node (RSN)
RSN DC voltage
100 kHz to 30 MHz, (See Figure F)
1.0
20
mVrms
4
4
IRSN = 0 mA
200 Hz to 3.4 kHz
0
10
V
Ω
RSN impedance
Logic Inputs (C2–C1 and D3–D1)
VIH, Input High voltage
VIL, Input Low voltage
IIH, Input High current
IIL, Input Low current
Logic Output (DET)
VOL, Output Low voltage
VOH, Output High voltage
Ring-Trip Detector Input (DA, DB)
Bias current
2.0
V
0.8
40
–75
–400
µA
IOUT = 0.3 mA, 15 kΩ to VCC
IOUT = –0.1 mA, 15 kΩ to VCC
0.40
+50
V
2.4
–500
–50
–50
0
nA
mV
Offset voltage
Source resistance = 2 MΩ
6
9
Zarlink Semiconductor Inc.
Le7920
Data Sheet
ELECTRICAL CHARACTERISTICS (continued)
Description
Loop Detector
Test Conditions (See Note 1)
Min
Typ
Max
Unit
Note
On threshold
Off threshold
Hysteresis
RD = 35.4 kΩ
RD = 35.4 kΩ
RD = 35.4 kΩ
11.5
9.4
0
17.3
14.1
4.4
mA
Relay Driver Output (RINGOUT, RYOUT1, RYOUT2, RYOUT3)
On voltage
Off leakage
Zener breakover
Zener On voltage
IOL = 40 mA
VOH = +5 V
IZ = 100 µA
IZ = 30 mA
+0.3
+0.7
100
V
µA
6
7.2
10
V
RELAY DRIVER SCHEMATICS
RINGOUT
RYOUT1, RYOUT2, RYOUT3
BGND
BGND
Notes:
1. Unless otherwise noted, test conditions are BAT = –52 V, V
= +5 V, R = 600 Ω, R
= R
DC2
= 27.17 kΩ, R
= 2350 Ω,
CC
= 0.1 µF, C = 0.33 µF, D1 = 1N400x, two-wire AC input impedance is a 600 Ω
CAS
L
DC1
TMG
R
= 35.4 kΩ, no fuse resistors, C
= 0.22 µF, C
D
HP
DC
resistance synthesized by the programming network shown below.
VTX
RT1 = 75 kΩ
CT1 = 120 pF
RT2 = 75 kΩ
RSN
RRX = 150 kΩ
VRX
2. a. Overload level is defined when THD = 1%.
b. Overload level is defined when THD = 1.5%.
3. Balance return signal is the signal generated at V by V . This specification assumes that the two-wire, AC-load impedance matches
TX RX
the programmed impedance.
4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
6. Tested with 0 Ω source impedance. 2 MΩ is specified for system design only.
7. Group delay can be greatly reduced by using a ZT network such as that shown in Note 1. The network reduces the group delay to less than
2 µs and increases 2WRL. The effect of group delay on linecard performance also may be compensated for by synthesizing complex
impedance with the QSLAC™ or DSLAC™ device.
8. Minimum current level guaranteed not to cause a false loop detect.
10
Zarlink Semiconductor Inc.
Le7920
Data Sheet
Table 1. SLIC Decoding
State
C2
C1
0
Two-Wire Status
DET Output
Ring trip
0
1
2
3
0
0
1
1
Disconnect
Ringing
Active
1
Ring trip
0
Loop detector
Loop detector
1
Standby
Table 2. User-Programmable Components
ZT is connected between the VTX and RSN pins. The fuse
ZT = 250(Z2WIN – 2RF)
resistors are RF, and Z2WIN is the desired 2-wire AC input
impedance. When computing ZT, the internal current amplifier
pole and any external stray capacitance between VTX and RSN
must be taken into account.
ZL
G42L
500ZT
ZT + 250(ZL + 2RF)
ZRX is connected from VRX to RSN. ZT is defined above, and
G42L is the desired receive gain.
------------
---------------------------------------------------
ZRX
=
•
1250
R
DC1 + RDC2 = ---------------
ILOOP
RDC1, RDC2, and CDC form the network connected to the RDC
pin. RDC1 and RDC2 are approximately equal. ILOOP is the
desired loop current in the constant-current region.
R
R
DC1 + RDC2
DC1 • RDC2
----------------------------------
CDC = 1.5 ms •
RD and CD form the network connected from RD to AGND/
DGND and IT is the threshold current between on hook and
off hook.
510
415
0.5 ms
RD
--------
IT
--------
IT
RDON
=
, RDOFF
=
, CD = ----------------
1
CCAS = ------------------------------
CCAS is the regulator filter capacitor and fc is the desired filter
cut-off frequency.
5
3.4 • 10 πfc
VBAT – 3 V
ISTANDBY = ---------------------------------
Standby loop current (resistive region).
400 Ω + RL
Thermal Management Equations (Normal Active and Tip Open States)
VBAT – 6 V
RTMG is connected from TMG to VBAT and saves power within
the SLIC in Active and Disconnect state constant-currents only.
RTMG ≥ --------------------------------- – 70 Ω
ILOOP
2
( VBAT – 6 V – (IL • RL))
------------------------------------------------------------------------
PRTMG
=
• RTMG
Power dissipated in the TMG resistor, RTMG, during Active and
Disconnect states.
2
(RTMG + 70 Ω)
Power dissipated in the SLIC while in Active and Disconnect
states.
PSLIC = VBAT • IL – PRTMG – RL(IL)2 + 0.12 W
11
Zarlink Semiconductor Inc.
Le7920
Data Sheet
DC FEED CHARACTERISTICS
60
3
2
VAB
(volts)
1
0
30
IL (mA)
RDC = RDC1 + RDC2 = 54.34 kΩ
BAT = –48 V
Notes:
1250
-----------
1. VAB = ILRL' =
RL' , where RL' = RL + 2RF
RDC
RDC
L----------
300
2. VAB = 0.857( VBAT + 3.3) – I
3. VAB = 0.857( VBAT + 1.2) – I
RDC
L----------
300
a. Load Line (Typical)
12
Zarlink Semiconductor Inc.
Le7920
Data Sheet
A
a
b
RSN
RDC
R
I
SLIC
L
L
RDC1
CDC
RDC2
B
Feed current programmed by RDC1 and RDC2
b. Feed Programming
Figure 1. DC Feed Characteristics
13
Zarlink Semiconductor Inc.
Le7920
Data Sheet
TEST CIRCUITS
A(TIP)
VTX
RL
2
SLIC
VAB
VL
RT
RRX
AGND
RL
2
RSN
B(RING)
I
L2-4 = 20 log (VTX / VAB
)
A. Two- to Four-Wire Insertion Loss
A(TIP)
VTX
SLIC
RT
RRX
VAB
RL
AGND
RSN
B(RING)
VRX
IL4-2 = 20 log (VAB / VRX
)
)
BRS = 20 log (VTX / VRX
B. Four- to Two-Wire Insertion Loss and Balance Return Signal
1
A(TIP)
SLIC
VTX
<< RL
S1
ωC
RL
2
C
VL
RT
VAB
AGND
RL
VL
RRX
S2
2
RSN
B(RING)
VRX
S2 Open, S1 Closed
L-T Long. Bal. = 20 log (VAB / VL)
L-4 Long. Bal. = 20 log (VTX / VL)
S2 Closed, S1 Open
4-L Long. Sig. Gen. = 20 log (VL / VRX
)
C. Longitudinal Balance
14
Zarlink Semiconductor Inc.
Le7920
Data Sheet
TEST CIRCUITS (continued)
ZD
A(TIP)
VTX
RT1
R
SLIC
VS
VM
AGND
RSN
R
ZIN
CT1
RT2
B(RING)
Z : The desired impedance;
D
RRX
e.g., the characteristic impedance of the line
Return loss = –20 log (2 V / V )
M
S
D. Two-Wire Return Loss Test Circuit
VCC
6.2 kΩ
A(TIP)
DET
15 pF
RL = 600 Ω
B(RING)
E1
E. Loop-Detector Switching
C1
L1
200 Ω
200 Ω
50 Ω
A
B
RF1
CAX
33 nF
RF2
HF
50 Ω
CBX
33 nF
GEN
VTX
C2
L2
50 Ω
SLIC
under test
1.5 Vrms
80% Amplitude
Modulated
100 kHz to 30 MHz
F. RFI Test Circuit
15
Zarlink Semiconductor Inc.
Le7920
Data Sheet
TEST CIRCUITS (continued)
+5 V
VCC
DA
DB
RD
CD
RD
2.2 nF
A(TIP)
VTX
VTX
A(TIP)
HPA
RRX
RT
CHP
VRX
RSN
RDC
HPB
B(RING)
B(RING)
2.2 nF
RDC2
RDC1
CDC
RINGOUT
RYOUT1
RYOUT3
RYOUT3
AGND/
DGND
D3
D2
D1
BATTERY
GROUND
BGND
C2
C1
VBREF
VBAT
BAT
ANALOG
GROUND
D1
DET
CAS
TMG
RTMG
DIGITAL
GROUND
CCAS
G. Le7920 Test Circuit
16
Zarlink Semiconductor Inc.
Le7920
Data Sheet
PHYSICAL DIMENSIONS
32-Pin PLCC
NOTES:
1
2
3
Dimensioning and tolerancing conform to ASME Y14,5M-1994.
32-Pin PLCC
JEDEC # MS-016
To be measured at seating plan - C - contact point.
Min
Nom
--
Max
0.140
0.095
0.495
0.453
Symbol
A
0.125
0.075
0.485
0.447
Dimensions “D1” and “E1” do not include mold protrusion.
Allowable mold protrusion is 0.010 inch per side. Dimensions
“D” and “E” include mold mismatch and determined at the
parting line; that is “D1” and “E1” are measured at the extreme
material condition at the upper or lower parting line.
A1
D
0.090
0.490
0.450
0.205 REF
0.590
0.550
0.255 REF
--
D1
D2
E
0.585
0.547
0.595
0.553
4
5
Exact shape of this feature is optional.
E1
E2
Ԧ
Details of pin 1 identifier are optional but must be located
within the zone indicated.
0 deg
10 deg
6
7
8
Sum of DAM bar protrusions to be 0.007 max per lead.
Controlling dimension : Inch.
Reference document : JEDEC MS-016
32-Pin PLCC
Note:
Packages may have mold tooling markings on the surface. These markings have no impact on the form, fit or function of the
device. Markings will vary with the mold tool used in manufacturing.
17
Zarlink Semiconductor Inc.
Le7920
Data Sheet
REVISION SUMMARY
Revision C to Revision D
•
Minor changes were made to the datasheet style and format to conform to Zarlink standards.
Revision D to Revision E
•
Absolute Maximum Ratings: Added ESD immunity specification.
Revision E to Revision F
•
Added the 28-pin SOIC connection diagram and the SC option to the ordering information.
Revision F to Revision G
•
The physical dimension (PL032) was added to the Physical Dimension section.
Revision G to Revision H
•
•
Deleted the plastic DIP package and references to it.
Updated the Pin Description table to correct inconsistencies.
Revision H to Revision I
•
•
•
•
•
Updated device name from "Am7920" to "Le7920" throughout document.
Absolute Maximum Ratings: Notes updated to standard.
Operating Ranges: Temperature statement updated to standard.
Updated "Sales Office Listing."
Updated physical dimension drawings.
Revision I1 to Revision J1
•
•
•
•
Added green package OPN to Ordering Information, on page 3
Added Package Assembly, on page 7
Updated 32-pin PLCC drawing in Physical Dimensions, on page 17
Removed SOIC package information
Revision J1 to Revision J2
•
•
Enhanced format of package drawing in Physical Dimensions, on page 17
Added new headers/footers due to Zarlink purchase of Legerity on August 3, 2007
18
Zarlink Semiconductor Inc.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a license under the Philips I2C Patent rights to use these components in an I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL, the Zarlink Semiconductor logo and the Legerity logo and combinations thereof, VoiceEdge, VoicePort, SLAC, ISLIC, ISLAC and VoicePath are
trademarks of Zarlink Semiconductor Inc.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
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