CA0612JRNPO7BB473 [YAGEO]
SURFACE-MOUNT CERAMIC MULTILAYER CAPACITORS; 表面贴装多层陶瓷电容器
| 型号： | CA0612JRNPO7BB473 |
| 厂家： | 
YAGEO CORPORATION |
| 描述： | SURFACE-MOUNT CERAMIC MULTILAYER CAPACITORS |
| 文件： | 总17页 (文件大小：391K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SURFACE-MOUNT CERAMIC
MULTILAYER CAPACITORS
C-Array
NP0/X7R/Y5V
16 V TO 50 V
sizes 0508 (4 x 0402) / 0612 (4 x 0603)
RoHS compliant & Halogen Free
Product specification
2
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
ORDERING INFORMATION-GLOBAL PART NUMBER, PHYCOMP
CTC & 12NC
All part numbers are identified by the series, size, tolerance, TC material,
packing style, voltage, process code, termination and capacitance value.
SCOPE
This specification describes
NP0/X7R/Y5V 4-capacitor Array
with lead-free terminations.
Please note that 12 digits ordering code will expire at the end of 2010.
APPLICATIONS
ꢀ Professional electronics
ꢀ High density consumer
YAGEO BRAND ordering code
(
)
GLOBAL PART NUMBER PREFERRED
electronics
CA XXXX
X
X
XXX
X
B
X XXX
(1) (2) (3) (4) (5)
(6) (7)
FEATURES
( )
1 SIZE – INCH BASED (METRIC)
ꢀ Supplied in tape on reel
ꢀ Nickel-barrier end termination
0508 (1220)
0612 (1632)
ꢀ 0508 (4x0402) / 0612 (4x0603)
capacitors (of the same
( )
2 TOLERANCE
capacitance value) per array
J = ±5%
ꢀ Less than 50% board space of
an equivalent discrete
component
K = ±10%
M = ±20%
Z = -20% to +80%
ꢀ High volumetric efficiency
( )
ꢀ Increased throughout, by time
3 PACKING STYLE
saved in mounting
ꢀ RoHS compliant
ꢀ Halogen Free compliant
R = Paper/PE taping reel; Reel 7 inch
( )
4 TC MATERIAL
NPO
X7R
Y5V
( )
5 RATED VOLTAGE
7 = 16 V
8 = 25 V
9 = 50 V
( )
6 PROCESS
N = NP0
B = X7R / Y5V
( )
7 CAPACITANCE VALUE
2 significant digits+number of zeros
The 3rd digit signifies the multiplying factor, and letter R is decimal point
Example: 121 = 12 x 101 = 120 pF
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Feb 05, 2010 V.1
Product specification
3
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
PHYCOMP BRAND ordering codes
GLOBAL PART NUMBER (preferred), PHYCOMP CTC (for North America) and 12NC (traditional) codes are
acceptable to order Phycomp brand products.
(
)
GLOBAL PART NUMBER PREFERRED
For detailed information of GLOBAL PART NUMBER and ordering example, please refer to page 2.
12NC CODE
2 2 X X X X
X
X
X
X
X X
(1)
Carrier type
55 = Paper/PE
Capacitance value
Tolerance
Voltage
5 = 5%
10 = 16 V
12 = 25 V
14 = 50 V
6 = 10%
7 = 20%
8 = -20% to +80%
Temperature characteristic
Size
YNM0030
1 = NP0
5 = X7R
9 = Y5V
7 = 0508 (4 x 0402)
6 = 0612 (4 x 0603)
(2)
Packaging
1 = reel: ∅180 mm; 7"
(1) Refer to “Conversion table of capacitance & last 2-digit of 12NC”
(2) Quantity on reel depends on thickness classification; see table 5
PHYCOMP CTC CODE (FOR NORTH AMERICA)
ꢁExample: 0508CG220K9B200
0508
CG
220
K
9
B
2
0
0
Size code Temp.
Char.
Capacitance
in pF
Tolerance
Voltage Termination
Packing
Marking
Range identifier
0508
(4 x 0402)
CG = NP0 101 = 100 pF;
J = ±5%
7 = 16 V B = NiSn
8 = 25 V
2 = 180 mm
7” Paper/PE
0 = no marking 0 = conv. Ceramic
D = Class 2 MLCC
the third digit
signifies the
multiplying factor:
2R = X7R
2F = Y5V
K = ±10%
0612
(4 x 0603)
M = ±20%
9 = 50 V
Z = -20% to +80%
0 = × 1
1 = × 10
2 = × 100
3 = × 1,000
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Feb 05, 2010 V.1
Product specification
4
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
CONSTRUCTION
The capacitor consists of a rectangular
block of ceramic dielectric in which
a number of interleaved metal
electrodes are contained. This
structure gives rise to a high
capacitance per unit volume.
CCA833
The inner electrodes are connected
to the two end terminations and
finally covered with a layer of
plated tin (NiSn).
Fig. 1 Simplified outline
The terminations are lead-free.
An outline of the structure is
shown in Fig.1.
DIMENSIONS
OUTLINES
Table 1
TYPE
0508
0612
For dimensions see Table 1
(4 X 0402) (4 X 0603)
L
L (mm)
2.0 ±0.15
1.25 ±0.15
0.50
3.2 ±0.15
1.60 ±0.15
0.70
W (mm)
Tmin. (mm)
Tmax. (mm)
A (mm)
W
B
0.70
0.90
0.28 ±0.10
0.2 ±0.10
0.5 ±0.10
0.4 ±0.10
0.3 ±0.20
0.8 ±0.10
P
A
B (mm)
P (mm)
T
HBK092
Fig. 2 Surface mounted multilayer ceramic capacitor dimension
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Feb 05, 2010 V.1
Product specification
5
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
CAPACITANCE RANGE & THICKNESS FOR 4C-ARRAY
Table 2 Temperature characteristic material from NP0
0508 (4 x 0402)
0612 (4 x 0603)
50 V
CAPACITANCE
Last 2-digit of
12NC
50 V
10 pF
15 pF
23
25
26
27
29
31
32
33
34
35
36
37
38
39
41
42
43
44
45
46
47
48
49
18 pF
22 pF
33 pF
39 pF
47 pF
0.6±0.1
56 pF
68 pF
0.8±0.1
82 pF
100 pF
120 pF
150 pF
180 pF
220 pF
270 pF
330 pF
390 pF
470 pF
560 pF
680 pF
820 pF
1.0 nF
NOTE
Values in shaded cells indicate thickness class in mm
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Feb 05, 2010 V.1
Product specification
6
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
CAPACITANCE RANGE & THICKNESS FOR 4C-ARRAY
Table 3 Temperature characteristic material from X7R
0508 (4 x 0402)
16 V
0612 (4 x 0603)
CAPACITANCE
Last 2-digit of
12NC
16 V
25 V
50 V
180 pF
220 pF
270 pF
330 pF
390 pF
470 pF
560 pF
680 pF
820 pF
1.0 nF
1.2 nF
1.5 nF
1.8 nF
2.2 nF
2.7 nF
3.3 nF
3.9 nF
4.7 nF
5.6 nF
6.8 nF
8.2 nF
10 nF
12 nF
15 nF
18 nF
22 nF
27 nF
33 nF
47 nF
56 nF
68 nF
82 nF
100 nF
13
14
15
16
17
18
19
21
22
23
24
25
26
27
28
29
31
32
33
34
35
36
37
38
39
41
42
43
45
46
47
48
49
0.8±0.1
0.8±0.1
0.6±0.1
0.8±0.1
NOTE
Values in shaded cells indicate thickness class in mm
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Feb 05, 2010 V.1
Product specification
7
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
CAPACITANCE RANGE & THICKNESS FOR 4C-ARRAY
Table 4 Temperature characteristic material from Y5V
0612 (4 x 0603)
25 V
CAPACITANCE
Last 2-digit of
12NC
10 nF
22 nF
36
41
45
49
0.6±0.1
47 nF
100 nF
NOTE
Values in shaded cells indicate thickness class in mm
THICKNESS CLASSES AND PACKING QUANTITY
Table 5
Ø180 MM / 7 INCH
Paper
SIZE
THICKNESS
TAPE WIDTH QUANTITY
PER REEL
CODE
CLASSIFICATION
0508
0612
0.6 ±0.1 mm
0.8 ±0.1 mm
8 mm
8 mm
4,000
4,000
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Feb 05, 2010 V.1
Product specification
8
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
ELECTRICAL CHARACTERISTICS
4C-ARRAY DIELECTRIC CAPACITORS; NISN TERMINATIONS
Unless otherwise stated all electrical values apply at an ambient temperature of 20±1 °C, an atmospheric
pressure of 86 to 106 kPa, and a relative humidity of 63 to 67%.
Table 6
VALUE
DESCRIPTION
Capacitance range
Rated voltage
10 pF to 100 nF
NP0
X7R
Y5V
50 V
0508: 16 V, 0612: 16 V to 50 V
0612: 25 V
Capacitance tolerance
Dissipation factor (D.F.)
NP0
X7R
Y5V
±5%, ±10%
±10%, ±20%
–20% to +80%
NP0
X7R
Y5V
≤ 0.1%
16 V ≤ 3.5%, 25V ≤ 2.5%, 50V ≤ 2.5%
0508 ≤ 9%, 0612 ≤ 7%
Insulation resistance after 1 minute at Ur (DC)
Rins ≥ 10 GΩ or Rins × Cr ≥ 500 seconds whichever is less
Maximum capacitance change as a function of temperature
(temperature characteristic/coefficient):
NP0
X7R
Y5V
±30 ppm/°C
±15%
+22% to –82%
Operating temperature range:
NP0
X7R
Y5V
–55 °C to +125 °C
–55 °C to +125 °C
–30 °C to +85 °C
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Feb 05, 2010 V.1
Product specification
9
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
NP0 0508/0612 50 V
Sample limits (broken lines)
Requirement levels (dotted lines)
MEA607
MEA608
10
tan δ
(x 10
40
4
)
TC
6
(x10 /K)
7.5
20
0
5
2.5
0
20
40
40
0
40
80
120
40
0
40
80
120
o
o
T ( C)
T ( C)
Fig. 3 Typical temperature coefficient as a function of
Fig. 4 Typical tan δ as a function of temperature
temperature
MEA614
15
ΔC
C
(%)
10
5
0
– 5
– 10
– 15
0
10
20
30
40
50
(V)
V
DC
Fig. 5 Typical capacitance change with respect to the
capacitance at 1 V as a function of DC voltage
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Feb 05, 2010 V.1
Product specification
10
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
X7R 0508 16 V
CCB966
CCB965
0
600
ΔC
C
(%)
tan δ
−4
(× 10
)
−20
−40
−60
−80
400
200
0
100
80
VDC (V)
0
20
40
60
−40
0
40
80
120
T (°C)
Fig. 6 Typical capacitance change with respect to the
capacitance at 1 V as a function of DC voltage
at 20 °C
Fig. 7 Typical tan δ as a function of temperature
YNM0013
15
ΔC
C
(%)
10
5
0
−5
−10
−15
−55
−25
5
40
65
95
T ( C)
125
o
Fig. 8 Typical capacitance change as a function of
temperature
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Feb 05, 2010 V.1
Product specification
11
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
X7R 0612 16 V to 50 V
Curve 1 = 16 V product
Curve 2 = 25 V product
Curve 3 = 50 V product
Curve 1 = 16 V product
Curve 2 = 25 V product
Curve 3 = 50 V product
CCB558
CCB559
0
600
handbook, halfpage
handbook, halfpage
ΔC
C
(%)
tan δ
−4
(× 10
)
1
−20
400
200
0
2
3
1
2
3
−40
−60
0
20
40
60
−60
−20
20
60
100
T (°C)
140
V
(V)
DC
Fig. 9 Typical capacitance change with respect to the
capacitance at 1 V as a function of DC voltage
at 25 °C
Fig. 10 Typical tan δ as a function of temperature
YNM0013
15
ΔC
C
(%)
10
5
0
−5
−10
−15
−55
−25
5
40
65
95
T ( C)
125
o
Fig. 11 Typical capacitance change as a function of
temperature
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Feb 05, 2010 V.1
Product specification
12
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
Y5V 0612 25 V
CCB401
CCB402
0
5000
tan δ
C
C
(%)
−4
(× 10
)
−20
4000
−40
−60
3000
2000
1000
0
−80
−100
0
10
20
30
40
V
50
(V)
−40 −20
0
20
40
60
80
100
DC
T (°C)
Fig. 12 Typical capacitance change with respect to the
capacitance at 1 V as a function of DC voltage
at 25 °C
Fig. 13 Typical tan δ as a function of temperature
CCB403
40
C
C
(%)
20
0
−20
−40
−60
−80
−40 −20
0
20
40
60
80
100
T (°C)
Fig. 14 Typical capacitance change as a function of
temperature
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Feb 05, 2010 V.1
Product specification
13
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
TESTS AND REQUIREMENTS
Table 7 Test procedures and requirements
TEST TEST METHOD PROCEDURE
REQUIREMENTS
No visible damage
IEC 60384- 4.3
21/22
The capacitors may be mounted on printed-circuit boards or
ceramic substrates
Mounting
4.4
Any applicable method using × 10 magnification
In accordance with specification
Visual
inspection
and
dimension
check
4.5.1 Class 1:
Within specified tolerance
Capacitance
f = 1 MHz for C ≤ 1 nF, measuring at voltage 1 Vrms at 20 °C
f = 1 KHz for C > 1 nF, measuring at voltage 1 Vrms at 20 °C
Class 2:
f = 1 KHz for C ≤ 10 µF, measuring at voltage 1 Vrms at 20 °C
f = 120 Hz for C >10 µF, measuring at voltage 0.5 Vrms at 20 °C
4.5.2 Class 1:
In accordance with specification
Dissipation
f = 1 MHz for C ≤ 1 nF , measuring at voltage 1 Vrms at 20 °C
factor (D.F.)
f = 1 KHz for C > 1 nF, measuring at voltage 1 Vrms at 20 °C
Class 2:
f = 1 KHz for C ≤ 10 µF, measuring at voltage 1 Vrms at 20 °C
f = 120 Hz for C > 10 µF, measuring at voltage 0.5 Vrms at 20 °C
4.5.3
At Ur (DC) for 1 minute
In accordance with specification
Insulation
resistance
<General purpose series>
ΔC/C:
Class 1: NP0: ±30 ppm/°C
4.6
Class 1:
Temperature
coefficient
Between minimum and maximum temperature
NP0: -55 °C to +125 °C
Normal Temperature: 20 °C
<General purpose series>
Class 2:
Temperature
characteristic
X5R/X7R: ±15%
Y5V: 22% to -82%
Class 2:
Between minimum and maximum temperature
X5R: -55 °C to +85 °C
X7R: -55 °C to +125 °C
Y5V: -30 °C to +85 °C
<High Capacitance series>
Class 2: X5R/X7R: ±15%
Y5V: 22% to -82%
Normal Temperature: 20 °C
4.7
A force applied for 10 seconds to the line joining the terminations Force
and in a plane parallel to the substrate
size ≥ 0603: 5N
Adhesion
size = 0402: 2.5N
size = 0201: 1N
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Feb 05, 2010 V.1
Product specification
14
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
TEST
TEST METHOD PROCEDURE
REQUIREMENTS
IEC 60384- 4.8
21/22
Mounting in accordance with IEC 60384-22
paragraph 4.3
No visible damage
Bond
strength of
plating on
end face
<General purpose series>
Conditions: bending 1 mm at a rate of 1 mm/s,
radius jig 340 mm
∆C/C
Class 1:
NP0: within ±1% or 0.5 pF, whichever is greater
Class2:
X5R/X7R/Y5V: ±10%
<High Capacitance series>
∆C/C
Class2:
X5R/X7R/Y5V: ±10%
4.9
Precondition: 150 +0/–10 °C for 1 hour, then
keep for 24 ±1 hours at room temperature
Dissolution of the end face plating shall not
exceed 25% of the length of the edge
concerned
Resistance to
soldering
heat
Preheating: for size ≤ 1206: 120 °C to 150 °C for
1 minute
<General purpose series>
Preheating: for size >1206: 100 °C to 120 °C for
1 minute and 170 °C to 200 °C for 1 minute
∆C/C
Class 1:
Solder bath temperature: 260 ±5 °C
Dipping time: 10 ±0.5 seconds
Recovery time: 24 ±2 hours
NP0: within ±0.5% or 0.5 pF, whichever is greater
Class2:
X5R/X7R: ±10%
Y5V: ±20%
<High Capacitance series>
∆C/C
Class2:
X5R/X7R: ±10%
Y5V: ±20%
D.F. within initial specified value
Rins within initial specified value
4.10
Preheated the temperature of 80 °C to 140 °C
and maintained for 30 seconds to 60 seconds.
The solder should cover over 95% of the critical
area of each termination
Solderability
Test conditions for lead containing solder alloy
Temperature: 235 ±5 °C
Dipping time: 2 ±0.2 seconds
Depth of immersion: 10 mm
Alloy Composition: 60/40 Sn/Pb
Number of immersions: 1
Test conditions for leadfree containing solder alloy
Temperature: 245 ±5 °C
Dipping time: 3 ±0.3 seconds
Depth of immersion: 10 mm
Alloy Composition: SAC305
Number of immersions: 1
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Feb 05, 2010 V.1
Product specification
15
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
TEST
TEST METHOD PROCEDURE
REQUIREMENTS
IEC 60384- 4.11
21/22
Preconditioning;
150 +0/–10 °C for 1 hour, then keep for
24 ±1 hours at room temperature
No visual damage
Rapid change
of
temperature
<General purpose series>
∆C/C
5 cycles with following detail:
Class 1:
30 minutes at lower category temperature
30 minutes at upper category temperature
NP0: within ±1% or 1 pF, whichever is greater
Class2:
X5R/X7R: ±15%
Y5V: ±20%
Recovery time 24 ±2 hours
<High Capacitance series>
∆C/C
Class2:
X5R/X7R: ±15%
Y5V: ±20%
D.F. meet initial specified value
R
ins meet initial specified value
4.13
No visual damage after recovery
Damp heat
with Ur load
1. Preconditioning, class 2 only:
150 +0/-10 °C /1 hour, then keep for
24 ±1 hour at room temp
<General purpose series>
∆C/C
2. Initial measure:
Spec: refer initial spec C, D, IR
Class 1:
NP0: within ±2% or 1 pF, whichever is greater
Class2:
3. Damp heat test:
500 ±12 hours at 40 ±2 °C;
90 to 95% R.H. 1.0 Ur applied
X5R/X7R: ±15%; Y5V: ±30%
4. Recovery:
D.F.
Class 1: 6 to 24 hours
Class 2: 24 ±2 hours
Class 1: NP0: ≤ 2 x specified value
Class2:
5. Final measure: C, D, IR
X5R/X7R: ≤ 16V: ≤ 7%
≥ 25V: ≤ 5%
Y5V: ≤ 15%
P.S. If the capacitance value is less than the
minimum value permitted, then after the
other measurements have been made the
capacitor shall be precondition according to
“IEC 60384 4.1” and then the requirement
shall be met.
Rins
Class 1:
NP0: ≥ 2,500 MΩ or Rins x Cr ≥ 25s whichever is less
Class2:
X5R/X7R/Y5V: ≥ 500 MΩ or Rins x Cr ≥ 25s
whichever is less
<High Capacitance series>
∆C/C
Class2: X5R/X7R: ±20%; Y5V: ±30%
D.F.
Class2: 2 x initial value max
Rins
Class2: 500 MΩ or Rins x Cr ≥ 25s, whichever is less
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Feb 05, 2010 V.1
Product specification
16
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
TEST
TEST METHOD
PROCEDURE
REQUIREMENTS
IEC 60384- 4.14
21/22
No visual damage
Endurance
1. Preconditioning, class 2 only:
150 +0/-10 °C /1 hour, then keep for
24 ±1 hour at room temp
<General purpose series>
∆C/C
2. Initial measure:
Class1:
Spec: refer initial spec C, D, IR
NP0: within ±2% or 1 pF, whichever is greater
Class2:
3. Endurance test:
Temperature: NP0/X7R: 125 °C
X5R/Y5V: 85 °C
X5R/X7R: ±15%; Y5V: ±30%
Specified stress voltage applied for 1,000 hours:
Applied 2.0 x Ur for general product.
Applied 1.5 x Ur for high cap. product.
High voltage series follows with below stress
condition:
D.F.
Class1:
NP0: ≤ 2 x specified value
Class2:
X5R/X7R: ≤ 16V: ≤ 7%
≥ 25V: ≤ 5%
Applied 1.3 x Ur for 500V series
Applied 1.2 x Ur for 1KV, 2KV, 3KV series
Y5V: ≤ 15%
4. Recovery time: 24 ±2 hours
5. Final measure: C, D, IR
Rins
Class1:
NP0: ≥ 4,000 MΩ or
Rins x Cr ≥ 40s whichever is less
P.S. If the capacitance value is less than the
minimum value permitted, then after the other
measurements have been made the capacitor shall
be precondition according to “IEC 60384 4.1” and
then the requirement shall be met.
Class2:
X5R/X7R/Y5V: ≥ 1,000 MΩ or
R
ins x Cr ≥ 50s whichever is less
<High Capacitance series>
∆C/C
Class 2:
X5R/X7R: ±20%; Y5V: ±30%
D.F.
Class 2:
2 x initial value max
Rins
Class 2:
1,000 MΩ or Rins x Cr ≥ 50s, whichever is less
IEC 60384-1 4.6
No breakdown or flashover
Specified stress voltage applied for 1 minute
Ur ≤ 100 V: series applied 2.5 Ur
100 V < Ur ≤ 200 V series applied (1.5 Ur + 100)
200 V < Ur ≤ 500 V series applied (1.3 Ur + 100)
Ur > 500 V: 1.3 Ur
Voltage proof
I: 7.5 mA
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Feb 05, 2010 V.1
Product specification
17
17
4C-Array
NP0/X7R/Y5V
16 V to 50 V
Surface-Mount Ceramic Multilayer Capacitors
REVISION HISTORY
REVISION DATE
CHANGE NOTIFICATION DESCRIPTION
Version 1
Feb 05, 2010
-
- The statement of "Halogen Free" on the cover added
- New datasheet for 4C-Array series with RoHS compliant
Version 0
Jun 22, 2009
-
- Replace from pdf files: 0508_16V to 50V_1, 0612_16V to 50V_0,
C-Array_NP0_50V_0508_7, C-Array_NP0_50V_0612_7,
C-Array_X7R_16V_25V_50V_0612_6, C-Array_X7R_16V_0508_5,
C-Array_Y5V_25V_0508_0, C-Array_Y5V_25V_0612_5
- Define global part number
- Description of "Halogen Free compliant" added
- Test method and procedure updated
www.yageo.com
Feb 05, 2010 V.1
相关型号：
CA0612JRNPO9BN220
Array/Network Capacitor, 50V, C0G, 0.000022uF, Surface Mount, CHIP-8, CHIP, HALOGEN FREE AND ROHS COMPLIANT
YAGEO
CA0612JRNPO9BN471
Array/Network Capacitor, 50V, C0G, 0.00047uF, Surface Mount, CHIP-8, CHIP, HALOGEN FREE AND ROHS COMPLIANT
YAGEO
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