XQ5VSX95T-2EF1136I [XILINX]
Field Programmable Gate Array, 1265MHz, 94208-Cell, CMOS, PBGA1136, FCBGA-1136;型号: | XQ5VSX95T-2EF1136I |
厂家: | XILINX, INC |
描述: | Field Programmable Gate Array, 1265MHz, 94208-Cell, CMOS, PBGA1136, FCBGA-1136 时钟 栅 可编程逻辑 |
文件: | 总74页 (文件大小:1748K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
74
Virtex-5Q FPGA Data Sheet:
DC and Switching Characteristics
DS714 (v2.2) January 17, 2011
Product Specification
Virtex-5Q FPGA Electrical Characteristics
Defense-grade Virtex®-5Q FPGAs are available in -2I, -1I,
and -1M (only FX70T and FX100T devices in -1M) speed
grades, with -2I having the highest performance. Virtex-5Q
FPGA DC and AC characteristics are specified for the
industrial temperature range. Except the operating
temperature range or unless otherwise noted, all the DC
and AC electrical parameters are the same for a particular
speed grade.
•
•
UG192, Virtex-5 FPGA System Monitor User Guide
UG193, Virtex-5 FPGA XtremeDSP™ Design
Considerations User Guide
•
•
•
•
•
•
•
UG194, Virtex-5 FPGA Embedded Tri-Mode Ethernet
MAC User Guide
UG195, Virtex-5 FPGA Packaging and Pinout
Specification
UG196, Virtex-5 FPGA RocketIO™ GTP Transceiver
User Guide
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The
parameters included are common to popular designs and
typical applications.
UG197, Virtex-5 FPGA Integrated Endpoint Block User
Guide for PCI Express® Designs
This Virtex-5Q FPGA data sheet, part of an overall set of
documentation on the Virtex-5 family of FPGAs, is available
on the Xilinx website:
UG198, Virtex-5 FPGA RocketIO GTX Transceiver
User Guide
UG200, Embedded Processor Block in Virtex-5 FPGAs
Reference Guide
•
•
•
DS174, Virtex-5Q Family Overview
UG190, Virtex-5 FPGA User Guide
UG191, Virtex-5 FPGA Configuration Guide
UG203, Virtex-5 FPGA PCB Designer’s Guide
All specifications are subject to change without notice.
Virtex-5Q FPGA DC Characteristics
(1)
Table 1: Absolute Maximum Ratings
Symbol
VCCINT
VCCAUX
VCCO
Description
Internal supply voltage relative to GND
Range
Units
–0.5 to 1.1
–0.5 to 3.0
–0.5 to 3.75
–0.5 to 4.05
–0.5 to 3.75
–0.75 to 4.05
V
V
V
V
V
V
Auxiliary supply voltage relative to GND
Output drivers supply voltage relative to GND
Key memory battery backup supply
VBATT
VREF
Input reference voltage
3.3V I/O input voltage relative to GND(2) (user and dedicated I/Os)
3.3V I/O input voltage relative to GND (restricted to maximum of 100 user I/Os)(4)
–0.85 to 4.3
(Industrial Temperature)
(3)
VIN
V
2.5V or below I/O input voltage relative to GND (user and dedicated I/Os)
Current applied to an I/O pin, powered or unpowered
–0.75 to VCCO + 0.5
100
V
mA
mA
V
IIN
Total current applied to all I/O pins, powered or unpowered
Voltage applied to 3-state 3.3V output(2) (user and dedicated I/Os)
Voltage applied to 3-state 2.5V or below output (user and dedicated I/Os)
Storage temperature (ambient)
100
–0.75 to 4.05
–0.75 to VCCO + 0.5
–65 to 150
VTS
V
TSTG
°C
© 2009-2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
DS714 (v2.2) January 17, 2011
www.xilinx.com
Product Specification
1
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
(1)
Table 1: Absolute Maximum Ratings (Cont’d)
Symbol Description
TSOL
Range
+220
Units
°C
Maximum soldering temperature(5)
Maximum junction temperature(5)
Tj
+125
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. For 3.3V I/O operation, refer to Virtex-5 FPGA User Guide, Chapter 6, 3.3V I/O Design Guidelines.
3. 3.3V I/O absolute maximum limit applied to DC and AC signals.
4. For more flexibility in specific designs, a maximum of 100 user I/Os can be stressed beyond the normal specification for no more than 20%
of a data period.
5. For soldering guidelines, refer to UG112: Device Package User Guide. For thermal considerations, refer to UG195: Virtex-5 FPGA
Packaging and Pinout Specification on the Xilinx website.
Table 2: Recommended Operating Conditions
Symbol
Description
Temperature Range
Industrial
Min
0.95
Max
1.05
2.625
3.45
3.45
Units
VCCINT
Internal supply voltage relative to GND, Tj = –40°C to +100°C
Auxiliary supply voltage relative to GND, Tj = –40°C to +100°C
Supply voltage relative to GND, Tj = –40°C to +100°C
3.3V supply voltage relative to GND, Tj = –40°C to +100°C
V
V
V
V
V
(1)
VCCAUX
Industrial
2.375
(2)(3)(4)
VCCO
VIN
Industrial
1.14
Industrial
GND – 0.20
2.5V and below supply voltage relative to GND,
Tj = –40°C to +100°C
Industrial
GND – 0.20 VCCO + 0.2
IIN
Maximum current through any pin in a powered or unpowered
bank when forward biasing the clamp diode.
Industrial
Industrial
10
mA
V
(5)
VBATT
Battery voltage relative to GND, Tj = –40°C to +100°C
1.0
3.6
Notes:
1. Recommended maximum voltage drop for V
is 10 mV/ms.
CCAUX
2. Configuration data is retained even if V
drops to 0V.
CCO
3. Includes V
of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.
CCO
4. The configuration supply voltage V
is also known as V
.
CCO_0
CC_CONFIG
5.
V
is required only when using bitstream encryption. If battery is not used, connect V
to either ground or V
.
CCAUX
BATT
BATT
Table 3: DC Characteristics Over Recommended Operating Conditions
Symbol
VDRINT
VDRI
IREF
Description
Min
0.75
2.0
Typ
Max
Units
V
Data retention VCCINT voltage (below which configuration data might be lost)
Data retention VCCAUX voltage (below which configuration data might be lost)
VREF leakage current per pin
V
10
10
µA
µA
pF
µA
µA
µA
µA
µA
µA
nA
n
IL
Input or output leakage current per pin (sample-tested)
Input capacitance (sample-tested)
CIN
8
(1)
IRPU
Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V
Pad pull-down (when selected) @ VIN = 2.5V
Battery supply current
20
10
5
150
90
45
3
30
2
15
(1)
IRPD
5
110
150
(2)
IBATT
n
r
Temperature diode ideality factor
1.0002
5.0
Series resistance
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. Maximum value specified for worst case process at 25°C.
DS714 (v2.2) January 17, 2011
www.xilinx.com
Product Specification
2
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Important Note
Typical values for quiescent supply current are now specified at nominal voltage, 85°C junction temperatures (T ). Xilinx
j
recommends analyzing static power consumption at T = 85°C because the majority of designs operate near the high end of
j
the commercial temperature range. Data sheets for older products (e.g., Virtex-4 devices) still specify typical quiescent
supply current at T = 25°C. Quiescent supply current is specified by speed grade for Virtex-5Q devices. Use the XPOWER
j
Estimator (XPE) spreadsheet tool (download at www.xilinx.com/power) to calculate static power consumption for conditions
other than those specified in Table 4.
Table 4: Typical Quiescent Supply Current
Speed and Temperature Grade
Symbol
Description
Device
Units
-2 (I)
507
1072
1391
1448
2674
2844
N/A
1092
1924
N/A
1658
2875
3041
N/A
1.5
3
-1 (I)
317
833
1109
1154
2188
2328
3492
840
1475
3168
1658
2875
3041
3755
1.5
3
-1 (M)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
1658
2875
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
6
ICCINTQ
Quiescent VCCINT supply current
XQ5VLX30T
XQ5VLX85
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
XQ5VLX30T
XQ5VLX85
ICCOQ
Quiescent VCCO supply current
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
4
4
4
4
8
8
8
8
N/A
2
12
2
4
4
N/A
6
12
6
7
7
7
8
8
N/A
N/A
N/A
10
DS714 (v2.2) January 17, 2011
www.xilinx.com
Product Specification
3
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Speed and Temperature Grade
Table 4: Typical Quiescent Supply Current (Cont’d)
Symbol
Description
Device
Units
-2 (I)
43
-1 (I)
43
-1 (M)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
110
150
N/A
N/A
ICCAUXQ
Quiescent VCCAUX supply current
XQ5VLX30T
XQ5VLX85
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
93
93
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
125
130
177
236
N/A
74
125
130
177
236
353
74
131
N/A
110
150
180
N/A
131
300
110
150
180
250
Notes:
1. Typical values are specified at nominal voltage, 85°C junction temperatures (T ). Industrial (I) and Military (M) grade devices have the
j
same typical values as commercial (C) grade devices at 85°C, but higher values at 100°C (I) and 125°C (M). Use the XPE/XPA power
tools to calculate values for conditions other than specified in this data sheet.
2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and
floating.
3. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPOWER Estimator
(XPE) or XPOWER Analyzer (XPA) tools.
DS714 (v2.2) January 17, 2011
www.xilinx.com
Product Specification
4
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current
during power-on to insure proper device initialization. The
actual current consumed depends on the power-on ramp
rate of the power supply.
Table 5: Power-On Current for Virtex-5Q Devices
ICCINTMIN ICCAUXMIN
ICCOMIN
Typ(1)
50
Device
Units
Typ(1)
Typ(1)
XQ5VLX30T
XQ5VLX85
246
86
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
The power supplies can be turned on in any sequence,
though the specifications shown in Table 5 are for the
492
186
250
260
368
472
706
148
262
662
232
298
392
534
100
100
100
100
150
150
50
recommended power-on sequence of V
, V
, and
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
623
CCINT CCAUX
V
. The I/O will remain 3-stated through power-on if the
CCO
651
recommended power-on sequence is followed. Xilinx does
not specify the current or I/O behavior for other power-on
sequences.
728
1056
1509
472
Table 5 shows the minimum current required by Virtex-5Q
devices for proper power-on and configuration.
804
100
150
100
100
150
150
If the current minimums shown in Table 5 are met, the
device powers on properly after all three supplies have
passed through their power-on reset threshold voltages.
1632
695
749
The FPGA must be configured after V
is applied.
CCINT
1111
1222
Once initialized and configured, use the XPOWER tools to
estimate current drain on these supplies.
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. The maximum startup current can be obtained using the
XPOWER Estimator (XPE) or XPOWER Analyzer (XPA) tools
and adding the quiescent plus dynamic current consumption.
Table 6: Power Supply Ramp Time
Symbol
VCCINT
VCCO
Description
Internal supply voltage relative to GND
Ramp Time
0.20 to 50.0
0.20 to 50.0
0.20 to 50.0
Units
ms
Output drivers supply voltage relative to GND
Auxiliary supply voltage relative to GND
ms
VCCAUX
ms
DS714 (v2.2) January 17, 2011
www.xilinx.com
Product Specification
5
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
SelectIO™ DC Input and Output Levels
Values for V and V are recommended input voltages. Values for I and I are guaranteed over the recommended
IL
IH
OL
OH
operating conditions at the V and V test points. Only selected standards are tested. These are chosen to ensure that
OL
OH
all standards meet their specifications. The selected standards are tested at a minimum V
with the respective V and
CCO
OL
V
voltage levels shown. Other standards are sample tested.
OH
Table 7: SelectIO DC Input and Output Levels
VIL
VIH
VOL
V, Max
0.4
VOH
IOL
mA
IOH
mA
I/O Standard
V, Min
V, Max
V, Min
V, Max
V, Min
LVTTL
–0.3
0.8
2.0
3.45
2.4
Note 3
Note 3
LVCMOS33,
LVDCI33
–0.3
–0.3
–0.3
–0.3
0.8
2.0
3.45
0.4
0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.45
75% VCCO
Note 3
Note 3
Note 4
Note 4
Note 3
Note 3
Note 4
Note 4
LVCMOS25,
LVDCI25
0.7
1.7
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
LVCMOS18,
LVDCI18
35% VCCO
35% VCCO
65% VCCO
65% VCCO
0.45
LVCMOS15,
LVDCI15
25% VCCO
LVCMOS12
PCI33_3(5)
PCI66_3(5)
PCI-X(5)
–0.3
–0.2
–0.2
–0.2
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
35% VCCO
30% VCCO
30% VCCO
35% VCCO
VREF – 0.1
VREF – 0.05
VREF – 0.1
VREF – 0.1
VREF – 0.1
VREF – 0.1
VREF – 0.1
65% VCCO
50% VCCO
50% VCCO
50% VCCO
VREF + 0.1
VCCO + 0.3
VCCO
25% VCCO
10% VCCO
10% VCCO
10% VCCO
0.6
75% VCCO
90% VCCO
90% VCCO
90% VCCO
–
Note 6
Note 5
Note 5
Note 5
36
Note 6
Note 5
Note 5
Note 5
–
VCCO
VCCO
GTLP
–
GTL
VREF + 0.05
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
–
0.4
–
32
–
HSTL I_12
HSTL I(2)
HSTL II(2)
HSTL III(2)
HSTL IV(2)
DIFF HSTL I(2)
DIFF HSTL II(2)
SSTL2 I
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
25% VCCO
0.4
75% VCCO
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.4
–
6.3
6.3
8
–8
0.4
16
–16
–8
0.4
24
0.4
48
–8
50% VCCO – 0.1 50% VCCO + 0.1 VCCO + 0.3
50% VCCO – 0.1 50% VCCO + 0.1 VCCO + 0.3
–
–
–
–
–
–
–
VREF – 0.15
VREF – 0.15
VREF + 0.15
VREF + 0.15
VCCO + 0.3
VCCO + 0.3
VTT – 0.61
VTT – 0.81
VTT + 0.61
VTT + 0.81
8.1
–8.1
–16.2
SSTL2 II
16.2
50%
VCCO – 0.15
50%
VCCO + 0.15
DIFF SSTL2 I
DIFF SSTL2 II
–0.3
–0.3
VCCO + 0.3
VCCO + 0.3
–
–
–
–
–
–
–
–
50%
CCO – 0.15
50%
VCCO + 0.15
V
SSTL18 I
SSTL18 II
–0.3
–0.3
VREF – 0.125
VREF – 0.125
VREF + 0.125
VREF + 0.125
VCCO + 0.3
VCCO + 0.3
VTT – 0.47
VTT – 0.60
VTT + 0.47
VTT + 0.60
6.7
–6.7
13.4
–13.4
50%
VCCO – 0.125
50%
VCCO + 0.125
DIFF SSTL18 I
–0.3
–0.3
VCCO + 0.3
VCCO + 0.3
–
–
–
–
–
–
–
–
50%
CCO – 0.125
50%
VCCO + 0.125
DIFF SSTL18 II
V
Notes:
1. Tested according to relevant specifications.
2. Applies to both 1.5V and 1.8V HSTL.
3. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.
4. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA.
5. For more information on PCI33_3, PCI66_3, and PCI-X, refer to Virtex-5 FPGA User Guide, Chapter 6, 3.3V I/O Design Guidelines.
6. Supported drive strengths of 2, 4, 6, or 8 mA.
DS714 (v2.2) January 17, 2011
www.xilinx.com
Product Specification
6
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
HT DC Specifications (HT_25)
Table 8: HT DC Specifications
Symbol
VCCO
DC Parameter
Supply Voltage
Conditions
Min
2.38
495
–15
495
–15
200
–15
440
–15
Typ
2.5
Max
2.63
840
15
Units
V
VOD
Differential Output Voltage
Change in VOD Magnitude
Output Common Mode Voltage
Change in VOCM Magnitude
Input Differential Voltage
RT = 100 across Q and Q signals
RT = 100 across Q and Q signals
600
mV
mV
mV
mV
mV
mV
mV
mV
VOD
VOCM
VOCM
VID
600
600
600
715
15
1000
15
VID
VICM
Change in VID Magnitude
Input Common Mode Voltage
Change in VICM Magnitude
780
15
VICM
LVDS DC Specifications (LVDS_25)
Table 9: LVDS DC Specifications
Symbol
VCCO
DC Parameter
Supply Voltage
Conditions
Min
Typ
Max
2.63
Units
2.38
2.5
V
V
V
VOH
VOL
Output High Voltage for Q and Q
Output Low Voltage for Q and Q
RT = 100 across Q and Q signals
RT = 100 across Q and Q signals
1.675
0.825
247
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
VODIFF
VOCM
VIDIFF
VICM
RT = 100 across Q and Q signals
RT = 100 across Q and Q signals
350
1.250
350
600
1.375
600
mV
V
Output Common-Mode Voltage
1.125
100
Differential Input Voltage (Q – Q),
Q = High (Q – Q), Q = High
mV
V
Input Common-Mode Voltage
0.3
1.2
2.2
Extended LVDS DC Specifications (LVDSEXT_25)
Table 10: Extended LVDS DC Specifications
Symbol
VCCO
DC Parameter
Supply Voltage
Conditions
Min
Typ
2.5
–
Max
2.63
1.785
–
Units
2.38
V
V
V
VOH
VOL
Output High Voltage for Q and Q
Output Low Voltage for Q and Q
RT = 100 across Q and Q signals
RT = 100 across Q and Q signals
0.715
350
–
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
VODIFF
VOCM
VIDIFF
VICM
RT = 100 across Q and Q signals
RT = 100 across Q and Q signals
Common-mode input voltage = 1.25V
Differential input voltage = 350 mV
–
1.250
–
820
1.475
1000
2.2
mV
V
Output Common-Mode Voltage
1.025
100
Differential Input Voltage (Q – Q),
Q = High (Q – Q), Q = High
mV
V
Input Common-Mode Voltage
0.3
1.2
DS714 (v2.2) January 17, 2011
www.xilinx.com
Product Specification
7
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
LVPECL DC Specifications (LVPECL_25)
These values are valid when driving a 100 differential load only, i.e., a 100 resistor between the two receiver pins. The
levels are 200 mV below standard LVPECL levels and are compatible with devices tolerant of lower common-mode
V
OH
ranges. Table 11 summarizes the DC output specifications of LVPECL. For more information on using LVPECL, see Virtex-5
FPGA User Guide, Chapter 6, SelectIO Resources.
Table 11: LVPECL DC Specifications
Symbol
VOH
DC Parameter
Output High Voltage
Min
VCC – 1.025
VCC – 1.81
0.6
Typ
Max
VCC – 0.88
VCC – 1.62
2.2
Units
1.545
0.795
V
V
V
V
VOL
Output Low Voltage
VICM
VIDIFF
Input Common-Mode Voltage
Differential Input Voltage(1)(2)
0.100
1.5
Notes:
1. Recommended input maximum voltage not to exceed V
+ 0.2V.
CCAUX
2. Recommended input minimum voltage not to go below –0.5V.
PowerPC 440 Switching Characteristics
Consult the Embedded Processor Block in Virtex-5 FPGAs Reference Guide for further information.
Table 12: Processor Block Switching Characteristics
Speed Grade
Clock Name
CPMC440CLK
Description
Units
-2I
-1I
400
-1M
400
CPU clock
Xbar clock
475
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
CPMINTERCONNECTCLK
CPMPPCS0PLBCLK
CPMPPCS1PLBCLK
CPMPPCMPLBCLK
CPMMCCLK
316.6
158.3
158.3
158.3
316.6
237.5
158.3
250
266.6
133.3
133.3
133.3
266.6
200
266.6
133.3
133.3
133.3
266.6
200
Slave 0 PLB clock(1)
Slave 1 PLB clock(1)
Master PLB clock(1)
Memory interface clock(1)(2)
FCM clock(1)
CPMFCMCLK
CPMDCRCLK
FPGA logic DCR clock(1)
DMA0 LL clock(1)
DMA1 LL clock(1)
DMA2 LL clock(1)
DMA3 LL clock(1)
JTAG clock
133.3
200
133.3
200
CPMDMA0LLCLK
CPMDMA1LLCLK
CPMDMA2LLCLK
CPMDMA3LLCLK
JTGC440TCK
250
200
200
250
200
200
250
200
200
50
50
50
CPMC440TIMERCLOCK
Timer clock
237.5
200
200
Notes:
1. Typical bus frequencies are provided for reference only, actual frequencies are user-design dependent.
2. Refer to DS567, DDR2 Memory Controller for PowerPC 440 Processors, for maximum clock speed of designs using the DDR2 Memory
Controller for PowerPC® 440 processors.
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8
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 13: Processor Block MIB Switching Characteristics
Speed Grade
-1I
Clock Name
Reference Clock
Units
-2I
-1M
Clock-to-out and setup relative to clock
TCK_CONTROL
TCK_ADDRESS
TCK_DATA
CPMMCCLK
CPMMCCLK
CPMMCCLK
CPMMCCLK
CPMMCCLK
1.247
1.136
1.172
0.844
0.95
1.463
1.38
1.463
1.38
ps
ps
ps
ps
ps
1.38
1.38
TCONTROL_CK
TDATA_CK
0.941
1.058
0.941
1.058
Table 14: Processor Block PLBM Switching Characteristics
Speed Grade
-1I
Clock Name
Reference Clock
Units
-2I
-1M
Clock-to-out and setup relative to clock
TCK_CONTROL
TCK_ADDRESS
TCK_DATA
CPMPPCMPLBCLK
CPMPPCMPLBCLK
CPMPPCMPLBCLK
CPMPPCMPLBCLK
CPMPPCMPLBCLK
1.095
1.372
1.257
1.79
1.354
1.673
1.535
1.86
1.354
1.673
1.535
1.86
ps
ps
ps
ps
ps
TCONTROL_CK
TDATA_CK
0.914
1.059
1.059
Table 15: Processor Block PLBS0 Switching Characteristics
Speed Grade
-1I
Clock Name
Reference Clock
Units
-2I
-1M
Clock-to-out and setup relative to clock
TCK_CONTROL
TCK_DATA
CPMPPCS0PLBCLK
CPMPPCS0PLBCLK
CPMPPCS0PLBCLK
CPMPPCS0PLBCLK
CPMPPCS0PLBCLK
1.196
1.189
1.545
1.492
0.971
1.462
1.461
1.836
1.787
1.124
1.462
1.461
1.836
1.787
1.124
ps
ps
ps
ps
ps
TCONTROL_CK
TADDRESS_CK
TDATA_CK
Table 16: Processor Block PLBS1 Switching Characteristics
Speed Grade
-1I
Clock Name
Reference Clock
Units
-2I
-1M
Clock-to-out and setup relative to clock
TCK_CONTROL
TCK_DATA
CPMPPCS1PLBCLK
CPMPPCS1PLBCLK
CPMPPCS1PLBCLK
CPMPPCS1PLBCLK
CPMPPCS1PLBCLK
1.234
1.298
1.596
1.568
0.969
1.525
1.615
1.921
1.864
1.127
1.525
1.615
1.921
1.864
1.127
ps
ps
ps
ps
ps
TCONTROL_CK
TADDRESS_CK
TDATA_CK
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 17: Processor Block DMA0 Switching Characteristics
Speed Grade
-1I
Clock Name
Reference Clock
Units
-2I
-1M
Clock-to-out and setup relative to clock
TCK_CONTROL
TCK_DATA
TCONTROL_CK
TDATA_CK
CPMDMA0LLCLK
CPMDMA0LLCLK
CPMDMA0LLCLK
CPMDMA0LLCLK
1.42
1.472
0.558
–0.105
1.665
1.712
0.716
–0.104
1.665
1.712
0.716
–0.104
ps
ps
ps
ps
Table 18: Processor Block DMA1 Switching Characteristics
Speed Grade
-1I
Clock Name
Reference Clock
Units
-2I
-1M
Clock-to-out and setup relative to clock
TCK_CONTROL
TCK_DATA
TCONTROL_CK
TDATA_CK
CPMDMA1LLCLK
CPMDMA1LLCLK
CPMDMA1LLCLK
CPMDMA1LLCLK
1.266
1.418
0.555
0.01
1.474
1.645
0.717
0.046
1.474
1.645
0.717
0.046
ps
ps
ps
ps
Table 19: Processor Block DMA2 Switching Characteristics
Speed Grade
-1I
Clock Name
Reference Clock
Units
-2I
-1M
Clock-to-out and setup relative to clock
TCK_CONTROL
TCK_DATA
TCONTROL_CK
TDATA_CK
CPMDMA2LLCLK
CPMDMA2LLCLK
CPMDMA2LLCLK
CPMDMA2LLCLK
1.235
1.262
0.924
0.142
1.437
1.463
1.155
0.168
1.437
1.463
1.155
0.168
ps
ps
ps
ps
Table 20: Processor Block DMA3 Switching Characteristics
Speed Grade
-1I
Clock Name
Reference Clock
Units
-2I
-1M
Clock-to-out and setup relative to clock
TCK_CONTROL
TCK_DATA
TCONTROL_CK
TDATA_CK
CPMDMA3LLCLK
CPMDMA3LLCLK
CPMDMA3LLCLK
CPMDMA3LLCLK
1.242
1.184
0.767
0.119
1.462
1.376
0.965
0.116
1.462
1.376
0.965
0.116
ps
ps
ps
ps
Table 21: Processor Block DCR Switching Characteristics
Clock Name
Speed Grade
-1I
Reference Clock
Units
-2I
-1M
Clock-to-out and setup relative to clock
TCK_CONTROL
TCK_ADDRESS
TCK_DATA
CPMDCRCLK
CPMDCRCLK
CPMDCRCLK
CPMDCRCLK
CPMDCRCLK
CPMDCRCLK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
TCONTROL_CK
TADDRESS_CK
TDATA_CK
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 22: Processor Block FCM Switching Characteristics
Speed Grade
-1I
Clock Name
Reference Clock
Units
-2I
-1M
Clock-to-out and setup relative to clock
TCK_CONTROL
TCK_DATA
CPMFCMCLK
CPMFCMCLK
CPMFCMCLK
CPMFCMCLK
CPMFCMCLK
CPMFCMCLK
1.084
1.158
0.818
1.218
0.698
0.698
1.324
1.4
1.324
1.4
ps
ps
ps
ps
ps
ps
TCK_INSTRUCTION
TCONTROL_CK
TDATA_CK
1.06
1.06
1.395
0.768
0.768
1.395
0.768
0.768
TRESULT_CK
Table 23: Processor Block MISC Switching Characteristics
Clock Name
Speed Grade
-1I
Reference Clock
Units
-2I
-1M
Clock-to-out and setup relative to clock
TCK_CONTROL
TCK_ADDRESS
TCK_DATA
CLK1
CLK2
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CLK3
CLK4
CLK5
CLK6
TCONTROL_CK
TADDRESS_CK
TDATA_CK
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
GTP_DUAL Tile Specifications
GTP_DUAL Tile DC Characteristics
Table 24: Absolute Maximum Ratings for GTP_DUAL Tiles
Symbol
MGTAVCCPLL
MGTAVTTTX
MGTAVTTRX
MGTAVCC
Description
Units
Analog supply voltage for the GTP_DUAL shared PLL relative to GND
Analog supply voltage for the GTP_DUAL transmitters relative to GND
Analog supply voltage for the GTP_DUAL receivers relative to GND
Analog supply voltage for the GTP_DUAL common circuits relative to GND
–0.5 to 1.32
–0.5 to 1.32
–0.5 to 1.32
–0.5 to 1.1
V
V
V
V
Analog supply voltage for the resistor calibration circuit of the GTP_DUAL
column
MGTAVTTRXC
–0.5 to 1.32
V
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
(1)(2)
Table 25: Recommended Operating Conditions for GTP_DUAL Tiles
Symbol
Description
Min
1.14
1.14
1.14
0.95
Max
1.26
1.26
1.26
1.05
Units
MGTAVCCPLL(1) Analog supply voltage for the GTP_DUAL shared PLL relative to GND
V
V
V
V
MGTAVTTTX(1)
MGTAVTTRX(1)
MGTAVCC(1)
Analog supply voltage for the GTP_DUAL transmitters relative to GND
Analog supply voltage for the GTP_DUAL receivers relative to GND
Analog supply voltage for the GTP_DUAL common circuits relative to GND
Analog supply voltage for the resistor calibration circuit of the GTP_DUAL
column
MGTAVTTRXC(1)
1.14
1.26
V
Notes:
1. Each voltage listed requires the filter circuit described in Virtex-5 FPGA RocketIO GTP Transceiver User Guide.
2. Voltages are specified for the temperature range of T = –40°C to +100°C.
j
(1)
Table 26: DC Characteristics Over Recommended Operating Conditions for GTP_DUAL Tiles
Symbol
IMGTAVTTTX
IMGTAVCCPLL
IMGTAVTTRXC
IMGTAVTTRX
IMGTAVCC
Description
Min
Typ
71
Max
Units
mA
mA
mA
mA
mA
GTP_DUAL tile transmitter termination supply current(2)
90
60
GTP_DUAL tile shared PLL supply current
36
GTP_DUAL tile resistor termination calibration supply current
GTP_DUAL tile receiver termination supply current(3)
GTP_DUAL tile internal analog supply current
0.1
0.1
56
0.5
0.5
110
MGTRREF
Precision reference resistor for internal calibration termination
49.9 1% tolerance
Notes:
1. Typical values are specified at nominal voltage, 25°C, with a 3.2 Gb/s line rate.
2. numbers are given per GTP_DUAL tile with both GTP transceivers operating with default settings.
I
CC
3. AC coupled TX/RX link.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 27: GTP_DUAL Tile Quiescent Supply Current
Symbol Description
IAVTTTXQ
IAVCCPLLQ
(1)
Typ
Max
18
Units
mA
Quiescent MGTAVTTTX (transmitter termination) supply current
Quiescent MGTAVCCPLL (PLL) supply current
8.5
8
18
mA
Quiescent MGTAVTTRX (receiver termination) supply current. Includes
MGTAVTTRXCQ.
IAVTTRXQ
0.1
2.5
0.8
11
mA
mA
IAVCCQ
Quiescent MGTAVCC (analog) supply current
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. Device powered and unconfigured.
3. Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER
Analyzer (XPA) tools.
4. GTP_DUAL tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of
available GTP_DUAL tiles in the target LXT or SXT device.
GTP_DUAL Tile DC Input and Output Levels
Table 28 summarizes the DC output specifications of the GTP_DUAL tiles in Virtex-5Q FPGAs. Figure 1, page 14 shows the
single-ended output voltage swing. Figure 2, page 14 shows the peak-to-peak differential output voltage.
Consult Virtex-5 FPGA RocketIO GTP Transceiver User Guide for further details.
Table 28: GTP_DUAL Tile DC Specifications
Symbol
DC Parameter
Conditions
Min
Typ
Max
Units
External AC coupled
3.2 Gb/s
150
2000
mV
Differential peak-to-peak
input voltage
DVPPIN
External AC coupled
3.2 Gb/s
180
2000
mV
mV
MGTAVTTRX
+ 400
up to 1320
VIN
Absolute input voltage
DC coupled
–400
DC coupled
MGTAVTTRX = 1.2V
VCMIN
Common mode input voltage
800
mV
mV
mV
mV
Differential peak-to-peak
output voltage(1)
TXBUFDIFFCTRL = 000,
TX_DIFF_BOOST = ON
DVPPOUT
VSEOUT
VCMOUT
1400
700
Single-ended output voltage TXBUFDIFFCTRL = 000,
swing(1)
TX_DIFF_BOOST = ON
Common mode output
voltage
Equation based
MGTAVTTTX = 1.2V
1200 – Amplitude/2
RIN
Differential input resistance
Differential output resistance
Transmitter output skew
90
90
100
100
120
120
15
ROUT
TOSKEW
CEXT
ps
nF
Recommended external AC coupling capacitor(2)
75
100
200
Notes:
1. The output swing and preemphasis levels are programmable using the attributes discussed in Virtex-5 FPGA RocketIO GTP Transceiver
User Guide and can result in values lower than reported in this table.
2. Values outside of this range can be used as appropriate to conform to specific protocols and standards.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
X-Ref Target - Figure 1
+V
0
P
N
VSEOUT
ds714_01_012109
Figure 1: Single-Ended Output Voltage Swing
X-Ref Target - Figure 2
+V
0
DVPPOUT
DVPPIN
P–N
–V
ds714_02_012109
Figure 2: Peak-to-Peak Differential Output Voltage
Table 29 summarizes the DC specifications of the clock input of the GTP_DUAL tile. Figure 3 shows the single-ended input
voltage swing. Figure 4 shows the peak-to-peak differential clock input voltage swing. Consult Virtex-5 FPGA RocketIO GTP
Transceiver User Guide for further details.
(1)
Table 29: GTP_DUAL Tile Clock DC Input Specifications
Symbol
VIDIFF
DC Parameter
Differential peak-to-peak input voltage
Single-ended input voltage
Conditions
Min
200
100
80
Typ
800
400
105
100
Max
2000
1000
130
Units
mV
mV
VISE
RIN
Differential input resistance
CEXT
Required external AC coupling capacitor
75
200
nF
Notes:
1.
V
= 0V and V = 1200 mV
MAX
MIN
X-Ref Target - Figure 3
+V
P
VISE
N
0
ds714_03_012109
Figure 3: Single-Ended Clock Input Voltage Swing Peak-to-Peak
X-Ref Target - Figure 4
+V
0
P – N
VIDIFF
–V
ds714_04_012109
Figure 4: Differential Clock Input Voltage Swing Peak-to-Peak
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
GTP_DUAL Tile Switching Characteristics
Consult Virtex-5 FPGA RocketIO GTP Transceiver User Guide for further information.
Table 30: GTP_DUAL Tile Performance
Speed Grade
Symbol
Description
Units
-2I
3.75
2.0
-1I
3.2
2.0
1.0
FGTPMAX
FGPLLMAX
FGPLLMIN
Maximum GTP transceiver data rate
Maximum PLL frequency
Gb/s
GHz
GHz
Minimum PLL frequency
1.0
Table 31: Dynamic Reconfiguration Port (DRP) in the GTP_DUAL Tile Switching Characteristics
Speed Grade
Symbol
Description
Units
-2I
-1I
FGTPDRPCLK
GTPDRPCLK maximum frequency
175
150
MHz
Table 32: GTP_DUAL Tile Reference Clock Switching Characteristics
All Speed Grades
Typ
Symbol
Description
Conditions
Units
Min
Max
350
400
400
60
FGCLK
Reference clock frequency range(1) CLK
60
MHz
ps
TRCLK
TFCLK
TDCREF
Reference clock rise time
Reference clock fall time
Reference clock duty cycle(2)
20% – 80%
200
200
50
80% – 20%
CLK
ps
40
%
Reference clock total jitter, peak-
peak(3)
TGJTT
TLOCK
CLK
40
1
ps
ms
µs
Clock recovery frequency
acquisition time
Initial PLL lock
Clock recovery phase acquisition
time
Lock to data after PLL has locked to
the reference clock
TPHASE
200
Notes:
1. The clock from the GTP_DUAL differential clock pin pair can be used for all serial bit rates. GREFCLK can be used for serial bit rates
up to 1 Gb/s.
2. For reference clock rates above 325 MHz, a duty cycle of 45% to 55% must be maintained.
3. Measured at the package pin. GTP_DUAL jitter characteristics measured using a clock with specification TGJTT
.
X-Ref Target - Figure 5
TRCLK
80%
20%
TFCLK
ds714_05_012109
Figure 5: Reference Clock Timing Parameters
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
(1)
Table 33: GTP_DUAL Tile User Clock Switching Characteristics
Speed Grade
Symbol
Description
Conditions
Units
-2I
375
-1I
FTXOUT
FRXREC
TRX
TXOUTCLK maximum frequency
320
320
320
320
160
320
320
160
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
RXRECCLK maximum frequency
RXUSRCLK maximum frequency
375
375
RXDATAWIDTH = 0
RXDATAWIDTH = 1
350
TRX2
TTX
RXUSRCLK2 maximum frequency
TXUSRCLK maximum frequency
TXUSRCLK2 maximum frequency
187.5
375
TXDATAWIDTH = 0
TXDATAWIDTH = 1
350
TTX2
187.5
Notes:
1. Clocking must be implemented as described in Virtex-5 FPGA RocketIO GTP Transceiver User Guide.
Table 34: GTP_DUAL Tile Transmitter Switching Characteristics
Symbol
Description
Min
Typ
Max
Units
Gb/s
ps
ps
ps
mV
ns
UI
FGTPTX
TRTX
Serial data rate range
TX Rise time
0.1
FGTPMAX
140
120
TFTX
TX Fall time
TLLSKEW
TX lane-to-lane skew(1)
Electrical idle amplitude
855
20
VTXOOBVDPP
TTXOOBTRANS
TJ3.75
DJ3.75
TJ3.2
Electrical idle transition time
Total Jitter(2)
40
0.35
0.19
0.35
0.19
0.30
0.14
0.30
0.14
0.20
0.10
0.20
0.10
0.10
0.04
0.02
0.01
3.75 Gb/s
3.20 Gb/s
2.50 Gb/s
2.00 Gb/s
1.25 Gb/s
1.00 Gb/s
500 Mb/s
100 Mb/s
Deterministic Jitter(2)
Total Jitter(2)
UI
UI
DJ3.2
Deterministic Jitter(2)
Total Jitter(2)
UI
TJ2.5
UI
DJ2.5
Deterministic Jitter(2)
Total Jitter(2)
UI
TJ2.0
UI
DJ2.0
Deterministic Jitter(2)
Total Jitter(2)
UI
TJ1.25
DJ1.25
TJ1.00
DJ1.00
TJ500
UI
Deterministic Jitter(2)
Total Jitter(2)
UI
UI
Deterministic Jitter(2)
Total Jitter(2)
UI
UI
DJ500
Deterministic Jitter(2)
Total Jitter(2)
UI
TJ100
UI
DJ100
Deterministic Jitter(2)
UI
Notes:
1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP_DUAL sites.
2. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1.
3. All jitter values are based on a Bit-Error Ratio of 1e–12
.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 35: GTP_DUAL Tile Receiver Switching Characteristics
Symbol
Description
Min
0.5
0.1
Typ
Max
FGTPMAX
0.5
Units
Gb/s
Gb/s
RX oversampler not enabled
RX oversampler enabled
FGTPRX
Serial data rate
OOB detect threshold
peak-to-peak
RXOOBVDPP
OOBDETECT_THRESHOLD = 100
60
105
165
mV
Receiver spread-spectrum
tracking(1)
RXSST
RXRL
Modulated @ 33 KHz
–5000
0
ppm
UI
Run length (CID)
Internal AC capacitor bypassed
150
200
CDR 2nd-order loop disabled with
PLL_RXDIVSEL_OUT = 1(2)
–200
–200
ppm
CDR 2nd-order loop disabled with
PLL_RXDIVSEL_OUT = 2(2)
200
ppm
Data/REFCLK PPM offset
tolerance
RXPPMTOL
CDR 2nd-order loop disabled with
PLL_RXDIVSEL_OUT = 4(2)
–100
100
ppm
ppm
CDR 2nd-order loop enabled
–1000
1000
SJ Jitter Tolerance
JT_SJ3.75
JT_SJ3.2
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
3.75 Gb/s
3.20 Gb/s
2.50 Gb/s
2.00 Gb/s
1.00 Gb/s
500 Mb/s
0.30
0.40
0.40
0.40
0.30
0.30
0.30
0.30
UI
UI
UI
UI
UI
UI
UI
UI
JT_SJ2.50
JT_SJ2.00
JT_SJ1.00
JT_SJ500
JT_SJ500
500 Mb/s OS
100 Mb/s OS
JT_SJ100
SJ Jitter Tolerance with Stressed Eye
Total Jitter with Stressed
JT_TJSE3.2
3.20 Gb/s
3.20 Gb/s
0.87
0.30
UI
UI
Eye(4)
Sinusoidal Jitter with
Stressed Eye(4)
JT_SJSE3.2
Notes:
1. Using PLL_RXDIVSEL_OUT = 1 only.
2. CDR 1st-order step size set to 2.
3. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
4. Stimulus signal includes 0.4UI of DJ and 0.17UI of RJ. RX equalizer is enabled.
–12
5. All jitter values are based on a Bit Error Ratio of 1e
.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
GTX_DUAL Tile Specifications
GTX_DUAL Tile DC Characteristics
Table 36: Absolute Maximum Ratings for GTX_DUAL Tiles
Symbol
MGTAVCCPLL
MGTAVTTTX
MGTAVTTRX
MGTAVCC
Description
Units
Analog supply voltage for the GTX_DUAL shared PLL relative to GND
Analog supply voltage for the GTX_DUAL transmitters relative to GND
Analog supply voltage for the GTX_DUAL receivers relative to GND
Analog supply voltage for the GTX_DUAL common circuits relative to GND
–0.5 to 1.1
–0.5 to 1.32
–0.5 to 1.32
–0.5 to 1.1
V
V
V
V
Analog supply voltage for the resistor calibration circuit of the GTX_DUAL
column
MGTAVTTRXC
–0.5 to 1.32
V
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
(1)(2)
Table 37: Recommended Operating Conditions for GTX_DUAL Tiles
Symbol
Description
Min
0.95
1.14
1.14
0.95
Max
1.05
1.26
1.26
1.05
Units
MGTAVCCPLL(1) Analog supply voltage for the GTX_DUAL shared PLL relative to GND
V
V
V
V
MGTAVTTTX(1)
MGTAVTTRX(1)
MGTAVCC(1)
Analog supply voltage for the GTX_DUAL transmitters relative to GND
Analog supply voltage for the GTX_DUAL receivers relative to GND
Analog supply voltage for the GTX_DUAL common circuits relative to GND
Analog supply voltage for the resistor calibration circuit of the GTX_DUAL
column
MGTAVTTRXC(1)
1.14
1.26
V
Notes:
1. Each voltage listed requires the filter circuit described in Virtex-5 FPGA RocketIO GTX Transceiver User Guide.
2. Voltages are specified for the temperature range of T = –40°C to +100°C.
j
(1)
Table 38: DC Characteristics Over Recommended Operating Conditions for GTX_DUAL Tiles
Symbol
IMGTAVTTTX
IMGTAVCCPLL
IMGTAVTTRXC
IMGTAVTTRX
IMGTAVCC
Description
Min
Typ
43.3
38.0
0.1
Max
Units
mA
mA
mA
mA
mA
GTX_DUAL tile transmitter termination supply current(2)
86.3
99.4
0.5
GTX_DUAL tile shared PLL supply current
GTX_DUAL tile resistor termination calibration supply current
GTX_DUAL tile receiver termination supply current(3)
GTX_DUAL tile internal analog supply current
40.3
80.5
56.5
179.5
MGTRREF
Precision reference resistor for internal calibration termination
59.0 1% tolerance
Notes:
1. Typical values are specified at nominal voltage, 25°C, with a 3.2 Gb/s line rate.
2. numbers are given per GTX_DUAL tile with both GTX transceivers operating with default settings.
3. AC coupled TX/RX link.
I
CC
4. Values for currents other than the values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER
Analyzer (XPA) tools.
DS714 (v2.2) January 17, 2011
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Product Specification
18
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 39: GTX_DUAL Tile Quiescent Supply Current
Symbol Description
IAVTTTXQ
IAVCCPLLQ
Typ(1)
8.2
Max
21.6
4.8
Units
mA
Quiescent MGTAVTTTX (transmitter termination) supply current
Quiescent MGTAVCCPLL (PLL) supply current
0.8
mA
Quiescent MGTAVTTRX (receiver termination) supply current. Includes
MGTAVTTRXCQ.
IAVTTRXQ
1.2
9.0
12.0
50.4
mA
mA
IAVCCQ
Quiescent MGTAVCC (analog) supply current
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. Device powered and unconfigured.
3. Currents for conditions other than values specified in this table can be obtained by using the XPOWER Estimator (XPE) or XPOWER
Analyzer (XPA) tools.
4. GTX_DUAL tile quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number
of available GTX_DUAL tiles in the target FXT device.
GTX_DUAL Tile DC Input and Output Levels
Table 40 summarizes the DC output specifications of the GTX_DUAL tiles in Virtex-5Q FPGAs. Figure 6, page 20 shows the
single-ended output voltage swing. Figure 7, page 20 shows the peak-to-peak differential output voltage.
Consult Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further details.
Table 40: GTX_DUAL Tile DC Specifications
Symbol
DC Parameter
Conditions
Min
Typ
Max
1800
1800
Units
mV
External AC coupled
4.25 Gb/s
200
Differential peak-to-peak input
voltage
DVPPIN
External AC coupled 4.25 Gb/s
125
mV
DC coupled
MGTAVTTRX = 1.2V
MGTAVTTRX +400
up to 1320
VIN
Absolute input voltage
–400
mV
DC coupled
MGTAVTTRX = 1.2V
VCMIN
Common mode input voltage
800
mV
mV
mV
mV
Differential peak-to-peak
output voltage(1)
DVPPOUT
VSEOUT
VCMOUT
TXBUFDIFFCTRL = 111
TXBUFDIFFCTRL = 111
1400
700
Single-ended output voltage
swing(1)
Equation based
MGTAVTTTX = 1.2V
Common mode output voltage
1200 – DVPPOUT/2
RIN
Differential input resistance
Differential output resistance
Transmitter output skew
85
85
100
100
2
120
ROUT
TOSKEW
CEXT
120
8
ps
nF
Recommended external AC coupling capacitor(2)
75
100
200
Notes:
1. The output swing and preemphasis levels are programmable using the attributes discussed in Virtex-5 FPGA RocketIO GTX Transceiver
User Guide and can result in values lower than reported in this table.
2. Values outside of this range can be used as appropriate to conform to specific protocols and standards.
DS714 (v2.2) January 17, 2011
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Product Specification
19
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
X-Ref Target - Figure 6
+V
0
P
N
VSEOUT
ds714_06_012109
Figure 6: Single-Ended Output Voltage Swing
X-Ref Target - Figure 7
+V
0
DVPPOUT
DVPPIN
P–N
–V
ds714_07_012109
Figure 7: Peak-to-Peak Differential Output Voltage
Table 41 summarizes the DC specifications of the clock input of the GTX_DUAL tile. Figure 8 shows the single-ended input
voltage swing. Figure 9 shows the peak-to-peak differential clock input voltage swing. Consult Virtex-5 FPGA RocketIO GTX
Transceiver User Guide for further details.
(1)
Table 41: GTX_DUAL Tile Clock DC Input Level Specification
Symbol
VIDIFF
DC Parameter
Differential peak-to-peak input voltage
Single-ended input voltage
Conditions
Min
210
105
90
Typ
800
400
105
100
Max
2000
750
Units
mV
mV
VISE
RIN
Differential input resistance
130
CEXT
Required external AC coupling capacitor
nF
Notes:
1.
V
= 0V and V
= 1200 mV
MIN
MAX
X-Ref Target - Figure 8
+V
P
N
VISE
0
ds714_08_012109
Figure 8: Single-Ended Clock Input Voltage Swing Peak-to-Peak
X-Ref Target - Figure 9
+V
0
P – N
VIDIFF
–V
ds714_09_012109
Figure 9: Differential Clock Input Voltage Swing Peak-to-Peak
DS714 (v2.2) January 17, 2011
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Product Specification
20
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
GTX_DUAL Tile Switching Characteristics
Consult Virtex-5 FPGA RocketIO GTX Transceiver User Guide for further information.
Table 42: GTX_DUAL Tile Performance
Speed Grade
Symbol
Description
Units
-2I
6.5
-1I
4.25
3.25
1.5
-1M
4.25
3.25
1.5
FGTXMAX
FGPLLMAX
FGPLLMIN
Maximum GTX transceiver data rate
Gb/s
GHz
GHz
Maximum PLL frequency
Minimum PLL frequency
3.25
1.5
Table 43: Dynamic Reconfiguration Port (DRP) in the GTX_DUAL Tile Switching Characteristics
Speed Grade
Symbol
Description
GTXDRPCLK maximum frequency
Units
-2I
-1I
-1M
FGTXDRPCLK
175
150
150
MHz
Table 44: GTX_DUAL Tile Reference Clock Switching Characteristics
All Speed Grades
Typ
Symbol
Description
Conditions
Units
Min
Max
FGCLK
Reference clock frequency range(1)
Reference clock rise time
CLK
60
650
MHz
ps
TRCLK
TFCLK
TDCREF
20% – 80%
80% – 20%
CLK
200
200
Reference clock fall time
ps
Reference clock duty cycle
40
50
60
%
At 100 KHz
At 1 MHz
–145
–150
dBc/Hz
dBc/Hz
TGJTT
Reference clock total jitter(2)(3)
Clock recovery frequency acquisition
time
TLOCK
Initial PLL lock
0.25
1
ms
µs
Lock to data after PLL has
locked to the reference clock
TPHASE
Clock recovery phase acquisition time
200
Notes:
1. GREFCLK can be used for serial bit rates up to 1 Gb/s; however, Jitter Specifications are not guaranteed when using GREFCLK.
2. GTX_DUAL jitter characteristics measured using a clock with specification T
link margin trade off.
. A reference clock with higher phase noise can be used with
GJTT
3. The selection of the reference clock is application dependent. This parameter describes the quality of the reference clock used during
transceiver jitter characterization - see Table 46, page 22 and Table 47, page 23.
X-Ref Target - Figure 10
TRCLK
80%
20%
TFCLK
ds714_10_012109
Figure 10: Reference Clock Timing Parameters
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21
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 45: GTX_DUAL Tile User Clock Switching Characteristics
Speed Grade
-1I
Symbol
Description
Conditions
Device
Units
-2I
-1M
FTXOUT
TXOUTCLK maximum frequency
Internal 20-bit datapath
Internal 16-bit datapath
FXT
FXT
FXT
FXT
FXT
325
212.5
212.5
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
406.25
406.25
406.25
312.5
265.625
265.625
265.625
235.625
265.625
132.813
265.625
235.625
265.625
132.813
265.625
265.625
265.625
235.625
265.625
132.813
265.625
235.625
265.625
132.813
FRXREC
TRX
RXRECCLK maximum frequency
RXUSRCLK maximum frequency
2 byte or 4 byte interface
TRX2
RXUSRCLK2 maximum frequency 1 byte interface
2 byte interface
390.625
203.125
406.25
312.5
4 byte interface
TTX
TXUSRCLK maximum frequency
TXUSRCLK2 maximum frequency 1 byte interface
2 byte interface
2 byte or 4 byte interface
FXT
FXT
TTX2
390.625
203.125
4 byte interface
Table 46: GTX_DUAL Tile Transmitter Switching Characteristics
Symbol Description Condition
Serial data rate range
Min
Typ
Max
Units
Gb/s
ps
ps
ps
mV
ns
UI
FGTXTX
TRTX
0.15
FGTXMAX
TX Rise time
20%–80%
80%–20%
120
120
TFTX
TX Fall time
TLLSKEW
TX lane-to-lane skew(1)
Electrical idle amplitude
Electrical idle transition time
Total Jitter(2)
350
15
VTXOOBVDPP
TTXOOBTRANSITION
TJ6.5
75
0.33
0.17
0.33
0.15
0.35(5)
0.14
0.34
0.16
0.20
0.10
0.36
0.16
0.20
0.08
0.15
0.06
0.10
0.03
0.02
0.01
6.5 Gb/s
5.0 Gb/s
4.25 Gb/s
3.75 Gb/s
3.2 Gb/s
3.2 Gb/s(3)
2.5 Gb/s
1.25 Gb/s
750 Mb/s
150 Mb/s
DJ6.5
Deterministic Jitter(2)
Total Jitter(2)
Deterministic Jitter(2)
Total Jitter(2)
Deterministic Jitter(2)
Total Jitter(2)
Deterministic Jitter(2)
Total Jitter(2)
Deterministic Jitter(2)
Total Jitter(2)
Deterministic Jitter(2)
Total Jitter(2)
Deterministic Jitter(2)
Total Jitter(2)
Deterministic Jitter(2)
Total Jitter(2)(4)
UI
TJ5.0
UI
DJ5.0
UI
TJ4.25
DJ4.25
TJ3.75
DJ3.75
TJ3.2
UI
UI
UI
UI
UI
DJ3.2
UI
TJ3.2L
DJ3.2L
TJ2.5
UI
UI
UI
DJ2.5
UI
TJ1.25
DJ1.25
TJ750
UI
UI
UI
DJ750
Deterministic Jitter(2)(4)
Total Jitter(2)(4)
Deterministic Jitter(2)(4)
UI
TJ150
UI
DJ150
UI
Notes:
1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTX_DUAL sites.
2. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. These values are NOT intended for protocol specific compliance determinations.
3. PLL frequency at 1.6 GHz and OUTDIV = 1.
4. GREFCLK can be used for serial data rates up to 1.0 Gb/s, but performance is not guaranteed.
5. M-temperature only (0.33 UI for I-temperature)
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 47: GTX_DUAL Tile Receiver Switching Characteristics
Symbol
Description
Min
0.75
0.15
Typ
Max
FGTXMAX
0.75
Units
Gb/s
Gb/s
RX oversampler not enabled
RX oversampler enabled
FGTXRX
Serial data rate
TIme for RXELECIDLE to
respond to loss or
restoration of data
TRXELECIDLE
OOBDETECT_THRESHOLD = 110
75
ns
OOB detect threshold
peak-to-peak
RXOOBVDPP
RXSST
RXRL
OOBDETECT_THRESHOLD = 110
55
135
0
mV
Receiver spread-spectrum
tracking(1)
Modulated @ 33 KHz
–5000
ppm
Run length (CID)
Internal AC capacitor bypassed
CDR 2nd-order loop disabled
CDR 2nd-order loop enabled
512
200
UI
–200
ppm
ppm
Data/REFCLK PPM offset
tolerance
RXPPMTOL
–2000
2000
SJ Jitter Tolerance(2)
JT_SJ6.5
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)
Sinusoidal Jitter(3)(5)
Sinusoidal Jitter(3)(5)
6.5 Gb/s
5.0 Gb/s
4.25 Gb/s
3.75 Gb/s
3.2 Gb/s
3.2 Gb/s(4)
2.5 Gb/s
1.25 Gb/s
750 Mb/s
150 Mb/s
0.44
0.44
0.44
0.44
0.45
0.45
0.50
0.50
0.57
0.57
UI
UI
UI
UI
UI
UI
UI
UI
UI
UI
JT_SJ5.0
JT_SJ4.25
JT_SJ3.75
JT_SJ3.2
JT_SJ3.2L
JT_SJ2.5
JT_SJ1.25
JT_SJ750
JT_SJ150
SJ Jitter Tolerance with Stressed Eye(2)
Total Jitter with Stressed
JT_TJSE4.25
4.25 Gb/s
4.25 Gb/s
0.69
0.1
UI
UI
Eye(6)
Sinusoidal Jitter with
Stressed Eye(6)
JT_SJSE4.25
Notes:
1. Using PLL_RXDIVSEL_OUT = 1, 2, and 4.
2. All jitter values are based on a Bit Error Ratio of 1e
–12
.
3. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
4. PLL frequency at 1.6 GHz and OUTDIV = 1.
5. GREFCLK can be used for serial data rates up to 1.0 Gb/s, but performance is not guaranteed.
6. Composite jitter with RX equalizer enabled. DFE disabled.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
CRC Block Switching Characteristics
Table 48: CRC Block Switching Characteristics
Speed Grade
Units
Symbol
FCRC
Description
CRCCLK maximum frequency
-2I
-1I
-1M
325
270
270
MHz
Ethernet MAC Switching Characteristics
Consult Virtex-5 FPGA Embedded Tri-Mode Ethernet MAC User Guide for further information.
Table 49: Maximum Ethernet MAC Performance
Speed Grade
Symbol
Description
Conditions
Units
-2I
1.25
12.5
125
125
2.5
-1I
1.25
12.5
125
125
2.5
-1M
1.25
12.5
125
125
2.5
FTEMACCLIENT Client interface maximum frequency
10 Mb/s – 8-bit width
100 Mb/s – 8-bit width
1000 Mb/s – 8-bit width
2000 Mb/s – 16-bit width
10 Mb/s – 4-bit width
100 Mb/s – 4-bit width
1000 Mb/s – 8-bit width
2000 Mb/s – 8-bit width
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
FTEMACPHY
Physical interface maximum frequency
25
25
25
125
250
125
250
125
250
Endpoint Block for PCI Express Designs Switching Characteristics
Consult Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs User Guide for further information.
Table 50: Maximum Performance for PCI Express Designs
Speed Grade
Symbol
Description
Units
-2I
-1I
-1M
250
250
FPCIECORE
FPCIEUSER
Core clock maximum frequency
User clock maximum frequency
250
250
250
250
MHz
MHz
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24
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
System Monitor Analog-to-Digital Converter Specification
Table 51: Analog-to-Digital Specifications
Parameter Symbol
Comments/Conditions
Min
Typ
Max
Units
AVDD = 2.5V 2%, VREFP = 2.5V, VREFN = 0V, ADCCLK = 5.2 MHz, TA = TMIN to TMAX, Typical values at TA=+25°C
DC Accuracy: All external input channels such as VP/VN and VAUXP[15:0]/VAUXN[15:0], Unipolar Mode,
and Common Mode = 0V
Resolution
10
Bits
Integral Nonlinearity
Differential Nonlinearity
INL
2
LSBs
LSBs
DNL
No missing codes (TMIN to TMAX
)
0.9
Guaranteed Monotonic
Unipolar Offset Error(1)
Bipolar Offset Error(1)
Gain Error(1)
Uncalibrated
2
30
30
LSBs
LSBs
%
Uncalibrated measured in bipolar mode
Uncalibrated, Tj = –40°C to 100°C
Uncalibrated, Tj = –55°C to 125°C
2
0.2
0.2
0.2
2.0
2.5
2.0
%
Bipolar Gain Error(1)
Uncalibrated measured in bipolar mode,
Tj = –40°C to 100°C
%
Uncalibrated measured in bipolar mode,
Tj = –55°C to 125°C
0.2
10
2.5
%
Total Unadjusted Error
(Uncalibrated)
TUE
TUE
Deviation from ideal transfer function.
VREFP – VREFN = 2.5V
LSBs
LSBs
Total Unadjusted Error
(Calibrated)
Deviation from ideal transfer function.
1
2
VREFP – VREFN = 2.5V
Calibrated Gain Temperature
Coefficient
Variation of FS code with temperature
0.01
70
LSB/°
C
DC Common-Mode Reject
CMRRDC
VN = VCM = 0.5V 0.5V,
VP – VN = 100mV
dB
Conversion Rate(2)
Conversion Time - Continuous tCONV
Number of CLK cycles
26
32
21
Conversion Time - Event
T/H Acquisition Time
DRP Clock Frequency
ADC Clock Frequency
tCONV
tACQ
Number of CLK cycles
Number of CLK cycles
4
8
DCLK
ADCCLK
DRP clock frequency
250
5.2
5.2
60
MHz
MHz
MHz
%
Derived from DCLK, Tj = –40°C to 100°C
Derived from DCLK, Tj = –55°C to 125°C
1
2.5
40
CLK Duty cycle
Analog Inputs(3)
Dedicated Analog Inputs
Input Voltage Range
VP - VN
Unipolar Operation
0
–0.25
0
1
V
Differential Inputs
+0.25
+0.5
+0.7
Unipolar Common Mode Range (FS input)
Differential Common Mode Range (FS input)
Bandwidth
+0.3
20
MHz
Volts
Auxiliary Analog Inputs
Input Voltage Range
Unipolar Operation
0
–0.25
0
1
Differential Operation
+0.25
+0.5
+0.7
VAUXP[0] /VAUXN[0] to VAUXP[15]
Unipolar Common Mode Range (FS input)
Differential Common Mode Range (FS input)
Bandwidth
/VAUXN[15]
+0.3
10
1.0
10
kHz
µA
Input Leakage Current
Input Capacitance
A/D not converting, ADCCLK stopped
pF
On-chip Supply Monitor Error
V
CCINT and VCCAUX with calibration enabled
1.0
%
Reading
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25
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 51: Analog-to-Digital Specifications (Cont’d)
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
On-chip Temperature Monitor
Error
–40°C to +125°C with calibration enabled
4
°C
External Reference Inputs(4)
Positive Reference Input Voltage VREFP
Range
Measured Relative to VREFN
Measured Relative to AGND
ADCCLK = 5.2 MHz
2.45
–50
2.5
0
2.55
100
100
Volts
mV
µA
Negative Reference Input
Voltage Range
VREFN
Input current
IREF
Power Requirements
Analog Power Supply
Analog Supply Current
AVDD
AIDD
Measured Relative to AVSS
ADCCLK = 5.2 MHz
2.45
5
2.5
2.55
13
V
mA
Notes:
1. Offset and gain errors are removed by enabling the System Monitor automatic gain calibration feature. See Virtex-5 FPGA System Monitor
User Guide.
2. See “System Monitor Timing” in Virtex-5 FPGA System Monitor User Guide.
3. See “Analog Inputs” in Virtex-5 FPGA System Monitor User Guide for a detailed description.
4. Any variation in the reference voltage from the nominal V
= 2.5V and V
= 0V will result is a deviation from the ideal transfer function.
REFP
REFN
This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external ratiometric
type applications allowing the supply voltage and reference to vary by 2% is permitted.
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in Virtex-5Q
devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject
to the same guidelines as the Switching Characteristics. Table 52 shows internal (register-to-register) performance.
Table 52: Register-to-Register Performance
Register-to-Register
(with I/O Delays)
Description
Units
Speed Grade
-1I
-2I
-1M
Basic Functions
16:1 Multiplexer
32:1 Multiplexer
64:1 Multiplexer
500
500
467
438
500
500
500
377
500
500
500
381
450
450
407
428
428
450
447
323
450
450
450
333
450
450
407
428
428
450
447
323
450
450
450
333
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
9 x 9 Logic Multiplier with 4 pipestages
9 x 9 Logic Multiplier with 5 pipestages
16-bit Adder
32-bit Adder
64-bit Adder
Register to LUT to Register
16-bit Counter
32-bit Counter
64-bit Counter
Memory
Cascaded block RAM (64K)
Block RAM Pipelined
Single-Port 512 x 36 bits
Single-Port 4096 x 4 bits
Dual-Port A: 4096 x 4 bits and B: 1024 x 18 bits
450
400
400
MHz
500
500
500
450
450
450
450
450
450
MHz
MHz
MHz
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 52: Register-to-Register Performance (Cont’d)
Register-to-Register
(with I/O Delays)
Description
Units
Speed Grade
-2I
-1I
-1M
Distributed RAM
Single-Port 16 x 8
500
500
500
450
450
450
450
450
450
MHz
MHz
MHz
MHz
Single-Port 32 x 8
Single-Port 64 x 8
Dual-Port 16 x 8
Shift Register Chain
16-bit
500
500
500
450
450
438
450
450
438
MHz
MHz
MHz
32-bit
64-bit
Dedicated Arithmetic Logic
DSP48E Quad 12-bit Adder/Subtracter
DSP48E Dual 24-bit Adder/Subtracter
DSP48E 48-bit Adder/Subtracter
DSP48E 48-bit Counter
DSP48E 48-bit Comparator
DSP48E 25 x 18 bit Pipelined Multiplier
DSP48E Direct 4-tap FIR Filter Pipelined
DSP48E Systolic n-tap FIR Filter Pipelined
500
500
500
500
500
500
458
500
450
450
450
450
450
450
397
450
450
450
450
450
450
450
397
450
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Notes:
1. Device used is the XQ5VLX50T- FF1136.
Table 53: Interface Performances
Speed Grade
-1I
Description
-2I
-1M
Networking Applications
SFI-4.1 (SDR LVDS Interface)(1)
SPI-4.2 (DDR LVDS Interface)(2)
Memory Interfaces
DDR(3)
710 MHz
1.25 Gb/s
645 MHz
1.0 Gb/s
645 MHz
1.0 Gb/s
200 MHz
300 MHz
300 MHz
300 MHz
200 MHz
267 MHz
250 MHz
250 MHz
200 MHz
267 MHz
250 MHz
250 MHz
DDR2(4)
QDR II SRAM(5)
RLDRAM II(6)
Notes:
1. Performance defined using design implementation described in application note XAPP856, SFI-4.1 16-Channel SDR Interface with
Bus Alignment.
2. Performance defined using design implementation described in application note XAPP860, 16-Channel, DDR LVDS Interface with
Real-time Window Monitoring.
3. Performance defined using design implementation described in application note XAPP851, DDR SDRAM Controller.
4. Performance defined using design implementation described in application note XAPP858, High-Performance DDR2 SDRAM
Interface Data Capture.
5. Performance defined using design implementation described in application note XAPP853, QDRII SRAM Interface.
6. Performance defined using design implementation described in application note XAPP852, Synthesizable RLDRAM II Controller.
DS714 (v2.2) January 17, 2011
www.xilinx.com
Product Specification
27
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Switching Characteristics
All values represented in this data sheet are based on
speed specification version 1.71. Switching characteristics
are specified on a per-speed-grade basis and can be
designated as Advance, Preliminary, or Production. Each
designation is defined as follows:
All specifications are always representative of worst-case
supply voltage and junction temperature conditions.
Since individual family members are produced at different
times, the migration from one category to another depends
completely on the status of the fabrication process for each
device.
Advance
These specifications are based on simulations only and are
typically available soon after device design specifications
are frozen. Although speed grades with this designation are
considered relatively stable and conservative, some under-
reporting might still occur.
Table 54 correlates the current status of each Virtex-5Q
device on a per speed grade basis.
Table 54: Virtex-5Q Device Speed Grade Designations
Speed Grade Designations
Device
Advance
Preliminary
Production
-2I, -1I
-2I, -1I
-2I, -1I
-2I, -1I
-2I, -1I
-2I, -1I
-1I
Preliminary
XQ5VLX30T
XQ5VLX85
These specifications are based on complete ES
(engineering sample) silicon characterization. Devices and
speed grades with this designation are intended to give a
better indication of the expected performance of production
silicon. The probability of under-reporting delays is greatly
reduced as compared to Advance data.
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
Production
These specifications are released once enough production
silicon of a particular device family member has been
characterized to provide full correlation between
specifications and devices over numerous production lots.
There is no under-reporting of delays, and customers
receive formal notification of any subsequent changes.
Typically, the slowest speed grades transition to Production
before faster speed grades.
-2I, -1I
-2I, -1I
-1I
-2I, -1I, -1M
-2I, -1I, -1M
-2I, -1I
-1I
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed
below are representative values.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and
back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-5Q devices.
DS714 (v2.2) January 17, 2011
www.xilinx.com
Product Specification
28
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Production Silicon and ISE Software Status
In some cases, a particular family member (and speed
grade) is released to production before a speed
specification is released with the correct label (Advance,
Preliminary, Production). Any labeling discrepancies are
corrected in subsequent speed specification releases.
Table 55 lists the production released Virtex-5Q family
member, speed grade, and the minimum corresponding
supported speed specification version and ISE® software
revisions. The ISE software and speed specifications listed
are the minimum releases required for production. All
subsequent releases of software and speed specifications
are valid.
(1)
Table 55: Virtex-5Q Device Production Software
and Speed Specification Release
Speed Grade Designations
Device
-2I
-1I
-1M
N/A
XQ5VLX30T
XQ5VLX85
ISE 11.2 v1.65
N/A
ISE 11.2 v1.65
ISE 11.2 v1.65
N/A
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
N/A
ISE 11.2 v1.65
N/A
ISE 11.2 v1.65
ISE 12.2 v1.71 ISE 11.2 v1.65
N/A
ISE 11.2 v1.65
ISE 11.2 v1.65
ISE 12.2 v1.71 ISE 11.2 v1.65
ISE 11.2 v1.65
N/A
N/A
N/A
N/A
N/A
N/A
ISE 11.2 v1.65
ISE 12.4 v1.71
ISE 12.4 v1.71
N/A
ISE 11.2 v1.65
ISE 11.2 v1.65
ISE 11.2 v1.65
N/A
N/A
Notes:
1. Listed software revisions are those for production-released
Virtex-5Q family members.
2. Blank entries indicate a device and/or speed grade in advance or
preliminary status.
DS714 (v2.2) January 17, 2011
www.xilinx.com
Product Specification
29
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
IOB Pad Input/Output/3-State Switching Characteristics
Table 56 summarizes the values of standard-specific data
input delay adjustments, output delays terminating at pads
(based on standard) and 3-state delays.
T
is described as the delay from the T pin to the IOB
IOTP
pad through the output buffer of an IOB pad, when 3-state is
disabled. The delay varies depending on the SelectIO
capability of the output buffer.
T
is described as the delay from IOB pad through the
IOPI
input buffer to the I-pin of an IOB pad. The delay varies
depending on the capability of the SelectIO input buffer.
Table 57, page 34 summarizes the value of T
.
IOTPHZ
T
is described as the delay from the T pin to the IOB
IOTPHZ
pad through the output buffer of an IOB pad, when 3-state is
enabled (i.e., a high impedance state).
T
is described as the delay from the O pin to the IOB
IOOP
pad through the output buffer of an IOB pad. The delay
varies depending on the capability of the SelectIO output
buffer.
Table 56: IOB Switching Characteristics
TIOPI
TIOOP
Speed Grade
-1(I)
TIOTP
Speed Grade
-1(I)
I/O Standard
Speed Grade
-1(I)
Units
-2(I)
0.90
1.16
0.90
0.90
0.90
0.90
0.70
0.70
0.70
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.70
0.70
0.70
0.70
0.70
0.70
0.70
-1(M)
1.11
1.36
1.11
1.12
1.11
1.11
1.05
1.05
1.05
1.11
1.05
1.07
1.05
1.40
1.40
1.26
1.13
1.45
1.45
1.11
1.11
1.02
1.02
1.02
1.02
1.02
1.02
1.02
-2(I)
1.29
1.34
1.26
1.38
1.29
1.27
2.06
2.06
1.56
1.63
1.68
1.57
1.53
1.60
1.60
1.55
1.51
1.61
1.57
1.64
1.55
4.47
3.09
2.91
2.30
2.15
2.04
2.07
-1(M)
1.79
1.82
1.79
1.91
1.79
1.79
2.41
2.41
2.03
2.10
2.14
1.96
1.84
2.03
2.07
1.91
1.79
1.98
1.92
1.94
1.83
6.05
4.13
3.91
2.91
2.56
2.47
2.48
-2(I)
1.29
1.34
1.26
1.38
1.29
1.27
2.06
2.06
1.56
1.63
1.68
1.57
1.53
1.60
1.60
1.55
1.51
1.61
1.57
1.64
1.55
4.47
3.09
2.91
2.30
2.15
2.04
2.07
-1(M)
1.79
1.82
1.79
1.91
1.79
1.79
2.41
2.41
2.03
2.10
2.14
1.96
1.84
2.03
2.07
1.91
1.79
1.98
1.92
1.94
1.83
6.05
4.13
3.91
2.91
2.56
2.47
2.48
LVDS_25
1.06
1.30
1.06
1.06
1.06
1.06
0.82
0.82
0.82
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
0.82
0.82
0.82
0.82
0.82
0.82
0.82
1.44
1.44
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVDSEXT_25
HT_25
1.49
1.49
1.40
1.40
BLVDS_25
1.58
1.58
RSDS_25 (point to point)
ULVDS_25
1.44
1.44
1.41
1.41
PCI33_3
2.38
2.38
PCI66_3
2.38
2.38
PCI-X
1.80
1.80
GTL
1.86
1.86
GTLP
1.93
1.93
HSTL_I
1.79
1.79
HSTL_II
1.74
1.74
HSTL_III
1.85
1.85
HSTL_IV
1.83
1.83
HSTL_I _18
HSTL_II _18
HSTL_III _18
HSTL_IV_18
SSTL2_I
1.77
1.77
1.72
1.72
1.85
1.85
1.81
1.81
1.78
1.78
SSTL2_II
1.76
1.76
LVTTL, Slow, 2 mA
LVTTL, Slow, 4 mA
LVTTL, Slow, 6 mA
LVTTL, Slow, 8 mA
LVTTL, Slow, 12 mA
LVTTL, Slow, 16 mA
LVTTL, Slow, 24 mA
5.01
5.01
3.41
3.41
3.29
3.29
2.61
2.61
2.46
2.46
2.34
2.34
2.38
2.38
DS714 (v2.2) January 17, 2011
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Product Specification
30
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 56: IOB Switching Characteristics (Cont’d)
TIOPI
TIOOP
Speed Grade
-1(I)
TIOTP
Speed Grade
-1(I)
I/O Standard
Speed Grade
-1(I)
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.89
0.89
0.89
0.89
Units
-2(I)
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.70
0.76
0.76
0.76
0.76
-1(M)
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.02
1.02
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.82
1.14
1.14
1.14
1.14
-2(I)
3.61
2.55
2.31
1.82
1.63
1.57
1.52
3.96
3.09
2.86
2.26
2.14
2.04
2.07
3.20
2.50
2.27
1.79
1.61
1.56
1.51
3.97
2.60
2.41
2.26
2.31
2.02
2.04
3.41
2.08
1.92
1.83
1.69
1.60
1.54
4.56
3.32
2.61
2.37
-1(M)
5.58
3.72
3.34
2.39
2.31
2.27
2.27
6.05
4.13
3.89
2.91
2.56
2.44
2.48
5.56
3.70
3.32
2.35
2.31
2.28
2.26
5.06
3.71
3.42
2.93
2.73
2.31
2.37
4.48
3.23
2.89
2.38
1.94
1.99
1.98
6.81
4.30
3.76
3.32
-2(I)
3.61
2.55
2.31
1.82
1.63
1.57
1.52
3.96
3.09
2.86
2.26
2.14
2.04
2.07
3.20
2.50
2.27
1.79
1.61
1.56
1.51
3.97
2.60
2.41
2.26
2.31
2.02
2.04
3.41
2.08
1.92
1.83
1.69
1.60
1.54
4.56
3.32
2.61
2.37
-1(M)
5.58
3.72
3.34
2.39
2.31
2.27
2.27
6.05
4.13
3.89
2.91
2.56
2.44
2.48
5.56
3.70
3.32
2.35
2.31
2.28
2.26
5.06
3.71
3.42
2.93
2.73
2.31
2.37
4.48
3.23
2.89
2.38
1.94
1.99
1.98
6.81
4.30
3.76
3.32
LVTTL, Fast, 2 mA
4.05
2.90
2.63
2.09
1.89
1.81
1.74
4.44
3.49
3.24
2.57
2.42
2.31
2.35
3.59
2.84
2.59
2.05
1.86
1.80
1.74
4.42
2.94
2.74
2.56
2.63
2.30
2.34
3.82
2.37
2.20
2.09
1.94
1.85
1.76
5.09
3.75
2.97
2.69
4.05
2.90
2.63
2.09
1.89
1.81
1.74
4.44
3.49
3.24
2.57
2.42
2.31
2.35
3.59
2.84
2.59
2.05
1.86
1.80
1.74
4.42
2.94
2.74
2.56
2.63
2.30
2.34
3.82
2.37
2.20
2.09
1.94
1.85
1.76
5.09
3.75
2.97
2.69
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVTTL, Fast, 4 mA
LVTTL, Fast, 6 mA
LVTTL, Fast, 8 mA
LVTTL, Fast, 12 mA
LVTTL, Fast, 16 mA
LVTTL, Fast, 24 mA
LVCMOS33, Slow, 2 mA
LVCMOS33, Slow, 4 mA
LVCMOS33, Slow, 6 mA
LVCMOS33, Slow, 8 mA
LVCMOS33, Slow, 12 mA
LVCMOS33, Slow, 16 mA
LVCMOS33, Slow, 24 mA
LVCMOS33, Fast, 2 mA
LVCMOS33, Fast, 4 mA
LVCMOS33, Fast, 6 mA
LVCMOS33, Fast, 8 mA
LVCMOS33, Fast, 12 mA
LVCMOS33, Fast, 16 mA
LVCMOS33, Fast, 24 mA
LVCMOS25, Slow, 2 mA
LVCMOS25, Slow, 4 mA
LVCMOS25, Slow, 6 mA
LVCMOS25, Slow, 8 mA
LVCMOS25, Slow, 12 mA
LVCMOS25, Slow, 16 mA
LVCMOS25, Slow, 24 mA
LVCMOS25, Fast, 2 mA
LVCMOS25, Fast, 4 mA
LVCMOS25, Fast, 6 mA
LVCMOS25, Fast, 8 mA
LVCMOS25, Fast, 12 mA
LVCMOS25, Fast, 16 mA
LVCMOS25, Fast, 24 mA
LVCMOS18, Slow, 2 mA
LVCMOS18, Slow, 4 mA
LVCMOS18, Slow, 6 mA
LVCMOS18, Slow, 8 mA
DS714 (v2.2) January 17, 2011
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Product Specification
31
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 56: IOB Switching Characteristics (Cont’d)
TIOPI
TIOOP
Speed Grade
-1(I)
TIOTP
Speed Grade
-1(I)
I/O Standard
Speed Grade
-1(I)
0.89
0.89
0.89
0.89
0.89
0.89
0.89
0.89
0.98
0.98
0.98
0.98
0.98
0.98
0.98
0.98
0.98
0.98
0.98
0.98
1.14
1.14
1.14
1.14
1.14
1.14
1.14
1.14
0.82
0.82
0.89
0.98
0.82
0.89
0.98
1.00
1.00
1.06
Units
-2(I)
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.76
0.83
0.83
0.83
0.83
0.83
0.83
0.83
0.83
0.83
0.83
0.83
0.83
0.96
0.96
0.96
0.96
0.96
0.96
0.96
0.96
0.70
0.70
0.76
0.83
0.70
0.76
0.83
0.85
0.85
0.90
-1(M)
1.14
1.14
1.14
1.14
1.14
1.14
1.14
1.14
1.23
1.23
1.23
1.23
1.23
1.23
1.23
1.23
1.23
1.23
1.23
1.23
1.61
1.61
1.61
1.61
1.61
1.61
1.61
1.61
1.02
0.82
1.14
1.23
0.82
1.14
1.23
1.11
1.05
1.12
-2(I)
2.16
2.14
3.71
2.61
2.06
1.87
1.68
1.61
3.84
2.40
2.20
2.12
1.95
1.91
3.07
1.95
1.80
1.74
1.60
1.53
3.98
2.33
2.18
2.14
3.38
1.91
1.78
1.70
1.66
1.71
1.78
1.75
1.51
1.60
1.65
1.47
1.52
1.42
-1(M)
2.59
2.53
6.23
3.80
3.30
2.66
2.07
1.97
5.08
3.48
2.55
2.46
2.28
2.23
4.99
3.39
2.41
2.26
1.99
1.92
5.58
3.13
2.54
2.51
5.54
3.01
2.44
2.28
2.66
2.65
2.85
2.74
2.12
2.16
2.33
1.79
1.94
1.91
-2(I)
2.16
2.14
3.71
2.61
2.06
1.87
1.68
1.61
3.84
2.40
2.20
2.12
1.95
1.91
3.07
1.95
1.80
1.74
1.60
1.53
3.98
2.33
2.18
2.14
3.38
1.91
1.78
1.70
1.66
1.71
1.78
1.75
1.51
1.60
1.65
1.47
1.52
1.42
-1(M)
2.59
2.53
6.23
3.80
3.30
2.66
2.07
1.97
5.08
3.48
2.55
2.46
2.28
2.23
4.99
3.39
2.41
2.26
1.99
1.92
5.58
3.13
2.54
2.51
5.54
3.01
2.44
2.28
2.66
2.65
2.85
2.74
2.12
2.16
2.33
1.79
1.94
1.91
LVCMOS18, Slow, 12 mA
LVCMOS18, Slow, 16 mA
LVCMOS18, Fast, 2 mA
LVCMOS18, Fast, 4 mA
LVCMOS18, Fast, 6 mA
LVCMOS18, Fast, 8 mA
LVCMOS18, Fast, 12 mA
LVCMOS18, Fast, 16 mA
LVCMOS15, Slow, 2 mA
LVCMOS15, Slow, 4 mA
LVCMOS15, Slow, 6 mA
LVCMOS15, Slow, 8 mA
LVCMOS15, Slow, 12 mA
LVCMOS15, Slow, 16 mA
LVCMOS15, Fast, 2 mA
LVCMOS15, Fast, 4 mA
LVCMOS15, Fast, 6 mA
LVCMOS15, Fast, 8 mA
LVCMOS15, Fast, 12 mA
LVCMOS15, Fast, 16 mA
LVCMOS12, Slow, 2 mA
LVCMOS12, Slow, 4 mA
LVCMOS12, Slow, 6 mA
LVCMOS12, Slow, 8 mA
LVCMOS12, Fast, 2 mA
LVCMOS12, Fast, 4 mA
LVCMOS12, Fast, 6 mA
LVCMOS12, Fast, 8 mA
LVDCI_33
2.47
2.45
4.16
2.98
2.35
2.13
1.93
1.86
4.34
2.74
2.52
2.43
2.25
2.20
3.48
2.23
2.06
2.00
1.86
1.77
4.58
2.66
2.45
2.48
3.87
2.20
2.08
1.97
1.90
1.93
1.99
2.02
1.74
1.85
1.91
1.65
1.76
1.62
2.47
2.45
4.16
2.98
2.35
2.13
1.93
1.86
4.34
2.74
2.52
2.43
2.25
2.20
3.48
2.23
2.06
2.00
1.86
1.77
4.58
2.66
2.45
2.48
3.87
2.20
2.08
1.97
1.90
1.93
1.99
2.02
1.74
1.85
1.91
1.65
1.76
1.62
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVDCI_25
LVDCI_18
LVDCI_15
LVDCI_DV2_25
LVDCI_DV2_18
LVDCI_DV2_15
GTL_DCI
GTLP_DCI
LVPECL_25
DS714 (v2.2) January 17, 2011
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Product Specification
32
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 56: IOB Switching Characteristics (Cont’d)
TIOPI
TIOOP
Speed Grade
-1(I)
TIOTP
Speed Grade
-1(I)
I/O Standard
Speed Grade
-1(I)
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.00
1.06
1.06
1.06
1.06
1.06
1.06
1.06
1.06
Units
-2(I)
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.90
0.90
0.90
0.90
0.90
0.90
0.90
0.90
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.85
0.90
0.90
0.90
0.90
0.90
0.90
0.90
0.90
-1(M)
1.08
1.07
1.05
1.05
1.40
1.40
1.26
1.13
1.13
1.45
1.45
1.10
1.10
1.10
1.10
1.10
1.10
1.10
1.10
1.11
1.11
1.11
1.08
1.08
1.08
1.08
1.08
1.11
1.11
1.10
1.10
1.11
1.11
1.10
1.10
-2(I)
1.61
1.56
1.48
1.56
1.72
1.46
1.50
1.43
1.50
1.69
1.44
1.55
1.50
1.57
1.56
1.51
1.43
1.53
1.48
1.56
1.48
1.56
1.61
1.53
1.53
1.44
1.53
1.64
1.56
1.61
1.53
1.55
1.48
1.53
1.44
-1(M)
1.98
1.98
1.86
1.98
2.27
1.84
1.95
1.77
1.95
2.16
1.84
1.91
1.91
1.91
1.95
1.91
1.91
1.91
1.91
3.30
1.97
3.30
1.94
1.81
1.97
1.86
1.97
1.97
1.94
1.94
1.94
1.91
1.90
1.91
1.91
-2(I)
1.61
1.56
1.48
1.56
1.72
1.46
1.50
1.43
1.50
1.69
1.44
1.55
1.50
1.57
1.56
1.51
1.43
1.53
1.48
1.56
1.48
1.56
1.61
1.53
1.53
1.44
1.53
1.64
1.56
1.61
1.53
1.55
1.48
1.53
1.44
-1(M)
1.98
1.98
1.86
1.98
2.27
1.84
1.95
1.77
1.95
2.16
1.84
1.91
1.91
1.91
1.95
1.91
1.91
1.91
1.91
3.30
1.97
3.30
1.94
1.81
1.97
1.86
1.97
1.97
1.94
1.94
1.94
1.91
1.90
1.91
1.91
HSTL_I_12
1.85
1.77
1.69
1.77
1.95
1.64
1.70
1.64
1.70
1.91
1.62
1.77
1.70
1.79
1.77
1.72
1.64
1.74
1.69
1.78
1.70
1.78
1.84
1.75
1.74
1.64
1.74
1.87
1.78
1.84
1.74
1.76
1.70
1.75
1.64
1.85
1.77
1.69
1.77
1.95
1.64
1.70
1.64
1.70
1.91
1.62
1.77
1.70
1.79
1.77
1.72
1.64
1.74
1.69
1.78
1.70
1.78
1.84
1.75
1.74
1.64
1.74
1.87
1.78
1.84
1.74
1.76
1.70
1.75
1.64
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HSTL_I_DCI
HSTL_II_DCI
HSTL_II_T_DCI
HSTL_III_DCI
HSTL_IV_DCI
HSTL_I_DCI_18
HSTL_II_DCI_18
HSTL_II _T_DCI_18
HSTL_III_DCI_18
HSTL_IV_DCI_18
DIFF_HSTL_I_18
DIFF_HSTL_I_DCI_18
DIFF_HSTL_I
DIFF_HSTL_I_DCI
DIFF_HSTL_II_18
DIFF_HSTL_II_DCI_18
DIFF_HSTL_II
DIFF_HSTL_II_DCI
SSTL2_I_DCI
SSTL2_II_DCI
SSTL2_II_T_DCI
SSTL18_I
SSTL18_II
SSTL18_I_DCI
SSTL18_II_DCI
SSTL18_II_T_DCI
DIFF_SSTL2_I
DIFF_SSTL2_I_DCI
DIFF_SSTL18_I
DIFF_SSTL18_I_DCI
DIFF_SSTL2_II
DIFF_SSTL2_II_DCI
DIFF_SSTL18_II
DIFF_SSTL18_II_DCI
Notes:
1. M-temperature IOB delays are slightly larger than timing analyzer/speeds specification values. Correct values are listed in this table. It is
necessary to allow for this difference in the design.
DS714 (v2.2) January 17, 2011
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Product Specification
33
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 57: IOB 3-state ON Output Switching Characteristics (T
)
IOTPHZ
Speed Grade
Symbol
Description
Units
-2I
-1I
-1M
TIOTPHZ
T input to Pad high-impedance
1.01
1.12
1.12
ns
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 58 shows the test setup parameters used for measuring input delay.
Table 58: Input Delay Measurement Methodology
VMEAS
VREF
(1)(2)
(1)(2)
Description
I/O Standard Attribute
VL
VH
(1)(4)(5)
(1)(3)(5)
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS, 2.5V
LVTTL
0
0
0
0
0
0
3.0
3.3
2.5
1.8
1.5
1.2
1.4
1.65
1.25
0.9
–
–
–
–
–
–
–
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
PCI33_3
LVCMOS, 1.8V
LVCMOS, 1.5V
0.75
0.6
LVCMOS, 1.2V
PCI (Peripheral Component Interconnect),
33 MHz, 3.3V
Per PCI™ Specification
PCI, 66 MHz, 3.3V
PCI66_3
PCIX
Per PCI Specification
–
PCI-X, 133 MHz, 3.3V
GTL (Gunning Transceiver Logic)
GTL Plus
Per PCI-X™ Specification
–
GTL
V
REF – 0.2
VREF + 0.2
VREF + 0.2
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF
VREF
VREF
VREF
VREF
0.80
1.0
GTLP
VREF – 0.2
VREF – 0.5
VREF – 0.5
VREF – 0.5
HSTL (High-Speed Transceiver Logic), Class I & II HSTL_I, HSTL_II
0.75
0.90
0.90
HSTL, Class III & IV
HSTL_III, HSTL_IV
HSTL, Class I & II, 1.8V
HSTL_I_18,
HSTL_II_18
HSTL, Class III & IV, 1.8V
HSTL_III_18,
HSTL_IV_18
V
REF – 0.5
VREF + 0.5
VREF
VREF
1.08
1.5
SSTL (Stub Terminated Transceiver Logic),
Class I & II, 3.3V
SSTL3_I, SSTL3_II
V
REF – 1.00
VREF + 1.00
SSTL, Class I & II, 2.5V
SSTL2_I, SSTL2_II
SSTL18_I, SSTL18_II
AGP
VREF – 0.75
VREF – 0.5
VREF + 0.75
VREF + 0.5
VREF
VREF
VREF
1.25
0.90
SSTL, Class I & II, 1.8V
AGP-2X/AGP (Accelerated Graphics Port)
VREF
–
VREF
+
AGP
Spec
(0.2xVCCO
)
(0.2xVCCO
)
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDSEXT (LVDS Extended Mode), 2.5V
LDT (HyperTransport), 2.5V
LVDS_25
1.2 – 0.125
1.2 – 0.125
0.6 – 0.125
1.15 – 0.3
1.2 + 0.125
1.2 + 0.125
0.6 + 0.125
1.15 – 0.3
0(6)
0(6)
0(6)
0(6)
LVDSEXT_25
LDT_25
LVPECL (Low-Voltage Positive Emitter-Coupled
Logic), 2.5V
LVPECL_25
Notes:
1. The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay
measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other
DCI standards are the same for the corresponding non-DCI standards.
2. Input waveform switches between V and V .
L
H
3. Measurements are made at typical, minimum, and maximum V
values listed are typical.
values. Reported delays reflect worst case of these measurements. V
REF
REF
4. Input voltage level from which measurement starts.
5. This is an input voltage reference that bears no relation to the V
page 35.
/ V
parameters found in IBIS models and/or noted in Figure 11,
REF
MEAS
6. The value given is the differential input voltage.
DS714 (v2.2) January 17, 2011
www.xilinx.com
Product Specification
34
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Output Delay Measurements
X-Ref Target - Figure 12
FPGA Output
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4" of FR4
microstrip trace. Standard termination was used for all
testing. The propagation delay of the 4" trace is
+
CREF
RREF VMEAS
characterized separately and subtracted from the final
measurement, and is therefore not included in the
generalized test setups shown in Figure 11 and Figure 12.
–
ds714_12_012109
X-Ref Target - Figure 11
Figure 12: Differential Test Setup
VREF
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it.
Parameters V
, R
, C
, and V
fully describe
REF
REF
REF
MEAS
RREF
FPGA Output
the test conditions for each I/O standard. The most accurate
prediction of propagation delay in any given application can
be obtained through IBIS simulation, using the following
method:
VMEAS
(voltage level when taking
delay measurement)
1. Simulate the output driver of choice into the generalized
test setup, using values from Table 59.
CREF
(probe capacitance)
2. Record the time to V
.
MEAS
DS714_11_012109
3. Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
Figure 11: Single Ended Test Setup
4. Record the time to V
.
MEAS
5. Compare the results of step 2 and step 4. The increase
or decrease in delay yields the actual propagation delay
of the PCB trace.
Table 59: Output Delay Measurement Methodology
(1)
I/O Standard
Attribute
RREF CREF
VMEAS VREF
Description
()
1M
1M
1M
1M
1M
1M
25
(pF)
(V)
(V)
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS, 2.5V
LVTTL (all)
0
0
1.4
0
LVCMOS33
1.65
1.25
0.9
0
LVCMOS25
0
0
LVCMOS, 1.8V
LVCMOS18
0
0
LVCMOS, 1.5V
LVCMOS15
0
0.75
0.6
0
LVCMOS, 1.2V
LVCMOS12
0
0
PCI33_3 (rising edge)
PCI33_3 (falling edge)
PCI66_3 (rising edge)
PCI66_3 (falling edge)
PCIX (rising edge)
PCIX (falling edge
GTL
10(2)
10(2)
10(2)
10(2)
10(3)
10(3)
0
0.94
2.03
0.94
2.03
0.94
2.03
0.8
0
PCI (Peripheral Component Interface), 33 MHz, 3.3V
PCI, 66 MHz, 3.3V
25
3.3
0
25
25
3.3
25
PCI-X, 133 MHz, 3.3V
25
3.3
1.2
GTL (Gunning Transceiver Logic)
GTL Plus
25
GTLP
25
0
1.0
1.5
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
HSTL_I
50
0
VREF
VREF
0.9
0.75
0.75
1.5
HSTL_II
25
0
HSTL, Class III
HSTL_III
50
0
DS714 (v2.2) January 17, 2011
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Product Specification
35
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 59: Output Delay Measurement Methodology (Cont’d)
(1)
I/O Standard
Attribute
RREF CREF
VMEAS VREF
Description
()
(pF)
(V)
(V)
1.5
0.9
0.9
1.8
1.8
0.9
0.9
1.25
1.25
1.2
1.2
0
HSTL, Class IV
HSTL_IV
25
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0.9
HSTL, Class I, 1.8V
HSTL, Class II, 1.8V
HSTL, Class III, 1.8V
HSTL, Class IV, 1.8V
HSTL_I_18
50
VREF
VREF
1.1
HSTL_II_18
HSTL_III_18
HSTL_IV_18
SSTL18_I
SSTL18_II
SSTL2_I
25
50
25
1.1
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
50
VREF
VREF
VREF
VREF
0(4)
25
SSTL, Class I, 2.5V
50
SSTL, Class II, 2.5V
SSTL2_II
25
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDSEXT (LVDS Extended Mode), 2.5V
BLVDS (Bus LVDS), 2.5V
LVDS_25
100
100
100
100
100
LVDS_25
0(4)
BLVDS_25
LDT_25
0(4)
LDT (HyperTransport), 2.5V
0(4)
0.6
0
LVPECL (Low-Voltage Positive Emitter-Coupled Logic),
2.5V
LVPECL_25
0(4)
LVDCI/HSLVDCI
LVDCI_33, HSLVDCI_33
1M
0
1.65
0
(Low-Voltage Digitally Controlled Impedance), 3.3V
LVDCI/HSLVDCI, 2.5V
LVDCI/HSLVDCI, 1.8V
LVDCI/HSLVDCI, 1.5V
LVDCI_25, HSLVDCI_25
LVDCI_18, HSLVDCI_18
LVDCI_15, HSLVDCI_15
1M
1M
1M
50
0
0
0
0
0
0
0
1.25
0.9
0
0
0.75
VREF
0.9
0
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI
0.75
1.5
0.9
1.8
HSTL, Class III & IV, with DCI
HSTL_III_DCI, HSTL_IV_DCI
50
HSTL, Class I & II, 1.8V, with DCI
HSTL, Class III & IV, 1.8V, with DCI
HSTL_I_DCI_18, HSTL_II_DCI_18
50
VREF
1.1
HSTL_III_DCI_18,
HSTL_IV_DCI_18
50
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI
50
50
50
50
0
0
0
0
VREF
VREF
0.8
0.9
1.25
1.2
SSTL, Class I & II, 2.5V, with DCI
GTL (Gunning Transceiver Logic) with DCI
GTL Plus with DCI
SSTL2_I_DCI, SSTL2_II_DCI
GTL_DCI
GTLP_DCI
1.0
1.5
Notes:
1.
C
is the capacitance of the probe, nominally 0 pF.
REF
2. Per PCI specifications.
3. Per PCI-X specifications.
4. The value given is the differential input voltage.
DS714 (v2.2) January 17, 2011
www.xilinx.com
Product Specification
36
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Input/Output Logic Switching Characteristics
Table 60: ILOGIC Switching Characteristics
Symbol Description
Setup/Hold
Speed Grade
-1I
Units
-2I
-1M
0.49
–0.24
0.59
–0.24
0.59
–0.17
TICE1CK/TICKCE1
TISRCK/TICKSR
TIDOCK/TIOCKD
TIDOCKD/TIOCKDD
CE1 pin Setup/Hold with respect to CLK
ns
ns
ns
ns
1.00
–0.20
1.22
–0.20
1.22
–0.22
SR/REV pin Setup/Hold with respect to CLK
0.37
–0.12
0.39
–0.12
0.39
–0.12
D pin Setup/Hold with respect to CLK without Delay
DDLY pin Setup/Hold with respect to CLK (using IODELAY)
0.33
–0.09
0.36
–0.08
0.36
–0.08
Combinatorial
TIDI
D pin to O pin propagation delay, no Delay
0.26
0.22
0.30
0.26
0.30
0.26
ns
ns
TIDID
DDLY pin to O pin propagation delay (using IODELAY)
Sequential Delays
TIDLO
D pin to Q1 pin using flip-flop as a latch without Delay
DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY)
CLK to Q outputs
0.50
0.46
0.52
1.28
7.30
0.58
0.55
0.60
1.53
10.10
0.58
0.55
0.60
1.53
10.10
ns
ns
ns
ns
ns
TIDLOD
TICKQ
TRQ
SR/REV pin to OQ/TQ out
TGSRQ
Global Set/Reset to Q outputs
Set/Reset
TRPW
Minimum Pulse Width, SR/REV inputs
0.95
1.20
1.20
ns, Min
Table 61: OLOGIC Switching Characteristics
Symbol Description
Setup/Hold
TODCK/TOCKD
OOCECK/TOCKOCE
OSRCK/TOCKSR
OTCK/TOCKT
OTCECK/TOCKTCE
Speed Grade
-1I
Units
-2I
-1M
0.36
–0.21
0.44
–0.21
0.44
–0.14
ns
ns
ns
ns
ns
D1/D2 pins Setup/Hold with respect to CLK
OCE pin Setup/Hold with respect to CLK
SR/REV pin Setup/Hold with respect to CLK
T1/T2 pins Setup/Hold with respect to CLK
TCE pin Setup/Hold with respect to CLK
0.19
–0.07
0.23
–0.07
0.23
–0.04
T
1.02
–0.20
1.16
–0.20
1.16
–0.20
T
0.34
–0.18
0.41
–0.18
0.41
–0.12
T
0.23
–0.06
0.29
–0.06
0.29
–0.01
T
Combinatorial
TDOQ
D1 to OQ out or T1 to TQ out
0.70
0.83
0.83
ns
Sequential Delays
TOCKQ
CLK to OQ/TQ out
0.62
1.89
7.30
0.62
2.27
0.62
2.27
ns
ns
ns
TRQ
SR/REV pin to OQ/TQ out
Global Set/Reset to Q outputs
TGSRQ
10.10
10.10
Set/Reset
TRPW
Minimum Pulse Width, SR/REV inputs
0.98
1.25
1.25
ns, Min
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 62: ISERDES Switching Characteristics
Speed Grade
-1I
Symbol
Description
Units
-2I
-1M
Setup/Hold for Control Lines
0.11
0.00
0.12
0.00
0.12
0.00
ns
ns
ns
TISCCK_BITSLIP/ TISCKC_BITSLIP
BITSLIP pin Setup/Hold with respect to CLKDIV
CE pin Setup/Hold with respect to CLK (for CE1)
CE pin Setup/Hold with respect to CLKDIV (for CE2)
0.49
–0.24
0.59
–0.24
0.59
–0.17
(2)
TISCCK_CE / TISCKC_CE
0.04
0.13
0.06
0.15
0.06
0.15
(2)
TISCCK_CE2 / TISCKC_CE2
Setup/Hold for Data Lines
0.37
–0.12
0.39
–0.12
0.39
–0.12
ns
ns
ns
ns
TISDCK_D /TISCKD_D
D pin Setup/Hold with respect to CLK
DDLY pin Setup/Hold with respect to CLK (using
IODELAY)
0.33
–0.09
0.36
–0.08
0.36
–0.08
TISDCK_DDLY /TISCKD_DDLY
0.37
–0.12
0.39
–0.12
0.39
–0.12
T
ISDCK_DDR /TISCKD_DDR
D pin Setup/Hold with respect to CLK at DDR mode
TISDCK_DDLY_DDR
TISCKD_DDLY_DDR
D pin Setup/Hold with respect to CLK at DDR mode
(using IODELAY)
0.33
–0.09
0.36
–0.08
0.36
–0.08
Sequential Delays
TISCKO_Q
CLKDIV to out at Q pin
D input to DO output pin
0.51
0.22
0.60
0.26
0.60
0.26
ns
ns
Propagation Delays
TISDO_DO
Notes:
1. Recorded at 0 tap value.
2.
T
and T
are reported as T
/T
in TRACE report.
ISCCK_CE2
ISCKC_CE2
ISCCK_CE ISCKC_CE
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Output Serializer/Deserializer Switching Characteristics
Table 63: OSERDES Switching Characteristics
Speed Grade
-1I
Symbol
Description
Units
-2I
-1M
Setup/Hold
0.24
–0.02
0.30
–0.02
0.30
–0.02
ns
ns
ns
ns
TOSDCK_D/TOSCKD_D
D input Setup/Hold with respect to CLKDIV
T input Setup/Hold with respect to CLK
T input Setup/Hold with respect to CLKDIV
0.34
–0.18
0.41
–0.18
0.41
–0.12
(1)
TOSDCK_T/TOSCKD_T
0.24
–0.03
0.28
–0.03
0.28
–0.03
(1)
TOSDCK_T2/TOSCKD_T2
TOSCCK_OCE/TOSCKC_OCE
TOSCCK_S
OSCCK_TCE/TOSCKC_TCE
0.19
–0.07
0.23
–0.07
0.23
–0.04
OCE input Setup/Hold with respect to CLK
SR (Reset) input Setup with respect to CLKDIV
TCE input Setup/Hold with respect to CLK
0.58
0.70
0.70
ns
ns
0.23
–0.06
0.29
–0.06
0.29
–0.01
T
Sequential Delays
TOSCKO_OQ
Clock to out from CLK to OQ
Clock to out from CLK to TQ
0.60
0.62
0.61
0.62
0.61
0.62
ns
ns
TOSCKO_TQ
Combinatorial
TOSDO_TTQ
T input to TQ Out
0.70
1.82
1.89
0.83
2.19
2.27
0.83
2.19
2.27
ns
ns
ns
TOSCO_OQ
Asynchronous Reset to OQ
Asynchronous Reset to TQ
TOSCO_TQ
Notes:
1.
T
and T
are reported as T
T
in TRACE report.
OSDCK_T2
OSCKD_T2
OSDCK_T/ OSCKD_T
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Input/Output Delay Switching Characteristics
Table 64: Input/Output Delay Switching Characteristics
Speed Grade
-1I
Symbol
Description
Units
-2I
-1M
IDELAYCTRL
TIDELAYCTRLCO_RDY
FIDELAYCTRL_REF
Reset to Ready for IDELAYCTRL
REFCLK frequency
3.00
200.00
10
3.00
200.00
10
3.00
200.00
10
µs
MHz
MHz
ns
IDELAYCTRL_REF_PRECISION REFCLK precision
TIDELAYCTRL_RPW
IODELAY
Minimum Reset pulse width
50.00
50.00
50.00
TIDELAYRESOLUTION
IODELAY Chain Delay Resolution
1/(64 x FREF x 1e6)(1)
0
ps
Pattern dependent period jitter in delay chain for clock
pattern
0
0
Note 2
TIDELAYPAT_JIT
Pattern dependent period jitter in delay chain for
random data pattern (PRBS 23)
5
5
5
Note 2
MHz
ns
TIODELAY_CLK_MAX
Maximum frequency of CLK input to IODELAY
CE pin Setup/Hold with respect to CK
250
250
250
0.34
–0.06
0.42
–0.06
0.42
–0.06
T
T
IODCCK_CE / TIODCKC_CE
IODCK_INC/ TIODCKC_INC
0.20
0.04
0.24
0.06
0.24
0.06
INC pin Setup/Hold with respect to CK
RST pin Setup/Hold with respect to CK
ns
ns
0.28
–0.12
0.33
–0.12
0.33
–0.12
TIODCK_RST/ TIODCKC_RST
TIODDO_T
TSCONTROL delay to MUXE/MUXF switching and
through IODELAY
Note 3
Note 3
Note 3
TIODDO_IDATAIN
TIODDO_ODATAIN
Propagation delay through IODELAY
Propagation delay through IODELAY
Note 3
Note 3
Note 3
Note 3
Note 3
Note 3
Notes:
1. Average Tap Delay at 200 MHz = 78 ps.
2. Units in ps, peak-to-peak per tap, in High Performance mode.
3. Delay depends on IODELAY tap setting. See TRACE report for actual values.
CLB Switching Characteristics
Table 65: CLB Switching Characteristics
Speed Grade
-1I
Symbol
Description
Units
-2I
-1M
Combinatorial Delays
TILO
An – Dn LUT address to A
0.09
0.22
0.35
0.77
0.44
0.52
0.36
0.62
0.41
0.10
0.25
0.40
0.90
0.53
0.61
0.42
0.73
0.48
0.10
0.25
0.40
0.90
0.53
0.61
0.42
0.73
0.48
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
An – Dn LUT address to AMUX/CMUX
An – Dn LUT address to BMUX_A
An – Dn inputs to A – D Q outputs
AX inputs to AMUX output
TITO
TAXA
TAXB
TAXC
TAXD
TBXB
AX inputs to BMUX output
AX inputs to CMUX output
AX inputs to DMUX output
BX inputs to BMUX output
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 65: CLB Switching Characteristics (Cont’d)
Symbol Description
BX inputs to DMUX output
Speed Grade
Units
-2I
-1I
-1M
0.59
0.42
0.49
0.49
0.59
0.51
0.43
0.40
0.50
0.37
0.26
0.26
0.11
0.31
0.35
0.36
0.41
TBXD
TCXB
TCXD
TDXD
0.51
0.36
0.42
0.42
0.50
0.44
0.37
0.34
0.42
0.30
0.22
0.22
0.10
0.27
0.30
0.32
0.35
0.59
0.42
0.49
0.49
0.59
0.51
0.43
0.40
0.50
0.37
0.26
0.26
0.11
0.31
0.35
0.36
0.41
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
CX inputs to CMUX output
CX inputs to DMUX output
DX inputs to DMUX output
An input to COUT output
Bn input to COUT output
Cn input to COUT output
Dn input to COUT output
AX input to COUT output
BX input to COUT output
CX input to COUT output
DX input to COUT output
CIN input to COUT output
CIN input to AMUX output
CIN input to BMUX output
CIN input to CMUX output
CIN input to DMUX output
TOPCYA
TOPCYB
TOPCYC
TOPCYD
TAXCY
TBXCY
TCXCY
TDXCY
TBYP
TCINA
TCINB
TCINC
TCIND
Sequential Delays
TCKO
Clock to AQ – DQ outputs
0.40
0.47
0.47
ns, Max
ns, Min
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
TDICK/TCKDI
TRCK
CECK/TCKCE
TSRCK/TCKSR
TCINCK/TCKCIN
AX – DX input to CLK on A – D Flip Flops
0.41
0.21
0.49
0.24
0.49
0.31
DX input to CLK when used as REV
CE input to CLK on A – D Flip Flops
0.42
0.51
0.51
ns, Min
ns, Min
0.20
–0.04
0.23
–0.04
0.23
–0.03
T
0.49
–0.19
0.59
–0.19
0.59
–0.19
ns, Min
ns, Min
SR input to CLK on A – D Flip Flops
CIN input to CLK on A – D Flip Flops
0.16
0.16
0.18
0.19
0.18
0.26
Set/Reset
TSRMIN
TRQ
SR input minimum pulse width
0.90
0.86
0.52
1265
0.90
1.03
0.63
1098
0.90
1.03
0.63
1098
ns, Min
ns, Max
ns, Max
MHz
Delay from SR or REV input to AQ – DQ flip-flops
Delay from CE input to AQ – DQ flip-flops
Toggle frequency (for export control)
TCEO
FTOG
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if a “0”
is listed, there is no positive hold time.
2. These items are of interest for Carry Chain applications.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 66: CLB Distributed RAM Switching Characteristics
Speed Grade
-1I
Symbol
Description
Units
-2I
-1M
Sequential Delays
TSHCKO
Clock to A – B outputs
Clock to AMUX – BMUX outputs
1.26
1.38
1.54
1.68
1.54
1.68
ns, Max
ns, Max
TSHCKO_1
Setup and Hold Times Before/After Clock CLK
0.84
0.22
1.03
0.26
1.03
0.26
ns, Min
ns, Min
ns, Min
ns, Min
TDS/TDH
A – D inputs to CLK
Address An inputs to clock
WE input to clock
0.46
0.22
0.54
0.27
0.54
0.27
TAS/TAH
0.39
–0.04
0.46
–0.02
0.46
–0.02
TWS/TWH
TCECK/TCKCE
0.42
–0.07
0.51
–0.06
0.51
–0.06
CE input to CLK
Clock CLK
TMPW
Minimum pulse width
Minimum clock period
0.82
1.64
1.00
2.00
1.00
2.00
ns, Min
ns, Min
TMCP
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2.
T
also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.
SHCKO
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 67: CLB Shift Register Switching Characteristics
Speed Grade
-1I
Symbol
Description
Units
-2I
-1M
Sequential Delays
TREG
Clock to A – D outputs
1.43
1.55
1.15
1.73
1.87
1.38
1.73
1.87
1.38
ns, Max
ns, Max
ns, Max
TREG_MUX
TREG_M31
Clock to AMUX – DMUX output
Clock to DMUX output via M31 output
Setup and Hold Times Before/After Clock CLK
0.24
–0.04
0.29
–0.02
0.29
–0.02
TWS/TWH
WE input
ns, Min
ns, Min
ns, Min
0.27
–0.07
0.33
–0.06
0.33
–0.06
TCECK/TCKCE
TDS/TDH
CE input to CLK
A – D inputs to CLK
0.66
0.09
0.78
0.11
0.78
0.11
Clock CLK
TMPW
Minimum pulse width
0.70
0.85
0.85
ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Block RAM and FIFO Switching Characteristics
Table 68: Block RAM and FIFO Switching Characteristics
Speed Grade
-1I
Symbol
Description
Units
-2I
-1M
Block RAM and FIFO Clock to Out Delays
(1)
TRCKO_DO and TRCKO_DOR
Clock CLK to DOUT output (without output register)(2)(3)
Clock CLK to DOUT output (with output register)(4)(5)
1.92
0.69
3.03
2.19
0.82
3.61
2.19
0.82
3.61
ns, Max
ns, Max
ns, Max
Clock CLK to DOUT output with ECC (without output
register)(2)(3)
Clock CLK to DOUT output with ECC (with output
register)(4)(5)
0.77
2.44
1.07
0.93
2.94
1.30
0.93
2.94
1.30
ns, Max
ns, Max
ns, Max
Clock CLK to DOUT output with Cascade (without output
register)(2)
Clock CLK to DOUT output with Cascade (with output
register)(4)
TRCKO_FLAGS
TRCKO_POINTERS
TRCKO_ECCR
TRCKO_ECC
Clock CLK to FIFO flags outputs(6)
0.87
1.26
0.77
2.85
1.47
0.89
1.02
1.48
0.93
3.41
1.74
1.05
1.02
1.48
0.93
3.41
1.74
1.05
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
Clock CLK to FIFO pointer outputs(7)
Clock CLK to BITERR (with output register)
Clock CLK to BITERR (without output register)
Clock CLK to ECCPARITY in standard ECC mode
Clock CLK to ECCPARITY in ECC encode only mode
Setup and Hold Times Before/After Clock CLK
0.40
0.32
0.48
0.36
0.48
0.36
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
TRCCK_ADDR/TRCKC_ADDR
TRDCK_DI/TRCKD_DI
ADDR inputs(8)
0.30
0.28
0.35
0.29
0.35
0.29
DIN inputs(9)
0.37
0.33
0.42
0.36
0.42
0.47
DIN inputs with ECC in standard mode(9)
DIN inputs with ECC encode only(9)
Block RAM Enable (EN) input
CE input of output register
Synchronous Set/ Reset (SSR) input
Write Enable (WE) input
T
RDCK_DI_ECC/TRCKD_DI_ECC
0.72
0.33
0.77
0.36
0.77
0.47
0.36
0.15
0.42
0.15
0.42
0.15
TRCCK_EN/TRCKC_EN
0.16
0.24
0.18
0.27
0.18
0.27
TRCCK_REGCE/TRCKC_REGCE
TRCCK_SSR/TRCKC_SSR
TRCCK_WE/TRCKC_WE
0.21
0.25
0.26
0.28
0.26
0.28
0.51
0.17
0.63
0.18
0.63
0.18
0.41
0.34
0.48
0.40
0.48
0.40
TRCCK_WREN/TRCKC_WREN
WREN/RDEN FIFO inputs(10)
Reset Delays
TRCO_FLAGS
Reset RST to FIFO Flags/Pointers(11)
1.26
1.48
1.48
ns, Max
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 68: Block RAM and FIFO Switching Characteristics (Cont’d)
Speed Grade
-1I
Symbol
Description
Units
-2I
-1M
Maximum Frequency
FMAX
Block RAM in all modes
500
450
500
375
450
400
450
325
450
400
450
325
MHz
MHz
MHz
MHz
FMAX_CASCADE
FMAX_FIFO
Block RAM in cascade configuration
FIFO in all modes
FMAX_ECC
Block RAM and FIFO in ECC configuration
Notes:
1. TRACE will report all of these parameters as TRCKO_DO
2. RCKO_DOR includes TRCKO_DOW, TRCKO_DOPR, and TRCKO_DOPW as well as the B port equivalent timing parameters.
3. These parameters also apply to synchronous FIFO with DO_REG = 0.
4. RCKO_DO includes TRCKO_DOP as well as the B port equivalent timing parameters.
5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
.
T
T
6.
7.
T
T
RCKO_FLAGS includes the following parameters: TRCKO_AEMPTY, TRCKO_AFULL, TRCKO_EMPTY, TRCKO_FULL, TRCKO_RDERR, TRCKO_WRERR
RCKO_POINTERS includes both TRCKO_RDCOUNT and TRCKO_WRCOUNT
.
.
8. The ADDR setup and hold must be met when EN is asserted even though WE is deasserted. Otherwise, block RAM data corruption is possible.
9. RCKO_DI includes both A and B inputs as well as the parity inputs of A and B.
10. These parameters also apply to RDEN.
11. RCO_FLAGS includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
T
T
DSP48E Switching Characteristics
Table 69: DSP48E Switching Characteristics
Speed Grade
-1I
Symbol
Description
Units
-2I
-1M
Setup and Hold Times of Data/Control Pins to the Input Register Clock
TDSPDCK_{AA, BB, ACINA, BCINB}/
TDSPCKD_{AA, BB, ACINA, BCINB}
{A, B, ACIN, BCIN} input to {A, B} register CLK
0.21
0.23
0.26
0.30
0.26
0.30
ns
ns
0.16
0.31
0.20
0.37
0.20
0.50
TDSPDCK_CC/TDSPCKD_CC
C input to C register CLK
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_{AM, BM, ACINM, BCINM}/
TDSPCKD_{AM, BM, ACINM, BCINM}
{A, B, ACIN, BCIN} input to M register CLK
1.44
0.19
1.71
0.19
1.71
0.19
ns
Setup and Hold Times of Data/Control Pins to the Output Register Clock
TDSPDCK_{AP, BP, ACINP, BCINP}_M/
TDSPCKD_{AP, BP, ACINP, BCINP}_M
{A, B, ACIN, BCIN} input to P register CLK
using multiplier
2.74
–0.30
3.25
–0.30
3.25
–0.30
ns
ns
ns
ns
TDSPDCK_{AP, BP, ACINP, BCINP}_NM/
TDSPCKD_{AP, BP, ACINP, BCINP}_NM
{A, B, ACIN, BCIN} input to P register CLK not
using multiplier
1.54
–0.10
1.83
–0.10
1.83
–0.10
1.42
–0.13
1.70
–0.13
1.70
–0.13
TDSPDCK_CP/TDSPCKD_CP
C input to P register CLK
TDSPDCK_{PCINP, CRYCINP,
MULTSIGNINP}/
{PCIN, CARRYCASCIN, MULTSIGNIN} input
to P register CLK
1.17
0.11
1.31
0.11
1.31
0.11
TDSPCKD_{PCINP, CRYCINP,
MULTSIGNINP}
Setup and Hold Times of the CE Pins
TDSPCCK_{CEA1A, CEA2A, CEB1B,
CEB2B}/
{CEA1, CEA2A, CEB1B, CEB2B} input to
{A, B} register CLK
0.28
0.25
0.33
0.31
0.33
0.31
ns
TDSPCKC_{CEA1A, CEA2A, CEB1A, CEB2B}
0.21
0.21
0.26
0.28
0.26
0.28
ns
ns
TDSPCCK_CECC/TDSPCKC_CECC
TDSPCCK_CEMM/TDSPCKC_CEMM
CEC input to C register CLK
CEM input to M register CLK
0.29
0.21
0.36
0.26
0.36
0.26
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Speed Grade
Table 69: DSP48E Switching Characteristics (Cont’d)
Symbol
Description
Units
-2I
-1I
-1M
0.63
0.01
0.73
0.01
0.73
0.01
ns
TDSPCCK_CEPP/TDSPCKC_CEPP
CEP input to P register CLK
Setup and Hold Times of the RST Pins
TDSPCCK_{RSTAA, RSTBB}/
TDSPCKC_{RSTAA, RSTBB}
0.28
0.26
0.33
0.31
0.33
0.31
ns
ns
ns
ns
{RSTA, RSTB} input to {A, B} register CLK
RSTC input to C register CLK
0.21
0.21
0.26
0.28
0.26
0.28
TDSPCCK_RSTCC/ TDSPCKC_RSTCC
TDSPCCK_RSTMM/ TDSPCKC_RSTMM
TDSPCCK_RSTPP/TDSPCKC_RSTPP
0.29
0.21
0.36
0.26
0.36
0.26
RSTM input to M register CLK
RSTP input to P register CLK
0.63
0.01
0.73
0.01
0.73
0.01
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_M {A, B} input to {P, CARRYOUT} output using
multiplier
3.22
1.77
1.67
3.84
2.22
2.08
3.84
2.22
2.08
ns
ns
ns
TDSPDO_{AP, ACRYOUT, BP, BCRYOUT}_NM {A, B} input to {P, CARRYOUT} output not
using multiplier
TDSPDO_{CP, CCRYOUT, CRYINP,
CRYINCRYOUT}
{C, CARRYIN} input to
{P, CARRYOUT} output
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{AACOUT, BBCOUT}
{A, B} input to
{ACOUT, BCOUT} output
1.12
3.22
1.31
3.84
1.31
3.84
ns
ns
TDSPDO_{APCOUT, ACRYCOUT,
AMULTSIGNOUT, BPCOUT, BCRYCOUT,
BMULTSIGNOUT}_M
{A, B} input to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output using multiplier
TDSPDO_{APCOUT, ACRYCOUT,
AMULTSIGNOUT, BPCOUT, BCRYCOUT,
BMULTSIGNOUT}_NM
{A, B} input to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output not using multiplier
1.92
1.82
2.42
2.28
2.42
2.28
ns
ns
TDSPDO_{CPCOUT, CCRYCOUT,
CMULTSIGNOUT, CRYINPCOUT,
CRYINCRYCOUT, CRYINMULTSIGNOUT}
{C, CARRYIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT} output
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_{ACINP, ACINCRYOUT, BCINP,
BCINCRYOUT}_M
{ACIN, BCIN} input to {P, CARRYOUT} output
using multiplier
3.22
1.77
1.12
3.22
3.84
2.22
1.31
3.84
3.84
2.22
1.31
3.84
ns
ns
ns
ns
TDSPDO_{ACINP, ACINCRYOUT, BCINP,
BCINCRYOUT}_NM
{ACIN, BCIN} input to {P, CARRYOUT} output
not using multiplier
TDSPDO_{ACINACOUT, BCINBCOUT}
{ACIN, BCIN} input to {ACOUT, BCOUT}
output
TDSPDO_{ACINPCOUT, ACINCRYCOUT,
ACINMULTSIGNOUT, BCINPCOUT,
BCINCRYCOUT, BCINMULTSIGNOUT}_M
{ACIN, BCIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT} output
using multiplier
TDSPDO_{ACINPCOUT, ACINCRYCOUT,
ACINMULTSIGNOUT, BCINPCOUT,
BCINCRYCOUT, BCINMULTSIGNOUT}_NM
{ACIN, BCIN} input to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT} output
not using multiplier
1.92
1.45
2.42
1.82
2.42
1.82
ns
ns
TDSPDO_{PCINP, CRYCINP, MULTSIGNINP, {PCIN, CARRYCASCIN, MULTSIGNIN} input
PCINCRYOUT, CRYCINCRYOUT,
MULTSIGNINCRYOUT}
to {P, CARRYOUT} output
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Speed Grade
Table 69: DSP48E Switching Characteristics (Cont’d)
Symbol
Description
Units
-2I
-1I
-1M
TDSPDO_{PCINPCOUT, CRYCINPCOUT,
MULTSIGNINPCOUT, PCINCRYCOUT,
{PCIN, CARRYCASCIN, MULTSIGNIN} input
to {PCOUT, CARRYCASCOUT,
1.60
2.02
2.02
ns
CRYCINCRYCOUT, MULTSIGNINCRYCOUT, MULTSIGNOUT} output
PCINMULTSIGNOUT,
CRYCINMULTSIGNOUT,
MULTSIGNINMULTSIGNOUT}
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_{PP, CRYOUTP}
CLK (PREG) to {P, CARRYOUT} output
0.48
0.53
0.56
0.62
0.56
0.62
ns
ns
TDSPCKO_{CRYCOUTP, PCOUTP,
MULTSIGNOUTP}
CLK (PREG) to {CARRYCASCOUT, PCOUT,
MULTSIGNOUT} output
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_{PM, CRYOUTM}
CLK (MREG) to {P, CARRYOUT} output
2.10
2.13
2.47
2.66
2.47
2.66
ns
ns
TDSPCKO_{PCOUTM, CRYCOUTM,
MULTSIGNOUTM}
CLK (MREG) to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_{PA, CRYOUTA, PB,
CRYOUTB}_M
CLK (AREG, BREG) to {P, CARRYOUT}
output using multiplier
3.57
2.11
2.11
4.23
2.63
2.62
4.23
2.63
2.62
ns
ns
ns
TDSPCKO_{PA, CRYOUTA, PB,
CRYOUTB}_NM
CLK (AREG, BREG) to {P, CARRYOUT}
output not using multiplier
TDSPCKO_{PC, CRYOUTC}
CLK (CREG) to {P, CARRYOUT} output
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUTA, BCOUTB}
CLK (AREG, BREG) to {ACOUT, BCOUT}
0.68
3.57
0.79
4.23
0.79
4.23
ns
ns
TDSPCKO_{PCOUTA, CRYCOUTA,
MULTSIGNOUTA, PCOUTB, CRYCOUTB,
MULTSIGNOUTB}_M
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT} output
using multiplier
TDSPCKO_{PCOUTA, CRYCOUTA,
MULTSIGNOUTA, PCOUTB, CRYCOUTB,
MULTSIGNOUTB}_NM
CLK (AREG, BREG) to {PCOUT,
CARRYCASCOUT, MULTSIGNOUT} output
not using multiplier
2.27
2.26
2.82
2.82
2.82
2.82
ns
ns
TDSPCKO_{PCOUTC, CRYCOUTC,
MULTSIGNOUTC}
CLK (CREG) to {PCOUT, CARRYCASCOUT,
MULTSIGNOUT} output
Maximum Frequency
FMAX
With all registers used
500
465
324
300
450
410
275
254
450
410
275
254
MHz
MHz
MHz
MHz
FMAX_PATDET
With pattern detector
FMAX_MULT_NOMREG
FMAX_MULT_NOMREG_PATDET
Two register multiply without MREG
Two register multiply without MREG with
pattern detect
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Configuration Switching Characteristics
Table 70: Configuration Switching Characteristics
Speed Grade
Symbol
Description
Units
-2I
-1I
-1M
Power-up Timing Characteristics
TPL
Program Latency
Power-on-Reset
3
3
3
ms, Max
10
50
10
50
10
50
ms, Min/Max
TPOR
TICCK
CCLK (output) delay
Program Pulse Width
400
250
400
250
400
250
ns, Min
ns, Min
TPROGRAM
Master/Slave Serial Mode Programming Switching(1)
4.0
0.0
4.0
0.0
5.0
0.0
ns, Min
ns, Min
TDCCK/TCCKD
DIN Setup/Hold, slave mode
DIN Setup/Hold, master mode
4.0
0.0
4.0
0.0
5.0
0.0
TDSCCK/TSCCKD
TCCO
DOUT
7.5
7.5
7.5
ns, Max
Maximum Frequency, master mode with respect to
nominal CCLK.
100
100
100
MHz, Max
FMCCK
Frequency Tolerance, master mode with respect to
nominal CCLK.
50
50
50
%
FMCCKTOL
FMSCCK
Slave mode external CCLK
100
100
100
MHz
SelectMAP Mode Programming Switching(1)
3.0
0.5
3.0
0.5
3.0
0.5
ns, Min
ns, Min
ns, Min
ns, Min
TSMDCCK/TSMCCKD
TSMCSCCK/TSMCCKCS
TSMCCKW/TSMWCCK
TSMCKCSO
SelectMAP Data Setup/Hold
3.0
0.5
3.0
0.5
3.0
0.5
CS_B Setup/Hold
8.0
0.5
8.0
0.5
8.0
0.5
RDWR_B Setup/Hold
CSO_B clock to out
(330 pull-up resistor required)
10
10
10
TSMCO
CCLK to DATA out in readback
9.0
7.5
100
60
9.0
7.5
100
60
9.0
7.5
100
60
ns, Max
ns, Max
TSMCKBY
FSMCCK
CCLK to BUSY out in readback
Maximum Frequency with respect to nominal CCLK
MHz, Max
MHz, Max
Maximum Readback Frequency with respect to
nominal CCLK
FRBCCK
FMCCKTOL
Frequency Tolerance with respect to nominal CCLK
50
50
50
%
Boundary-Scan Port Timing Specifications
TTAPTCK
TTCKTAP
TTCKTDO
FTCK
TMS and TDI Setup time before TCK
1.0
2.0
6
1.0
2.0
6
1.0
2.0
6
ns, Min
ns, Min
TMS and TDI Hold time after TCK
TCK falling edge to TDO output valid
ns, Max
Maximum configuration TCK clock frequency
Maximum boundary-scan TCK clock frequency
66
66
66
66
66
66
MHz, Max
MHz, Max
FTCKB
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 70: Configuration Switching Characteristics (Cont’d)
Speed Grade
Symbol
Description
Units
-2I
-1I
-1M
BPI Master Flash Mode Programming Switching
ADDR[25:0], RS[1:0], FCS_B, FOE_B, FWE_B outputs
valid after CCLK rising edge
10
10
10
ns
ns
(4)
TBPICCO
TBPIDCC/TBPICCD
TINITADDR
3.0
0.5
3.0
0.5
3.0
0.5
Setup/Hold on D[15:0] data input pins
Minimum period of initial ADDR[25:0] address cycles
3.0
3.0
3.0
CCLK cycles
SPI Master Flash Mode Programming Switching
4.0
0.0
4.0
0.0
5.0
0.0
ns
TSPIDCC/TSPIDCCD
DIN Setup/Hold before/after the rising CCLK edge
TSPICCM
MOSI clock to out
10
10
2
10
10
2
10
10
2
ns
ns
µs
TSPICCFC
FCS_B clock to out
TFSINIT/TFSINITH
CCLK Output (Master Modes)
TMCCKL
FS[2:0] to INIT_B rising edge Setup and Hold
Master CCLK clock minimum Low time
Master CCLK clock minimum High time
3.0
3.0
3.0
3.0
3.0
3.0
ns, Min
ns, Min
TMCCKH
CCLK Input (Slave Modes)
TSCCKL
Slave CCLK clock minimum Low time
Slave CCLK clock minimum High time
2.0
2.0
2.0
2.0
2.0
2.0
ns, Min
ns, Min
TSCCKH
Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK
FDCK
Maximum frequency for DCLK
450
400
400
MHz
ns
1.35
0.0
1.56
0.0
1.56
0.0
T
DMCCK_DADDR/TDMCKC_DADDR
DADDR Setup/Hold
1.35
0.0
1.56
0.0
1.56
0.0
ns
ns
ns
TDMCCK_DI/TDMCKC_DI
TDMCCK_DEN/TDMCKC_DEN
TDMCCK_DWE/TDMCKC_DWE
DI Setup/Hold
1.35
0.0
1.56
0.0
1.56
0.0
DEN Setup/Hold time
DWE Setup/Hold time
1.35
0.0
1.56
0.0
1.56
0.0
TDMCKO_DO
CLK to out of DO(3)
CLK to out of DRDY
1.12
1.12
1.30
1.30
1.30
1.30
ns
ns
TDMCKO_DRDY
Notes:
1. Maximum frequency and setup/hold timing parameters are for 3.3V and 2.5V configuration voltages.
2. To support longer delays in configuration, use the design solutions described in the Virtex-5 FPGA User Guide.
3. DO will hold until next DRP operation.
4. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Clock Buffers and Networks
Table 71: Global Clock Switching Characteristics (Including BUFGCTRL)
Speed Grade
-1I
Symbol
Description
Devices
Units
-2I
-1M
0.27
0.00
0.31
0.00
0.31
0.00
ns
(1)
TBCCCK_CE/TBCCKC_CE
CE pins Setup/Hold
S pins Setup/Hold
All
All
0.27
0.00
0.31
0.00
0.31
0.00
ns
ns
(1)
TBCCCK_S/TBCCKC_S
LX30T, LX85, LX110, LX110T,
SX50T, FX70T, FX100T, and
FX130T
0.22
0.25
0.25
BUFGCTRL delay from
I0/I1 to O
(2)
TBCCKO_O
LX155T
0.14
0.22
0.30
0.25
N/A
N/A
ns
ns
LX220T, LX330T, SX95T,
SX240T, and FX200T
Maximum Frequency
LX30T, LX85, LX110, LX110T,
SX50T, and FX70T(I)
667
600
600
550
N/A
550
MHz
MHz
LX155T, FX70T(M), and
FX100T
FMAX
Global clock tree (BUFG)
FX130T
500
500
450
450
N/A
N/A
MHz
MHz
LX220T, LX330T, SX95T,
SX240T, and FX200T
Notes:
1.
T
and T
must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
BCCCK_CE
BCCKC_CE
parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold
times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching
between clocks.
2.
T
(BUFG delay from I0 to O) values are the same as T
values.
BCCKO_O
BGCKO_O
Table 72: Input/Output Clock Switching Characteristics (BUFIO)
Symbol Description
TBUFIOCKO_O Clock to out delay from I to O
Speed Grade
Units
-2I
-1I
-1M
1.16
1.29
1.29
ns
Maximum Frequency
FMAX
I/O clock tree (BUFIO)
710
644
644
MHz
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 73: Regional Clock Switching Characteristics (BUFR)
Speed Grade
Symbol
Description
Devices
Units
-2I
-1I
-1M
LX30T, LX85, LX110, LX110T, SX50T,
FX100T, and FX130T
0.59
0.67
0.67
ns
FX70T
0.74
0.80
0.59
0.83
0.90
0.67
0.83
N/A
N/A
ns
ns
ns
TBRCKO_O
Clock to out delay from I to O
LX155T
LX220T, LX330T, SX95T, SX240T, and
FX200T
LX30T, LX85, LX110, LX110T, SX50T,
FX70T, FX100T, and FX130T
0.24
0.26
0.26
ns
Clock to out delay from I to O with
Divide Bypass attribute set
TBRCKO_O_BYP
LX155T
0.26
0.24
0.30
0.26
N/A
N/A
ns
ns
LX220T, LX330T, SX95T, SX240T, and
FX200T
TBRDO_CLRO
Propagation delay from CLR to O All
0.70
250
0.82
250
0.82
250
ns
Maximum Frequency
FMAX
Regional clock tree (BUFR)
All
MHz
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
PLL Switching Characteristics
Table 74: PLL Specification
Speed Grade
Symbol
Description
Units
-2I
710
19
-1I
645
19
-1M
645
19
FINMAX
FINMIN
FINJITTER
FINDUTY
Maximum Input Clock Frequency
MHz
MHz
Minimum Input Clock Frequency
Maximum Input Clock Period Jitter
Allowable Input Duty Cycle: 19—49 MHz
Allowable Input Duty Cycle: 50—199 MHz
Allowable Input Duty Cycle: 200—399 MHz
Allowable Input Duty Cycle: 400—499 MHz
Allowable Input Duty Cycle: >500 MHz
Minimum PLL VCO Frequency
<20% of clock input period or 1 ns Max
25/75
30/70
35/65
40/60
45/55
400
%
%
%
%
%
FVCOMIN
FVCOMAX
400
1200
1
400
1000
1
MHz
MHz
MHz
MHz
ps
Maximum PLL VCO Frequency
1000
1
Low PLL Bandwidth at Typical(1)
High PLL Bandwidth at Typical(1)
Static Phase Offset of the PLL Outputs
PLL Output Jitter(2)
FBANDWIDTH
4
4
4
TSTAPHAOFFSET
TOUTJITTER
TOUTDUTY
120
120
120
Note 1
PLL Output Clock Duty Cycle Precision(3)
PLL Maximum Lock Time(4)
200
100
667
200
100
600
200
100
N/A
ps
µs
TLOCKMAX
FOUTMAX
PLL Maximum Output Frequency for LX30T, LX85, LX110,
LX110T, SX50T, and FX70T(I) devices
MHz
PLL Maximum Output Frequency for LX155T, FX70T(M), and
FX100T devices
600
550
550
MHz
PLL Maximum Output Frequency for FX130T devices
500
500
450
450
N/A
N/A
MHz
MHz
PLL Maximum Output Frequency for LX220T, LX330T, SX95T,
SX240T, and FX200T devices
FOUTMIN
PLL Minimum Output Frequency(5)
3.125
3.125
3.125
MHz
TEXTFDVAR
RSTMINPULSE
FPFDMAX
External Clock Feedback Variation
< 20% of clock input period or 1 ns Max
Minimum Reset Pulse Width
5
5
5
ns
Maximum Frequency at the Phase Frequency Detector
Minimum Frequency at the Phase Frequency Detector
Maximum Delay in the Feedback Path
500
19
450
19
450
19
MHz
MHz
FPFDMIN
TFBDELAY
3 ns Max or one CLKIN cycle
Notes:
1. The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. Values for this parameter are available in the Architecture Wizard.
3. Includes global clock buffer.
4. The LOCK signal must be sampled after T
expired.
. The LOCK signal is invalid after configuration or reset until the T
time has
LOCKMAX
LOCKMAX
5. Calculated as F
/128 assuming output duty cycle is 50%.
VCO
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 75: PLL in PMCD Mode Switching Characteristics
Speed Grade
-1I
Symbol
Description
Units
-2I
-1M
0.00
0.60
0.00
0.60
0.00
0.60
ns
TPLLCCK_REL/TPLLCKC_REL
REL Setup and Hold for all Outputs
TPLLCCKO
Maximum Clock Propagation Delay
Maximum Input Frequency
4.6
710
1
5.2
645
5.2
645
1
ns
MHz
MHz
%
CLKIN_FREQ_MAX
CLKIN_FREQ_MIN
CLKIN_DUTY_CYCLE
Minimum Input Frequency
1
Allowable Input Duty Cycle: 1—49 MHz
Allowable Input Duty Cycle: 50—199 MHz
Allowable Input Duty Cycle: 200—399 MHz
Allowable Input Duty Cycle: 400—499 MHz
Allowable Input Duty Cycle: >500 MHz
Minimum Pulse Width for RST and REL
25/75
30/70
35/65
40/60
45/55
5
%
%
%
%
RES_REL_PULSE_MIN
5
5
ns
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
DCM Switching Characteristics
Table 76: Operating Frequency Ranges for DCM in Maximum Speed (MS) Mode
Speed Grade
-1I
Symbol
Description
Units
-2I
-1M
Outputs Clocks (Low Frequency Mode)
F1XLFMSMIN
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV(5)
32.00
135.00
64.00
270.00
2.0
32.00
120.00
64.00
240.00
2.0
32.00
120.00
64.00
240.00
2.0
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
F1XLFMSMAX
F2XLFMSMIN
F2XLFMSMAX
FDVLFMSMIN
FDVLFMSMAX
90.00
32.00
160.00
80.00
32.00
140.00
80.00
32.00
140.00
FFXLFMSMIN
CLKFX, CLKFX180
FFXLFMSMAX
Input Clocks (Low Frequency Mode)
FDLLLFMSMIN
CLKIN (using DLL outputs)(1)(3)(4)
CLKIN (using DFS outputs only)(2)(3)(4)
PSCLK
32.00
135.00
1.00
32.00
120.00
1.00
32.00
120.00
1.00
MHz
MHz
MHz
MHz
KHz
MHz
FDLLLFMSMAX
FCLKINLFFXMSMIN
FCLKINLFFXMSMAX
FPSCLKLFMSMIN
160.00
1.00
140.00
1.00
140.00
1.00
FPSCLKLFMSMAX
Outputs Clocks (High Frequency Mode)
F1XHFMSMIN
500.00
450.00
450.00
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV(5)
120.00
500.00
240.00
500.00
7.5
120.00
450.00
240.00
450.00
7.5
120.00
450.00
240.00
450.00
7.5
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
F1XHFMSMAX
F2XHFMSMIN
F2XHFMSMAX
FDVHFMSMIN
FDVHFMSMAX
333.34
140.00
375.00
300.00
140.00
350.00
300.00
140.00
350.00
FFXHFMSMIN
CLKFX, CLKFX180(5)
FFXHFMSMAX
Input Clocks (High Frequency Mode)
FDLLHFMSMIN
CLKIN (using DLL outputs)(1)(3)(4)
CLKIN (using DFS outputs only)(2)(3)(4)(5)
PSCLK
120.00
500.00
25.00
120.00
450.00
25.00
120.00
450.00
25.00
MHz
MHz
MHz
MHz
KHz
MHz
FDLLHFMSMAX
FCLKINHFFXMSMIN
FCLKINHFFXMSMAX
FPSCLKHFMSMIN
FPSCLKHFMSMAX
375.00
1.00
350.00
1.00
350.00
1.00
500.00
450.00
450.00
Notes:
1. DLL outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input
frequency.
4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within 5% (45/55
to 55/45).
5. Only available for I-temperature conditions.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
(5)
Table 77: Operating Frequency Ranges for DCM in Maximum Range (MR) Mode
Speed Grade
-1I
Symbol
Description
Units
-2I
-1M
Outputs Clocks (Low Frequency Mode)
F1XMRMIN
19.00
32.00
38.00
64.00
1.19
19.00
32.00
38.00
64.00
1.19
19.00
32.00
38.00
64.00
1.19
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180
CLKDV
F1XMRMAX
F2XMRMIN
F2XMRMAX
FDLLMRMIN
FDLLMRMAX
21.34
19.00
40.00
21.34
19.00
40.00
21.34
19.00
40.00
FFXMRMIN
CLKFX, CLKFX180
FFXMRMAX
Input Clocks (Low Frequency Mode)
FCLKINDLLMRMIN
FCLKINDLLMRMAX
FCLKINFXMRMIN
FCLKINFXMRMAX
FPSCLKMRMIN
19.00
32.00
1.00
19.00
32.00
1.00
19.00
32.00
1.00
MHz
MHz
MHz
MHz
KHz
MHz
CLKIN (using DLL outputs)(1)(3)(4)
CLKIN (using DFS outputs only)(2)(3)(4)
PSCLK
40.00
1.00
40.00
1.00
40.00
1.00
FPSCLKMRMAX
270.00
240.00
240.00
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. When using the DCMs CLKIN_DIVIDE_BY_2 attribute these values should be doubled. Other resources can limit the maximum input
frequency.
4. When using a CLKIN frequency > 400 MHz and the DCMs CLKIN_DIVIDE_BY_2 attribute, the CLKIN duty cycle must be within 5% (45/55
to 55/45).
5. Maximum range is not available outside of I-temperature conditions.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 78: Input Clock Tolerances
Symbol
Description
Frequency Range
Value
Units
Duty Cycle Input Tolerance (in %)
TDUTYCYCRANGE_1
PSCLK only
< 1 MHz
1 - 50 MHz
25 - 75
25 - 75
30 - 70
40 - 60
45 - 55
45 - 55
%
%
%
%
%
%
TDUTYCYCRANGE_1_50
TDUTYCYCRANGE_50_100
TDUTYCYCRANGE_100_200
TDUTYCYCRANGE_200_400
TDUTYCYCRANGE_400
50 - 100 MHz
100 - 200 MHz
200 - 400 MHz(4)
> 400 MHz
PSCLK and CLKIN
Speed Grade
-1I
Input Clock Cycle-Cycle Jitter (Low Frequency Mode)
Units
-2I
-1M
TCYCLFDLL
TCYCLFFX
Input Clock Cycle-Cycle Jitter (High Frequency Mode)
CLKIN (using DLL outputs)(1)
CLKIN (using DFS outputs)(2)
300.00
300.00
345.00
345.00
345.00
345.00
ps
ps
TCYCHFDLL
CLKIN (using DLL outputs)(1)
150.00
150.00
173.00
173.00
173.00
173.00
ps
ps
TCYCHFFX
CLKIN (using DFS outputs)(2)
Input Clock Period Jitter (Low Frequency Mode)
TPERLFDLL
TPERLFFX
Input Clock Period Jitter (High Frequency Mode)
CLKIN (using DLL outputs)(1)
CLKIN (using DFS outputs)(2)
1.00
1.00
1.15
1.15
1.15
1.15
ns
ns
TPERHFDLL
CLKIN (using DLL outputs)(1)
1.00
1.00
1.15
1.15
1.15
1.15
ns
ns
TPERHFFX
CLKIN (using DFS outputs)(2)
Feedback Clock Path Delay Variation
TCLKFB_DELAY_VAR
CLKFB off-chip feedback
1.00
1.15
1.15
ns
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. If both DLL and DFS outputs are used, follow the more restrictive specifications.
4. This duty cycle specification does not apply to the GTP_DUAL to DCM or GTX_DUAL to DCM connection. The GTP transceivers drive the
DCMs at the following frequencies: 320 MHz for -1I speed grade devices, or 375 MHz for -2I speed grade devices. The GTX transceivers
drive the DCMs at the following frequencies: 450 MHz for -1I speed grade devices or 500 MHz for
-2I speed grade devices.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Output Clock Jitter
Table 79: Output Clock Jitter
Speed Grade
Symbol
Description
Units
-2I
-1I
-1M
Clock Synthesis Period Jitter
TPERJITT_0
CLK0
120
120
120
120
120
120
ps
ps
ps
ps
ps
ps
ps
ps
TPERJITT_90
CLK90
TPERJITT_180
CLK180
120
120
120
TPERJITT_270
CLK270
120
120
120
TPERJITT_2X
CLK2X, CLK2X180
CLKDV (integer division)
CLKDV (non-integer division)
CLKFX, CLKFX180
200
230
230
TPERJITT_DV1
150
180
180
TPERJITT_DV2
300
345
345
TPERJITT_FX
Note 1
Note 1
Note 1
Notes:
1. Values for this parameter are available in the Architecture Wizard.
Output Clock Phase Alignment
Table 80: Output Clock Phase Alignment
Speed Grade
-1I
Symbol
Description
Units
-2I
-1M
Phase Offset Between CLKIN and CLKFB
TIN_FB_OFFSET
CLKIN/CLKFB
50
60
60
ps
Phase Offset Between Any DCM Outputs(1)
TOUT_OFFSET_1X
TOUT_OFFSET_2X
TOUT_OFFSET_FX
Duty Cycle Precision(2)
TDUTY_CYC_DLL
CLK0, CLK90, CLK180, CLK270
CLK2X, CLK2X180, CLKDV
CLKFX, CLKFX180
140
150
160
160
200
220
160
200
220
ps
ps
ps
DLL outputs(3)
DFS outputs(4)
150
150
180
180
180
180
ps
ps
TDUTY_CYC_FX
Notes:
1. All phase offsets are with respect to group CLK1X.
2. CLKOUT_DUTY_CYCLE_DLL applies to the 1X clock outputs (CLK0, CLK90, CLK180, and CLK270) only if
DUTY_CYCLE_CORRECTION = TRUE. The duty cycle distortion includes the global clock tree (BUFG).
3. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
4. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Speed Grade
Table 81: Miscellaneous Timing Parameters
Symbol
Description
Units
-2I
-1I
-1M
Time Required to Achieve LOCK
TDLL_240
DLL output – Frequency range > 240 MHz(1)
DLL output – Frequency range 120 - 240 MHz(1)
DLL output – Frequency range 60 - 120 MHz(1)
DLL output – Frequency range 50 - 60 MHz(1)
DLL output – Frequency range 40 - 50 MHz(1)
DLL output – Frequency range 30 - 40 MHz(1)
DLL output – Frequency range 24 - 30 MHz(1)
DLL output – Frequency range < 30 MHz(1)
80.00
250.00
900.00
80.00
250.00
900.00
80.00
250.00
900.00
µs
µs
µs
µs
µs
µs
µs
µs
ms
ms
TDLL_120_240
TDLL_60_120
TDLL_50_60
TDLL_40_50
TDLL_30_40
TDLL_24_30
TDLL_30
1300.00 1300.00 1300.00
2000.00 2000.00 2000.00
3600.00 3600.00 3600.00
5000.00 5000.00 5000.00
5000.00 5000.00 5000.00
TFX_MIN
10.00
10.00
2.00
10.00
10.00
2.00
10.00
10.00
2.00
DFS outputs(2)
TFX_MAX
TDLL_FINE_SHIFT
Fine Phase Shifting
TRANGE_MS
Multiplication factor for DLL lock time with Fine Shift
Absolute shifting range in maximum speed mode
Absolute shifting range in maximum range mode
7.00
7.00
7.00
ns
ns
(3)
TRANGE_MR
10.00
10.00
10.00
Delay Lines
TTAP_MS_MIN
TTAP_MS_MAX
Tap delay resolution (Min) in maximum speed mode
Tap delay resolution (Max) in maximum speed mode
Tap delay resolution (Min) in maximum range mode
Tap delay resolution (Max) in maximum range mode
7.00
30.00
10.00
40.00
7.00
30.00
10.00
40.00
7.00
30.00
10.00
40.00
ps
ps
ps
ps
(3)
TTAP_MR_MIN
(3)
TTAP_MR_MAX
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
3. Maximum range is not available outside of I-temperature conditions.
Table 82: Frequency Synthesis
Attribute
Min
2
Max
33
CLKFX_MULTIPLY
CLKFX_DIVIDE
1
32
Table 83: DCM Switching Characteristics
Speed Grade
Symbol
Description
Units
-2I
-1I
-1M
1.35
0.00
1.56
0.00
1.56
0.00
ns
TDMCCK_PSEN/ TDMCKC_PSEN
PSEN Setup/Hold
1.35
0.00
1.56
0.00
1.56
0.00
ns
ns
TDMCCK_PSINCDEC/ TDMCKC_PSINCDEC
TDMCKO_PSDONE
PSINCDEC Setup/Hold
Clock to out of PSDONE
1.12
1.30
1.30
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Virtex-5Q Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 84. Values are expressed in nanoseconds unless otherwise noted.
Table 84: Global Clock Input to Output Delay Without DCM or PLL
Speed Grade
Symbol
Description
Device
Units
-2I
-1I
-1M
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without DCM or PLL
TICKOF
Global Clock and OUTFF without DCM or PLL
XQ5VLX30T
XQ5VLX85
6.04
6.28
6.35
6.35
6.68
6.99
N/A
6.73
6.99
7.06
7.06
7.52
7.71
7.91
6.97
7.30
7.98
7.04
7.44
7.52
7.91
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
7.04
7.44
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
6.27
6.59
N/A
6.33
6.73
6.80
N/A
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 85: Global Clock Input to Output Delay With DCM in System-Synchronous Mode
Speed Grade
-1I
Symbol
Description
Device
Units
-2I
-1M
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM
in System-Synchronous Mode
TICKOFDCM
Global Clock and OUTFF with DCM
XQ5VLX30T
XQ5VLX85
2.56
2.63
2.69
2.69
2.74
2.83
N/A
2.93
3.00
3.06
3.06
3.10
3.18
3.37
3.05
3.00
3.36
3.12
3.00
3.07
3.27
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.12
3.00
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
2.69
2.64
N/A
2.74
2.59
2.67
N/A
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM output jitter is already included in the timing calculation.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 86: Global Clock Input to Output Delay With DCM in Source-Synchronous Mode
Speed Grade
-1I
Symbol
Description
Device
Units
-2I
-1M
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM
in Source-Synchronous Mode
TICKOFDCM_0
Global Clock and OUTFF with DCM
XQ5VLX30T
XQ5VLX85
3.71
3.86
3.92
3.92
4.18
4.41
N/A
4.15
4.29
4.36
4.36
4.62
4.85
5.04
4.35
4.59
5.11
4.41
4.53
4.74
5.03
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
4.41
4.53
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
3.91
4.16
N/A
3.96
4.10
4.29
N/A
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM output jitter is already included in the timing calculation.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 87: Global Clock Input to Output Delay With PLL in System-Synchronous Mode
Speed Grade
-1I
Symbol
Description
Device
Units
-2I
-1M
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL
in System-Synchronous Mode
TICKOFPLL
Global Clock and OUTFF with PLL
XQ5VLX30T
XQ5VLX85
2.30
2.49
2.53
2.53
2.60
2.74
N/A
2.70
2.88
2.92
2.92
3.01
3.12
3.27
2.76
2.69
3.34
3.10
3.10
3.17
3.35
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.10
3.10
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
2.36
2.29
N/A
2.71
2.70
2.75
N/A
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is included in the timing calculation.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 88: Global Clock Input to Output Delay With PLL in Source-Synchronous Mode
Symbol Description Device
Speed Grade
-1I
Units
-2I
-1M
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL
in Source-Synchronous Mode
TICKOFPLL_0
Global Clock and OUTFF with PLL
XQ5VLX30T
XQ5VLX85
4.32
4.40
4.44
4.44
4.66
4.85
N/A
4.82
4.88
4.92
4.92
5.16
5.29
5.44
5.02
5.14
5.51
5.02
5.19
5.40
5.55
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
5.02
5.19
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
4.54
4.68
N/A
4.54
4.70
4.86
N/A
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is included in the timing calculation.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 89: Global Clock Input to Output Delay With DCM and PLL in System-Synchronous Mode
Speed Grade
-1I
Symbol
Description
Device
Units
-2I
-1M
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM and PLL
in System-Synchronous Mode
TICKOFDCM_PLL
Global Clock and OUTFF with DCM and PLL
XQ5VLX30T
XQ5VLX85
2.48
2.55
2.61
2.61
2.66
2.75
N/A
2.84
2.91
2.97
2.97
3.01
3.09
3.28
2.96
2.91
3.27
3.03
2.91
2.98
3.18
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
3.03
2.91
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
2.61
2.56
N/A
2.66
2.51
2.59
N/A
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM and PLL output jitter are already included in the timing calculation.
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 90: Global Clock Input to Output Delay With DCM and PLL in Source-Synchronous Mode
Speed Grade
-1I
Symbol
Description
Device
Units
-2I
-1M
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM and PLL
in Source-Synchronous Mode
TICKOFDCM0_PLL
Global Clock and OUTFF with DCM and PLL
XQ5VLX30T
XQ5VLX85
3.63
3.78
3.84
3.84
4.10
4.33
N/A
4.06
4.20
4.27
4.27
4.53
4.76
4.95
4.26
4.50
5.02
4.32
4.44
4.65
4.94
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
4.32
4.44
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
3.83
4.08
N/A
3.88
4.02
4.21
N/A
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM and PLL output jitter are already included in the timing calculation.
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Product Specification
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Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Virtex-5Q Device Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 91. Values are expressed in nanoseconds unless otherwise noted.
Table 91: Global Clock Setup and Hold without DCM or PLL
Speed Grade
Symbol
Description
Device
Units
-2I
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1)
-1I
-1M
TPSFD/ TPHFD
Full Delay (Legacy Delay or Default Delay)
Global Clock and IFF(2) without DCM or PLL
1.60
–0.35
1.76
–0.35
XQ5VLX30T
XQ5VLX85
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.89
–0.49
2.09
–0.49
1.88
–0.43
2.09
–0.43
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
1.88
–0.43
2.09
–0.43
2.36
–0.50
2.78
–0.49
2.57
–0.74
2.86
–0.74
2.86
–0.56
N/A
1.74
–0.31
1.93
–0.31
2.10
–0.44
2.32
–0.44
2.28
0.18
N/A
2.06
–0.30
2.35
–0.30
2.35
–0.30
2.38
–0.42
2.66
–0.42
2.66
–0.42
2.59
–0.54
2.95
–0.54
N/A
N/A
2.81
–0.43
N/A
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0"
is listed, there is no positive hold time.
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Product Specification
65
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 92: Global Clock Setup and Hold with DCM in System-Synchronous Mode
Speed Grade
-1I
Symbol
Description
Device
Units
-2I
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1)
-1M
TPSDCM/ TPHDCM
No Delay Global Clock and IFF(2) with DCM in
System-Synchronous Mode
1.70
–0.50
1.88
–0.50
XQ5VLX30T
XQ5VLX85
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.76
–0.43
1.95
–0.43
1.76
–0.37
1.95
–0.37
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
1.76
–0.37
1.95
–0.37
2.16
–0.32
2.38
–0.32
2.17
–0.27
2.44
–0.27
2.44
–0.10
N/A
1.76
–0.37
1.95
–0.37
2.34
–0.41
2.35
–0.41
2.54
–0.10
N/A
1.86
–0.36
1.98
–0.36
1.98
–0.36
2.35
–0.51
2.49
–0.49
2.49
–0.49
2.48
–0.43
2.72
–0.42
N/A
N/A
2.43
–0.21
N/A
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
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Product Specification
66
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 93: Global Clock Setup and Hold with DCM in Source-Synchronous Mode
Speed Grade
-1I
Symbol
Description
Device
Units
-2I
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1)
-1M
TPSDCM0/ TPHDCM0 No Delay Global Clock and IFF(2) with DCM in
Source-Synchronous Mode
0.27
0.62
0.27
0.66
XQ5VLX30T
XQ5VLX85
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
0.24
0.76
0.24
0.80
0.24
0.82
0.24
0.87
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
0.24
0.82
0.24
0.87
0.14
1.08
0.16
1.13
0.21
1.31
0.22
1.36
0.22
1.55
N/A
0.25
0.82
0.25
0.86
0.24
1.06
0.24
1.11
0.21
1.62
N/A
0.14
0.86
0.14
0.92
0.14
0.92
0.21
1.00
0.21
1.05
0.21
1.05
0.21
1.19
0.24
1.25
N/A
N/A
0.16
1.55
N/A
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
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67
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 94: Global Clock Setup and Hold with PLL in System-Synchronous Mode
Speed Grade
-1I
Symbol
Description
Device
Units
-2I
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1)
-1M
TPSPLL/ TPHPLL
No Delay Global Clock and IFF(2) with PLL in
System-Synchronous Mode
1.68
–0.80
1.90
–0.79
XQ5VLX30T
XQ5VLX85
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.95
–0.62
2.09
–0.61
1.96
–0.57
2.10
–0.57
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
1.96
–0.57
2.10
–0.57
2.09
–0.49
2.37
–0.47
1.93
–0.36
2.09
–0.36
2.34
–0.21
N/A
2.07
–0.72
2.20
–0.72
2.17
–0.80
2.35
–0.79
2.33
–0.14
N/A
1.90
–0.30
2.07
–0.30
2.07
–0.30
1.91
–0.40
2.09
–0.38
2.09
–0.38
1.95
–0.28
2.14
–0.24
N/A
N/A
2.29
–0.14
N/A
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
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68
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 95: Global Clock Setup and Hold with PLL in Source-Synchronous Mode
Speed Grade
-1I
Symbol
Description
Device
Units
-2I
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1)
-1M
TPSPLL0/ TPHPLL0
No Delay Global Clock and IFF(2) with PLL in
Source-Synchronous Mode
–0.33
1.22
–0.33
1.34
XQ5VLX30T
XQ5VLX85
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–0.23
1.30
–0.22
1.39
–0.24
1.34
–0.23
1.43
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
–0.25
1.34
–0.23
1.43
–0.12
1.56
–0.10
1.67
–0.34
1.75
–0.30
1.80
–0.30
1.95
N/A
–0.26
1.44
–0.25
1.53
–0.26
1.58
–0.24
1.65
–0.31
2.02
N/A
–0.10
1.44
–0.09
1.53
–0.09
1.53
–0.18
1.60
–0.18
1.71
–0.18
1.71
–0.11
1.76
–0.09
1.92
N/A
N/A
–0.10
2.06
N/A
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS714 (v2.2) January 17, 2011
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69
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 96: Global Clock Setup and Hold with DCM and PLL in System-Synchronous Mode
Speed Grade
-1I
Symbol
Description
Device
Units
-2I
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard(1)
-1M
TPSDCMPLL
/
No Delay Global Clock and IFF(2) with
DCM and PLL in System-Synchronous Mode
1.89
–0.58
2.06
–0.58
XQ5VLX30T
XQ5VLX85
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TPHDCMPLL
1.93
–0.51
2.13
–0.51
1.93
–0.45
2.13
–0.45
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
1.93
–0.45
2.13
–0.45
2.31
–0.40
2.55
–0.40
2.32
–0.35
2.61
–0.35
2.61
–0.18
N/A
1.94
–0.45
2.14
–0.45
2.51
–0.49
2.53
–0.49
2.70
–0.18
N/A
2.03
–0.44
2.16
–0.44
2.16
–0.44
2.51
–0.59
2.66
–0.58
2.66
–0.58
2.64
–0.51
2.89
–0.51
N/A
N/A
2.59
–0.30
N/A
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include CMT jitter; DCM CLK0
driving PLL, PLL CLKOUT0 driving BUFG.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
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Product Specification
70
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 97: Global Clock Setup and Hold with DCM and PLL in Source-Synchronous Mode
Speed Grade
-1I
Symbol
Description
Device
Units
-2I
-1M
(1)
Example Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin, using DCM, PLL, and Global Clock Buffer. For
situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values
shown in IOB Switching Characteristics.
TPSDCMPLL_0
/
No Delay Global Clock and IFF(2) with DCM and
PLL in Source-Synchronous Mode
0.46
0.54
0.46
0.57
XQ5VLX30T
XQ5VLX85
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TPHDCMPLL_0
0.42
0.68
0.42
0.71
0.41
0.74
0.41
0.78
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
0.41
0.74
0.41
0.78
0.29
1.00
0.33
1.04
0.36
1.23
0.38
1.27
0.38
1.46
N/A
0.43
0.74
0.43
0.77
0.41
0.98
0.41
1.02
0.38
1.53
N/A
0.32
0.78
0.32
0.83
0.32
0.83
0.35
0.92
0.35
0.96
0.35
0.96
0.37
1.11
0.41
1.16
N/A
N/A
0.33
1.46
N/A
Notes:
1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. The timing values were measured using the fine-phase
adjustment feature of the DCM. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. Package
skew is not included in these measurements.
2. IFF = Input Flip-Flop
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71
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-5Q FPGA source-
synchronous transmitter and receiver data-valid windows.
Table 98: Duty Cycle Distortion and Clock-Tree Skew
Speed Grade
Symbol
Description
Device
Units
-2I
-1I
-1M
0.12
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.43
0.86
N/A
N/A
0.10
0.08
0.25
TDCD_CLK
Global Clock Tree Duty Cycle Distortion(1)
Global Clock Tree Skew(2)
All
0.12
0.22
0.43
0.50
0.50
0.85
1.07
N/A
0.12
0.22
0.45
0.51
0.51
0.88
1.10
1.29
0.45
0.74
1.36
0.43
0.86
0.86
1.29
0.10
0.08
0.25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCKSKEW
XQ5VLX30T
XQ5VLX85
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T
XQ5VFX70T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T
All
0.44
0.72
N/A
0.42
0.84
0.84
N/A
TDCD_BUFIO
TBUFIOSKEW
TDCD_BUFR
I/O clock tree duty cycle distortion
0.10
0.07
0.25
I/O clock tree skew across one clock region
Regional clock tree duty cycle distortion
All
All
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
2. The T
value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
CKSKEW
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
DS714 (v2.2) January 17, 2011
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Product Specification
72
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
(1)
Table 99: Package Skew
Symbol
Description
Package Skew(2)
Device
XQ5VLX30T(3)
XQ5VLX85
Package
FF323
Value
127
142
142
173
163
147
156
155
103
176
161
102
153
144
172
181
164
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
TPKGSKEW
EF676
XQ5VLX110
XQ5VLX110
XQ5VLX110T
XQ5VLX155T
XQ5VLX220T
XQ5VLX330T
XQ5VSX50T
XQ5VSX95T
XQ5VSX240T(3)
XQ5VFX70T
XQ5VFX70T
XQ5VFX100T
XQ5VFX100T
XQ5VFX130T
XQ5VFX200T(3)
EF676
EF1153
EF1136
EF1136
EF1738
EF1738
EF665
EF1136
FF1738
EF665
EF1136
EF1136
EF1738
EF1738
FF1738
Notes:
1. Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
2. These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time
from Pad to Ball (7.0 ps per mm).
3. The EF package is not available for these devices.
Table 100: Sample Window
Speed Grade
Symbol
Description
Device
Units
-2I
-1I
-1M
550
450
TSAMP
Sampling Error at Receiver Pins(1)
All
All
500
400
550
450
ps
ps
TSAMP_BUFIO
Sampling Error at Receiver Pins using BUFIO(2)
Notes:
1. This parameter indicates the total sampling error of Virtex-5Q FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 DCM jitter
- DCM accuracy (phase offset)
- DCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of Virtex-5Q FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.
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73
Virtex-5Q FPGA Data Sheet: DC and Switching Characteristics
Table 101: Source-Synchronous Pin-to-Pin Setup/Hold and Clock-to-Out
Symbol Description
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
Speed Grade
-1I
Units
-2I
-1M
–0.54
1.72
–0.54
1.91
–0.54
1.91
TPSCS/TPHCS
Setup/Hold of I/O clock
ns
ns
Pin-to-Pin Clock-to-Out Using BUFIO
TICKOFCS Clock-to-Out of I/O clock
4.82
5.40
5.40
Revision History
The following table shows the revision history for this document.
Date
Version
1.0
Description of Revisions
05/05/09
12/17/09
Initial Xilinx release.
2.0
Changed the document classification from Preliminary Product Specification to Product Specification.
Updated XQ5VSX240T, XQ5VFX70T, and XQ5VFX200T to production devices in Table 54 and
Table 55.
Updated package information for XQ5VFX200T and XQ5VSX240T in Table 99.
07/23/10
2.1
Production release of XQ5VFX70T and XQ5VFX100T in the -1M speed grade. This includes changes
to Table 54 and Table 55. Added a -1M column to any table with speed grades. Also updated the -2I
speed grade software in Table 55 for the XQ5VLX220T and XQ5VSX95T device.
Added -1(M) column to Table 4 including values for XQ5VFX70T and XQ5VFX100T. Revised
maximum VOD in Table 8. Updated both minimum and maximum VOCM in Table 10. Updated minimum
DVPPIN in Table 40. In Table 46, updated TJ4.25 and added note 5. In Table 51, added I-grade and M-
grade delineation for gain error, bipolar gain error, and ADCCLK revised AIDD maximum specification.
Added note 1 to Table 57. In Table 71, added the FX70T (M) specification for the global clock tree
(BUFG) FMAX. Added the FX70T (M) specification for the FOUTMAX to Table 74. Added note 5 to
Table 76. Added note 5 to Table 77. Added note 3 to Table 81.
01/17/11
2.2
Revised production release of the XQ5VFX70T and XQ5VFX100T in the -1M speed grade to software
version ISE 12.4 using the v1.71 speed specification (see Table 55).
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
XILINX PRODUCTS (INCLUDING HARDWARE, SOFTWARE AND/OR IP CORES) ARE NOT DESIGNED OR INTENDED TO BE FAIL-
SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE PERFORMANCE, SUCH AS IN LIFE-SUPPORT OR SAFETY
DEVICES OR SYSTEMS, CLASS III MEDICAL DEVICES, NUCLEAR FACILITIES, APPLICATIONS RELATED TO THE DEPLOYMENT
OF AIRBAGS, OR ANY OTHER APPLICATIONS THAT COULD LEAD TO DEATH, PERSONAL INJURY OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (INDIVIDUALLY AND COLLECTIVELY, “CRITICAL APPLICATIONS”). FURTHERMORE, XILINX
PRODUCTS ARE NOT DESIGNED OR INTENDED FOR USE IN ANY APPLICATIONS THAT AFFECT CONTROL OF A VEHICLE OR
AIRCRAFT, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR.
CUSTOMER AGREES, PRIOR TO USING OR DISTRIBUTING ANY SYSTEMS THAT INCORPORATE XILINX PRODUCTS, TO
THOROUGHLY TEST THE SAME FOR SAFETY PURPOSES. TO THE MAXIMUM EXTENT PERMITTED BY APPLICABLE LAW,
CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY USE OF XILINX PRODUCTS IN CRITICAL APPLICATIONS.
DS714 (v2.2) January 17, 2011
www.xilinx.com
Product Specification
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