XC7V1500T-2FFG1157E [XILINX]
Field Programmable Gate Array, 229050 CLBs, PBGA1157, LEAD FREE, FBGA-1157;型号: | XC7V1500T-2FFG1157E |
厂家: | XILINX, INC |
描述: | Field Programmable Gate Array, 229050 CLBs, PBGA1157, LEAD FREE, FBGA-1157 栅 可编程逻辑 |
文件: | 总49页 (文件大小:1194K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Virtex-7 FPGAs Data Sheet:
DC and Switching Characteristics
DS183 (v1.0) March 1, 2011
Advance Product Specification
NOTICE: This document contains preliminary information and is subject to change without notice. Information provided herein relates to products and/or
services not yet available for sale, and provided solely for information purposes and are not intended, or to be construed, as an offer for sale or an attempted
commercialization of the products and/or services referred to herein.
Virtex-7 FPGA Electrical Characteristics
Virtex-7 FPGAs are available in -3, -2, -1, and -1L speed
grades, with -3 having the highest performance. Virtex-7
FPGA DC and AC characteristics are specified for both
commercial and industrial grades. Except the operating
temperature range or unless otherwise noted, all the DC
and AC electrical parameters are the same for a particular
speed grade (that is, the timing characteristics of a -1 speed
grade industrial device are the same as for a -1 speed grade
commercial device). However, only selected speed grades
and/or devices might be available in the industrial range.
All supply voltage and junction temperature specifications
are representative of worst-case conditions. The
parameters included are common to popular designs and
typical applications.
This Virtex-7 FPGA data sheet, part of an overall set of
documentation on the 7 series FPGAs, is available on the
Xilinx website at www.xilinx.com/7.
All specifications are subject to change without notice.
Virtex-7 FPGA DC Characteristics
(1)
Table 1: Absolute Maximum Ratings
Symbol
Description
Internal supply voltage relative to GND
Units
–0.5 to 1.1
–0.5 to 1.0
V
V
VCCINT
For -1L devices: Internal supply voltage relative to GND
Auxiliary supply voltage relative to GND
VCCAUX
–0.5 to 2.0
V
VCCAUX_IO
Auxiliary supply voltage relative to GND
–0.5 to 2.06
–0.5 to 3.6
V
Output drivers supply voltage relative to GND for 3.3V HR banks
Output drivers supply voltage relative to GND for 1.8V HP banks
Supply voltage for the block RAM memories
XADC supply relative to GNDADC
V
VCCO
–0.5 to 2.0
V
VCCBRAM
VCCADC
VCCBATT
VREF
–0.5 to 1.1
V
–0.5 to 2.0
V
Key memory battery backup supply
–0.5 to 2.0
V
Input reference voltage
–0.5 to 2.0
V
VREFP
XADC reference input relative to GNDADC
–0.5 to 2.0
V
3.3V or below I/O input voltage relative to GND(3) (user and dedicated I/Os)
1.8V or below I/O input voltage relative to GND(3) (user and dedicated I/Os)
Voltage applied to 3-state 1.8V or below output(3) (user and dedicated I/Os)
Storage temperature (ambient)
Maximum soldering temperature(4)
Maximum junction temperature(4)
–0.5 to VCCO + 0.5
–0.5 to VCCO + 0.5
–0.5 to VCCO + 0.5
–65 to 150
V
(2)
VIN
V
VTS
TSTG
TSOL
Tj
V
°C
°C
°C
+220
+125
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
2. The 3.3V and 1.8V I/O absolute maximum limit applied to DC and AC signals.
3. For I/O operation, refer to the 7 Series FPGAs SelectIO Resources User Guide.
4. For soldering guidelines and thermal considerations, see 7 Series FPGA Packaging and Pinout Specification.
© 2011 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Kintex, Artix, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
DS183 (v1.0) March 1, 2011
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Advance Product Specification
1
Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
(1)
Table 2: Recommended Operating Conditions
Symbol
VCCINT
VCCAUX
Description
Min
0.97
0.87
1.71
1.71
1.11
1.11
0.97
1.0
Max
1.03
0.93
1.89
2.06
3.45
1.89
1.03
1.98
Units
V
Internal supply voltage relative to GND, Tj = 0°C to +85°C
For -1L devices: internal supply voltage relative to GND, Tj = 0°C to +85°C
Auxiliary supply voltage relative to GND, Tj = 0°C to +85°C
V
V
VCCAUX_IO Auxiliary supply voltage relative to GND
Supply voltage for 3.3V HR I/O banks relative to GND, Tj = 0°C to +85°C
V
V
(2)(4)(5)
VCCO
Supply voltage for 1.8V HP I/O banks relative to GND, Tj = 0°C to +85°C
Block RAM supply voltage
V
VCCBRAM
V
(3)
VCCBATT
VIN
Battery voltage relative to GND, Tj = 0°C to +85°C
I/O input voltage relative to GND, Tj = 0°C to +85°C
V
GND – 0.20 VCCO + 0.2
V
Maximum current through any pin in a powered or unpowered bank when forward
biasing the clamp diode.
–
10
mA
(6)
IIN
Notes:
1. All voltages are relative to ground.
2. Configuration data is retained even if V
drops to 0V.
CCO
3.
V
is required only when using bitstream encryption. If battery is not used, connect V
to either ground or V
.
CCAUX
CCBATT
CCBATT
4. Includes V
of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.
CCO
5. The configuration supply voltage V
is also known as V
.
CC_CONFIG
CCO_0
6. A total of 100 mA per bank should not be exceeded.
Table 3: DC Characteristics Over Recommended Operating Conditions
Symbol Description
VDRINT Data retention VCCINT voltage (below which configuration data might be lost)
Min
Typ(1)
Max
Units
V
VDRI
IREF
IL
Data retention VCCAUX voltage (below which configuration data might be lost)
VREF leakage current per pin
V
µA
µA
pF
µA
µA
µA
µA
µA
µA
µA
nA
n
Input or output leakage current per pin (sample-tested)
Die input capacitance at the pad
(2)
CIN
Pad pull-up (when selected) @ VIN = 0V, VCCO = 3.3V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 2.5V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.8V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.5V
Pad pull-up (when selected) @ VIN = 0V, VCCO = 1.2V
Pad pull-down (when selected) @ VIN = 3.3V
Pad pull-down (when selected) @ VIN = 1.8V
Battery supply current
IRPU
IRPD
(3)
IBATT
n
r
Temperature diode ideality factor
Series resistance
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. This measurement represents the die capacitance at the pad, not including the package.
3. Maximum value specified for worst case process at 25°C.
DS183 (v1.0) March 1, 2011
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Advance Product Specification
2
Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Important Note
Typical values for quiescent supply current are specified at nominal voltage, 85°C junction temperatures (T). Xilinx
j
recommends analyzing static power consumption at T = 85°C because the majority of designs operate near the high end of
j
the commercial temperature range. Quiescent supply current is specified by speed grade for Virtex-7 devices. Use the
XPOWER™ Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate static power
consumption for conditions other than those specified in Table 4.
Table 4: Typical Quiescent Supply Current
Speed and Temperature Grade
Symbol
Description
Device
Units
-3
-2
-1
-1L
N/A
N/A
N/A
ICCINTQ
Quiescent VCCINT supply current XC7V285T
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
XC7V450T
XC7V585T
XC7V855T
XC7V1500T
XC7V2000T
XC7VX485T
N/A
N/A
ICCOQ
Quiescent VCCO supply current
XC7V285T
XC7V450T
XC7V585T
XC7V855T
XC7V1500T
XC7V2000T
XC7VX485T
N/A
N/A
ICCAUXQ
Quiescent VCCAUX supply current XC7V285T
XC7V450T
XC7V585T
XC7V855T
XC7V1500T
XC7V2000T
XC7VX485T
N/A
N/A
Notes:
1. Typical values are specified at nominal voltage, 85°C junction temperatures (T ).
j
2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and
floating.
3. If DCI or differential signaling is used, more accurate quiescent current estimates can be obtained by using the XPOWER Estimator (XPE)
or XPOWER Analyzer (XPA) tools.
DS183 (v1.0) March 1, 2011
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Advance Product Specification
3
Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual
current consumed depends on the power-on ramp rate of the power supply.
The recommended power-on and reverse power-off sequence for Virtex-7 devices is V
, V
, V
, V
,
CCINT CCBRAM CCAUX CCAUX_IO
and V
to achieve minimum current draw and ensure I/Os are 3-stated at power-up. In cases where the recommended
CCO
sequence cannot be met, the following rules ensure that the I/Os remain 3-stated and no device damage will occur. V
CCINT
and V
can be powered on or off at any time as long as the following rules are met:
CCBRAM
•
V
and V
must be powered prior to V
. The sequencing of V
and V
relative to each
CCAUX_IO
CCAUX
CCAUX_IO
CCO
CCAUX
other does not matter.
•
•
•
V
V
and V
can be powered by the same supply.
CCO
CCAUX
CCAUX
, V
, and V
can ramp simultaneously.
CCO
CCAUX_IO
During operation, the V
,V
, and V
voltages must stay within their specifications (see Table 2).
CCINT
CCAUX CCAUX_IO
When powering down, the reverse power-up sequencing rules are recommended for the same reasons given during power
up. V must be powered down prior to V and V , or if powered by the same supply, V can be powered
CCO
CCAUX
CCAUX_IO
CCO
down simultaneously.
In -3, -2, and -1 devices, if V
and V
have the same recommended voltage levels, then both can be powered by
CCBRAM
CCINT
the same supply. Both V
and V
can be powered up or down any time during the recommended sequence.
CCINT
CCBRAM
Table 5 shows the minimum current, in addition to I
, that are required by Virtex-7 devices for proper power-on and
CCQ
configuration. If the current minimums shown in Table 4 and Table 5 are met, the device powers on after all three supplies
have passed through their power-on reset threshold voltages. The FPGA must not be configured until after V
applied.
is
CCINT
Once initialized and configured, use the XPOWER tools to estimate current drain on these supplies.
Table 5: Power-On Current for Virtex-7 Devices
ICCINTMIN
Typ(1)
ICCAUXMIN
Typ(1)
ICCOMIN
Typ(1)
Device
Units
XC7V285T
XC7V450T
XC7V585T
XC7V855T
XC7V1500T
XC7V2000T
XC7VX485T
mA
mA
mA
mA
mA
mA
mA
Notes:
1. Typical values are specified at nominal voltage, 25°C.
2. Use the XPOWER™ Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate maximum power-on currents.
Table 6: Power Supply Ramp Time
Symbol
VCCINT
Description
Internal supply voltage relative to GND
Ramp Time
0.20 to 50.0
0.20 to 50.0
0.20 to 50.0
0.20 to 50.0
Units
ms
VCCO
Output drivers supply voltage relative to GND
Auxiliary supply voltage relative to GND
Block RAM supply voltage relative to GND
ms
VCCAUX
VCCBRAM
ms
ms
DS183 (v1.0) March 1, 2011
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Advance Product Specification
4
Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
SelectIO™ DC Input and Output Levels
Values for V and V are recommended input voltages. Values for I and I are guaranteed over the recommended
IL
IH
OL
OH
operating conditions at the V and V test points. Only selected standards are tested. These are chosen to ensure that
OL
OH
all standards meet their specifications. The selected standards are tested at a minimum V
with the respective V and
CCO
OL
V
voltage levels shown. Other standards are sample tested.
OH
(1)(2)
Table 7: SelectIO DC Input and Output Levels
VIL
VIH
VOL
V, Max
0.4
VOH
IOL
IOH
I/O Standard
V, Min
–0.3
–0.3
–0.3
–0.3
V, Max
0.8
V, Min
2.0
V, Max
3.45
V, Min
2.4
mA
mA
LVTTL
Note 3
Note 4
Note 4
Note 5
Note 3
Note 4
Note 4
Note 5
LVCMOS33
LVCMOS25
0.8
2.0
3.45
0.4
VCCO – 0.4
VCCO – 0.4
VCCO – 0.45
0.7
1.7
VCCO + 0.3
VCCO + 0.3
0.4
LVCMOS18,
LVDCI18
35% VCCO
65% VCCO
0.45
LVCMOS15,
LVDCI15
–0.3
30% VCCO
70% VCCO
VCCO + 0.3
25% VCCO
75% VCCO
Note 6
Note 6
LVCMOS12
PCI33_3
–0.3
–0.5
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
35% VCCO
30% VCCO
65% VCCO
50% VCCO
VREF + 0.1
VREF + 0.1
VREF + 0.1
VCCO + 0.3
VCCO + 0.5
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
25% VCCO
75% VCCO
90% VCCO
75% VCCO
VCCO – 0.4
VCCO – 0.4
–
Note 7
Note 7
–0.5
6.3
–8
10% VCCO
1.5
6.3
8
HSTL I_12
HSTL I(8)
V
REF – 0.1
25% VCCO
VREF – 0.1
VREF – 0.1
0.4
0.4
–
HSTL II(8)
16
–
–16
–
DIFF HSTL I(8)
DIFF HSTL II(8)
SSTL135
50% VCCO – 0.1 50% VCCO + 0.1 VCCO + 0.3
50% VCCO – 0.1 50% VCCO + 0.1 VCCO + 0.3
–
–
–
–
VREF – 0.15
50%
VREF + 0.15
VCCO + 0.3
VCCO + 0.3
DIFF SSTL135
50%
VCCO + 0.15
VCCO – 0.15
SSTL18 I
–0.3
–0.3
–0.3
V
REF – 0.125
REF – 0.125
50%
VREF + 0.125
VREF + 0.125
VCCO + 0.3
VCCO + 0.3
VCCO + 0.3
VTT – 0.47
VTT – 0.60
VTT – 0.608
VTT + 0.47
VTT + 0.60
VTT + 0.608
8
13.4
–
–8
–13.4
–
SSTL18 II
V
DIFF SSTL18 I
50%
VCCO + 0.125
VCCO – 0.125
DIFF SSTL18 II
–0.3
–0.3
50%
50%
VCCO + 0.125
V
CCO + 0.3
–
–
–
–
VCCO – 0.125
VREF – 0.1
SSTL15
VREF + 0.1
VCCO + 0.3
VTT – 0.175
VTT + 0.175
17.8
17.8
Notes:
1. Tested according to relevant specifications.
2. 3.3V and 2.5V standards are only supported in 3.3V I/O banks.
3. Supported drive strengths of 4, 8, 12, 16, or 24 mA
4. Supported drive strengths of 4, 8, 12, or 16 mA
5. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, 16, or 24 mA in HR I/O banks.
6. Supported drive strengths of 2, 4, 6, 8, 12, or 16 mA in HP I/O banks and 4, 8, 12, or 16 mA in HR I/O banks.
7. Supported drive strengths of 2, 4, 6, or 8 mA in HP I/O banks and 4, 8, or 12 mA in HR I/O banks.
8. Applies to both 1.5V and 1.8V HSTL.
9. For detailed interface specific DC voltage levels, see the 7 Series FPGAs SelectIO Resources User Guide.
DS183 (v1.0) March 1, 2011
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Advance Product Specification
5
Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
LVDS DC Specifications (LVDS_25)
Table 8: LVDS_25 DC Specifications
Symbol
VCCO
VOH
DC Parameter
Supply Voltage
Conditions
Min
Typ
Max
Units
V
Output High Voltage for Q and Q
Output Low Voltage for Q and Q
RT = 100 across Q and Q signals
RT = 100 across Q and Q signals
RT = 100 across Q and Q signals
V
VOL
V
VODIFF
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
mV
VOCM
VIDIFF
Output Common-Mode Voltage
RT = 100 across Q and Q signals
V
Differential Input Voltage (Q – Q),
Q = High (Q – Q), Q = High
mV
VICM
Input Common-Mode Voltage
V
LVDS DC Specifications (LVDS)
Table 9: LVDS DC Specifications
Symbol
VCCO
VOH
DC Parameter
Supply Voltage
Conditions
Min
Typ
Max
Units
V
Output High Voltage for Q and Q
Output Low Voltage for Q and Q
RT = 100 across Q and Q signals
RT = 100 across Q and Q signals
RT = 100 across Q and Q signals
V
VOL
V
VODIFF
Differential Output Voltage (Q – Q),
Q = High (Q – Q), Q = High
mV
VOCM
VIDIFF
Output Common-Mode Voltage
RT = 100 across Q and Q signals
V
Differential Input Voltage (Q – Q),
Q = High (Q – Q), Q = High
Common-mode input voltage = 1.25V
mV
VICM
Input Common-Mode Voltage
Differential input voltage = 350 mV
V
eFUSE Read Endurance and Programming Conditions
Table 10 lists the maximum number of read cycle operations expected. Table 11 lists the programming conditions
specifically for eFUSE. For more information, see the 7 Series FPGA Configuration User Guide.
Table 10: eFUSE Read Endurance
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
DNA_CYCLES
Number of DNA_PORT READ operations or JTAG ISC_DNA read
command operations. Unaffected by SHIFT operations.
Read
Cycles
AES_CYCLES
Number of JTAG FUSE_KEY or FUSE_CNTL read command
operations. Unaffected by SHIFT operations.
Read
Cycles
Table 11: eFUSE Programming Conditions
Symbol
Description
Min
Typ
–
Max
40
Units
mA
IFS
t j
VCCAUX supply current
Temperature range
–
15
–
85
°C
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
GTX Transceiver Specifications
GTX Transceiver DC Characteristics
(1)(2)
Table 12: Recommended Operating Conditions for GTX Transceivers
Symbol
Description
Min
Typ
Max
Units
Analog supply voltage for the GTX transmitter and receiver circuits relative to
GND
0.97
1.0
1.03
MGTAVCC
V
Analog supply voltage for the GTX transmitter and receiver termination circuits
relative to GND
MGTAVTT
1.17
1.2
1.23
V
Analog supply voltage for the resistor calibration circuit of the GTX transceiver
column
MGTAVTTRCAL
1.17
1.75
1.2
1.23
1.85
V
V
MGTVCCAUX
Auxiliary analog Quad PLL (QPLL) voltage supply for the transceivers
1.80
Notes:
1. Each voltage listed requires the filter circuit described in 7 Series FPGAs Transceiver User Guide.
2. Voltages are specified for the temperature range of T = 0°C to +85°C.
j
GTX Transceiver DC Input and Output Levels
Table 13 summarizes the DC output specifications of the GTX transceivers in Virtex-7 FPGAs. Consult the 7 Series FPGAs
Transceiver User Guide for further details.
Table 13: GTX Transceiver DC Specifications
Symbol
DC Parameter
Conditions
Min
Typ
Max
Units
Differential peak-to-peak input External AC coupled
voltage
–
2000
mV
DVPPIN
Absolute input voltage
DC coupled
MGTAVTT = 1.2V
–400
–
MGTAVTT
mV
mV
mV
mV
VIN
Common mode input voltage
DC coupled
MGTAVTT = 1.2V
–
–
2/3 MGTAVTT
–
–
VCMIN
Differential peak-to-peak output Transmitter output swing is set to
1000
DVPPOUT
VCMOUTDC
voltage(1)
maximum setting
DC common mode output
voltage.
Equation based
MGTAVTT – DVPPOUT/4
RIN
Differential input resistance
Differential output resistance
100
100
ROUT
TOSKEW
CEXT
Transmitter output pair (TXP and TXN) intra-pair skew
Recommended external AC coupling capacitor(2)
–
–
10
–
ps
nF
100
Notes:
1. The output swing and preemphasis levels are programmable using the attributes discussed in the 7 Series FPGAs Transceiver User Guide
and can result in values lower than reported in this table.
2. Other values can be used as appropriate to conform to specific protocols and standards.
DS183 (v1.0) March 1, 2011
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
X-Ref Target - Figure 1
+V
0
P
N
Single-Ended
Voltage
ds183_01_021611
Figure 1: Single-Ended Peak-to-Peak Voltage
X-Ref Target - Figure 2
+V
0
Differential
Voltage
P–N
–V
ds183_02_021611
Figure 2: Differential Peak-to-Peak Voltage
Table 14 summarizes the DC specifications of the clock input of the GTX transceiver. Consult the 7 Series FPGAs
Transceiver User Guide for further details.
Table 14: GTX Transceiver Clock DC Input Level Specification
Symbol
VIDIFF
DC Parameter
Differential peak-to-peak input voltage
Min
Typ
Max
Units
mV
250
2000
RIN
Differential input resistance
100
100
CEXT
Required external AC coupling capacitor
–
–
nF
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
GTX Transceiver Switching Characteristics
Consult 7 Series FPGAs Transceiver User Guide for further information.
Table 15: GTX Transceiver Performance
Speed Grade
Output
Symbol
Description
Units
Divider
-3
-2
-1
6.6
-1L(1)
6.6
(2)
FGTXMAX
Maximum GTX transceiver data rate
12.5
0.500
10.3125
0.500
Gb/s
Gb/s
Gb/s
Gb/s
Gb/s
Gb/s
Gb/s
Gb/s
Gb/s
Gb/s
(2)
FGTXMIN
Minimum GTX transceiver data rate
0.500
0.500
1
2
3.2–6.6
1.6–3.3
0.8–1.65
FGTXCRANGE
CPLL line rate range
4
8
0.5–0.825
N/A
16
1
5.93–8.0
2.965–4.0
1.4825–2.0
0.74125–1.0
N/A
5.93–8.0
5.93–6.6
2.965–3.3
5.93–6.6
2.965–3.3
2
2.965–4.0
1.4825–2.0
0.74125–1.0
N/A
FGTXQRANGE1 QPLL line rate range 1
4
1.4825–1.65
1.4825–1.65
8
0.74125–0.825 0.74125–0.825 Gb/s
16
1
N/A
N/A
N/A
N/A
Gb/s
Gb/s
Gb/s
Gb/s
Gb/s
Gb/s
GHz
9.8–12.5
9.8–10.3125
4.9–5.15625
2.45–2.578125
1.225–1.2890625
2
4.9–6.25
N/A
N/A
FGTXQRANGE2 QPLL line rate range 2
4
2.45–3.125
1.225–1.5625
N/A
N/A
8
N/A
N/A
16
0.6125–0.78125 0.6125–0.64453125
N/A
N/A
FGCPLLRANGE GTX transceiver CPLL frequency
range
1.6–3.3
5.93–8.0
9.8–12.5
1.6–3.3
1.6–3.3
1.6–3.3
FGCPLLRANGE1 GTX transceiver QPLL frequency
range 1
5.93–8.0
5.93–6.6
N/A
5.93–6.6
N/A
GHz
GHz
FGCPLLRANGE2 GTX transceiver QPLL frequency
range 2
9.8–10.3125
Notes:
1. The -1L speed grade requires a 4-byte internal data width for operation above 5.0 Gb/s.
2. Data rates between 8.0 Gb/s and 9.8 Gb/s are not available.
Table 16: GTX Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
FGTXDRPCLK
GTXDRPCLK maximum frequency
150
150
125
125
MHz
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 17: GTX Transceiver Reference Clock Switching Characteristics
All Speed Grades
Symbol
Description
Conditions
Units
Min
60
–
Typ
–
Max
650
–
FGCLK
TRCLK
TFCLK
TDCREF
Reference clock frequency range
Reference clock rise time
Reference clock fall time
MHz
ps
20% – 80%
200
200
50
–
80% – 20%
–
–
ps
Reference clock duty cycle
Transceiver PLL only
40
–
60
%
Clock recovery frequency acquisition
time
ms
TLOCK
Initial PLL lock
Lock to data after PLL has locked
to the reference clock
–
–
µs
TPHASE
Clock recovery phase acquisition time
X-Ref Target - Figure 3
TRCLK
80%
20%
TFCLK
ds183_03_021611
Figure 3: Reference Clock Timing Parameters
Integrated Interface Block for PCI Express Designs Switching Characteristics
More information and documentation on solutions for PCI Express designs can be found at:
http://www.xilinx.com/technology/protocols/pciexpress.htm
Table 18: Maximum Performance for PCI Express Designs
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
250
250
250
250
FPIPECLK
Pipe clock maximum frequency
250
500
250
250
250
500
250
250
250
250
250
250
MHz
MHz
MHz
MHz
FUSERCLK
FUSERCLK2
FDRPCLK
User clock maximum frequency
User clock 2 maximum frequency
DRP clock maximum frequency
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
XADC Specifications
Table 19: XADC Specifications
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
VCCADC = 1.8V 5%, VREFP = 1.25V, VREFN = 0V, ADCCLK = 26 MHz, Tj = –40°C to 100°C, Typical values at Tj=+40°C
ADC Accuracy(1)
Resolution
12
–
–
–
–
–
–
–
–
Bits
LSBs
LSBs
LSBs
%
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
2
DNL
No missing codes, guaranteed monotonic
–
1
4
Calibrated
Calibrated
–
Gain Error
–
0.4
10
Channel Matching
Based on two individual ADC instances with
calibration enabled
–
LSBs
Sample Rate
0.1
60
–
–
–
–
3
–
1
–
2
–
–
MS/s
dB
Signal to Noise Ratio
RMS Code Noise
SNR
THD
FSAMPLE = 500KS/s, FIN = 20KHz
External 1.25V reference
On-chip reference
LSBs
LSBs
dB
–
Total Harmonic Distortion
FSAMPLE = 500KS/s, FIN = 20KHz
75
ADC Accuracy at Extended Temperatures (-55°C to 125°C)
Resolution
10
–
–
–
–
–
1
1
Bits
Integral Nonlinearity
Differential Nonlinearity
Analog Inputs(2)
INL
LSB
(at 10 bits)
DNL
No missing codes, guaranteed monotonic
–
ADC Input Ranges
Unipolar operation
0
–
–
–
–
–
1
V
V
V
V
V
Bipolar operation
–0.5
0
+0.5
Unipolar common mode range (FS input)
Bipolar common mode range (FS input)
+0.5
+0.5
–0.1
+0.6
Maximum External Channel
Input Ranges
Adjacent channels set within these ranges
should not corrupt measurements on adjacent
channels
VCCADC
Auxiliary Channel Full
Resolution Bandwidth
FRBW
250
–
–
KHz
On-Chip Sensors
Temperature Sensor Error
Tj = –40°C to 100°C.
Tj = –55°C to +125°C
–
–
–
–
–
–
4
6
1
°C
°C
%
Supply Sensor Error
Measurement range of VCCAUX 1.8V 5%
Tj = –40°C to +100°C
Measurement range of VCCAUX 1.8V 5%
Tj = –55°C to +125°C
–
–
2
%
Conversion Rate(3)
Conversion Time - Continuous tCONV
Number of ADCCLK cycles
Number of CLK cycles
DRP clock frequency
Derived from DCLK
26
–
–
–
–
–
–
32
21
cycle
cycle
MHz
MHz
%
Conversion Time - Event
DRP Clock Frequency
ADC Clock Frequency
DCLK Duty Cycle
tCONV
DCLK
8
250
26
ADCCLK
1
40
60
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 19: XADC Specifications (Cont’d)
Parameter
XADC Reference(4)
External Reference
On-Chip Reference
Symbol
Comments/Conditions
Min
Typ
Max
Units
VREFP
Externally supplied reference voltage
1.20
1.25
1.25
1.30
V
V
Ground VREFP pin to AGND,
Tj = –40°C to 100°C
1.2375
1.2625
Power Requirements
Analog Power Supply
Analog Supply Current
VCCADC
ICCADC
1.71
–
1.8
–
1.89
20
V
Analog circuits in powered up state
mA
Notes:
1. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature.
2. See the ADC chapter in the 7 Series FPGAs XADC User Guide for a detailed description.
3. See the Timing chapter in the 7 Series FPGAs XADC User Guide for a detailed description.
4. Any variation in the reference voltage from the nominal V
= 1.25V and V
= 0V will result in a deviation from the ideal transfer
REFP
REFN
function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external
ratiometric type applications allowing reference to vary by 4% is permitted. On-chip reference variation is 1%.
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in Virtex-7
devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject
to the same guidelines as the Switching Characteristics, page 13. In each table, the I/O bank type is either High
Performance (HP) or High Range (HR).
Table 20: Networking Applications Interface Performances
Speed Grade
Description
I/O Bank Type
Units
-3
-2
-1
-1L
SDR LVDS transmitter
(using OSERDES; DATA_WIDTH = 4 to 8)
HR
HP
HR
HP
HR
HP
HR
HP
710
710
710
800
1400
710
710
800
1400
625
625
667
1250
625
625
667
1250
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
710
DDR LVDS transmitter
(using OSERDES; DATA_WIDTH = 4 to 10)
1055
1600
710
SDR LVDS receiver (SFI-4.1)(1)
DDR LVDS receiver (SPI-4.2)(1)
710
1055
1600
Notes:
1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate
deterministic performance.
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
(1)
Table 21: Maximum Physical Interface (PHY) Rate for Memory Interfaces
Speed Grade
Memory
Standard
I/O Bank Type
VCCAUX_IO
Units
-3
-2
-1
-1L
HP
HP
HR
HP
HP
HR
HP
HP
HR
HP
HP
HR
HP
HP
HR
HP
HP
HR
HP
HP
HR
2.0V
1.8V
N/A
1866
1600
1066
1600
1066
800
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
Mb/s
DDR3
1333
1066
2.0V
1.8V
N/A
1333
800
DDR3L
1333
800
1066
800
667
2.0V
1.8V
N/A
DDR2
800
800
800
Mb/s
2.0V
1.8V
N/A
550
500
500
450
450
400
MHz
MHz
QDR II+
2.0V
1.8V
N/A
RLDRAM II
RLDRAM III
533
500
450
MHz
2.0V
1.8V
N/A
MHz
MHz
N/A
2.0V
1.8V
N/A
Mb/s
Mb/s
Mb/s
LPDDR2
Notes:
1. Advance performance numbers pending characterization on Xilinx memory platforms designed according to the guidelines in the 7 Series
FPGAs Memory Interface Solutions User Guide.
Switching Characteristics
All values represented in this data sheet are based on the advance speed specifications in ISE® software.
Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or
Production. Each designation is defined as follows:
Advance
These specifications are based on simulations only and are typically available soon after device design specifications are
frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-
reporting might still occur.
Preliminary
These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades
with this designation are intended to give a better indication of the expected performance of production silicon. The
probability of under-reporting delays is greatly reduced as compared to Advance data.
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Production
These specifications are released once enough production silicon of a particular device family member has been
characterized to provide full correlation between specifications and devices over numerous production lots. There is no
under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest
speed grades transition to Production before faster speed grades.
All specifications are always representative of worst-case supply voltage and junction temperature conditions.
Since individual family members are produced at different times, the migration from one category to another depends
completely on the status of the fabrication process for each device.
Table 22 correlates the current status of each Virtex-7 device on a per speed grade basis.
Table 22: Virtex-7 Device Speed Grade Designations
Speed Grade Designations
Device
Advance
-1L, -1, -2, -3
-1L, -1, -2, -3
-1L, -1, -2, -3
-1L, -1, -2, -3
-1L, -1, -2
Preliminary
Production
XC7V285T
XC7V450T
XC7V585T
XC7V855T
XC7V1500T
XC7V2000T
XC7VX485T
-1L, -1, -2
-1, -2, -3
Testing of Switching Characteristics
All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed
below are representative values.
For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and
back-annotate to the simulation net list. Unless otherwise noted, values apply to all Virtex-7 devices.
Production Silicon and ISE Software Status
In some cases, a particular family member (and speed grade) is released to production before a speed specification is
released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent
speed specification releases.
Table 23 lists the production released Virtex-7 device, speed grade, and the minimum corresponding supported speed
specification version and ISE software revisions. The ISE software and speed specifications listed are the minimum releases
required for production. All subsequent releases of software and speed specifications are valid.
Table 23: Virtex-7 Device Production Software and Speed Specification Release
Speed Grade Designations
Device
-3
-2
-1
-1L
XC7V285T
XC7V450T
XC7V585T
XC7V855T
XC7V1500T
XC7V2000T
XC7VX485T
N/A
N/A
N/A
Notes:
1. Blank entries indicate a device and/or speed grade in advance or preliminary status.
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
IOB Pad Input/Output/3-State Switching Characteristics
Table 24 (3.3V high-range IOB (HR)) and Table 25 (1.8V high-performance IOB (HP)) summarizes the values of standard-
specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays.
T
is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies depending
IOPI
on the capability of the SelectIO input buffer.
T
is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies
IOOP
depending on the capability of the SelectIO output buffer.
T
is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is
IOTP
disabled. The delay varies depending on the SelectIO capability of the output buffer.
Table 26 summarizes the value of T . T is described as the delay from the T pin to the IOB pad through the
IOTPHZ IOTPHZ
output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state).
Table 24: 3.3V IOB High Range (HR) Switching Characteristics
TIOPI
TIOOP
TIOTP
I/O Standard
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-1L
-3
-2
-1
-1L
-3
-2
-1
-1L
LVDS_25(1)
0.61 0.66 0.74
0.61 0.65 0.72
0.61 0.67 0.76
0.61 0.66 0.75
0.63 0.68 0.76
0.72 0.79 0.90
1.32 1.44 1.62
0.56 0.60 0.65
0.54 0.58 0.64
0.57 0.61 0.67
0.57 0.61 0.67
0.58 0.61 0.67
0.58 0.61 0.67
0.61 0.65 0.70
0.61 0.65 0.70
0.62 0.66 0.73
0.62 0.66 0.73
0.57 0.61 0.67
0.57 0.61 0.67
0.58 0.61 0.67
0.58 0.61 0.67
0.61 0.65 0.70
0.61 0.65 0.70
0.62 0.66 0.73
0.62 0.66 0.73
1.19 1.27 1.40
1.19 1.27 1.40
1.64 1.80 2.04
1.19 1.27 1.40
1.17 1.27 1.42
1.25 1.33 1.45
2.52 2.78 3.18
1.99 2.25 2.66
1.66 1.86 2.15
1.30 1.41 1.58
0.96 1.03 1.14
1.12 1.21 1.35
1.01 1.09 1.21
1.21 1.30 1.45
0.94 1.00 1.10
1.07 1.15 1.27
0.93 1.00 1.10
0.93 1.01 1.13
0.84 0.92 1.02
0.91 0.99 1.10
0.85 0.92 1.03
0.88 0.96 1.06
0.82 0.89 1.00
0.88 0.95 1.06
0.81 0.88 0.98
1.19 1.27 1.40
1.19 1.27 1.40
1.64 1.80 2.04
1.19 1.27 1.40
1.17 1.27 1.42
1.25 1.33 1.45
2.52 2.78 3.18
1.99 2.25 2.66
1.66 1.86 2.15
1.30 1.41 1.58
0.96 1.03 1.14
1.12 1.21 1.35
1.01 1.09 1.21
1.21 1.30 1.44
1.20 1.30 1.46
1.23 1.32 1.46
1.25 1.36 1.51
0.93 1.01 1.13
0.84 0.92 1.02
0.91 0.99 1.10
0.85 0.92 1.03
1.21 1.30 1.44
1.20 1.30 1.46
1.23 1.32 1.46
1.25 1.36 1.51
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MINI_LVDS_25
BLVDS_25(1)
RSDS_25 (point to point)(1)
PPDS_25(1)
TMDS_33(1)
PCI33_3(1)
HSUL_12
DIFF_HSUL_12
HSTL_I_S
HSTL_II_S
HSTL_I_18_S
HSTL_II_18_S
DIFF_HSTL_I_S
DIFF_HSTL_II_S
DIFF_HSTL_I_18_S
DIFF_HSTL_II_18_S
HSTL_I_F
HSTL_II_F
HSTL_I_18_F
HSTL_II_18_F
DIFF_HSTL_I_F
DIFF_HSTL_II_F
DIFF_HSTL_I_18_F
DIFF_HSTL_II_18_F
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 24: 3.3V IOB High Range (HR) Switching Characteristics (Cont’d)
TIOPI
TIOOP
TIOTP
I/O Standard
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-1L
-3
-2
-1
-1L
-3
-2
-1
-1L
LVCMOS33, Slow, 4 mA
LVCMOS33, Slow, 8 mA
LVCMOS33, Slow, 12 mA
LVCMOS33, Slow, 16 mA
LVCMOS33, Fast, 4 mA
LVCMOS33, Fast, 8 mA
LVCMOS33, Fast, 12 mA
LVCMOS33, Fast, 16 mA
LVCMOS25, Slow, 4 mA
LVCMOS25, Slow, 8 mA
LVCMOS25, Slow, 12 mA
LVCMOS25, Slow, 16 mA
LVCMOS25, Fast, 4 mA
LVCMOS25, Fast, 8 mA
LVCMOS25, Fast, 12 mA
LVCMOS25, Fast, 16 mA
LVCMOS18, Slow, 4 mA
LVCMOS18, Slow, 8 mA
LVCMOS18, Slow, 12 mA
LVCMOS18, Slow, 16 mA
LVCMOS18, Slow, 24 mA(1)
LVCMOS18, Fast, 4 mA
LVCMOS18, Fast, 8 mA
LVCMOS18, Fast, 12 mA
LVCMOS18, Fast, 16 mA
LVCMOS18, Fast, 24 mA(1)
LVCMOS15, Slow, 4 mA
LVCMOS15, Slow, 8 mA
LVCMOS15, Slow, 12 mA
LVCMOS15, Slow, 16 mA
LVCMOS15, Fast, 4 mA
LVCMOS15, Fast, 8 mA
LVCMOS15, Fast, 12 mA
LVCMOS15, Fast, 16 mA
LVCMOS12, Slow, 4 mA
LVCMOS12, Slow, 8 mA
LVCMOS12, Slow, 12 mA(1)
LVCMOS12, Fast, 4 mA
1.52 1.62 1.78
1.52 1.62 1.78
1.52 1.62 1.78
1.52 1.62 1.78
1.52 1.62 1.78
1.52 1.62 1.78
1.52 1.62 1.78
1.52 1.62 1.78
1.27 1.36 1.48
1.27 1.36 1.48
1.27 1.36 1.48
1.27 1.36 1.48
1.27 1.36 1.48
1.27 1.36 1.48
1.27 1.36 1.48
1.27 1.36 1.48
0.67 0.71 0.77
0.67 0.71 0.77
0.67 0.71 0.77
0.67 0.71 0.77
0.67 0.71 0.77
0.67 0.71 0.77
0.67 0.71 0.77
0.67 0.71 0.77
0.67 0.71 0.77
0.67 0.71 0.77
0.69 0.74 0.81
0.69 0.74 0.81
0.69 0.74 0.81
0.69 0.74 0.81
0.69 0.74 0.81
0.69 0.74 0.81
0.69 0.74 0.81
0.69 0.74 0.81
0.77 0.82 0.89
0.77 0.82 0.89
0.77 0.82 0.89
0.77 0.82 0.89
4.81 5.16 5.68
4.08 4.47 5.05
3.29 3.64 4.15
2.82 3.15 3.65
4.30 4.56 4.96
3.66 3.91 4.29
2.33 2.93 3.83
2.22 2.44 2.79
4.22 4.64 5.26
3.31 3.69 4.25
2.63 3.10 3.81
3.01 3.38 3.94
4.00 4.31 4.77
2.33 2.80 3.51
2.33 2.80 3.51
1.86 2.16 2.60
3.17 3.35 3.63
2.49 2.79 3.25
2.49 2.79 3.25
1.72 1.94 2.25
1.60 1.77 2.01
3.06 3.20 3.41
1.81 2.10 2.53
1.81 2.10 2.53
1.37 1.52 1.74
1.16 1.27 1.43
3.53 3.75 4.07
2.14 2.43 2.87
1.72 1.91 2.20
1.63 1.81 2.07
3.38 3.57 3.86
1.59 1.80 2.12
1.23 1.36 1.54
1.21 1.32 1.50
3.97 431 4.82
2.71 3.12 3.74
1.99 2.25 2.66
3.51 3.76 4.14
4.81 5.16 5.68
4.08 4.47 5.05
3.29 3.64 4.15
2.82 315 3.65
4.30 4.56 4.96
3.66 3.91 4.29
2.33 2.93 3.83
2.22 2.44 2.79
4.22 4.64 5.26
3.31 3.69 4.25
2.63 3.10 3.81
3.01 3.38 3.94
4.00 4.31 4.77
2.33 2.80 3.51
2.33 2.80 3.51
1.86 2.16 2.60
3.17 3.35 3.63
2.49 2.79 3.25
2.49 2.79 3.25
1.72 1.94 2.25
1.60 1.77 2.01
3.06 3.20 3.41
1.81 2.10 2.53
1.81 2.10 2.53
1.37 1.52 1.74
1.16 1.27 1.43
3.53 3.75 4.07
2.14 2.43 2.87
1.72 1.91 2.20
1.63 1.81 2.07
3.38 3.57 3.86
1.59 1.80 2.12
1.23 1.36 1.54
1.21 1.32 1.50
3.97 431 4.82
2.71 3.12 3.74
1.99 2.25 2.66
3.51 3.76 4.14
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 24: 3.3V IOB High Range (HR) Switching Characteristics (Cont’d)
TIOPI
TIOOP
TIOTP
I/O Standard
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-1L
-3
-2
-1
-1L
-3
-2
-1
-1L
LVCMOS12, Fast, 8 mA
LVCMOS12, Fast, 12 mA(1)
SSTL135_S
0.77 0.82 0.89
0.77 0.82 0.89
0.57 0.60 0.64
0.58 0.61 0.67
0.58 0.61 0.67
0.58 0.61 0.67
0.56 0.61 0.69
0.61 0.65 0.70
0.62 0.66 0.73
0.62 0.66 0.73
0.57 0.60 0.64
0.57 0.61 0.67
0.58 0.61 0.67
0.58 0.61 0.67
0.56 0.61 0.69
0.61 0.65 0.70
0.62 0.66 0.73
0.62 0.66 0.73
1.69 2.22 3.02
1.40 1.57 1.82
0.96 1.03 1.14
0.96 1.03 1.13
1.34 1.45 1.62
0.95 1.02 1.13
0.96 1.03 1.14
0.96 1.03 1.13
1.30 1.41 1.57
0.92 0.99 1.09
0.85 0.93 1.04
0.84 0.92 1.03
0.93 1.01 1.12
0.84 0.91 1.01
0.85 0.93 1.04
0.84 0.82 1.03
0.90 .097 1.08
0.82 0.89 0.99
1.69 2.22 3.02
1.40 1.57 1.82
0.96 1.03 1.14
0.96 1.03 1.13
1.34 1.45 1.62
0.95 1.02 1.13
0.96 1.03 1.14
0.96 1.03 1.13
1.30 1.41 1.57
0.92 0.99 1.09
0.85 0.93 1.04
0.84 0.92 1.03
0.93 1.01 1.12
0.84 0.91 1.01
0.85 0.93 1.04
0.84 0.82 1.03
0.90 .097 1.08
0.82 0.89 0.99
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SSTL15_S
SSTL18_I_S
SSTL18_II_S
DIFF_SSTL135_S
DIFF_SSTL15_S
DIFF_SSTL18_I_S
DIFF_SSTL18_II_S
SSTL135_F
SSTL15_F
SSTL18_I_F
SSTL18_II_F
DIFF_SSTL135_F
DIFF_SSTL15_F
DIFF_SSTL18_I_F
DIFF_SSTL18_II_F
Notes:
1. This I/O standard is only available in the 3.3V high-range (HR) banks.
DS183 (v1.0) March 1, 2011
www.xilinx.com
Advance Product Specification
17
Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 25: 1.8V IOB High Performance (HP) Switching Characteristics
TIOPI
TIOOP
TIOTP
I/O Standard
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-1L
-3
-2
-1
-1L
-3
-2
-1
-1L
LVDS
0.77 0.85 0.99
0.71 0.83 0.96
0.71 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
1.21 1.29 1.41
1.23 1.32 1.46
1.23 1.32 1.46
1.21 1.30 1.44
1.20 1.31 1.46
1.18 1.28 1.43
1.23 1.32 1.46
1.25 1.36 1.52
1.19 1.29 1.43
1.23 1.33 1.48
1.19 1.28 1.41
1.15 1.25 1.40
1.17 1.26 1.39
1.12 1.21 1.36
1.19 1.28 1.41
1.13 1.22 1.35
1.19 1.28 1.41
1.20 1.28 1.42
1.21 1.30 1.44
1.20 1.31 1.46
1.17 1.26 1.39
1.15 1.25 1.40
1.23 1.32 1.46
1.25 1.36 1.52
1.19 1.28 1.41
1.13 1.22 1.35
1.19 1.28 1.41
1.21 1.30 1.44
1.20 1.31 1.46
1.18 1.28 1.43
1.23 1.32 1.46
1.25 1.36 1.52
1.19 1.29 1.43
1.23 1.33 1.48
1.19 1.28 1.41
1.15 1.25 1.40
1.17 1.26 1.39
1.12 1.21 1.36
1.21 1.29 1.41
1.23 1.32 1.46
1.23 1.32 1.46
1.21 1.30 1.44
1.20 1.31 1.46
1.18 1.28 1.43
1.23 1.32 1.46
1.25 1.36 1.51
1.19 1.29 1.43
1.23 1.33 1.48
1.19 1.28 1.41
1.15 1.25 1.40
1.17 1.26 1.39
1.12 1.21 1.35
1.19 1.28 1.41
1.13 1.22 1.35
1.19 1.28 1.41
1.20 1.28 1.42
1.21 1.30 1.44
1.20 1.31 1.46
1.17 1.26 1.39
1.15 1.25 1.40
1.23 1.32 1.46
1.25 1.36 1.51
1.19 1.28 1.41
1.13 1.22 1.35
1.19 1.28 1.41
1.21 1.30 1.44
1.20 1.30 1.46
1.18 1.28 1.43
1.23 1.32 1.46
1.25 1.36 1.51
1.19 1.29 1.43
1.23 1.33 1.48
1.19 1.28 1.41
1.15 1.25 1.40
1.17 1.26 1.39
1.12 1.21 1.35
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HSUL_12
DIFF_HSUL_12
HSTL_I_S
HSTL_II_S
HSTL_III_S
HSTL_I_18_S
HSTL_II_18_S
HSTL_III_18_S
HSTL_I_12_S
HSTL_I_DCI_S
HSTL_II_DCI_S
HSTL_II_T_DCI_S
HSTL_III_DCI_S
HSTL_I_DCI_18_S
HSTL_II_DCI_18_S
HSTL_II _T_DCI_18_S
HSTL_III_DCI_18_S
DIFF_HSTL_I_S
DIFF_HSTL_II_S
DIFF_HSTL_I_DCI_S
DIFF_HSTL_II_DCI_S
DIFF_HSTL_I_18_S
DIFF_HSTL_II_18_S
DIFF_HSTL_I_DCI_18_S
DIFF_HSTL_II_DCI_18_S
DIFF_HSTL_II _T_DCI_18_S
HSTL_I_F
HSTL_II_F
HSTL_III_F
HSTL_I_18_F
HSTL_II_18_F
HSTL_III_18_F
HSTL_I_12_F
HSTL_I_DCI_F
HSTL_II_DCI_F
HSTL_II_T_DCI_F
HSTL_III_DCI_F
DS183 (v1.0) March 1, 2011
www.xilinx.com
Advance Product Specification
18
Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 25: 1.8V IOB High Performance (HP) Switching Characteristics (Cont’d)
TIOPI
TIOOP
TIOTP
I/O Standard
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-1L
-3
-2
-1
-1L
-3
-2
-1
-1L
HSTL_I_DCI_18_F
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.50 0.56 0.65
0.50 0.56 0.65
0.50 0.56 0.65
0.50 0.56 0.65
0.50 0.56 0.65
0.50 0.56 0.65
0.50 0.56 0.65
0.50 0.56 0.65
0.50 0.56 0.65
0.50 0.56 0.65
0.50 0.56 0.65
0.50 0.56 0.65
0.58 0.66 0.77
0.58 0.66 0.77
0.58 0.66 0.77
0.58 0.66 0.77
0.58 0.66 0.77
0.58 0.66 0.77
0.58 0.66 0.77
0.58 0.66 0.77
0.58 0.66 0.77
0.58 0.66 0.77
0.58 0.66 0.77
0.58 0.66 0.77
0.66 0.73 0.84
1.19 1.28 1.41
1.13 1.22 1.35
1.19 1.28 1.41
1.20 1.28 1.42
1.21 1.30 1.44
1.20 1.31 1.46
1.17 1.26 1.39
1.15 1.25 1.40
1.23 1.32 1.46
1.25 1.36 1.52
1.19 1.28 1.41
1.13 1.22 1.35
1.19 1.28 1.41
3.52 3.74 4.07
2.33 2.41 2.68
1.92 2.04 2.20
1.68 1.77 1.90
1.57 1.66 1.79
1.53 1.63 1.77
3.34 3.53 3.82
2.19 2.31 2.49
1.80 1.90 2.06
1.58 1.66 1.78
1.41 1.51 1.65
1.37 1.46 1.59
2.86 3.16 3.59
2.15 2.33 2.59
1.74 1.94 2.24
1.52 1.66 1.87
1.47 1.60 1.79
1.41 1.53 1.71
2.87 3.16 3.58
1.98 2.12 2.32
1.51 1.71 2.02
1.47 1.59 1.76
1.37 1.48 1.64
1.36 1.47 1.64
2.63 2.83 3.13
1.19 1.28 1.41
1.13 1.22 1.35
1.19 1.28 1.41
1.20 1.28 1.42
1.21 1.30 1.44
1.20 1.31 1.46
1.17 1.26 1.39
1.15 1.25 1.40
1.23 1.32 1.46
1.25 1.36 1.51
1.19 1.28 1.41
1.13 1.22 1.35
1.19 1.28 1.41
3.52 3.74 4.07
2.33 2.41 2.68
1.92 2.03 2.20
1.68 1.77 1.90
1.57 1.66 1.79
1.53 1.63 1.77
3.34 3.53 3.82
2.19 2.31 2.49
1.80 1.90 2.06
1.58 1.66 1.78
1.41 1.51 1.65
1.37 1.46 1.59
2.86 3.16 3.59
2.15 2.33 2.59
1.74 1.94 2.24
1.51 1.66 1.87
1.47 1.60 1.79
1.41 1.53 1.70
2.87 3.16 3.58
1.98 2.12 2.32
1.51 1.71 2.02
1.47 1.59 1.76
1.37 1.48 1.64
1.35 1.47 1.64
2.63 2.83 3.13
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
HSTL_II_DCI_18_F
HSTL_II _T_DCI_18_F
HSTL_III_DCI_18_F
DIFF_HSTL_I_F
DIFF_HSTL_II_F
DIFF_HSTL_I_DCI_F
DIFF_HSTL_II_DCI_F
DIFF_HSTL_I_18_F
DIFF_HSTL_II_18_F
DIFF_HSTL_I_DCI_18_F
DIFF_HSTL_II_DCI_18_F
DIFF_HSTL_II _T_DCI_18_F
LVCMOS18, Slow, 2 mA
LVCMOS18, Slow, 4 mA
LVCMOS18, Slow, 6 mA
LVCMOS18, Slow, 8 mA
LVCMOS18, Slow, 12 mA
LVCMOS18, Slow, 16 mA
LVCMOS18, Fast, 2 mA
LVCMOS18, Fast, 4 mA
LVCMOS18, Fast, 6 mA
LVCMOS18, Fast, 8 mA
LVCMOS18, Fast, 12 mA
LVCMOS18, Fast, 16 mA
LVCMOS15, Slow, 2 mA
LVCMOS15, Slow, 4 mA
LVCMOS15, Slow, 6 mA
LVCMOS15, Slow, 8 mA
LVCMOS15, Slow, 12 mA
LVCMOS15, Slow, 16 mA
LVCMOS15, Fast, 2 mA
LVCMOS15, Fast, 4 mA
LVCMOS15, Fast, 6 mA
LVCMOS15, Fast, 8 mA
LVCMOS15, Fast, 12 mA
LVCMOS15, Fast, 16 mA
LVCMOS12, Slow, 2 mA
DS183 (v1.0) March 1, 2011
www.xilinx.com
Advance Product Specification
19
Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 25: 1.8V IOB High Performance (HP) Switching Characteristics (Cont’d)
TIOPI
TIOOP
TIOTP
I/O Standard
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-1L
-3
-2
-1
-1L
-3
-2
-1
-1L
LVCMOS12, Slow, 4 mA
LVCMOS12, Slow, 6 mA
LVCMOS12, Slow, 8 mA
LVCMOS12, Fast, 2 mA
LVCMOS12, Fast, 4 mA
LVCMOS12, Fast, 6 mA
LVCMOS12, Fast, 8 mA
LVDCI_18
0.66 0.73 0.84
0.66 0.73 0.84
0.66 0.73 0.84
0.66 0.73 0.84
0.66 0.73 0.84
0.66 0.73 0.84
0.66 0.73 0.84
0.50 0.56 0.65
0.58 0.66 0.77
0.50 0.56 0.65
0.58 0.66 0.77
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
2.03 2.20 2.45
1.60 1.77 2.01
1.56 1.69 1.88
2.26 2.49 2.83
1.61 1.81 2.10
1.47 1.58 1.76
1.41 1.52 1.69
1.73 1.87 2.07
1.55 1.68 1.87
1.41 1.52 1.67
1.40 1.48 1.59
1.73 1.87 2.07
1.55 1.68 1.87
1.23 1.32 1.46
1.16 1.26 1.40
1.17 1.26 1.39
1.14 1.23 1.36
1.17 1.26 1.39
1.19 1.28 1.43
1.18 1.27 1.40
1.18 1.27 1.40
1.19 1.28 1.43
1.18 1.27 1.40
1.18 1.27 1.40
1.23 1.32 1.46
1.23 1.32 1.46
1.23 1.32 1.46
1.23 1.32 1.46
1.16 1.26 1.40
1.17 1.26 1.39
1.14 1.23 1.36
1.17 1.26 1.39
1.19 1.28 1.43
1.18 1.27 1.40
1.18 1.27 1.40
1.19 1.28 1.43
1.18 1.27 1.40
1.18 1.27 1.40
2.03 2.20 2.45
1.60 1.76 2.01
1.56 1.69 1.88
2.26 2.49 2.83
1.61 1.81 2.10
1.47 1.58 1.76
1.41 1.52 1.69
1.73 1.87 2.07
1.55 1.68 1.87
1.41 1.52 1.67
1.40 1.48 1.59
1.73 1.87 2.07
1.55 1.68 1.87
1.23 1.32 1.46
1.16 1.25 1.40
1.17 1.26 1.39
1.14 1.23 1.36
1.17 1.26 1.39
1.19 1.28 1.43
1.18 1.27 1.40
1.18 1.27 1.40
1.19 1.28 1.43
1.18 1.27 1.40
1.18 1.27 1.40
1.23 1.32 1.46
1.23 1.32 1.46
1.23 1.32 1.46
1.23 1.32 1.46
1.16 1.26 1.40
1.17 1.26 1.39
1.14 1.23 1.36
1.17 1.26 1.39
1.19 1.28 1.43
1.18 1.27 1.40
1.18 1.27 1.40
1.19 1.28 1.43
1.18 1.27 1.40
1.18 1.27 1.40
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LVDCI_15
LVDCI_DV2_18
LVDCI_DV2_15
HSLVDCI_18
HSLVDCI_15
SSTL18_I_S
SSTL18_II_S
SSTL18_I_DCI_S
SSTL18_II_DCI_S
SSTL18_II_T_DCI_S
SSTL15_S
SSTL15_DCI_S
SSTL15_T_DCI_S
SSTL135_S
SSTL135_DCI_S
SSTL135_T_DCI_S
SSTL12_S
SSTL12_DCI_S
SSTL12_T_DCI_S
DIFF_SSTL18_I_S
DIFF_SSTL18_II_S
DIFF_SSTL18_I_DCI_S
DIFF_SSTL18_II_DCI_S
DIFF_SSTL18_II_T_DCI_S
DIFF_SSTL15_S
DIFF_SSTL15_DCI_S
DIFF_SSTL15_T_DCI_S
DIFF_SSTL135_S
DIFF_SSTL135_DCI_S
DIFF_SSTL135_T_DCI_S
DS183 (v1.0) March 1, 2011
www.xilinx.com
Advance Product Specification
20
Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 25: 1.8V IOB High Performance (HP) Switching Characteristics (Cont’d)
TIOPI
TIOOP
TIOTP
I/O Standard
Speed Grade
Speed Grade
Speed Grade
Units
-3
-2
-1
-1L
-3
-2
-1
-1L
-3
-2
-1
-1L
DIFF_SSTL12_S
0.71 0.83 0.96
0.71 0.83 0.96
0.71 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.71 0.83 0.96
0.71 0.83 0.96
0.71 0.83 0.96
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.77 0.85 0.99
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.74 0.83 0.96
0.71 0.83 0.96
0.71 0.83 0.96
0.71 0.83 0.96
1.23 1.32 1.46
1.23 1.32 1.46
1.23 1.32 1.46
1.23 1.32 1.46
1.16 1.26 1.40
1.17 1.26 1.39
1.14 1.23 1.36
1.17 1.26 1.39
1.19 1.28 1.43
1.18 1.27 1.40
1.18 1.27 1.40
1.19 1.28 1.43
1.18 1.27 1.40
1.18 1.27 1.40
1.23 1.32 1.46
1.23 1.32 1.46
1.23 1.32 1.46
1.23 1.32 1.46
1.16 1.26 1.40
1.17 1.26 1.39
1.14 1.23 1.36
1.17 1.26 1.39
1.19 1.28 1.43
1.18 1.27 1.40
1.18 1.27 1.40
1.19 1.28 1.43
1.18 1.27 1.40
1.18 1.27 1.40
1.23 1.32 1.46
1.23 1.32 1.46
1.23 1.32 1.46
1.23 1.32 1.46
1.23 1.32 1.46
1.23 1.32 1.46
1.23 1.32 1.46
1.16 1.26 1.40
1.17 1.26 1.39
1.14 1.23 1.36
1.17 1.26 1.39
1.19 1.28 1.43
1.18 1.27 1.40
1.18 1.27 1.40
1.19 1.28 1.43
1.18 1.27 1.40
1.18 1.27 1.40
1.23 1.32 1.46
1.23 1.32 1.46
1.23 1.32 1.46
1.23 1.32 1.46
1.16 1.25 1.40
1.17 1.26 1.39
1.14 1.23 1.36
1.17 1.26 1.39
1.19 1.28 1.43
1.18 1.27 1.40
1.18 1.27 1.40
1.19 1.28 1.43
1.18 1.27 1.40
1.18 1.27 1.40
1.23 1.32 1.46
1.23 1.32 1.46
1.23 1.32 1.46
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DIFF_SSTL12_DCI_S
DIFF_SSTL12_T_DCI_S
SSTL18_I_F
SSTL18_II_F
SSTL18_I_DCI_F
SSTL18_II_DCI_F
SSTL18_II_T_DCI_F
SSTL15_F
SSTL15_DCI_F
SSTL15_T_DCI_F
SSTL135_F
SSTL135_DCI_F
SSTL135_T_DCI_F
SSTL12_F
SSTL12_DCI_F
SSTL12_T_DCI_F
DIFF_SSTL18_I_F
DIFF_SSTL18_II_F
DIFF_SSTL18_I_DCI_F
DIFF_SSTL18_II_DCI_F
DIFF_SSTL18_II_T_DCI_F
DIFF_SSTL15_F
DIFF_SSTL15_DCI_F
DIFF_SSTL15_T_DCI_F
DIFF_SSTL135_F
DIFF_SSTL135_DCI_F
DIFF_SSTL135_T_DCI_F
DIFF_SSTL12_F
DIFF_SSTL12_DCI_F
DIFF_SSTL12_T_DCI_F
Notes:
1. This I/O standard is only available in the 1.8V high-performance (HP) banks.
Table 26: IOB 3-state ON Output Switching Characteristics (T
)
IOTPHZ
Speed Grade
Symbol
Description
Units
-3
-2
2.17
-1
-1L
TIOTPHZ
T input to Pad high-impedance
2.03
2.38
ns
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 27 shows the test setup parameters used for measuring input delay.
Table 27: Input Delay Measurement Methodology
VMEAS
VREF
(1)(2)
(1)(2)
Description
I/O Standard Attribute
VL
VH
(1)(4)(5)
(1)(3)(5)
LVTTL
LVTTL
0
0
0
0
0
3.3
3.3
1.65
1.65
1.25
0.9
–
–
LVCMOS, 3.3V
LVCMOS, 2.5V
LVCMOS, 1.8V
LVCMOS, 1.5V
LVCMOS33
LVCMOS25
LVCMOS18
LVCMOS15
HSTL_I, HSTL_II
2.5
–
1.8
–
1.5
0.75
VREF
–
HSTL (High-Speed Transceiver Logic),
Class I & II
V
REF – 0.5
VREF + 0.5
0.75
HSTL, Class I & II, 1.8V
HSTL_I_18, HSTL_II_18
SSTL15, SSTL135
V
REF – 0.5
VREF + 0.5
VREF
VREF
0.90
SSTL (Stub Terminated Transceiver Logic),
1.5V and 1.35V
V
REF – 1.00
REF – 0.5
VREF + 1.00
0.75,
0.675
SSTL, Class I & II, 1.8V
SSTL18_I, SSTL18_II
V
VREF + 0.5
1.2 + 0.125
1.2 + 0.125
VREF
0.90
–
(6)
LVDS (Low-Voltage Differential Signaling), HR I/O Banks LVDS_25
LVDS (Low-Voltage Differential Signaling), HP I/O Banks LVDS
1.2 – 0.125
1.2 – 0.125
0
(6)
0
–
Notes:
1. The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay
measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other
DCI standards are the same for the corresponding non-DCI standards.
2. Input waveform switches between V and V .
L
H
3. Measurements are made at typical, minimum, and maximum V
values listed are typical.
values. Reported delays reflect worst case of these measurements. V
REF
REF
4. Input voltage level from which measurement starts.
5. This is an input voltage reference that bears no relation to the V
6. The value given is the differential input voltage.
/ V
parameters found in IBIS models and/or noted in Figure 4.
REF
MEAS
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Output Delay Measurements
X-Ref Target - Figure 5
FPGA Output
Output delays are measured using a Tektronix P6245
TDS500/600 probe (< 1 pF) across approximately 4" of FR4
microstrip trace. Standard termination was used for all
testing. The propagation delay of the 4" trace is
+
CREF
RREF VMEAS
characterized separately and subtracted from the final
measurement, and is therefore not included in the
generalized test setups shown in Figure 4 and Figure 5.
–
ds183_05_021611
X-Ref Target - Figure 4
Figure 5: Differential Test Setup
VREF
Measurements and test conditions are reflected in the IBIS
models except where the IBIS format precludes it.
Parameters V
, R
, C
, and V
fully describe
REF
REF
REF
MEAS
RREF
FPGA Output
the test conditions for each I/O standard. The most accurate
prediction of propagation delay in any given application can
be obtained through IBIS simulation, using the following
method:
VMEAS
(voltage level when taking
delay measurement)
1. Simulate the output driver of choice into the generalized
test setup, using values from Table 28.
CREF
(probe capacitance)
2. Record the time to V
.
MEAS
ds183_04_021611
3. Simulate the output driver of choice into the actual PCB
trace and load, using the appropriate IBIS model or
capacitance value to represent the load.
Figure 4: Single Ended Test Setup
4. Record the time to V
.
MEAS
5. Compare the results of steps 2 and 4. The increase or
decrease in delay yields the actual propagation delay of
the PCB trace.
Table 28: Output Delay Measurement Methodology
(1)
I/O Standard
Attribute
RREF CREF
VMEAS VREF
Description
()
1M
1M
1M
1M
1M
50
(pF)
0
(V)
1.65
1.25
0.9
(V)
LVCMOS, 3.3V
LVCMOS33
0
LVCMOS, 2.5V
LVCMOS25
LVCMOS18
LVCMOS15
LVCMOS12
HSTL_I
0
0
LVCMOS, 1.8V
0
0
LVCMOS, 1.5V
0
0.75
0.75
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
0(2)
0
LVCMOS, 1.2V
0
0
HSTL (High-Speed Transceiver Logic), Class I
HSTL, Class II
0
0.75
0.75
0.9
0.9
0.9
0.9
0.75
0.675
1.2
0
HSTL_II
25
0
HSTL, Class I, 1.8V
HSTL_I_18
HSTL_II_18
SSTL18_I
50
0
HSTL, Class II, 1.8V
25
0
SSTL (Stub Series Terminated Logic), Class I, 1.8V
SSTL, Class II, 1.8V
50
0
SSTL18_II
25
0
SSTL15
SSTL15
50
0
SSTL135
SSTL135
50
0
LVDS (Low-Voltage Differential Signaling), 2.5V
BLVDS (Bus LVDS), 2.5V
LVDCI/HSLVDCI, 1.8V
LVDCI/HSLVDCI, 1.5V
LVDS_25
100
100
1M
1M
0
BLVDS_25
0
0(2)
LVDCI_18, HSLVDCI_18
LVDCI_15, HSLVDCI_15
0
0.9
0
0
0.75
0
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 28: Output Delay Measurement Methodology (Cont’d)
(1)
I/O Standard
Attribute
RREF CREF
VMEAS VREF
Description
()
50
50
50
50
50
(pF)
(V)
(V)
0.75
0.9
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI
HSTL, Class I & II, 1.8V, with DCI HSTL_I_DCI_18, HSTL_II_DCI_18
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI
0
0
0
0
0
VREF
VREF
VREF
VREF
VREF
0.9
SSTL15, with DCI
SSTL135, with DCI
SSTL15_DCI
SSTL135_DCI
0.675
0.75
Notes:
1.
C
is the capacitance of the probe, nominally 0 pF.
REF
2. The value given is the differential output voltage.
Input/Output Logic Switching Characteristics
Table 29: ILOGIC Switching Characteristics
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
Setup/Hold
ICE1CK/TICKCE1
T
CE1 pin Setup/Hold with respect to CLK
SR pin Setup/Hold with respect to CLK
0.31/
0.05
0.36/
0.06
0.44/
0.07
ns
ns
ns
ns
ns
ns
TISRCK/TICKSR
IDOCKE2/TIOCKDE2
1.00/
–0.14
1.15/
–0.14
1.39/
–0.14
T
D pin Setup/Hold with respect to CLK without Delay
(HP I/O banks only)
0.11/
0.38
0.13/
0.42
0.15/
0.49
TIDOCKDE2/TIOCKDDE2 DDLY pin Setup/Hold with respect to CLK (using IDELAY)
(HP I/O banks only)
0.14/
0.29
0.17/
0.32
0.20/
0.37
TIDOCKE3/TIOCKDE3
D pin Setup/Hold with respect to CLK without Delay
(HR I/O banks only)
0.11/
0.38
0.13/
0.42
0.15/
0.49
T
IDOCKDE3/TIOCKDDE3 DDLY pin Setup/Hold with respect to CLK (using IDELAY)
0.14/
0.29
0.17/
0.32
0.20/
0.37
(HR I/O banks only)
Combinatorial
TIDIE2
D pin to O pin propagation delay, no Delay
(HP I/O banks only)
0.19
0.22
0.19
0.22
0.21
0.24
0.21
0.24
0.24
0.28
0.24
0.28
ns
ns
ns
ns
TIDIDE2
TIDIE3
DDLY pin to O pin propagation delay (using IDELAY)
(HP I/O banks only)
D pin to O pin propagation delay, no Delay
(HR I/O banks only)
TIDIDE3
DDLY pin to O pin propagation delay (using IDELAY)
(HR I/O banks only)
Sequential Delays
TIDLOE2
D pin to Q1 pin using flip-flop as a latch without Delay
(HP I/O banks only)
0.48
0.51
0.48
0.51
0.55
0.54
0.57
0.54
0.57
0.61
0.62
0.66
0.62
0.66
0.70
ns
ns
ns
ns
ns
TIDLODE2
TIDLOE3
TIDLODE3
TICKQ
DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY)
(HP I/O banks only)
D pin to Q1 pin using flip-flop as a latch without Delay
(HR I/O banks only)
DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY)
(HR I/O banks only)
CLK to Q outputs
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 29: ILOGIC Switching Characteristics (Cont’d)
Speed Grade
Units
Symbol
Description
-3
-2
-1
-1L
TRQ_ILOGICE2
TGSRQ_ILOGICE2
TRQ_ILOGICE3
TGSRQ_ILOGICE3
Set/Reset
SR pin to OQ/TQ out (HP I/O banks only)
1.12
7.67
1.12
7.67
1.29
7.67
1.29
7.67
1.54
10.61
1.54
10.61
ns
ns
ns
ns
Global Set/Reset to Q outputs (HP I/O banks only)
SR pin to OQ/TQ out (HR I/O banks only)
Global Set/Reset to Q outputs (HR I/O banks only)
TRPW_ILOGICE2
TRPW_ILOGICE3
Minimum Pulse Width, SR inputs (HP I/O banks only)
Minimum Pulse Width, SR inputs (HR I/O banks only)
0.63
0.82
0.66
1.00
0.71
1.26
ns, Min
ns, Min
Table 30: OLOGIC Switching Characteristics
Symbol Description
Speed Grade
Units
-3
-2
-1
-1L
Setup/Hold
ODCK/TOCKD
T
D1/D2 pins Setup/Hold with respect to CLK
OCE pin Setup/Hold with respect to CLK
SR pin Setup/Hold with respect to CLK
T1/T2 pins Setup/Hold with respect to CLK
TCE pin Setup/Hold with respect to CLK
0.55/
–0.22
0.61/
–0.22
0.71/
–0.22
ns
ns
ns
ns
ns
T
OOCECK/TOCKOCE
TOSRCK/TOCKSR
TOTCK/TOCKT
OTCECK/TOCKTCE
0.13/
–0.06
0.15/
–0.06
0.18/
–0.06
0.54/
–0.20
0.64/
–0.20
0.79/
–0.20
0.53/
–0.21
0.59/
–0.21
0.69/
–0.21
T
0.12/
–0.05
0.14/
–0.05
0.17/
–0.05
Combinatorial
TODQ
D1 to OQ out or T1 to TQ out
0.78
0.88
1.03
ns
Sequential Delays
TOCKQ
CLK to OQ/TQ out
0.31
0.56
7.67
0.56
7.67
0.35
0.64
7.67
0.64
7.67
0.41
0.76
ns
ns
ns
ns
ns
TRQ_OLOGICE2
TGSRQ_OLOGICE2
TRQ_OLOGICE3
TGSRQ_OLOGICE3
Set/Reset
SR pin to OQ/TQ out (HP I/O banks only)
Global Set/Reset to Q outputs (HP I/O banks only)
SR pin to OQ/TQ out (HR I/O banks only)
Global Set/Reset to Q outputs (HR I/O banks only)
10.61
0.76
10.61
TRPW_OLOGICE2
TRPW_OLOGICE3
Minimum Pulse Width, SR inputs (HP I/O banks only)
Minimum Pulse Width, SR inputs (HR I/O banks only)
0.63
0.82
0.66
1.00
0.71
1.26
ns, Min
ns, Min
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 31: ISERDES Switching Characteristics
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
Setup/Hold for Control Lines
TISCCK_BITSLIP/ TISCKC_BITSLIP BITSLIP pin Setup/Hold with respect to CLKDIV
0.13/
0.11
0.15/
0.12
0.18/
0.15
ns
ns
ns
(2)
TISCCK_CE / TISCKC_CE
CE pin Setup/Hold with respect to CLK (for CE1)
0.22/
–0.04
0.26/
–0.04
0.32/
–0.04
(2)
T
ISCCK_CE2 / TISCKC_CE2
CE pin Setup/Hold with respect to CLKDIV (for
CE2)
0.06/
0.14
0.06/
0.15
0.07/
0.18
Setup/Hold for Data Lines
TISDCK_D /TISCKD_D
D pin Setup/Hold with respect to CLK
0.02/
0.12
0.03/
0.14
0.03/
0.17
ns
ns
ns
ns
TISDCK_DDLY /TISCKD_DDLY
DDLY pin Setup/Hold with respect to CLK (using
IDELAY)(1)
0.05/
0.09
0.06/
0.10
0.08/
0.12
TISDCK_D_DDR /TISCKD_D_DDR
D pin Setup/Hold with respect to CLK at DDR
mode
0.02/
0.12
0.03/
0.14
0.03/
0.17
TISDCK_DDLY_DDR
/
D pin Setup/Hold with respect to CLK at DDR
mode (using IDELAY)(1)
0.05/
0.09
0.06/
0.10
0.08/
0.12
TISCKD_DDLY_DDR
Sequential Delays
TISCKO_Q
CLKDIV to out at Q pin
D input to DO output pin
0.59
0.22
0.66
0.24
0.76
0.28
ns
ns
Propagation Delays
TISDO_DO
Notes:
1. Recorded at 0 tap value.
2.
T
and T
are reported as T
/T
in TRACE report.
ISCCK_CE2
ISCKC_CE2
ISCCK_CE ISCKC_CE
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Output Serializer/Deserializer Switching Characteristics
Table 32: OSERDES Switching Characteristics
Speed Grade
Symbol Description
Units
-3
-2
-1
-1L
Setup/Hold
TOSDCK_D/TOSCKD_D
D input Setup/Hold with respect to CLKDIV
T input Setup/Hold with respect to CLK
T input Setup/Hold with respect to CLKDIV
OCE input Setup/Hold with respect to CLK
0.48/
–0.21
0.54/
–0.21
0.63/
–0.21
ns
ns
ns
ns
(1)
TOSDCK_T/TOSCKD_T
0.53/
–0.22
0.59/
–0.22
0.69/
–0.22
(1)
TOSDCK_T2/TOSCKD_T2
0.48/
–0.22
0.56/
–0.22
0.68/
–0.22
TOSCCK_OCE/TOSCKC_OCE
0.13/
–0.06
0.15/
–0.06
0.18/
–0.06
TOSCCK_S
OSCCK_TCE/TOSCKC_TCE
SR (Reset) input Setup with respect to CLKDIV
TCE input Setup/Hold with respect to CLK
0.72
0.82
0.98
ns
ns
T
0.12/
–0.05
0.14/
–0.05
0.17/
–0.05
Sequential Delays
TOSCKO_OQ
Clock to out from CLK to OQ
Clock to out from CLK to TQ
0.28
0.28
0.32
0.32
0.37
0.37
ns
ns
TOSCKO_TQ
Combinatorial
TOSDO_TTQ
T input to TQ Out
0.78
0.88
1.03
ns
Notes:
1.
T
and T
are reported as T
/T
in TRACE report.
OSDCK_T2
OSCKD_T2
OSDCK_T OSCKD_T
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Input/Output Delay Switching Characteristics
Table 33: Input/Output Delay Switching Characteristics
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
IDELAYCTRL
TDLYCCO_RDY
Reset to Ready for IDELAYCTRL
Attribute REFCLK frequency = 200.0(1)
Attribute REFCLK frequency = 300.0(1)
REFCLK precision
3.25
200
300
10
3.25
200
300
10
3.25
200
N/A
10
µs
FIDELAYCTRL_REF
MHz
MHz
MHz
ns
IDELAYCTRL_REF_PRECISION
TIDELAYCTRL_RPW
Minimum Reset pulse width
52.5
52.5
52.5
IDELAY/ODELAY
TIDELAYRESOLUTION
IDELAY/ODELAY chain delay resolution
1/(32 x 2 x FREF
)
ps
Pattern dependent period jitter in delay
chain for clock pattern.
0
5
0
0
ps
per tap
TIDELAYPAT_JIT_CLOCK
TIDELAYPAT_JIT_DATA
(HP I/O banks only)(2)
Pattern dependent period jitter in delay
chain for random data pattern
(PRBS 23)
5
5
ps
per tap
(HP I/O banks only)(2)
TIDELAYPAT_JIT_CLOCK
Pattern dependent period jitter in delay
chain for clock pattern.
0
9
0
0
ps
per tap
(HR I/O banks only)(2)
TIDELAYPAT_JIT_DATA
Pattern dependent period jitter in delay
chain for random data pattern
(PRBS 23)
9
9
ps
per tap
(HR I/O banks only)(2)
TIDELAY_CLK_MAX
/
Maximum frequency of CLK input to
IDELAY/ODELAY
920
920
816.5
MHz
ns
TODELAY_CLK_MAX
TIDCCK_CE / TIDCKC_CE
CE pin Setup/Hold with respect to C for
IDELAY
–0.02/
0.21
–0.02/
0.24
–0.02/
0.30
T
ODCCK_CE / TODCKC_CE
TIDCCK_INC/ TIDCKC_INC
TODCCK_INC/ TODCKC_INC
IDCCK_RST/ TIDCKC_RST
CE pin Setup/Hold with respect to C for
ODELAY
–0.02/
0.21
–0.02/
0.25
–0.02/
0.30
ns
INC pin Setup/Hold with respect to C for
IDELAY
0.10/
0.24
0.11/
0.28
0.12/
0.34
ns
INC pin Setup/Hold with respect to C for
ODELAY
0.11/
0.24
0.11/
0.28
0.12/
0.34
ns
T
RST pin Setup/Hold with respect to C for
IDELAY
0.10/
0.26
0.12/
0.31
0.14/
0.38
ns
TODCCK_RST/ TODCKC_RST
RST pin Setup/Hold with respect to C for
ODELAY
0.10/
0.27
0.12/
0.32
0.15/
0.38
ns
TIDDO_IDATAIN
Propagation delay through IDELAY
Propagation delay through ODELAY
Note 2
Note 2
Note 2
Note 2
Note 2
Note 2
ps
ps
TODDO_ODATAIN
Notes:
1. Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps.
2. Delay depends on IDELAY/ODELAY tap setting. See TRACE report for actual values.
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
CLB Switching Characteristics
Table 34: CLB Switching Characteristics
Speed Grade
Units
Symbol
Description
-3
-2
-1
-1L
Combinatorial Delays
TILO
An – Dn LUT address to A
An – Dn LUT address to AMUX/CMUX
An – Dn LUT address to BMUX_A
An – Dn inputs to A – D Q outputs
AX inputs to AMUX output
AX inputs to BMUX output
AX inputs to CMUX output
AX inputs to DMUX output
BX inputs to BMUX output
BX inputs to DMUX output
CX inputs to CMUX output
CX inputs to DMUX output
DX inputs to DMUX output
An input to COUT output
Bn input to COUT output
Cn input to COUT output
Dn input to COUT output
AX input to COUT output
BX input to COUT output
CX input to COUT output
DX input to COUT output
CIN input to COUT output
CIN input to AMUX output
CIN input to BMUX output
CIN input to CMUX output
CIN input to DMUX output
0.05
0.17
0.25
0.57
0.32
0.35
0.35
0.40
0.29
0.37
0.24
0.32
0.30
0.31
0.31
0.24
0.22
0.26
0.22
0.17
0.16
0.06
0.22
0.23
0.22
0.24
0.06
0.19
0.28
0.65
0.37
0.40
0.40
0.45
0.33
0.41
0.26
0.35
0.34
0.35
0.35
0.27
0.26
0.29
0.25
0.19
0.18
0.06
0.25
0.26
0.24
0.27
0.07
0.23
0.35
0.80
0.46
0.50
0.50
0.54
0.41
0.49
0.31
0.42
0.41
0.43
0.44
0.33
0.32
0.34
0.30
0.22
0.22
0.07
0.30
0.32
0.29
0.33
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
TILO_2
TILO_3
TITO
TAXA
TAXB
TAXC
TAXD
TBXB
TBXD
TCXC
TCXD
TDXD
TOPCYA
TOPCYB
TOPCYC
TOPCYD
TAXCY
TBXCY
TCXCY
TDXCY
TBYP
TCINA
TCINB
TCINC
TCIND
Sequential Delays
TCKO
Clock to AQ – DQ outputs
0.27
0.31
0.30
0.35
0.36
0.42
ns, Max
ns, Max
TSHCKO
Clock to AMUX – DMUX outputs
Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK
T
DICK/TCKDI
A – D input to CLK on A – D Flip Flops
CE input to CLK on A – D Flip Flops
SR input to CLK on A – D Flip Flops
CIN input to CLK on A – D Flip Flops
0.35/
0.14
0.40/
0.15
0.51/
0.19
ns, Min
ns, Min
ns, Min
ns, Min
TCECK_CLB
TCKCE_CLB
/
0.12/
0.00
0.14/
0.00
0.16/
0.00
TSRCK/TCKSR
TCINCK/TCKCIN
0.32/
0.02
0.37/
0.02
0.44/
0.03
0.15/
0.14
0.18/
0.15
0.24/
0.19
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 34: CLB Switching Characteristics (Cont’d)
Speed Grade
Units
Symbol
Description
-3
-2
-1
-1L
Set/Reset
TSRMIN
TRQ
SR input minimum pulse width
0.50
0.40
0.37
1412
0.75
0.45
0.41
1286
1.00
0.53
0.50
1098
ns, Min
ns, Max
ns, Max
MHz
Delay from SR input to AQ – DQ flip-flops
Delay from CE input to AQ – DQ flip-flops
Toggle frequency (for export control)
TCEO
FTOG
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2. These items are of interest for Carry Chain applications.
CLB Distributed RAM Switching Characteristics (SLICEM Only)
Table 35: CLB Distributed RAM Switching Characteristics
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
Sequential Delays
TSHCKO
Clock to A – B outputs
Clock to AMUX – BMUX outputs
0.72
0.97
0.81
1.09
0.99
1.33
ns, Max
ns, Max
TSHCKO_1
Setup and Hold Times Before/After Clock CLK
DS_LRAM/TDH_LRAM A – D inputs to CLK
T
0.47/
0.24
0.52/
0.26
0.62/
0.30
ns, Min
ns, Min
ns, Min
ns, Min
TAS_LRAM/TAH_LRAM
Address An inputs to clock
0.15/
0.51
0.17/
0.55
0.22/
0.62
TWS_LRAM/TWH_LRAM WE input to clock
0.32/
0.08
0.36/
0.08
0.45/
0.09
TCECK_LRAM
/
CE input to CLK
0.33/
0.08
0.37/
0.08
0.46/
0.09
TCKCE_LRAM
Clock CLK
TMPW_LRAM
TMCP
Minimum pulse width
Minimum clock period
0.73
1.46
0.86
1.71
1.09
2.18
ns, Min
ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
2.
T
also represents the CLK to XMUX output. Refer to TRACE report for the CLK to XMUX path.
SHCKO
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 36: CLB Shift Register Switching Characteristics
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
Sequential Delays
TREG
Clock to A – D outputs
0.92
1.18
0.82
1.03
1.32
0.92
1.26
1.61
1.13
ns, Max
ns, Max
ns, Max
TREG_MUX
TREG_M31
Clock to AMUX – DMUX output
Clock to DMUX output via M31 output
Setup and Hold Times Before/After Clock CLK
TWS_SHFREG
/
WE input
0.29/
0.08
0.33/
0.08
0.41/
0.09
ns, Min
ns, Min
ns, Min
TWH_SHFREG
TCECK_SHFREG
TCKCE_SHFREG
/
CE input to CLK
A – D inputs to CLK
0.30/
0.08
0.34/
0.08
0.42/
0.09
TDS_SHFREG
/
0.29/
0.28
0.32/
0.30
0.39/
0.35
TDH_SHFREG
Clock CLK
TMPW_SHFREG
Minimum pulse width
0.63
0.73
0.93
ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
Block RAM and FIFO Switching Characteristics
Table 37: Block RAM and FIFO Switching Characteristics
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
Block RAM and FIFO Clock-to-Out Delays
T
RCKO_DO and
Clock CLK to DOUT output (without output
register)(2)(3)
1.83
0.56
2.38
0.58
2.18
1.01
2.03
0.62
2.74
0.65
2.46
1.12
2.34
0.71
3.27
0.76
2.88
1.29
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
ns, Max
(1)
TRCKO_DO_REG
Clock CLK to DOUT output (with output
register)(4)(5)
TRCKO_DO_ECC and
TRCKO_DO_ECC_REG
Clock CLK to DOUT output with ECC
(without output register)(2)(3)
Clock CLK to DOUT output with ECC (with
output register)(4)(5)
T
RCKO_DO_CASCOUT and
Clock CLK to DOUT output with Cascade
(without output register)(2)
TRCKO_DO_CASCOUT_REG
Clock CLK to DOUT output with Cascade
(with output register)(4)
TRCKO_FLAGS
Clock CLK to FIFO flags outputs(6)
Clock CLK to FIFO pointers outputs(7)
0.69
0.79
0.66
0.75
0.86
0.72
0.84
0.97
0.81
ns, Max
ns, Max
ns, Max
TRCKO_POINTERS
TRCKO_PARITY_ECC
Clock CLK to ECCPARITY in ECC encode
only mode
TRCKO_SDBIT_ECC and
TRCKO_SDBIT_ECC_REG
Clock CLK to BITERR (without output
register)
2.20
0.54
2.53
0.60
3.03
0.70
ns, Max
ns, Max
Clock CLK to BITERR (with output
register)
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 37: Block RAM and FIFO Switching Characteristics (Cont’d)
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
TRCKO_RDADDR_ECC and
TRCKO_RDADDR_ECC_REG
Clock CLK to RDADDR output with ECC
(without output register)
0.64
0.70
0.80
ns, Max
Clock CLK to RDADDR output with ECC
(with output register)
0.69
0.77
0.88
ns, Max
Setup and Hold Times Before/After Clock CLK
T
RCCK_ADDRA/TRCKC_ADDRA
ADDR inputs(8)
0.37/
0.21
0.40/
0.23
0.45/
0.25
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
T
RDCK_DI/TRCKD_DI
DIN inputs(9)
0.87/
0.22
0.99/
0.23
1.18/
0.24
TRDCK_DI_ECC/TRCKD_DI_ECC
DIN inputs with block RAM ECC in
standard mode(9)
0.35/
0.22
0.41/
0.23
0.52/
0.24
DIN inputs with block RAM ECC encode
only(9)
0.76/
0.22
0.88/
0.23
1.05/
0.24
DIN inputs with FIFO ECC in standard
mode(9)
0.87/
0.22
0.99/
0.23
1.18/
0.24
TRCCK_CLK/TRCKC_CLK
Inject single/double bit error in ECC mode
Block RAM Enable (EN) input
CE input of output register
0.51/
0.17
0.58/
0.18
0.68/
0.18
TRCCK_RDEN/TRCKC_RDEN
0.36/
0.18
0.39/
0.19
0.44/
0.21
T
RCCK_REGCE/TRCKC_REGCE
TRCCK_RSTREG/TRCKC_RSTREG
TRCCK_RSTRAM/TRCKC_RSTRAM
RCCK_WEA/TRCKC_WEA
TRCCK_WREN/TRCKC_WREN
TRCCK_RDEN/TRCKC_RDEN
0.32/
0.05
0.34/
0.06
0.39/
0.06
Synchronous RSTREG input(10)
Synchronous RSTRAM input
Write Enable (WE) input (Block RAM only)
WREN FIFO inputs
0.37/
0.04
0.40/
0.04
0.45/
0.04
0.24/
0.14
0.25/
0.15
0.27/
0.16
T
0.39/
0.15
0.43/
0.16
0.49/
0.17
0.46/
0.18
0.51/
0.19
0.59/
0.21
RDEN FIFO inputs
0.42/
0.18
0.49/
0.19
0.59/
0.21
Reset Delays (Flags)
TRCO_RST
Reset RST to FIFO Flags/Pointers(11)
0.76
601
0.83
544
0.94
458
ns, Max
MHz
Maximum Frequency
FMAX_BRAM_WF_NC
Block RAM
(Write first and No change modes)
When not in SDP RF mode
FMAX_BRAM_RF_PERFORMANCE
Block RAM
(Read first, Performance mode)
When in SDP RF mode but no address
overlap between port A and port B
601
541
544
485
458
401
MHz
MHz
FMAX_BRAM_RF_DELAYED_WRITE
Block RAM
(Read first, Delayed_write mode)
When in SDP RF mode and there is
possibility of overlap between port A and
port B addresses
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 37: Block RAM and FIFO Switching Characteristics (Cont’d)
Symbol Description
FMAX_CAS_WF_NC Block RAM Cascade
Speed Grade
Units
-3
-2
-1
-1L
529
475
392
MHz
(Write first, No change mode)
When cascade but not in RF mode
FMAX_CAS_RF_PERFORMANCE
Block RAM Cascade
(Read first, Performance mode)
When in cascade with RF mode and no
possibility of address overlap/one port is
disabled
529
492
475
437
392
353
MHz
MHz
FMAX_CAS_RF_DELAYED_WRITE
When in cascade RF mode and there is a
possibility of address overlap between port
A and port B
FMAX_FIFO
FMAX_ECC
FIFO in all modes without ECC
601
495
544
427
458
326
MHz
MHz
Block RAM and FIFO in ECC configuration
Notes:
1. TRACE will report all of these parameters as T
.
RCKO_DO
2.
3. These parameters also apply to synchronous FIFO with DO_REG = 0.
4. includes T as well as the B port equivalent timing parameters.
5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.
T
includes T
, T
, and T
as well as the B port equivalent timing parameters.
RCKO_DOR
RCKO_DOW RCKO_DOPR
RCKO_DOPW
T
RCKO_DO
RCKO_DOP
6.
7.
T
T
includes the following parameters: T
, T , T , T , T , T
RCKO_FLAGS
RCKO_AEMPTY RCKO_AFULL RCKO_EMPTY RCKO_FULL RCKO_RDERR RCKO_WRERR.
includes both T
and T
RCKO_POINTERS
RCKO_RDCOUNT
RCKO_WRCOUNT.
8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is
possible.
9.
T
includes both A and B inputs as well as the parity inputs of A and B.
RCKO_DI
10. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the
slowest clock (WRCLK or RDCLK).
11. T
includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.
RCO_FLAGS
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
DSP48E1 Switching Characteristics
Table 38: DSP48E1 Switching Characteristics
Speed
Symbol
Description
Units
-3
-2
-1
-1L
Setup and Hold Times of Data/Control Pins to the Input Register Clock
A input to A register CLK
B input to B register CLK
C input to C register CLK
D input to D register CLK
ACIN input to A register CLK
BCIN input to B register CLK
0.31/
0.10
0.37/
0.11
0.51/
0.16
ns
ns
ns
ns
ns
ns
T
T
T
T
T
T
/ T
DSPDCK_A_AREG DSPCKD_A_AREG
0.36/
0.11
0.42/
0.12
0.57/
0.17
/T
DSPDCK_B_BREG DSPCKD_B_BREG
0.24/
0.15
0.28/
0.16
0.40/
0.22
/T
DSPDCK_C_CREG DSPCKD_C_CREG
0.29/
0.14
0.35/
0.15
0.50/
0.20
/T
DSPDCK_D_DREG DSPCKD_D_DREG
0.28/
0.10
0.34/
0.11
0.47/
0.16
/T
DSPDCK_ACIN_AREG DSPCKD_ACIN_AREG
0.30/
0.11
0.35/
0.12
0.48/
0.17
/T
DSPDCK_BCIN_BREG DSPCKD_BCIN_BREG
Setup and Hold Times of Data Pins to the Pipeline Register Clock
TDSPDCK_ A, B _MREG_MULT
/
{A, B,} input to M register CLK using
multiplier
2.43/
2.81/
3.61/
ns
ns
{
}
TDSPCKD_B_MREG_MULT
–0.03 –0.03 –0.01
TDSPDCK_ A, B _ADREG/ TDSPCKD_ D_ADREG
{A, D} input to AD register CLK
1.28/ 1.46/ 1.85/
–0.04 –0.04 –0.03
{
}
Setup and Hold Times of Data/Control Pins to the Output Register Clock
{A, B,} input to P register CLK using
multiplier
3.97/
4.57/
5.78/
ns
ns
ns
ns
ns
T
T
/
A, B
A, B
DSPDCK_{
DSPCKD_{
}_PREG_MULT
} _PREG_MULT
–0.16 –0.16 –0.16
D input to P register CLK using
multiplier
3.87/ 4.48/ 5.69/
–0.56 –0.56 –0.56
T
T
/
DSPDCK_D_PREG_MULT
DSPCKD_D_PREG_MULT
B input to P register CLK not using
multiplier
1.70/ 1.94/ 2.45/
T
T
/
DSPDCK_B_PREG
DSPCKD_B_PREG
–0.16 –0.16 –0.16
1.50/ 1.72/ 2.18/
C input to P register CLK not using
multiplier
T
T
/
DSPDCK_C_PREG
DSPCKD_C_PREG
–0.13 –0.13 –0.13
TDSPDCK_PCIN_PREG
TDSPCKD_PCIN_PREG
/
PCIN input to P register CLK
1.30/ 1.48/ 1.87/
–0.04 –0.04 –0.03
Setup and Hold Times of the CE Pins
{CEA; CEB} input to {A; B} register CLK 0.38/
0.08
0.46/
0.09
0.62/
0.13
ns
ns
ns
ns
ns
T
T
/
DSPDCK_{CEA;CEB}_{AREG;BREG}
DSPCKD_{CEA;CEB}_{AREG;BREG}
CEC input to C register CLK
CED input to D register CLK
CEM input to M register CLK
CEP input to P register CLK
0.31/
0.09
0.38/
0.10
0.51/
0.14
T
T
T
T
/ T
DSPDCK_CEC_CREG DSPCKD_CEC_CREG
0.40/
0.47/
0.63/
/ T
DSPDCK_CED_DREG DSPCKD_CED_DREG
–0.03 –0.03 –0.02
0.31/
0.06
0.37/
0.07
0.51/
0.10
/ T
DSPDCK_CEM_MREG DSPCKD_CEM_MREG
0.36/
0.02
0.43/
0.02
0.58/
0.05
/ T
DSPDCK_CEP_PREG DSPCKD_CEP_PREG
Setup and Hold Times of the RST Pins
{RSTA, RSTB} input to {A, B} register
CLK
0.42/
0.11
0.49/
0.12
0.63/
0.16
ns
ns
T
T
/
DSPDCK_{RSTA; RSTB}_{AREG; BREG}
DSPCKD_{RSTA; RSTB}_{AREG; BREG}
RSTC input to C register CLK
0.10/
0.08
0.12/
0.09
0.17/
0.13
T
/ T
DSPDCK_RSTC_CREG DSPCKD_RSTC_CREG
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 38: DSP48E1 Switching Characteristics (Cont’d)
Speed
Symbol
Description
Units
-3
-2
-1
-1L
RSTD input to D register CLK
RSTM input to M register CLK
RSTP input to P register CLK
0.47/
0.07
0.55/
0.08
0.71/
0.12
ns
T
T
T
/ T
DSPDCK_RSTD_DREG DSPCKD_RSTD_DREG
0.37/
0.08
0.43/
0.09
0.55/
0.12
ns
ns
/ T
DSPDCK_RSTM_MREG DSPCKD_RSTM_MREG
0.26/
0.02
0.30/
0.03
0.39/
0.05
/ T
DSPDCK_RSTP_PREG DSPCKD_RSTP_PREG
Combinatorial Delays from Input Pins to Output Pins
TDSPDO_A_CARRYOUT_MULT
A input to CARRYOUT output using
multiplier
3.75
4.32
5.46
ns
TDSPDO_D_P_MULT
TDSPDO_B_P
D input to P output using multiplier
B input to P output not using multiplier
C input to P output
3.67
1.50
1.30
4.25
1.72
1.50
5.40
2.16
1.89
ns
ns
ns
TDSPDO_C_P
Combinatorial Delays from Input Pins to Cascading Output Pins
TDSPDO_{A; B}_{ACOUT; BCOUT}
{A, B} input to {ACOUT, BCOUT} output 0.54
0.62
4.60
0.79
5.81
ns
ns
TDSPDO_{A, B}_CARRYCASCOUT_MULT
{A, B} input to CARRYCASCOUT
output using multiplier
3.99
3.90
1.72
1.52
TDSPDO_D_CARRYCASCOUT_MULT
TDSPDO_{A, B}_CARRYCASCOUT
TDSPDO_C_CARRYCASCOUT
D input to CARRYCASCOUT output
using multiplier
4.51
1.98
1.75
5.72
2.48
2.21
ns
ns
ns
{A, B} input to CARRYCASCOUT
output not using multiplier
C input to CARRYCASCOUT output
Combinatorial Delays from Cascading Input Pins to All Output Pins
TDSPDO_ACIN_P_MULT ACIN input to P output using multiplier
TDSPDO_ACIN_P
3.58
1.31
4.13
1.51
5.23
1.91
ns
ns
ACIN input to P output not using
multiplier
TDSPDO_ACIN_ACOUT
ACIN input to ACOUT output
0.35
3.81
0.41
4.39
0.53
5.55
ns
ns
TDSPDO_ACIN_CARRYCASCOUT_MULT
ACIN input to CARRYCASCOUT output
using multiplier
TDSPDO_ACIN_CARRYCASCOUT
ACIN input to CARRYCASCOUT output
not using multiplier
1.54
1.10
1.77
2.23
ns
TDSPDO_PCIN_P
PCIN input to P output
1.26
1.51
1.57
1.90
ns
ns
TDSPDO_PCIN_CARRYCASCOUT
PCIN input to CARRYCASCOUT output 1.32
Clock to Outs from Output Register Clock to Output Pins
TDSPCKO_P_PREG
CLK (PREG) to P output
0.29
0.48
0.33
0.54
0.42
0.68
ns
ns
TDSPCKO_CARRYCASCOUT_PREG
CLK (PREG) to CARRYCASCOUT
output
Clock to Outs from Pipeline Register Clock to Output Pins
TDSPCKO_P_MREG
CLK (MREG) to P output
1.58
1.80
1.82
2.07
2.30
2.62
ns
ns
TDSPCKO_CARRYCASCOUT_MREG
CLK (MREG) to CARRYCASCOUT
output
TDSPCKO_P_ADREG_MULT
CLK (ADREG) to P output using
multiplier
2.68
2.91
3.09
3.35
3.91
4.23
ns
ns
TDSPCKO_CARRYCASCOUT_ADREG_MULT
CLK (ADREG) to CARRYCASCOUT
output using multiplier
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 38: DSP48E1 Switching Characteristics (Cont’d)
Symbol
Speed
Description
Units
-3
-2
-1
-1L
Clock to Outs from Input Register Clock to Output Pins
TDSPCKO_P_AREG_MULT
TDSPCKO_P_BREG
CLK (AREG) to P output using multiplier 3.87
4.46
1.81
5.63
2.26
ns
ns
CLK (BREG) to P output not using
multiplier
1.58
1.62
3.84
TDSPCKO_P_CREG
CLK (CREG) to P output not using
multiplier
1.85
4.45
2.32
5.64
ns
ns
TDSPCKO_P_DREG_MULT
CLK (DREG) to P output using
multiplier
Clock to Outs from Input Register Clock to Cascading Output Pins
TDSPCKO_{ACOUT; BCOUT}_{AREG; BREG}
CLK (ACOUT, BCOUT) to {A,B} register
output
0.61
4.10
0.70
4.72
0.89
5.95
ns
ns
TDSPCKO_CARRYCASCOUT_{AREG, BREG}_MULT
CLK (AREG, BREG) to
CARRYCASCOUT output using
multiplier
TDSPCKO_CARRYCASCOUT_ BREG
TDSPCKO_CARRYCASCOUT_ DREG_MULT
TDSPCKO_CARRYCASCOUT_ CREG
CLK (BREG) to CARRYCASCOUT
output not using multiplier
1.80
4.07
1.84
2.06
4.70
2.11
2.59
5.97
2.64
ns
ns
ns
CLK (DREG) to CARRYCASCOUT
output using multiplier
CLK (CREG) to CARRYCASCOUT
output
Maximum Frequency
FMAX
With all registers used
617
533
350
321
533
461
304
279
419
363
241
221
MHz
MHz
MHz
MHz
FMAX_PATDET
With pattern detector
FMAX_MULT_NOMREG
FMAX_MULT_NOMREG_PATDET
Two register multiply without MREG
Two register multiply without MREG
with pattern detect
FMAX_PREADD_MULT_NOADREG
FMAX_PREADD_MULT_NOADREG_PATDET
FMAX_NOPIPELINEREG
Without ADREG
399
399
263
345
345
228
272
272
181
MHz
MHz
MHz
Without ADREG with pattern detect
Without pipeline registers (MREG,
ADREG)
FMAX_NOPIPELINEREG_PATDET
Without pipeline registers (MREG,
ADREG) with pattern detect
246
214
169
MHz
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Configuration Switching Characteristics
Table 39: Configuration Switching Characteristics
Speed Grade
Units
Symbol
Description
-3
-2
-1
-1L
Power-up Timing Characteristics
(1)
TPL
Program Latency
Power-on-Reset
ms, Max
ms, Max
ns, Min
ns, Min
(1)
TPOR
50
TICCK
CCLK (output) delay
Program Pulse Width
TPROGRAM
250
Master/Slave Serial Mode Programming Switching
TDCCK/TCCKD
TDSCCK/TSCCKD
TCCO
DIN Setup/Hold, slave mode
DIN Setup/Hold, master mode
DOUT at 3.3V
5.0/0.0
5.0/0.0
ns, Min
ns, Min
ns, Max
ns, Max
ns, Max
DOUT at 2.5V
DOUT at 1.8V
FMCCK
Maximum Frequency, master mode with respect to
nominal CCLK.
100
55
MHz,
Max
FMCCKTOL
Frequency Tolerance, master mode with respect to
nominal CCLK.
%
FMSCCK
Slave mode external CCLK
100
MHz
SelectMAP Mode Programming Switching
TSMDCCK/TSMCCKD SelectMAP Data Setup/Hold
SMCSCCK/TSMCCKCS CSI_B Setup/Hold
5.0/0.0
ns, Min
ns, Min
ns, Min
ns, Max
T
TSMCCKW/TSMWCCK
TSMCKCSO
RDWR_B Setup/Hold
CSO_B clock to out
(330 pull-up resistor required)
TSMCO
CCLK to DATA out in readback at 3.3V
CCLK to DATA out in readback at 2.5V
CCLK to DATA out in readback at 1.8V
Maximum Frequency with respect to nominal CCLK.
ns, Max
ns, Max
ns, Max
FSMCCK
FRBCCK
100
70
MHz, Max
MHz, Max
Maximum Readback Frequency with respect to
nominal CCLK
FMCCKTOL
Frequency Tolerance with respect to nominal CCLK.
55
%
Boundary-Scan Port Timing Specifications
TMS and TDI Setup time before TCK/ Hold time after
TTAPTCK/TTCKTAP
ns, Min
TCK
TTCKTDO
TCK falling edge to TDO output valid at 3.3V
TCK falling edge to TDO output valid at 2.5V
TCK falling edge to TDO output valid at 1.8V
Maximum configuration TCK clock frequency
Maximum boundary-scan TCK clock frequency
ns, Max
ns, Max
ns, Max
FTCK
20
20
MHz, Max
MHz, Max
FTCKB
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 39: Configuration Switching Characteristics (Cont’d)
Symbol Description
Speed Grade
Units
-3
-2
-1
-1L
BPI Master Flash Mode Programming Switching
(2)
TBPICCO
A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B, ADV_B
outputs valid after CCLK rising edge at 3.3V
ns
ns
ns
ns
A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B, ADV_B
outputs valid after CCLK rising edge at 2.5V
A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B, ADV_B
outputs valid after CCLK rising edge at 1.8V
TBPIDCC/TBPICCD
Setup/Hold on D[15:00] data input pins
5.0/0.0
5.0/0.0
SPI Master Flash Mode Programming Switching
TSPIDCC/TSPIDCCD DIN Setup/Hold before/after the rising CCLK edge
TSPICCM
ns
ns
ns
ns
ns
ns
ns
MOSI clock to out at 3.3V
MOSI clock to out at 2.5V
MOSI clock to out at 1.8V
FCS_B clock to out at 3.3V
FCS_B clock to out at 2.5V
FCS_B clock to out at 1.8V
TSPICCFC
CCLK Output (Master Modes)
FMCCK_START Master CCLK frequency at start of configuration
TMCCKL
2
MHz, Typ
%, Min/Max
%, Min/Max
Master CCLK clock Low time duty cycle
Master CCLK clock High time duty cycle
TMCCKH
CCLK Input (Slave Modes)
TSCCKL Slave CCLK clock minimum Low time
TSCCKH Slave CCLK clock minimum High time
Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK
ns, Min
ns, Min
FDCK
Maximum frequency for DCLK
DADDR Setup/Hold
200
200
200
MHz
ns
TMMCMDCK_DADDR
TMMCMCKD_DADDR
/
1.25/
0.00
1.40/
0.00
1.63/
0.00
TMMCMDCK_DI
TMMCMCKD_DI
/
DI Setup/Hold
1.25/
0.00
1.40/
0.00
1.63/
0.00
ns
ns
ns
TMMCMDCK_DEN
TMMCMCKD_DEN
/
DEN Setup/Hold time
DWE Setup/Hold time
1.76/
0.00
1.97/
0.00
2.29/
0.00
TMMCMDCK_DWE
TMMCMCKD_DWE
/
1.25/
0.00
1.40/
0.00
1.63/
0.00
TMMCMCKO_DO
CLK to out of DO(3)
CLK to out of DRDY
3.10
0.43
3.61
0.49
4.37
0.58
ns
ns
TMMCMCKO_DRDY
Notes:
1. To support longer delays in configuration, use the design solutions described in 7 Series FPGA Configuration User Guide.
2. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
3. DO will hold until next DRP operation.
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Clock Buffers and Networks
Table 40: Global Clock Switching Characteristics (Including BUFGCTRL)
Speed Grade
Symbol
TBCCCK_CE/TBCCKC_CE
(1)
Description
CE pins Setup/Hold
Units
-3
-2
-1
-1L
(1)
0.10/
0.04
0.12/
0.05
0.15/
0.05
ns
T
BCCCK_S/TBCCKC_S
S pins Setup/Hold
0.10/
0.04
0.12/
0.05
0.15/
0.05
ns
ns
(2)
TBCCKO_O
BUFGCTRL delay from I0/I1 to O
0.08
0.09
0.11
Maximum Frequency0.08
FMAX_BUFG
Global clock tree (BUFG)
710
710
625
MHz
Notes:
1.
T
and T
must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
BCCCK_CE
BCCKC_CE
parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are
optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
2.
T
(BUFG delay from I0 to O) values are the same as T
values.
BCCKO_O
BGCKO_O
Table 41: Input/Output Clock Switching Characteristics (BUFIO)
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
TBIOCKO_O
Clock to out delay from I to O
1.14
1.29
1.52
ns
Maximum Frequency
FMAX_BUFIO
I/O clock tree (BUFIO)
800
800
710
MHz
Table 42: Regional Clock Buffer Switching Characteristics (BUFR)
Symbol Description
Clock to out delay from
Speed Grade
Units
-3
-2
-1
-1L
0.77
0.87
1.03
ns
TBRCKO_O
I to O
Clock to out delay from I to O with Divide Bypass
attribute set
0.39
0.67
0.44
0.76
0.53
0.89
ns
ns
TBRCKO_O_BYP
TBRDO_O
Propagation delay from CLR to O
Maximum Frequency
(1)
FMAX_BUFR
Regional clock tree (BUFR)
575
484
345
MHz
Notes:
1. The maximum input frequency to the BUFR is the BUFIO F
frequency.
MAX
Table 43: Horizontal Clock Buffer Switching Characteristics (BUFH)
Symbol Description
BUFH delay from I to O
Speed Grade
Units
-3
-2
-1
-1L
TBHCKO_O
BHCCK_CE/TBHCKC_CE
0.09
0.10
0.12
ns
ns
0.09/
0.05
0.11/
0.05
0.14/
0.06
T
CE pin Setup and Hold
Maximum Frequency
FMAX_BUFH
Horizontal clock buffer (BUFH)
710
710
625
MHz
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
MMCM Switching Characteristics
Table 44: MMCM Specification
Speed Grade
Units
Symbol
Description
-3
1066
10
-2
933
10
-1
800
10
-1L
MMCM_FINMAX
MMCM_FINMIN
MMCM_FINDUTY
Maximum Input Clock Frequency
MHz
MHz
%
Minimum Input Clock Frequency
Allowable Input Duty Cycle: 19—49 MHz
Allowable Input Duty Cycle: 50—199 MHz
Allowable Input Duty Cycle: 200—399 MHz
Allowable Input Duty Cycle: 400—499 MHz
Allowable Input Duty Cycle: >500 MHz
Minimum Dynamic Phase Shift Clock Frequency
Maximum Dynamic Phase Shift Clock Frequency
Minimum MMCM VCO Frequency
25
25
25
30
30
30
%
35
35
35
%
40
40
40
%
45
45
45
%
MMCM_FMIN_PSCLK
MMCM_FMAX_PSCLK
MMCM_FVCOMIN
0.01
550
600
1600
1.22
4.88
0.12
0.19
122
1066
4.69
5.00
550
0.01
500
600
1440
1.22
4.88
0.12
0.25
122
933
4.69
5.00
500
0.01
450
600
1200
1.22
4.88
0.12
0.25
122
800
4.69
5.00
450
MHz
MHz
MHz
MHz
MHz
MHz
ns
MMCM_FVCOMAX
MMCM_FBANDWIDTH
Maximum MMCM VCO Frequency
Low MMCM Bandwidth at Typical(1)
High MMCM Bandwidth at Typical(1)
Static Phase Offset of the MMCM Outputs(2)
MMCM Output Clock Duty Cycle Precision(3)
MMCM Maximum Lock Time
MMCM_TSTATPHAOFFSET
MMCM_TOUTDUTY
MMCM_TLOCKMAX
MMCM_FOUTMAX
ns
µs
MMCM Maximum Output Frequency
MMCM Minimum Output Frequency(4)(5)
Minimum Reset Pulse Width
MHz
MHz
ns
MMCM_FOUTMIN
MMCM_RSTMINPULSE
MMCM_FPFDMAX
Maximum Frequency at the Phase Frequency
Detector with Bandwidth Set to High or Optimized
MHz
Maximum Frequency at the Phase Frequency
Detector with Bandwidth Set to Low
550
10
500
10
450
10
MHz
MHz
MMCM_FPFDMIN
Minimum Frequency at the Phase Frequency
Detector
MMCM Switching Characteristics Setup and Hold
TMMCMDCK_PSEN
/
Setup and Hold of Phase Shift Enable
1.04/
0.00
1.04/
0.00
1.04/
0.00
ns
ns
ns
TMMCMCKD_PSEN
TMMCMDCK_PSINCDEC
TMMCMCKD_PSINCDEC
/
Setup and Hold of Phase Shift
Increment/Decrement
1.04/
0.00
1.04/
0.00
1.04/
0.00
TMMCMCKO_PSDONE
Phase Shift Clock-to-Out of PSDONE
0.62
0.70
0.84
Notes:
1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any MMCM outputs with identical phase.
3. Includes global clock buffer.
4. Calculated as F
/128 assuming output duty cycle is 50%.
VCO
5. When CASCADE4_OUT = TRUE, F
is 0.036 MHz.
OUTMIN
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
PLL Switching Characteristics
Table 45: PLL Specification
Speed Grade
Units
Symbol
Description
-3
1066
19
-2
933
19
-1
800
19
-1L
FINMAX
FINMIN
FINJITTER
FINDUTY
Maximum Input Clock Frequency
Minimum Input Clock Frequency
Maximum Input Clock Period Jitter
Allowable Input Duty Cycle: 19—49 MHz
Allowable Input Duty Cycle: 50—199 MHz
Allowable Input Duty Cycle: 200—399 MHz
Allowable Input Duty Cycle: 400—499 MHz
Allowable Input Duty Cycle: >500 MHz
Minimum PLL VCO Frequency
MHz
MHz
< 20% of clock input period or 1 ns Max
25
30
25
30
25
30
%
%
35
35
35
%
40
40
40
%
45
45
45
%
FVCOMIN
800
2133
1.00
4.00
0.12
800
1866
1.00
4.00
0.12
800
1600
1.00
4.00
0.12
Note 1
0.20
100
800
6.25
MHz
MHz
MHz
MHz
ns
FVCOMAX
FBANDWIDTH
Maximum PLL VCO Frequency
Low PLL Bandwidth at Typical(1)
High PLL Bandwidth at Typical(1)
Static Phase Offset of the PLL Outputs(2)
PLL Output Jitter(3)
TSTATPHAOFFSET
TOUTJITTER
TOUTDUTY
TLOCKMAX
FOUTMAX
PLL Output Clock Duty Cycle Precision(4)
PLL Maximum Lock Time
0.15
100
0.20
100
933
6.25
ns
µs
PLL Maximum Output Frequency
PLL Minimum Output Frequency(5)(6)
External Clock Feedback Variation
Minimum Reset Pulse Width
1066
6.25
MHz
MHz
FOUTMIN
TEXTFDVAR
RSTMINPULSE
FPFDMAX
< 20% of clock input period or 1 ns Max
5.00
550
5.00
500
5.00
450
ns
Maximum Frequency at the Phase Frequency
Detector with Bandwidth Set to High or Optimized
MHz
Maximum Frequency at the Phase Frequency
Detector with Bandwidth Set to Low
550
19
500
19
450
19
MHz
MHz
FPFDMIN
Minimum Frequency at the Phase Frequency
Detector
TFBDELAY
Maximum Delay in the Feedback Path
3 ns Max or one CLKIN cycle
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 45: PLL Specification (Cont’d)
Speed Grade
Units
Symbol
Description
-3
-2
-1
-1L
PLL Switching Characteristics Setup and Hold
TPLLCCK_DEN
/
Setup and Hold of D enable
Setup and Hold of D address
Setup and Hold of D input
1.76/
0.00
1.97/
0.00
2.29/
0.00
ns
ns
ns
ns
TPLLCKC_DEN
TPLLCCK_DADDR
TPLLCKC_DADDR
/
1.25/
0.00
1.40/
0.00
1.63/
0.00
TPLLCCK_DI
/
1.25/
0.00
1.40/
0.00
1.63/
0.00
TPLLCKC_DI
TPLLCCK_DWE
TPLLCKC_DWE
/
Setup and Hold of D write enable
1.25/
0.00
1.40/
0.00
1.63/
0.00
Notes:
1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any PLL outputs with identical phase.
3. Values for this parameter are available in the Architecture Wizard.
4. Includes global clock buffer.
5. Calculated as F
/128 assuming output duty cycle is 50%.
VCO
6. When CASCADE4_OUT = TRUE, F
is 0.036 MHz.
OUTMIN
Virtex-7 Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 46. Values are expressed in nanoseconds unless otherwise noted.
Table 46: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)
Speed Grade
Symbol
Description
Device
Units
-3
-2
-1
-1L
LVCMOS Clock-Capable Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without MMCM/PLL.
TICKOF
Clock-capable clock input and OUTFF
without MMCM/PLL (near clock region)
XC7V285T
XC7V450T
XC7V585T
XC7V855T
XC7V1500T
XC7V2000T
XC7VX485T
6.69
6.94
6.97
7.12
N/A
7.39
7.66
7.70
7.86
8.46
8.76
8.81
8.99
ns
ns
ns
ns
ns
ns
ns
N/A
5.45
6.03
6.92
N/A
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 47: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)
Speed Grade
-2 -1
LVCMOS Clock-Capable Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without MMCM/PLL.
Symbol
Description
Device
Units
-3
-1L
TICKOF_FAR
Clock-capable clock input and OUTFF
without MMCM/PLL (far clock region)
XC7V285T
XC7V450T
XC7V585T
XC7V855T
XC7V1500T
XC7V2000T
XC7VX485T
7.45
7.17
7.98
8.14
N/A
8.22
7.92
8.79
8.97
9.39
9.05
ns
ns
ns
ns
ns
ns
ns
10.04
10.24
N/A
6.22
6.86
7.86
N/A
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
Table 48: Clock-Capable Clock Input to Output Delay With MMCM
Speed Grade
Symbol
Description
Device
Units
-3
-2
-1
-1L
LVCMOS Clock-Capable Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with MMCM.
TICKOFMMCMCC
Clock-capable clock input and OUTFF
with MMCM
XC7V285T
XC7V450T
XC7V585T
XC7V855T
XC7V1500T
XC7V2000T
XC7VX485T
2.32
2.20
2.31
2.31
N/A
2.40
2.26
2.38
2.38
2.47
2.31
2.45
2.45
ns
ns
ns
ns
ns
ns
ns
N/A
0.94
0.88
0.74
N/A
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. MMCM output jitter is already included in the timing calculation.
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 49: Clock-Capable Clock Input to Output Delay With PLL
Speed Grade
-2 -1
LVCMOS Clock-Capable Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL.
Symbol
Description
Device
Units
-3
-1L
TICKOF_PLL_CC
Clock-capable clock input and OUTFF
with PLL
XC7V285T
XC7V450T
XC7V585T
XC7V855T
XC7V1500T
XC7V2000T
XC7VX485T
2.32
2.20
2.31
2.31
N/A
2.40
2.26
2.38
2.38
2.47
2.31
2.45
2.45
ns
ns
ns
ns
ns
ns
ns
N/A
0.94
0.88
0.74
N/A
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. PLL output jitter is already included in the timing calculation.
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Virtex-7 Device Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 50. Values are expressed in nanoseconds unless otherwise noted.
Table 50: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks
Speed Grade
Symbol
Description
Device
Units
-3
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS Standard.(1)
-2
-1
-1L
TPSFD/ TPHFD
Full Delay (Legacy Delay or Default
Delay)
XC7V285T
XC7V450T
XC7V585T
XC7V855T
–1.13/
3.38
–1.13/
3.76
–1.13/
4.35
ns
ns
ns
ns
Global Clock Input and IFF(2) without
MMCM/PLL with ZHOLD_DELAY on
HR I/O Banks
–0.98/
3.12
–0.98/
3.47
–0.98/
4.03
–1.46/
3.92
–1.46/
4.35
–1.46/
5.02
–1.55/
4.08
–1.55/
4.51
–1.55/
5.20
XC7V1500T
XC7V2000T
XC7VX485T
N/A
N/A
ns
ns
ns
–0.76/
3.11
–0.76/
3.47
–0.76/
4.03
N/A
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0"
is listed, there is no positive hold time.
Table 51: Clock-Capable Clock Input Setup and Hold With MMCM
Speed Grade
Symbol
Description
Device
Units
-3
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS Standard.(1)
-2
-1
-1L
TPSMMCMCC
/
No Delay clock-capable clock input and XC7V285T
IFF(2) with MMCM
1.82/
–0.58
2.03/
–0.58
2.32/
–0.58
ns
ns
ns
ns
TPHMMCMCC
XC7V450T
XC7V585T
XC7V855T
1.71/
–0.58
1.91/
–0.58
2.19/
–0.58
1.91/
–0.61
2.13/
–0.61
2.44/
–0.61
1.91/
2.13/
2.44/
–0.61
–0.61
–0.61
XC7V1500T
XC7V2000T
XC7VX485T
N/A
N/A
ns
ns
ns
1.82/
–0.58
2.03/
–0.58
2.32/
–0.58
N/A
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 52: Clock-Capable Clock Input Setup and Hold With PLL
Speed Grade
Symbol
Description
Device
Units
-3
-2
-1
-1L
Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for LVCMOS Standard.(1)
TPSPLLCC
/
No Delay clock-capable clock input and XC7V285T
IFF(2) with PLL
1.82/
–0.58
2.03/
–0.58
2.32/
–0.58
ns
ns
ns
ns
TPHPLLCC
XC7V450T
XC7V585T
XC7V855T
1.71/
–0.58
1.91/
–0.58
2.19/
–0.58
1.91/
–0.61
2.13/
–0.61
2.44/
–0.61
1.91/
2.13/
2.44/
–0.61
–0.61
–0.61
XC7V1500T
XC7V2000T
XC7VX485T
N/A
N/A
ns
ns
ns
1.82/
–0.58
2.03/
–0.58
2.32/
–0.58
N/A
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Clock Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-7 FPGA clock
transmitter and receiver data-valid windows.
Table 53: Duty Cycle Distortion and Clock-Tree Skew
Speed Grade
Symbol
TDCD_CLK
Description
Device
Units
-3
-2
-1
-1L
Global Clock Tree Duty Cycle
Distortion(1)
All
0.12
0.12
0.12
ns
TCKSKEW
Global Clock Tree Skew(2)
XC7V285T
XC7V450T
XC7V585T
XC7V855T
XC7V1500T
XC7V2000T
XC7VX485T
All
0.48
0.33
0.62
0.62
N/A
0.53
0.36
0.68
0.69
0.61
0.41
0.78
0.78
ns
ns
ns
ns
ns
ns
ns
ns
ns
N/A
0.47
0.08
0.04
0.52
0.08
0.04
0.59
0.08
0.04
N/A
TDCD_BUFIO
TBUFIOSKEW
I/O clock tree duty cycle distortion
I/O clock tree skew across one clock
region
All
TDCD_BUFR
Regional clock tree duty cycle
distortion
All
0.15
0.15
0.15
ns
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
2. The T
value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
CKSKEW
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Table 54: Package Skew
Symbol
Description
Package Skew(1)
Device
Package
FFG484
Value
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
TPKGSKEW
FFG784
XC7V285T
FFG1157
FFG1761
FFG784
XC7V450T
FFG1157
FFG1761
FFG1157
FFG1761
FFG1157
FFG1761
FHG1157
FFG1761
FHG1761
FFG1925
FFG1157
FFG1158
FFG1761
FFG1929
XC7V585T
XC7V855T
XC7V1500T
XC7V2000T
XC7VX485T
Notes:
1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time
from Pad to Ball (7.0 ps per mm).
2. Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
Table 55: Sample Window
Speed Grade
Symbol
Description
Units
-3
-2
-1
-1L
TSAMP
Sampling Error at Receiver Pins(1)
0.51
0.30
0.56
0.35
0.61
0.40
ps
ps
TSAMP_BUFIO
Sampling Error at Receiver Pins using BUFIO(2)
Notes:
1. This parameter indicates the total sampling error of the Virtex-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements
include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of the Virtex-7 FPGAs DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of
operation. These measurements do not include package or clock tree skew.
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Virtex-7 FPGAs Data Sheet: DC and Switching Characteristics
Speed Grade
Table 56: Pin-to-Pin Setup/Hold and Clock-to-Out
Symbol
Description
Units
-3
-2
-1
-1L
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
TPSCS/TPHCS
Setup/Hold of I/O clock
–0.20/
1.79
–0.20/
2.01
–0.20/
2.33
ns
Pin-to-Pin Clock-to-Out Using BUFIO
TICKOFCS
Clock-to-Out of I/O clock
5.48
6.05
6.92
ns
Revision History
The following table shows the revision history for this document:
Date
Version
Description
03/01/11
1.0
Initial Xilinx release.
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XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-
SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A
VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN
THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)
USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY
USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.
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