XC7A200T-2SB484C_技术文档

Artix-7 FPGAs Data Sheet:

DC and Switching Characteristics

DS181 (v1.13) May 13, 2014

Product Specification

Introduction

Artix®-7 FPGAs are available in -3, -2, -1, and -2L speed

grades, with -3 having the highest performance. The -2L

temperature range. For example, -1M is only available in the

defense-grade Artix-7Q family and -1Q is only available in

XA Artix-7 FPGAs.

devices can operate at either of two V

voltages, 0.9V

CCINT

and 1.0V and are screened for lower maximum static power.

When operated at V = 1.0V, the speed specification of

All supply voltage and junction temperature specifications

are representative of worst-case conditions. The

parameters included are common to popular designs and

typical applications.

CCINT

a -2L device is the same as the -2 speed grade. When

operated at V = 0.9V, the -2L static and dynamic

CCINT

power is reduced.

Available device and package combinations can be found in

:

Artix-7 FPGA DC and AC characteristics are specified in

commercial, extended, industrial, expanded (-1Q), and

military (-1M) temperature ranges. Except the operating

temperature range or unless otherwise noted, all the DC

and AC electrical parameters are the same for a particular

speed grade (that is, the timing characteristics of a -1M

speed grade military device are the same as for a -1C

speed grade commercial device). However, only selected

speed grades and/or devices are available in each

•

7 Series FPGAs Overview (DS180)

Defense-Grade 7 Series FPGAs Overview (DS185)

XA Artix-7 FPGAs Overview (DS197)

This Artix-7 FPGA data sheet, part of an overall set of

documentation on the 7 series FPGAs, is available on the

Xilinx website at www.xilinx.com/7.

DC Characteristics

Table 1: Absolute Maximum Ratings

(1)

Symbol

FPGA Logic

V_CCINT

Description

Min

Max

Units

Internal supply voltage

–0.5

–0.4

1.1

2.0

V

Auxiliary supply voltage

V_CCAUX

Supply voltage for the block RAM memories

Output drivers supply voltage for 3.3V HR I/O banks

Input reference voltage

1.1

V_CCBRAM

V_CCO

3.6

2.0

V_REF

I/O input voltage

V_CCO+ 0.55

2.625

(2)(3)(4)

V_IN

I/O input voltage (when V_CCO= 3.3V) for V_REFand differential I/O standards

except TMDS_33⁽⁵⁾

Key memory battery backup supply

–0.5

2.0

V

V_CCBATT

GTP Transceiver

V_MGTAVCC

V_MGTAVTT

Analog supply voltage for the GTP transmitter and receiver circuits

Analog supply voltage for the GTP transmitter and receiver termination circuits

Reference clock absolute input voltage

–0.5

–

1.1

1.32

1.26

14

V

V_MGTREFCLK

V_IN

I_DCIN-FLOAT

I_DCIN-MGTAVTT

V

Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage

DC input current for receiver input pins DC coupled RX termination = floating

DC input current for receiver input pins DC coupled RX termination = V_MGTAVTT

V

mA

–

12

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Product Specification

1

Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

(1)

Table 1: Absolute Maximum Ratings (Cont’d)

Symbol Description

I_DCIN-GND

Min

–

Max

6.5

14

Units

mA

DC input current for receiver input pins DC coupled RX termination = GND

DC output current for transmitter pins DC coupled RX termination = floating

DC output current for transmitter pins DC coupled RX termination = V_MGTAVTT

–

I_DCOUT-FLOAT

I_{DCOUT-MGTAVTT}

XADC

mA

–

12

mA

XADC supply relative to GNDADC

–0.5

2.0

V

V_CCADC

XADC reference input relative to GNDADC

V_REFP

Temperature

T_STG

Storage temperature (ambient)

–65

–

150

°C

Maximum soldering temperature for Pb/Sn component bodies⁽⁶⁾

Maximum soldering temperature for Pb-free component bodies⁽⁶⁾

Maximum junction temperature⁽⁶⁾

+220

+260

+125

T_SOL

–

T_j

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.

Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.

2. The lower absolute voltage specification always applies.

3. For I/O operation, refer to UG471: 7 Series FPGAs SelectIO Resources User Guide.

4. The maximum limit applies to DC signals. For maximum undershoot and overshoot AC specifications, see Table 4.

5. See Table 9 for TMDS_33 specifications.

6. For soldering guidelines and thermal considerations, see UG475: 7 Series FPGA Packaging and Pinout Specification.

(1)(2)

Table 2: Recommended Operating Conditions

Symbol

Description

Min

Typ

Max

Units

FPGA Logic

Internal supply voltage

0.95

0.87

1.00

0.90

1.80

1.00

–

1.05

0.93

V

(3)

V_CCINT

For -2L (0.9V) devices: internal supply voltage

Auxiliary supply voltage

V_CCAUX

1.71

1.89

(3)

V_CCBRAM

Block RAM supply voltage

0.95

1.14

1.05

(4)(5)

V_CCO

Supply voltage for 3.3V HR I/O banks

I/O input voltage

3.465

–0.20

–

V_CCO+ 0.20

2.625

(6)

V_IN

I/O input voltage (when V_CCO= 3.3V) for V_REFand differential I/O standards

except TMDS_33⁽⁷⁾

–

Maximum current through any pin in a powered or unpowered bank when

forward biasing the clamp diode.

–

10

mA

V

(8)

I_IN

(9)

V_CCBATT

Battery voltage

1.0

1.89

GTP Transceiver

(10)

V_MGTAVCC

Analog supply voltage for the GTP transmitter and receiver circuits

0.97

1.17

1.0

1.2

1.03

1.23

V

(10)

V_MGTAVTT

Analog supply voltage for the GTP transmitter and receiver termination circuits

XADC

V_CCADC

V_REFP

XADC supply relative to GNDADC

Externally supplied reference voltage

1.71

1.20

1.80

1.25

1.89

1.30

V

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Product Specification

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

(1)(2)

Table 2: Recommended Operating Conditions

(Cont’d)

Symbol

Description

Min

Typ

Max

Units

Temperature

Junction temperature operating range for commercial (C) temperature devices

Junction temperature operating range for extended (E) temperature devices

Junction temperature operating range for industrial (I) temperature devices

Junction temperature operating range for expanded (Q) temperature devices

Junction temperature operating range for military (M) temperature devices

0

–

85

°C

0

100

125

T_j

–40

–55

Notes:

1. All voltages are relative to ground.

2. For the design of the power distribution system consult UG483, 7 Series FPGAs PCB Design and Pin Planning Guide.

3. If V and V are operating at the same voltage, V and V should be connected to the same supply.

CCINT

CCBRAM

CCINT

CCBRAM

4. Configuration data is retained even if V

drops to 0V.

CCO

5. Includes V

of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V at 5ꢀ.

CCO

6. The lower absolute voltage specification always applies.

7. See Table 9 for TMDS_33 specifications.

8. A total of 200 mA per bank should not be exceeded.

9.

V

is required only when using bitstream encryption. If battery is not used, connect V

to either ground or V

.

CCAUX

CCBATT

10. Each voltage listed requires the filter circuit described in UG482: 7 Series FPGAs GTP Transceiver User Guide.

Table 3: DC Characteristics Over Recommended Operating Conditions

Symbol

V_DRINT

Description

Data retention V_CCINTvoltage (below which configuration data might be lost)

Data retention V_CCAUXvoltage (below which configuration data might be lost)

V_REFleakage current per pin

Min

0.75

1.5

–

Typ⁽¹⁾

Max

–

Units

V

–

V_DRI

I_REF

I_L

–

V

–

15

µA

pF

µA

mA

nA

Ω

Input or output leakage current per pin (sample-tested)

Die input capacitance at the pad

–

15

(2)

C_IN

–

8

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 3.3V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 2.5V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 1.8V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 1.5V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 1.2V

Pad pull-down (when selected) @ V_IN= 3.3V

90

68

34

23

12

68

–

330

250

220

150

120

330

25

–

I_RPU

–

I_RPD

–

I_CCADC

Analog supply current, analog circuits in powered up state

Battery supply current

–

(3)

I_BATT

–

150

55

Thevenin equivalent resistance of programmable input termination to V_CCO/2

(UNTUNED_SPLIT_40)

28

40

Thevenin equivalent resistance of programmable input termination to V_CCO/2

(UNTUNED_SPLIT_50)

35

44

50

60

65

83

Ω

(4)

R_{IN_TERM}

Thevenin equivalent resistance of programmable input termination to V_CCO/2

(UNTUNED_SPLIT_60)

n

r

Temperature diode ideality factor

–

1.010

2

–

Temperature diode series resistance

Ω

Notes:

1. Typical values are specified at nominal voltage, 25°C.

2. This measurement represents the die capacitance at the pad, not including the package.

3. Maximum value specified for worst case process at 25°C.

4. Termination resistance to a V

/2 level.

CCO

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

(1)(2)

Table 4: V Maximum Allowed AC Voltage Overshoot and Undershoot for 3.3V HR I/O Banks

IN

AC Voltage Overshoot

% of UI @–55°C to 125°C

AC Voltage Undershoot

% of UI @–55°C to 125°C

–0.40

–0.45

–0.50

–0.55

–0.60

–0.65

–0.70

–0.75

–0.80

–0.85

–0.90

–0.95

100

61.7

25.8

11.0

4.77

2.10

0.94

0.43

0.20

0.09

0.04

0.02

V_CCO+ 0.55

100

V_CCO+ 0.60

46.6

21.2

9.75

4.55

2.15

1.02

0.49

0.24

V_CCO+ 0.65

V_CCO+ 0.70

V_CCO+ 0.75

V_CCO+ 0.80

V_CCO+ 0.85

V

_CCO+ 0.90

_CCO+ 0.95

V

Notes:

1. A total of 200 mA per bank should not be exceeded.

2. The peak voltage of the overshoot or undershoot, and the duration above V

in this table.

+ 0.20V or below GND – 0.30V, must not exceed the values

CCO

Table 5: Typical Quiescent Supply Current

Speed Grade

Symbol

Description

Device

1.0V

0.9V

-2L

66

Units

-3

-2

-2L

95

-1

I_CCINTQ

Quiescent V_CCINTsupply current

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

XA7A35T

XA7A50T

XA7A75T

XA7A100T

XQ7A50T

XQ7A100T

XQ7A200T

95

mA

95

66

155

328

N/A

155

328

95

155

328

N/A

155

328

95

108

232

N/A

95

155

95

155

95

155

328

155

328

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Speed Grade

Table 5: Typical Quiescent Supply Current (Cont’d)

Symbol

Description

Device

1.0V

0.9V

-2L

1

Units

-3

1

-2

1

-2L

1

-1

1

I_CCOQ

Quiescent V_CCOsupply current

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

XA7A35T

XA7A50T

XA7A75T

XA7A100T

XQ7A50T

XQ7A100T

XQ7A200T

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

XA7A35T

XA7A50T

XA7A75T

XA7A100T

XQ7A50T

XQ7A100T

XQ7A200T

mA

1

4

5

N/A

22

1

N/A

22

1

N/A

22

1

4

1

4

5

I_CCAUXQ

Quiescent V_CCAUXsupply current

22

36

73

22

36

22

36

73

22

36

73

22

36

22

36

73

22

36

73

N/A

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Product Specification

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Speed Grade

Table 5: Typical Quiescent Supply Current (Cont’d)

Symbol

Description

Device

1.0V

0.9V

-2L

2

Units

-3

2

-2

2

-2L

2

-1

2

I_CCBRAMQQuiescent V_CCBRAMsupply current

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

XA7A35T

XA7A50T

XA7A75T

XA7A100T

XQ7A50T

XQ7A100T

XQ7A200T

mA

2

4

11

2

11

2

11

N/A

2

4

2

4

11

Notes:

1. Typical values are specified at nominal voltage, 85°C junction temperature (T ) with single-ended SelectIO resources.

j

2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and

floating.

3. Use the Xilinx Power Estimator (XPE) spreadsheet tool (download at http://www.xilinx.com/power) to calculate static power consumption for

conditions other than those specified.

Power-On/Off Power Supply Sequencing

The recommended power-on sequence is V

, V

, and V

to achieve minimum current draw and

CCO

CCINT CCBRAM

CCAUX

ensure that the I/Os are 3-stated at power-on. The recommended power-off sequence is the reverse of the power-on

sequence. If V and V have the same recommended voltage levels then both can be powered by the same

CCINT

CCBRAM

supply and ramped simultaneously. If V

and V

have the same recommended voltage levels then both can be

CCAUX

CCO

powered by the same supply and ramped simultaneously.

For V voltages of 3.3V in HR I/O banks and configuration bank 0:

CCO

•

The voltage difference between V

power-on/off cycle to maintain device reliability levels.

and V

must not exceed 2.625V for longer than T

for each

CCO

CCAUX

VCCO2VCCAUX

The T time can be allocated in any percentage between the power-on and power-off ramps.

VCCO2VCCAUX

The recommended power-on sequence to achieve minimum current draw for the GTP transceivers is V

, V

,

CCINT MGTAVCC

V

OR V

, V

. Both V

and V

can be ramped simultaneously. The recommended

MGTAVTT

MGTAVCC CCINT MGTAVTT

MGTAVCC

CCINT

power-off sequence is the reverse of the power-on sequence to achieve minimum current draw.

If these recommended sequences are not met, current drawn from V

power-up and power-down.

can be higher than specifications during

MGTAVTT

•

When V

is powered before V

and V

– V

> 150 mV and V

< 0.7V, the

MGTAVTT

MGTAVCC

MGTAVTT

MGTAVCC

V

current draw can increase by 460 mA per transceiver during V

ramp up. The duration of the current

MGTAVTT

MGTAVCC

draw can be up to 0.3 x T

(ramp time from GND to 90ꢀ of V

). The reverse is true for power-down.

MGTAVCC

•

When V

is powered before V

and V

– V

> 150 mV and V

< 0.7V, the V

current

MGTAVTT

CCINT

MGTAVTT

CCINT

draw can increase by 50 mA per transceiver during V

ramp up. The duration of the current draw can be up to

CCINT

0.3 x T

(ramp time from GND to 90ꢀ of V

). The reverse is true for power-down.

VCCINT

CCINT

Table 6 shows the minimum current, in addition to I

, that is required by Artix-7 devices for proper power-on and

CCQ

configuration. If the current minimums shown in Table 5 and Table 6 are met, the device powers on after all four supplies

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Product Specification

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

have passed through their power-on reset threshold voltages. The FPGA must not be configured until after V

applied.

is

CCINT

Once initialized and configured, use the Xilinx Power Estimator (XPE) tools to estimate current drain on these supplies.

Table 6: Power-On Current for Artix-7 Devices

Device

XC7A35T

I_CCINTMIN

I_CCAUXMIN

I_CCOMIN

I_CCBRAMMIN

I_CCBRAMQ+ 60

I_CCBRAMQ+ 80

I_CCBRAMQ+ 60

I_CCBRAMQ+ 80

Units

mA

I_CCINTQ+ 120

I_CCAUXQ+ 40

I_CCAUXQ+ 50

I_CCAUXQ+ 40

I_CCAUXQ+ 50

I_CCOQ+ 40 mA per bank

XC7A50T

XC7A75T

XC7A100T

XC7A200T

XA7A35T

XA7A50T

XA7A75T

XA7A100T

XQ7A50T

XQ7A100T

XQ7A200T

I

_CCINTQ+ 120

I_CCINTQ+ 170

_CCINTQ+ 170

I

I_CCINTQ+ 340

I_CCINTQ+ 120

I

_CCINTQ+ 120

I_CCINTQ+ 170

I

_CCINTQ+ 120

_CCINTQ+ 170

I

I_CCINTQ+ 340

Table 7: Power Supply Ramp Time

Symbol

Description

Conditions

Min

0.2

–

Max

50

Units

ms

T_VCCINT

T_VCCO

T_VCCAUX

T_VCCBRAM

Ramp time from GND to 90ꢀ of V_CCINT

Ramp time from GND to 90ꢀ of V_CCO

Ramp time from GND to 90ꢀ of V_CCAUX

Ramp time from GND to 90ꢀ of V_CCBRAM

50

ms

50

ms

50

ms

T_J= 125°C⁽¹⁾

300

500

800

50

T_VCCO2VCCAUX

Allowed time per power cycle for V_CCO– V_CCAUX> 2.625V

T_J= 100°C⁽¹⁾

T_J= 85°C⁽¹⁾

–

ms

–

T_MGTAVCC

T_MGTAVTT

Ramp time from GND to 90ꢀ of V_MGTAVCC

Ramp time from GND to 90ꢀ of V_MGTAVTT

0.2

ms

50

Notes:

1. Based on 240,000 power cycles with nominal V

of 3.3V or 36,500 power cycles with worst case V

of 3.465V.

CCO

DC Input and Output Levels

Values for V and V are recommended input voltages. Values for I and I are guaranteed over the recommended

IL

IH

OL

OH

operating conditions at the V and V test points. Only selected standards are tested. These are chosen to ensure that

OL

OH

all standards meet their specifications. The selected standards are tested at a minimum V

with the respective V and

CCO

OL

V

voltage levels shown. Other standards are sample tested.

OH

(1)(2)

Table 8: SelectIO DC Input and Output Levels

V_IL

V_IH

V_OL

V, Max

0.400

V_OH

I_OL

I_OH

I/O Standard

V, Min

–0.300

V, Max

V, Min

V, Max

V, Min

mA, Max mA, Min

HSTL_I

V_REF– 0.100

V_REF+ 0.100 V_CCO+ 0.300

V_CCO– 0.400

8.00

–8.00

HSTL_I_18

HSTL_II

V

_REF– 0.100

16.00

–16.00

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

(1)(2)

Table 8: SelectIO DC Input and Output Levels

(Cont’d)

V_IH

V_IL

V_OL

V, Max

0.400

V_OH

I_OL

I_OH

I/O Standard

V, Min

–0.300

–0.400

–0.300

V, Max

V, Min

V, Max

V, Min

mA, Max mA, Min

HSTL_II_18

HSUL_12

V_REF– 0.100

V_REF+ 0.100 V_CCO+ 0.300

V_REF+ 0.130 V_CCO+ 0.300

V_CCO– 0.400

80ꢀ V_CCO

V_CCO– 0.400

75ꢀ V_CCO

V_CCO– 0.450

V_CCO– 0.400

2.400

16.00

0.10

–16.00

–0.10

V

_REF– 0.130

20ꢀ V_CCO

0.400

LVCMOS12

LVCMOS15

LVCMOS18

LVCMOS25

LVCMOS33

LVTTL

35ꢀ V_CCO

0.7

65ꢀ V_CCO

1.700

V_CCO+ 0.300

3.450

Note 3

Note 4

Note 5

Note 4

Note 5

0.10

Note 3

Note 4

Note 5

Note 4

Note 5

–0.10

25ꢀ V_CCO

0.450

0.400

0.8

2.000

0.400

0.8

2.000

3.450

0.400

MOBILE_DDR

PCI33_3

20ꢀ V_CCO

30ꢀ V_CCO

80ꢀ V_CCO

50ꢀ V_CCO

V_CCO+ 0.300

V_CCO+ 0.500

10ꢀ V_CCO

90ꢀ V_CCO

1.50

–0.50

SSTL135

V

_REF– 0.090

V_REF– 0.090

V_REF+ 0.090 V_CCO+ 0.300 V_CCO/2 – 0.150 V_CCO/2 + 0.150 13.00

V_REF+ 0.090 V_CCO+ 0.300 V_CCO/2 – 0.150 V_CCO/2 + 0.150 8.90

V_REF+ 0.100 V_CCO+ 0.300 V_CCO/2 – 0.175 V_CCO/2 + 0.175 13.00

–13.00

–8.90

SSTL135_R

SSTL15

V_REF– 0.100

_REF– 0.100

–13.00

–8.90

SSTL15_R

SSTL18_I

SSTL18_II

V

V_REF+ 0.100 V_CCO+ 0.300 V_CCO/2 – 0.175 V_CCO/2 + 0.175

V_REF+ 0.125 V_CCO+ 0.300 V_CCO/2 – 0.470 V_CCO/2 + 0.470

8.90

8.00

V_REF– 0.125

–8.00

V_REF+ 0.125 V_CCO+ 0.300 V_CCO/2 – 0.600 V_CCO/2 + 0.600 13.40

–13.40

Notes:

1. Tested according to relevant specifications.

2. 3.3V and 2.5V standards are only supported in 3.3V I/O banks.

3. Supported drive strengths of 4, 8, or 12 mA in HR I/O banks.

4. Supported drive strengths of 4, 8, 12, or 16 mA in HR I/O banks.

5. Supported drive strengths of 4, 8, 12, 16, or 24 mA in HR I/O banks.

6. For detailed interface specific DC voltage levels, see UG471: 7 Series FPGAs SelectIO Resources User Guide.

Table 9: Differential SelectIO DC Input and Output Levels

(1)

(2)

(3)

(4)

V_ICM

V, Min V, Typ V, Max V, Min V, Typ V, Max

0.300 1.200 1.425 0.100

V_ID

V_OCM

V_OD

I/O Standard

V, Min

–

V, Typ

1.250

1.200

0.950

1.200

V, Max

–

V, Min V, Typ V, Max

Note 5

BLVDS_25

–

MINI_LVDS_25 0.300 1.200 V_CCAUX0.200 0.400 0.600

1.000

0.500

1.000

1.400

0.300 0.450 0.600

0.100 0.250 0.400

0.100 0.350 0.600

PPDS_25

RSDS_25

TMDS_33

0.200 0.900 V_CCAUX0.100 0.250 0.400

0.300 0.900

2.700 2.965

1.500

3.230

0.100 0.350 0.600

0.150 0.675 1.200

V

_CCO–0.405 V_CCO–0.300 V_CCO–0.190 0.400 0.600 0.800

Notes:

1.

2.

3.

4.

5.

V

is the input common mode voltage.

is the input differential voltage (Q – Q).

ICM

ID

is the output common mode voltage.

OCM

is the output differential voltage (Q – Q).

for BLVDS will vary significantly depending on topology and loading.

OD

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Table 10: Complementary Differential SelectIO DC Input and Output Levels

(1)

(2)

(3)

(4)

V_ICM

V_ID

V_OL

V_OH

I_OL

mA, Max

8.00

I_OH

mA, Min

–8.00

–16.00

–0.100

–13.0

–8.9

I/O Standard

V, Min V,Typ V, Max V,Min V, Max

V, Max

0.400

V, Min

DIFF_HSTL_I

0.300 0.750 1.125 0.100

0.300 0.900 1.425 0.100

0.300 0.750 1.125 0.100

0.300 0.900 1.425 0.100

0.300 0.600 0.850 0.100

–

V_CCO–0.400

DIFF_HSTL_I_18

DIFF_HSTL_II

0.400

8.00

0.400

V

_CCO–0.400

16.00

0.100

13.0

DIFF_HSTL_II_18

DIFF_HSUL_12

0.400

V_CCO–0.400

80ꢀ V_CCO

90ꢀ V_CCO

20ꢀ V_CCO

10ꢀ V_CCO

DIFF_MOBILE_DDR 0.300 0.900 1.425 0.100

DIFF_SSTL135

DIFF_SSTL135_R

DIFF_SSTL15

0.300 0.675 1.000 0.100

0.300 0.750 1.125 0.100

0.300 0.900 1.425 0.100

(V_CCO/2) – 0.150 (V_CCO/2) + 0.150

(V_CCO/2) – 0.175 (V_CCO/2) + 0.175

(V_CCO/2) – 0.470 (V_CCO/2) + 0.470

(V_CCO/2) – 0.600 (V_CCO/2) + 0.600

8.9

13.0

–13.0

–8.9

DIFF_SSTL15_R

DIFF_SSTL18_I

DIFF_SSTL18_II

8.9

8.00

–8.00

–13.4

13.4

Notes:

1.

2.

3.

4.

V

is the input common mode voltage.

is the input differential voltage (Q – Q).

is the single-ended low-output voltage.

ICM

ID

OL

OH

is the single-ended high-output voltage.

LVDS DC Specifications (LVDS_25)

(1)

Table 11: LVDS_25 DC Specifications

Symbol

V_CCO

V_OH

DC Parameter

Supply Voltage

Conditions

Min

Typ

2.500

–

Max

Units

2.375

–

2.625

1.675

–

V

Output High Voltage for Q and Q

Output Low Voltage for Q and Q

R_T= 100 Ω across Q and Q signals

V_OL

0.700

247

–

V

V_ODIFF

Differential Output Voltage:

(Q – Q), Q = High

350

600

mV

(Q – Q), Q = High

V_OCM

V_IDIFF

Output Common-Mode Voltage

R_T= 100 Ω across Q and Q signals

1.000

100

1.250

350

1.425

600

V

Differential Input Voltage:

(Q – Q), Q = High

mV

(Q – Q), Q = High

V_ICM

Input Common-Mode Voltage

0.300

1.200

1.425

V

Notes:

1. Differential inputs for LVDS_25 can be placed in banks with V

levels that are different from the required level for outputs. Consult the

CCO

7 Series FPGAs SelectIO Resources User Guide (UG471) for more information.

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

AC Switching Characteristics

All values represented in this data sheet are based on the speed specifications from the ISE® Design Suite 14.7 and

Vivado® Design Suite 2014.1 as outlined in Table 12.

Table 12: Artix-7 FPGA Speed Specification Version By Device

Version In:

Typical V_CCINT

(Table 2)

1.0V

Device

ISE 14.7 Vivado 2014.1

N/A

1.12

1.08

1.12

1.08

1.09

1.08

XC7A35T, XC7A50T, XC7A75T

XC7A100T, XC7A200T

XA7A35T, XA7A50T, XA7A75T

XA7A100T

0.9V

1.10

1.07

N/A

1.0V

0.9V

1.0V

1.07

1.06

1.0V

XQ7A100T, XQ7A200T

Switching characteristics are specified on a per-speed-grade basis and can be designated as Advance, Preliminary, or

Production. Each designation is defined as follows:

Advance Product Specification

These specifications are based on simulations only and are typically available soon after device design specifications are

frozen. Although speed grades with this designation are considered relatively stable and conservative, some under-

reporting might still occur.

Preliminary Product Specification

These specifications are based on complete ES (engineering sample) silicon characterization. Devices and speed grades

with this designation are intended to give a better indication of the expected performance of production silicon. The

probability of under-reporting delays is greatly reduced as compared to Advance data.

Production Product Specification

These specifications are released once enough production silicon of a particular device family member has been

characterized to provide full correlation between specifications and devices over numerous production lots. There is no

under-reporting of delays, and customers receive formal notification of any subsequent changes. Typically, the slowest

speed grades transition to Production before faster speed grades.

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Testing of AC Switching Characteristics

Internal timing parameters are derived from measuring internal test patterns. All AC switching characteristics are

representative of worst-case supply voltage and junction temperature conditions.

For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and

back-annotate to the simulation net list. Unless otherwise noted, values apply to all Artix-7 FPGAs.

Speed Grade Designations

Since individual family members are produced at different times, the migration from one category to another depends

completely on the status of the fabrication process for each device. Table 13 correlates the current status of each Artix-7

device on a per speed grade basis.

Table 13: Artix-7 Device Speed Grade Designations

Speed Grade Designations

Device

Advance

Preliminary

Production

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

XA7A35T

XA7A50T

XA7A75T

XA7A100T

XQ7A50T

XQ7A100T

XQ7A200T

-3, -2, -2L (1.0V), -1, and -2L (0.9V)

-2I, -1I, and -1Q

-2I, -1I, and -1M

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Production Silicon and Software Status

In some cases, a particular family member (and speed grade) is released to production before a speed specification is

released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent

speed specification releases.

Table 14 lists the production released Artix-7 device, speed grade, and the minimum corresponding supported speed

specification version and software revisions. The software and speed specifications listed are the minimum releases

required for production. All subsequent releases of software and speed specifications are valid.

Table 14: Artix-7 Device Production Software and Speed Specification Release

Speed Grade

Device

1.0V

0.9V⁽¹⁾

-2L

-3

-2

-2L

-1

-1Q

-1M

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

Vivado tools 2013.4 v1.11

Vivado tools 2013.3 v1.10

N/A

Vivado tools

2013.4 v1.08

N/A

Vivado tools

2013.4 v1.08

Vivado tools

2013.3 v1.07

ISE tools 14.4 or Vivado tools 2012.4 with the

14.4/2012.4 device pack v1.07

ISE tools 14.5

or Vivado tools

2013.1 v1.05

ISE tools 14.4 or Vivado tools 2012.4 with the

14.4/2012.4 device pack v1.07

XA7A35T

XA7A50T

XA7A75T

XA7A100T

N/A

ISE tools 14.5

or Vivado tools

2013.1 v1.05

N/A

ISE tools 14.5 ISE tools 14.6

or Vivado tools or Vivado tools

N/A

2013.1 v1.05

2013.2 v1.06

XQ7A50T

N/A

XQ7A100T

ISE tools 14.5

or Vivado tools

2013.1 v1.04

ISE tools 14.5

or Vivado tools

2013.1 v1.04

N/A

ISE tools 14.6

or Vivado tools

2013.2 v1.05

XQ7A200T

N/A

ISE tools 14.5

or Vivado tools

2013.1 v1.04

N/A

ISE tools 14.5

or Vivado tools

2013.1 v1.04

N/A

ISE tools 14.6

or Vivado tools

2013.2 v1.05

N/A

Notes:

1. In the software, -2L (0.9V) designs are distinguished from -2L (1.0V) designs via an additional "L" following the device name, e.g.,

XC7A100TL is the device name for a -2L (0.9V) design and XC7A100T is the part name for a -2L (1.0V) design. For the -2L (0.9V) speed

specification, select the Artix-7 Low Voltage family in the software.

2. Blank entries indicate a device and/or speed grade in advance or preliminary status.

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Performance Characteristics

This section provides the performance characteristics of some common functions and designs implemented in Artix-7

devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject

to the same guidelines as the AC Switching Characteristics, page 10.

Table 15: Networking Applications Interface Performances

Speed Grade

Description

1.0V

-2/-2L

680

0.9V

-2L

Units

-3

-1

SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8)

DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 14)

SDR LVDS receiver (SFI-4.1)⁽¹⁾

680

600

950

600

950

600

950

600

950

Mb/s

1250

680

1250

680

DDR LVDS receiver (SPI-4.2)⁽¹⁾

1250

Notes:

1. LVDS receivers are typically bounded with certain applications where specific dynamic phase-alignment (DPA) algorithms dominate

deterministic performance.

Table 16: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface

(1)(2)

Generator

Speed Grade

Memory Standard

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

-1Q/-1M

4:1 Memory Controllers

DDR3

1066

800

667

800

667

800

667

533

667

N/A

533

400

800

667

533

Mb/s

DDR3L

DDR2

LPDDR2

2:1 Memory Controllers

DDR3

DDR3L

DDR2

800

700

620

N/A

533

620

Mb/s

Notes:

1.

V

tracking is required. For more information, see UG586, 7 Series FPGAs Memory Interface Solutions User Guide.

REF

2. When using the internal V , the maximum data rate is 800 Mb/s (400 MHz).

REF

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

IOB Pad Input/Output/3-State

Table 17 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based

on standard) and 3-state delays.

•

T

is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies

IOPI

depending on the capability of the SelectIO input buffer.

T

is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies

IOOP

depending on the capability of the SelectIO output buffer.

T

is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is

IOTP

disabled. The delay varies depending on the SelectIO capability of the output buffer. In HR I/O banks, the IN_TERM

termination turn-on time is always faster than T when the INTERMDISABLE pin is used.

IOTP

Table 17: 3.3V IOB High Range (HR) Switching Characteristics

T

IOTP

IOPI

IOOP

Speed Grade

1.0V

Speed Grade

1.0V

Speed Grade

1.0V

I/O Standard

Units

0.9V

-3 -2/-2L -1 -1Q/-1M -2L

LVTTL_S4

1.26 1.34 1.41

0.73 0.81 0.88

1.24 1.32 1.39

0.67 0.75 0.82

0.68 0.76 0.83

0.76 0.84 0.91

0.70 0.78 0.85

0.67 0.75 0.82

0.65 0.73 0.80

0.67 0.75 0.82

0.66 0.75 0.81

1.53

0.89

0.88

0.89

0.92

1.52

0.88

0.86

0.91

0.85

0.86

0.88

1.58 3.80 3.93 4.18

4.18

3.92

3.90

3.45

3.67

3.64

3.12

3.10

2.93

3.23

1.67

1.65

2.76

1.65

1.67

1.79

3.48

2.18

1.67

2.18

1.67

2.06

1.76

2.07

1.82

1.99

1.79

1.67

1.79

4.41 3.82 3.96 4.20

4.20

3.93

3.91

3.46

3.68

3.65

3.13

3.12

2.95

3.24

1.68

1.66

2.77

1.66

1.68

1.80

3.49

2.20

1.68

2.20

1.68

2.07

1.77

2.09

1.84

2.01

1.81

1.68

1.80

4.05

3.78

3.77

3.31

3.53

3.50

2.99

2.97

2.80

2.86

1.50

1.52

2.08

1.52

1.63

3.34

2.05

1.53

1.84

1.42

1.88

1.61

1.88

1.64

1.83

1.63

1.50

1.61

ns

LVTTL_S8

1.58 3.54 3.66 3.92

1.58 3.52 3.65 3.90

1.58 3.07 3.19 3.45

1.58 3.29 3.41 3.67

1.58 3.26 3.38 3.64

1.58 2.74 2.87 3.12

1.58 2.73 2.85 3.10

1.58 2.56 2.68 2.93

1.58 2.52 2.65 2.90

0.90 1.29 1.41 1.67

0.90 1.27 1.40 1.65

0.90 1.84 1.96 2.21

0.90 1.27 1.40 1.65

0.90 1.29 1.41 1.67

0.90 1.41 1.54 1.79

1.57 3.10 3.22 3.48

0.87 1.81 1.93 2.18

0.87 1.29 1.41 1.67

0.88 1.81 1.93 2.18

0.88 1.29 1.41 1.67

0.96 1.68 1.80 2.06

0.96 1.38 1.51 1.76

0.87 1.70 1.82 2.07

0.87 1.45 1.57 1.82

0.87 1.62 1.74 1.99

0.85 1.41 1.54 1.79

0.87 1.29 1.41 1.67

0.87 1.41 1.54 1.79

4.15 3.56 3.69 3.93

4.13 3.54 3.68 3.91

3.68 3.09 3.22 3.46

3.90 3.31 3.44 3.68

3.86 3.28 3.41 3.65

3.35 2.76 2.90 3.13

3.33 2.74 2.88 3.12

3.16 2.57 2.71 2.95

3.22 2.54 2.68 2.91

1.86 1.31 1.44 1.68

1.88 1.29 1.43 1.66

2.44 1.85 1.99 2.23

1.88 1.29 1.43 1.66

1.88 1.31 1.44 1.68

1.99 1.43 1.57 1.80

3.71 3.12 3.25 3.49

2.41 1.82 1.96 2.20

1.90 1.31 1.44 1.68

2.21 1.82 1.96 2.20

1.79 1.31 1.44 1.68

2.24 1.70 1.83 2.07

1.97 1.40 1.54 1.77

2.24 1.71 1.85 2.09

2.00 1.46 1.60 1.84

2.19 1.63 1.77 2.01

1.99 1.43 1.57 1.80

1.86 1.31 1.44 1.68

1.97 1.43 1.57 1.80

LVTTL_S12

LVTTL_S16

LVTTL_S24

LVTTL_F4

LVTTL_F8

LVTTL_F12

LVTTL_F16

LVTTL_F24

LVDS_25

MINI_LVDS_25

BLVDS_25

RSDS_25 (point to point)

PPDS_25

TMDS_33

PCI33_3

HSUL_12_S

HSUL_12_F

DIFF_HSUL_12_S

DIFF_HSUL_12_F

MOBILE_DDR_S

MOBILE_DDR_F

DIFF_MOBILE_DDR_S

DIFF_MOBILE_DDR_F

HSTL_I_S

HSTL_II_S

HSTL_I_18_S

HSTL_II_18_S

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Table 17: 3.3V IOB High Range (HR) Switching Characteristics (Cont’d)

T

IOTP

IOPI

IOOP

Speed Grade

1.0V

Speed Grade

1.0V

Speed Grade

1.0V

I/O Standard

Units

0.9V

-3 -2/-2L -1 -1Q/-1M -2L

DIFF_HSTL_I_S

0.68 0.76 0.83

0.71 0.79 0.86

0.70 0.78 0.85

0.67 0.75 0.82

0.65 0.73 0.80

0.67 0.75 0.82

0.66 0.75 0.81

0.68 0.76 0.83

0.71 0.79 0.86

0.70 0.78 0.85

1.26 1.34 1.41

1.12 1.20 1.27

0.74 0.83 0.89

0.77 0.86 0.93

0.86

0.88

0.86

0.88

0.86

0.88

1.52

1.38

0.97

0.96

0.85 1.59 1.71 1.96

1.96

1.88

1.76

1.84

1.49

1.54

1.51

1.56

1.59

4.18

3.90

3.46

3.78

3.64

3.12

2.93

3.06

3.51

3.26

2.85

3.20

3.12

2.56

2.54

2.63

1.99

2.56

1.90

2.40

1.82

2.06

1.78

2.28

2.43

2.13 1.60 1.74 1.98

1.98

1.90

1.77

1.85

1.51

1.56

1.52

1.57

1.60

4.20

3.91

3.48

3.79

3.65

3.13

2.95

3.07

3.52

3.27

2.87

3.21

3.13

2.57

2.56

2.65

2.01

2.57

1.91

2.41

1.84

2.07

1.79

2.29

2.45

1.77

1.70

1.59

1.64

1.33

1.34

1.36

1.34

1.41

4.05

3.77

3.33

3.64

3.50

2.99

2.80

3.36

3.13

2.72

3.06

2.99

2.42

2.41

2.25

1.83

2.42

1.77

1.84

1.69

1.92

1.64

1.58

2.14

ns

DIFF_HSTL_II_S

DIFF_HSTL_I_18_S

DIFF_HSTL_II_18_S

HSTL_I_F

0.85 1.51 1.63 1.88

0.87 1.38 1.51 1.76

0.87 1.46 1.58 1.84

0.87 1.10 1.22 1.48

0.85 1.12 1.24 1.49

0.87 1.13 1.26 1.51

0.87 1.12 1.24 1.49

0.85 1.18 1.30 1.56

0.85 1.21 1.33 1.59

0.87 1.21 1.33 1.59

1.62 3.80 3.93 4.18

1.62 3.52 3.65 3.90

1.62 3.09 3.21 3.46

1.62 3.40 3.52 3.77

1.62 3.26 3.38 3.64

1.62 2.74 2.87 3.12

1.62 2.56 2.68 2.93

1.43 3.13 3.26 3.51

1.43 2.88 3.01 3.26

1.43 2.48 2.60 2.85

1.43 2.82 2.94 3.20

1.43 2.74 2.87 3.12

1.43 2.18 2.30 2.56

1.43 2.16 2.29 2.54

1.43 2.01 2.13 2.39

0.94 1.62 1.74 1.99

0.94 2.18 2.30 2.56

0.94 1.52 1.65 1.90

0.94 1.60 1.72 1.98

0.94 1.45 1.57 1.82

0.94 1.68 1.80 2.06

0.94 1.40 1.52 1.77

0.94 1.34 1.46 1.71

0.98 2.05 2.18 2.43

2.07 1.52 1.66 1.90

1.96 1.40 1.54 1.77

2.00 1.48 1.61 1.85

1.69 1.12 1.25 1.49

1.71 1.13 1.27 1.51

1.72 1.15 1.29 1.52

1.71 1.13 1.27 1.51

1.77 1.20 1.33 1.57

1.77 1.23 1.36 1.60

4.41 3.82 3.96 4.20

4.13 3.54 3.68 3.91

3.69 3.10 3.24 3.48

4.00 3.42 3.55 3.79

3.86 3.28 3.41 3.65

3.35 2.76 2.90 3.13

3.16 2.57 2.71 2.95

3.72 3.15 3.29 3.52

3.49 2.90 3.04 3.27

3.08 2.49 2.63 2.87

3.43 2.84 2.97 3.21

3.35 2.76 2.90 3.13

2.79 2.20 2.33 2.57

2.77 2.18 2.32 2.55

2.61 2.03 2.16 2.40

2.19 1.63 1.77 2.01

2.79 2.20 2.33 2.57

2.13 1.54 1.68 1.91

2.21 1.62 1.75 1.99

2.05 1.46 1.60 1.84

2.29 1.70 1.83 2.07

2.00 1.42 1.55 1.79

1.94 1.35 1.49 1.73

2.50 2.07 2.21 2.45

HSTL_II_F

HSTL_I_18_F

HSTL_II_18_F

DIFF_HSTL_I_F

DIFF_HSTL_II_F

DIFF_HSTL_I_18_F

DIFF_HSTL_II_18_F

LVCMOS33_S4

LVCMOS33_S8

LVCMOS33_S12

LVCMOS33_S16

LVCMOS33_F4

LVCMOS33_F8

LVCMOS33_F12

LVCMOS33_F16

LVCMOS25_S4

LVCMOS25_S8

LVCMOS25_S12

LVCMOS25_S16

LVCMOS25_F4

LVCMOS25_F8

LVCMOS25_F12

LVCMOS25_F16

LVCMOS18_S4

LVCMOS18_S8

LVCMOS18_S12

LVCMOS18_S16

LVCMOS18_S24

LVCMOS18_F4

LVCMOS18_F8

LVCMOS18_F12

LVCMOS18_F16

LVCMOS18_F24

LVCMOS15_S4

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Product Specification

15

Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Table 17: 3.3V IOB High Range (HR) Switching Characteristics (Cont’d)

T

IOTP

IOPI

IOOP

Speed Grade

1.0V

Speed Grade

1.0V

Speed Grade

1.0V

I/O Standard

Units

0.9V

-3 -2/-2L -1 -1Q/-1M -2L

LVCMOS15_S8

0.77 0.86 0.93

0.87 0.95 1.02

0.67 0.75 0.82

0.60 0.68 0.75

0.67 0.75 0.82

0.68 0.76 0.83

0.71 0.79 0.86

0.67 0.75 0.82

0.60 0.68 0.75

0.67 0.75 0.82

0.68 0.76 0.83

0.71 0.79 0.86

0.96

1.19

0.88

0.75

0.86

0.88

0.75

0.86

0.88

0.98 2.09 2.21 2.46

2.46

1.96

2.23

1.98

1.73

2.07

2.95

2.46

2.17

2.35

1.92

1.76

1.73

1.71

2.04

1.68

1.73

1.71

2.06

1.76

1.49

1.45

1.53

1.51

1.49

1.45

1.60

1.59

2.69 2.10 2.24 2.48

2.48

1.98

2.24

1.99

1.74

2.09

2.96

2.48

2.18

2.37

1.93

1.77

1.74

1.73

2.06

1.70

1.74

1.73

2.07

1.77

1.51

1.46

1.54

1.52

1.51

1.46

1.62

1.60

2.33

1.83

1.91

1.84

1.59

1.58

2.81

2.33

2.03

2.22

1.78

1.61

1.56

1.52

1.88

1.55

1.56

1.52

1.88

1.58

1.34

1.31

1.36

1.34

1.31

1.44

1.42

ns

LVCMOS15_S12

LVCMOS15_S16

LVCMOS15_F4

LVCMOS15_F8

LVCMOS15_F12

LVCMOS15_F16

LVCMOS12_S4

LVCMOS12_S8

LVCMOS12_S12

LVCMOS12_F4

LVCMOS12_F8

LVCMOS12_F12

SSTL135_S

0.98 1.59 1.71 1.96

0.98 1.85 1.97 2.23

0.98 1.60 1.72 1.98

0.98 1.35 1.47 1.73

0.98 1.34 1.46 1.71

1.08 2.57 2.69 2.95

1.08 2.09 2.21 2.46

1.08 1.79 1.91 2.17

1.08 1.98 2.10 2.35

1.08 1.54 1.66 1.92

1.08 1.38 1.51 1.76

0.87 1.35 1.47 1.73

0.80 1.30 1.43 1.68

0.87 1.67 1.79 2.04

0.85 1.31 1.43 1.68

0.87 1.35 1.47 1.73

0.87 1.30 1.43 1.68

0.87 1.68 1.80 2.06

0.87 1.38 1.51 1.76

0.87 1.12 1.24 1.49

0.80 1.07 1.19 1.45

0.87 1.12 1.24 1.49

0.85 1.12 1.24 1.49

0.87 1.12 1.24 1.49

0.87 1.07 1.19 1.45

0.87 1.23 1.35 1.60

0.87 1.21 1.33 1.59

2.19 1.60 1.74 1.98

2.27 1.87 2.00 2.24

2.21 1.62 1.75 1.99

1.96 1.37 1.50 1.74

1.94 1.35 1.49 1.73

3.18 2.59 2.72 2.96

2.69 2.10 2.24 2.48

2.40 1.81 1.94 2.18

2.58 1.99 2.13 2.37

2.15 1.56 1.69 1.93

1.97 1.40 1.54 1.77

1.93 1.37 1.50 1.74

1.88 1.32 1.46 1.69

2.24 1.68 1.82 2.06

1.91 1.32 1.46 1.70

1.93 1.37 1.50 1.74

1.88 1.32 1.46 1.69

2.24 1.70 1.83 2.07

1.94 1.40 1.54 1.77

1.71 1.13 1.27 1.51

1.68 1.09 1.22 1.46

1.72 1.13 1.27 1.51

1.71 1.13 1.27 1.51

1.68 1.09 1.22 1.46

1.80 1.24 1.38 1.62

1.79 1.23 1.36 1.60

SSTL15_S

SSTL18_I_S

SSTL18_II_S

DIFF_SSTL135_S

DIFF_SSTL15_S

DIFF_SSTL18_I_S

DIFF_SSTL18_II_S

SSTL135_F

SSTL15_F

SSTL18_I_F

SSTL18_II_F

DIFF_SSTL135_F

DIFF_SSTL15_F

DIFF_SSTL18_I_F

DIFF_SSTL18_II_F

Table 18 specifies the values of T

and T

. T

is described as the delay from the T pin to the IOB pad

IOTPHZ

IOIBUFDISABLE IOTPHZ

through the output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). T

is described

IOIBUFDISABLE

as the IOB delay from IBUFDISABLE to O output. In HR I/O banks, the internal IN_TERM termination turn-off time is always

faster than T when the INTERMDISABLE pin is used.

IOTPHZ

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Product Specification

16

Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Speed Grade

Table 18: IOB 3-state Output Switching Characteristics

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

2.19

-1

-1Q/-1M

2.37

T_IOTPHZ

T_{IOIBUFDISABLE}

T input to pad high-impedance

2.06

2.11

2.37

2.60

2.03

2.17

ns

IBUF turn-on time from IBUFDISABLE to O

output

2.30

2.60

Input/Output Logic Switching Characteristics

Table 19: ILOGIC Switching Characteristics

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

-1Q/-1M

Setup/Hold

T_ICE1CK/T_ICKCE1CE1 pin setup/hold with respect to CLK

0.48/0.02 0.54/0.02 0.76/0.02 0.76/0.02 0.50/–0.07

0.60/0.01 0.70/0.01 1.13/0.01 1.13/0.01 0.88/–0.35

0.01/0.27 0.01/0.29 0.01/0.33 0.01/0.33 0.01/0.33

ns

T

_ISRCK/T_ICKSR

_IDOCK/T_IOCKD

SR pin setup/hold with respect to CLK

D pin setup/hold with respect to CLK

without Delay

T_IDOCKD/T_IOCKDDDDLY pin setup/hold with respect to CLK

(using IDELAY)

0.02/0.27 0.02/0.29 0.02/0.33 0.02/0.33 0.01/0.33

ns

Combinatorial

T_IDI

D pin to O pin propagation delay, no Delay

0.11

0.12

0.13

0.14

0.13

0.14

0.15

ns

T_IDID

DDLY pin to O pin propagation delay (using

IDELAY)

Sequential Delays

T_IDLO

D pin to Q1 pin using flip-flop as a latch

without Delay

0.41

0.44

0.51

0.54

0.55

ns

T_IDLOD

DDLY pin to Q1 pin using flip-flop as a latch

(using IDELAY)

T_ICKQ

CLK to Q outputs

0.53

0.96

7.60

0.57

1.08

7.60

0.66

1.32

0.66

1.32

0.71

1.32

ns

T_{RQ_ILOGIC}

T_{GSRQ_ILOGIC}

Set/Reset

T_{RPW_ILOGIC}

SR pin to OQ/TQ out

Global set/reset to Q outputs

10.51

11.39

Minimum pulse width, SR inputs

0.61

0.72

ns, Min

Table 20: OLOGIC Switching Characteristics

Speed Grade

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

-1Q/-1M

Setup/Hold

_ODCK/T_OCKD

T

D1/D2 pins setup/hold with respect to CLK 0.67/–0.11 0.71/–0.11 0.84/–0.11 0.84/–0.06 0.64/0.03

0.32/0.58 0.34/0.58 0.51/0.58 0.51/0.58 0.28/0.01

ns

T_OOCECK/T_OCKOCEOCE pin setup/hold with respect to CLK

T_OSRCK/T_OCKSR

SR pin setup/hold with respect to CLK

0.37/0.21 0.44/0.21 0.80/0.21 0.80/0.21 0.62/–0.25 ns

T

_OTCK/T_OCKT

T1/T2 pins setup/hold with respect to CLK

0.69/–0.14 0.73/–0.14 0.89/–0.14 0.89/–0.11 0.66/0.02

0.32/0.01 0.34/0.01 0.51/0.01 0.51/0.10 0.24/0.05

ns

T_OTCECK/T_OCKTCETCE pin setup/hold with respect to CLK

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Speed Grade

Table 20: OLOGIC Switching Characteristics (Cont’d)

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

-1Q/-1M

Combinatorial

T_ODQ

D1 to OQ out or T1 to TQ out

0.83

0.96

1.16

1.36

ns

Sequential Delays

T_OCKQ

CLK to OQ/TQ out

0.47

0.72

7.60

0.49

0.80

7.60

0.56

0.95

0.56

0.95

0.63

1.12

ns

T_{RQ_OLOGIC}

T_{GSRQ_OLOGIC}

Set/Reset

SR pin to OQ/TQ out

Global set/reset to Q outputs

10.51

11.39

T_{RPW_OLOGIC}

Minimum pulse width, SR inputs

0.64

0.74

ns,

Min

Input Serializer/Deserializer Switching Characteristics

Table 21: ISERDES Switching Characteristics

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

-1Q/-1M

Setup/Hold for Control Lines

T_{ISCCK_BITSLIP}/ T_{ISCKC_BITSLIP}BITSLIP pin setup/hold with

respect to CLKDIV

0.01/0.14 0.02/0.15 0.02/0.17 0.02/0.17 0.02/0.21

ns

(2)

T_{ISCCK_CE}/ T_{ISCKC_CE}

CE pin setup/hold with respect to 0.45/–0.01 0.50/–0.01 0.72/–0.01 0.72/–0.01 0.45/–0.11

CLK (for CE1)

(2)

T_{ISCCK_CE2}/ T_{ISCKC_CE2}

CE pin setup/hold with respect to –0.10/0.33 –0.10/0.36 –0.10/0.40 –0.10/0.40 –0.17/0.40

CLKDIV (for CE2)

Setup/Hold for Data Lines

T

_{ISDCK_D}/T_{ISCKD_D}

D pin setup/hold with respect to –0.02/0.12 –0.02/0.14 –0.02/0.17 –0.02/0.17 –0.04/0.19

CLK

ns

_{ISDCK_DDLY}/T_{ISCKD_DDLY}

DDLY pin setup/hold with respect –0.02/0.12 –0.02/0.14 –0.02/0.17 –0.02/0.17 –0.03/0.19

to CLK (using IDELAY)⁽¹⁾

T_{ISDCK_D_DDR}/T_{ISCKD_D_DDR}D pin setup/hold with respect to –0.02/0.12 –0.02/0.14 –0.02/0.17 –0.02/0.17 –0.04/0.19

CLK at DDR mode

T_{ISDCK_DDLY_DDR}

T_{ISCKD_DDLY_DDR}

/

D pin setup/hold with respect to 0.12/0.12 0.14/0.14 0.17/0.17 0.17/0.17 0.19/0.19

CLK at DDR mode (using

IDELAY)⁽¹⁾

Sequential Delays

T_{ISCKO_Q}

CLKDIV to out at Q pin

D input to DO output pin

0.53

0.11

0.54

0.11

0.66

0.13

0.66

0.13

0.67

0.14

ns

Propagation Delays

T_{ISDO_DO}

Notes:

1. Recorded at 0 tap value.

2.

T

and T

are reported as T

/T

in the timing report.

ISCCK_CE2

ISCKC_CE2

ISCCK_CE ISCKC_CE

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Output Serializer/Deserializer Switching Characteristics

Table 22: OSERDES Switching Characteristics

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

-1Q/-1M

Setup/Hold

T_{OSDCK_D}/T_{OSCKD_D}

D input setup/hold with respect to

CLKDIV

0.42/0.03 0.45/0.03 0.63/0.03 0.63/0.08 0.44/–0.02

0.69/–0.13 0.73/–0.13 0.88/–0.13 0.88/–0.13 0.66/–0.25

0.31/–0.13 0.34/–0.13 0.39/–0.13 0.39/–0.13 0.46/–0.25

0.32/0.58 0.34/0.58 0.51/0.58 0.51/0.58 0.28/–0.04

ns

(1)

T_{OSDCK_T}/T_{OSCKD_T}

T input setup/hold with respect to

CLK

(1)

T_{OSDCK_T2}/T_{OSCKD_T2}

T input setup/hold with respect to

CLKDIV

T_{OSCCK_OCE}/T_{OSCKC_OCE}OCE input setup/hold with respect

to CLK

T_{OSCCK_S}

SR (reset) input setup with respect

to CLKDIV

0.47

0.52

0.85

0.70

T_{OSCCK_TCE}/T_{OSCKC_TCE}TCE input setup/hold with respect

0.32/0.01 0.34/0.01 0.51/0.01 0.51/0.10 0.24/0.00

to CLK

Sequential Delays

T_{OSCKO_OQ}

Clock to out from CLK to OQ

Clock to out from CLK to TQ

0.40

0.47

0.42

0.49

0.48

0.56

0.48

0.56

0.54

0.63

ns

T_{OSCKO_TQ}

Combinatorial

T_{OSDO_TTQ}

T input to TQ Out

0.83

0.92

1.11

1.18

ns

Notes:

1.

T

and T

are reported as T

/T

in the timing report.

OSDCK_T2

OSCKD_T2

OSDCK_T OSCKD_T

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Input/Output Delay Switching Characteristics

Table 23: Input/Output Delay Switching Characteristics

Speed Grade

Symbol

Description

1.0V

-1

0.9V

-2L

Units

-3

-2/-2L

-1Q/-1M

IDELAYCTRL

T_{DLYCCO_RDY}

Reset to ready for IDELAYCTRL

3.67

µs

F_{IDELAYCTRL_REF}

Attribute REFCLK

200.00

MHz

frequency = 200.00⁽¹⁾

Attribute REFCLK

300.00

400.00

300.00

400.00

300.00

N/A

300.00

N/A

300.00

N/A

MHz

frequency = 300.00⁽¹⁾

Attribute REFCLK

frequency = 400.00⁽¹⁾

IDELAYCTRL_REF_PRECISION

T_{IDELAYCTRL_RPW}

IDELAY

REFCLK precision

10

MHz

ns

Minimum Reset pulse width

59.28

T_{IDELAYRESOLUTION}

IDELAY chain delay resolution

1/(32 x 2 x F_REF

)

ps

Pattern dependent period jitter in

delay chain for clock pattern.⁽²⁾

0

5

0

5

0

5

ps

per tap

Pattern dependent period jitter in

delay chain for random data

pattern (PRBS 23)⁽³⁾

5

9

5

9

ps

per tap

T_{IDELAYPAT_JIT}

Pattern dependent period jitter in

delay chain for random data

pattern (PRBS 23)⁽⁴⁾

9

ps

per tap

T_{IDELAY_CLK_MAX}

Maximum frequency of CLK input

to IDELAY

680.00

600.00

520.00

MHz

ns

T_{IDCCK_CE}/ T_{IDCKC_CE}

T_{IDCCK_INC}/ T_{IDCKC_INC}

_{IDCCK_RST}/ T_{IDCKC_RST}

CE pin setup/hold with respect to 0.12/0.11 0.16/0.13 0.21/0.16 0.21/0.16 0.14/0.16

C for IDELAY

INC pin setup/hold with respect to 0.12/0.16 0.14/0.18 0.16/0.22 0.16/0.23 0.10/0.23

C for IDELAY

ns

T

RST pin setup/hold with respect 0.15/0.09 0.16/0.11 0.18/0.14 0.18/0.14 0.22/0.19

to C for IDELAY

ns

T_{IDDO_IDATAIN}

Propagation delay through

IDELAY

Note 5

ps

Notes:

1. Average Tap Delay at 200 MHz = 78 ps, at 300 MHz = 52 ps, and at 400 MHz = 39 ps.

2. When HIGH_PERFORMANCE mode is set to TRUE or FALSE.

3. When HIGH_PERFORMANCE mode is set to TRUE.

4. When HIGH_PERFORMANCE mode is set to FALSE.

5. Delay depends on IDELAY tap setting. See the timing report for actual values.

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Speed Grade

Table 24: IO_FIFO Switching Characteristics

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

-1Q/-1M

IO_FIFO Clock to Out Delays

T_{OFFCKO_DO}

RDCLK to Q outputs

0.55

0.60

0.61

0.68

0.77

0.68

0.77

0.81

0.79

ns

T_{CKO_FLAGS}

Clock to IO_FIFO flags

Setup/Hold

T

_{CCK_D}/T_{CKC_D}

D inputs to WRCLK

0.47/0.02 0.51/0.02 0.58/0.02 0.58/0.18 0.76/0.09

0.42/–0.01 0.47/–0.01 0.53/–0.01 0.53/–0.01 0.70/–0.05

0.53/0.02 0.58/0.02 0.66/0.02 0.66/0.02 0.79/–0.02

ns

T_{IFFCCK_WREN}/T_{IFFCKC_WREN}WREN to WRCLK

_{OFFCCK_RDEN}/T_{OFFCKC_RDEN}RDEN to RDCLK

T

Minimum Pulse Width

T_{PWH_IO_FIFO}

RESET, RDCLK, WRCLK

1.62

2.15

ns

T_{PWL_IO_FIFO}

Maximum Frequency

F_MAX

RDCLK and WRCLK

266.67

200.00

MHz

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

CLB Switching Characteristics

Table 25: CLB Switching Characteristics

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

-1Q/-1M

Combinatorial Delays

T_ILO

An – Dn LUT address to A

An – Dn LUT address to AMUX/CMUX

An – Dn LUT address to BMUX_A

An – Dn inputs to A – D Q outputs

AX inputs to AMUX output

AX inputs to BMUX output

AX inputs to CMUX output

AX inputs to DMUX output

BX inputs to BMUX output

BX inputs to DMUX output

CX inputs to CMUX output

CX inputs to DMUX output

DX inputs to DMUX output

0.10

0.27

0.42

0.94

0.62

0.58

0.60

0.68

0.51

0.62

0.42

0.53

0.52

0.11

0.30

0.46

1.05

0.69

0.66

0.68

0.75

0.57

0.69

0.48

0.59

0.58

0.13

0.36

0.55

1.27

0.84

0.83

0.82

0.90

0.69

0.82

0.58

0.71

0.70

0.13

0.36

0.55

1.27

0.84

0.83

0.82

0.90

0.69

0.82

0.58

0.71

0.70

0.15

0.41

0.65

1.51

1.01

0.98

1.08

0.82

0.99

0.69

0.86

0.84

ns, Max

T_{ILO_2}

T_{ILO_3}

T_ITO

T_AXA

T_AXB

T_AXC

T_AXD

T_BXB

T_BXD

T_CXC

T_CXD

T_DXD

Sequential Delays

T_CKO

Clock to AQ – DQ outputs

Clock to AMUX – DMUX outputs

0.40

0.47

0.44

0.53

0.66

0.53

0.66

0.62

0.73

ns, Max

T_SHCKO

Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK

A_N– D_Ninput to CLK on A – D flip-flops

A_X– D_Xinput to CLK on A – D flip-flops

0.07/0.12 0.09/0.14 0.11/0.18 0.11/0.28

0.06/0.19 0.07/0.21 0.09/0.26 0.09/0.35

0.59/0.08 0.66/0.09 0.81/0.11 0.81/0.20

T

_AS/T_AH

0.11/0.22

0.09/0.33

0.97/0.15

ns, Min

T

_DICK/T_CKDI

A_X– D_Xinput through MUXs and/or carry

logic to CLK on A – D flip-flops

CE input to CLK on A – D flip-flops

0.15/0.00 0.17/0.00 0.21/0.01 0.21/0.13

0.38/0.03 0.43/0.04 0.53/0.05 0.53/0.18

T_{CECK_CLB}

/

0.34/–0.01 ns, Min

T_{CKCE_CLB}

SR input to CLK on A – D flip-flops

T

_SRCK/T_CKSR

0.62/0.19

ns, Min

Set/Reset

T_SRMIN

T_RQ

SR input minimum pulse width

0.52

0.53

0.52

1412

0.78

0.59

0.58

1286

1.04

0.71

0.70

1098

1.04

0.71

0.70

1098

0.95

0.83

1098

ns, Min

ns, Max

MHz

Delay from SR input to AQ – DQ flip-flops

Delay from CE input to AQ – DQ flip-flops

Toggle frequency (for export control)

T_CEO

F_TOG

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

CLB Distributed RAM Switching Characteristics (SLICEM Only)

Table 26: CLB Distributed RAM Switching Characteristics

Speed Grade

Symbol

Description

1.0V

-1

0.9V

-2L

Units

-3

-2/-2L

-1Q/-1M

Sequential Delays

T_SHCKO

Clock to A – B outputs

Clock to AMUX – BMUX outputs

0.98

1.37

1.09

1.53

1.32

1.86

1.32

1.86

1.54

2.18

ns, Max

T_{SHCKO_1}

Setup and Hold Times Before/After Clock CLK

_{DS_LRAM}/T_{DH_LRAM}A – D inputs to CLK

T_{AS_LRAM}/T_{AH_LRAM}Address An inputs to clock

T

0.54/0.28 0.60/0.30 0.72/0.35 0.72/0.37 0.96/0.40 ns, Min

0.27/0.55 0.30/0.60 0.37/0.70 0.37/0.71 0.43/0.71 ns, Min

Address An inputs through MUXs and/or 0.69/0.18 0.77/0.21 0.94/0.26 0.94/0.35 1.11/0.31 ns, Min

carry logic to clock

T

_{WS_LRAM}/T_{WH_LRAM}WE input to clock

0.38/0.10 0.43/0.12 0.53/0.17 0.53/0.17 0.62/0.13 ns, Min

0.39/0.10 0.44/0.11 0.53/0.17 0.53/0.17 0.63/0.12 ns, Min

T_{CECK_LRAM}

T_{CKCE_LRAM}

/

CE input to CLK

Clock CLK

T_{MPW_LRAM}

T_MCP

Minimum pulse width

Minimum clock period

1.05

2.10

1.13

2.26

1.25

2.50

1.25

2.50

1.61

3.21

ns, Min

Notes:

1.

T

also represents the CLK to XMUX output. Refer to the timing report for the CLK to XMUX path.

SHCKO

CLB Shift Register Switching Characteristics (SLICEM Only)

Table 27: CLB Shift Register Switching Characteristics

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

-1Q/-1M

Sequential Delays

T_REG

Clock to A – D outputs

1.19

1.58

1.12

1.33

1.77

1.23

1.61

2.15

1.46

1.61

2.15

1.46

1.89

2.53

1.68

ns, Max

T_{REG_MUX}

T_{REG_M31}

Clock to AMUX – DMUX output

Clock to DMUX output via M31 output

Setup and Hold Times Before/After Clock CLK

0.37/0.10 0.41/0.12 0.51/0.17 0.51/0.17

0.37/0.10 0.42/0.11 0.52/0.17 0.52/0.17

0.33/0.34 0.37/0.37 0.44/0.43 0.44/0.44

T_{WS_SHFREG}

/

WE input

0.59/0.13

0.60/0.12

0.54/0.55

ns, Min

T_{WH_SHFREG}

T_{CECK_SHFREG}

T_{CKCE_SHFREG}

/

CE input to CLK

A – D inputs to CLK

T_{DS_SHFREG}

/

T_{DH_SHFREG}

Clock CLK

T_{MPW_SHFREG}

Minimum pulse width

0.77

0.86

0.98

1.22

ns, Min

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Product Specification

23

Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Block RAM and FIFO Switching Characteristics

Table 28: Block RAM and FIFO Switching Characteristics

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

-1Q/-1M

Block RAM and FIFO Clock-to-Out Delays

T_{RCKO_DO}and

T_{RCKO_DO_REG}

Clock CLK to DOUT output

1.85

0.64

2.77

2.13

0.74

3.04

2.46

0.89

3.84

2.46

0.89

3.84

2.87

1.02

5.30

ns, Max

(without output register)⁽²⁾⁽³⁾

(1)

Clock CLK to DOUT output

(with output register)⁽⁴⁾⁽⁵⁾

T_{RCKO_DO_ECC}and

Clock CLK to DOUT output with

ECC (without output

register)⁽²⁾⁽³⁾

T_{RCKO_DO_ECC_REG}

Clock CLK to DOUT output with

ECC (with output register)⁽⁴⁾⁽⁵⁾

0.73

2.61

0.81

2.88

0.94

3.30

0.94

3.30

1.11

3.76

ns, Max

T_{RCKO_DO_CASCOUT}and

T_{RCKO_DO_CASCOUT_REG}

Clock CLK to DOUT output with

cascade (without output

register)⁽²⁾

Clock CLK to DOUT output with

cascade (with output

register)⁽⁴⁾

1.16

1.28

1.46

1.56

ns, Max

T_{RCKO_FLAGS}

Clock CLK to FIFO flags

outputs⁽⁶⁾

0.76

0.94

0.78

2.56

0.68

0.75

0.87

1.02

0.85

2.81

0.76

0.88

1.05

1.15

0.94

3.55

0.89

1.07

1.05

1.15

0.94

3.55

0.89

1.07

1.14

1.30

1.10

4.90

1.05

1.15

ns, Max

T_{RCKO_POINTERS}

T_{RCKO_PARITY_ECC}

Clock CLK to FIFO pointers

outputs⁽⁷⁾

Clock CLK to ECCPARITY in

ECC encode only mode

T_{RCKO_SDBIT_ECC}and

T_{RCKO_SDBIT_ECC_REG}

Clock CLK to BITERR (without

output register)

Clock CLK to BITERR (with

output register)

T_{RCKO_RDADDR_ECC}and

T_{RCKO_RDADDR_ECC_REG}

Clock CLK to RDADDR output

with ECC (without output

register)

Clock CLK to RDADDR output

with ECC (with output register)

0.84

0.93

1.08

1.29

ns, Max

Setup and Hold Times Before/After Clock CLK

T_{RCCK_ADDRA}/T_{RCKC_ADDRA}

ADDR inputs⁽⁸⁾

0.45/0.31 0.49/0.33 0.57/0.36 0.57/0.52 0.77/0.45 ns, Min

0.58/0.60 0.65/0.63 0.74/0.67 0.74/0.67 0.92/0.76 ns, Min

T_{RDCK_DI_WF_NC}

/

Data input setup/hold time

when block RAM is configured

in WRITE_FIRST or

T_{RCKD_DI_WF_NC}

NO_CHANGE mode⁽⁹⁾

T_{RDCK_DI_RF}/T_{RCKD_DI_RF}

Data input setup/hold time

when block RAM is configured

in READ_FIRST mode⁽⁹⁾

0.20/0.29 0.22/0.34 0.25/0.41 0.25/0.50 0.29/0.38 ns, Min

T_{RDCK_DI_ECC}/T_{RCKD_DI_ECC}

DIN inputs with block RAM

ECC in standard mode⁽⁹⁾

0.50/0.43 0.55/0.46 0.63/0.50 0.63/0.50 0.78/0.54 ns, Min

0.93/0.43 1.02/0.46 1.17/0.50 1.17/0.50 1.38/0.48 ns, Min

1.04/0.56 1.15/0.59 1.32/0.64 1.32/0.64 1.55/0.77 ns, Min

T_{RDCK_DI_ECCW}

/

DIN inputs with block RAM

ECC encode only⁽⁹⁾

T_{RCKD_DI_ECCW}

T_{RDCK_DI_ECC_FIFO}

/

DIN inputs with FIFO ECC in

standard mode⁽⁹⁾

T_{RCKD_DI_ECC_FIFO}

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Product Specification

24

Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Table 28: Block RAM and FIFO Switching Characteristics (Cont’d)

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

-1Q/-1M

T_{RCCK_INJECTBITERR}

/

Inject single/double bit error in 0.58/0.35 0.64/0.37 0.74/0.40 0.74/0.52 0.92/0.48 ns, Min

ECC mode

T_{RCKC_INJECTBITERR}

T_{RCCK_EN}/T_{RCKC_EN}

Block RAM enable (EN) input

CE input of output register

0.35/0.20 0.39/0.21 0.45/0.23 0.45/0.41 0.57/0.26 ns, Min

0.24/0.15 0.29/0.15 0.36/0.16 0.36/0.39 0.40/0.19 ns, Min

0.29/0.07 0.32/0.07 0.35/0.07 0.35/0.17 0.41/0.07 ns, Min

0.32/0.42 0.34/0.43 0.36/0.46 0.36/0.57 0.40/0.47 ns, Min

T_{RCCK_REGCE}/T_{RCKC_REGCE}

T_{RCCK_RSTREG}/T_{RCKC_RSTREG}Synchronous RSTREG input

T_{RCCK_RSTRAM}/T_{RCKC_RSTRAM}Synchronous RSTRAM input

T_{RCCK_WEA}/T_{RCKC_WEA}

Write enable (WE) input (block 0.44/0.18 0.48/0.19 0.54/0.20 0.54/0.42 0.64/0.23 ns, Min

RAM only)

T_{RCCK_WREN}/T_{RCKC_WREN}

T_{RCCK_RDEN}/T_{RCKC_RDEN}

Reset Delays

WREN FIFO inputs

RDEN FIFO inputs

0.46/0.30 0.46/0.35 0.47/0.43 0.47/0.43 0.77/0.44 ns, Min

0.42/0.30 0.43/0.35 0.43/0.43 0.43/0.62 0.71/0.50 ns, Min

T_{RCO_FLAGS}

Reset RST to FIFO

flags/pointers⁽¹⁰⁾

0.90

0.98

1.10

1.25

ns, Max

T_{RREC_RST}/T_{RREM_RST}

FIFO reset recovery and

removal timing⁽¹¹⁾

1.87/–0.81 2.07/–0.81 2.37/–0.81 2.37/–0.58 2.44/–0.71 ns, Max

Maximum Frequency

F_{MAX_BRAM_WF_NC}

Block RAM (write first and no

change modes) when not in

SDP RF mode

509.68

460.83

388.20

315.66

MHz

F_{MAX_BRAM_RF_PERFORMANCE}

Block RAM (read first,

performance mode) when in

SDP RF mode but no address

overlap between port A and

port B

F_{MAX_BRAM_RF_DELAYED_WRITE}Block RAM (read first, delayed

write mode) when in SDP RF

447.63

404.53

339.67

268.96

MHz

mode and there is possibility of

overlap between port A and

port B addresses

F_{MAX_CAS_WF_NC}

Block RAM cascade (write first,

no change mode) when

cascade but not in RF mode

467.07

418.59

345.78

273.30

MHz

F_{MAX_CAS_RF_PERFORMANCE}

Block RAM cascade (read first,

performance mode) when in

cascade with RF mode and no

possibility of address

overlap/one port is disabled

F_{MAX_CAS_RF_DELAYED_WRITE}

When in cascade RF mode and

there is a possibility of address

overlap between port A and

port B

405.35

362.19

297.35

226.60

MHz

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Product Specification

25

Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Table 28: Block RAM and FIFO Switching Characteristics (Cont’d)

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

FIFO in all modes without ECC 509.68

-2/-2L

460.83

365.10

-1

-1Q/-1M

388.20

297.53

F_{MAX_FIFO}

F_{MAX_ECC}

388.20

297.53

315.66

215.38

MHz

Block RAM and FIFO in ECC

configuration

410.34

Notes:

1. The timing report shows all of these parameters as T

.

RCKO_DO

2.

3. These parameters also apply to synchronous FIFO with DO_REG = 0.

4. includes T as well as the B port equivalent timing parameters.

5. These parameters also apply to multirate (asynchronous) and synchronous FIFO with DO_REG = 1.

T

includes T

, T

, and T

as well as the B port equivalent timing parameters.

RCKO_DOR

RCKO_DOW RCKO_DOPR

RCKO_DOPW

T

RCKO_DO

RCKO_DOP

6.

7.

T

includes the following parameters: T

, T , T , T , T , T

RCKO_FLAGS

RCKO_AEMPTY RCKO_AFULL RCKO_EMPTY RCKO_FULL RCKO_RDERR RCKO_WRERR.

includes both T

and T

RCKO_POINTERS

RCKO_RDCOUNT

RCKO_WRCOUNT.

8. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible.

9. These parameters include both A and B inputs as well as the parity inputs of A and B.

10. T

includes the following flags: AEMPTY, AFULL, EMPTY, FULL, RDERR, WRERR, RDCOUNT, and WRCOUNT.

RCO_FLAGS

11. RDEN and WREN must be held Low prior to and during reset. The FIFO reset must be asserted for at least five positive clock edges of the

slowest clock (WRCLK or RDCLK).

DS181 (v1.13) May 13, 2014

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Product Specification

26

Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

DSP48E1 Switching Characteristics

Table 29: DSP48E1 Switching Characteristics

Speed Grade

1.0V

-1

Symbol

Description

0.9V Units

-2L

-3

-2/-2L

-1Q/-1M

Setup and Hold Times of Data/Control Pins to the Input Register Clock

T_{DSPDCK_A_AREG}

/

A input to A register CLK

B input to B register CLK

C input to C register CLK

D input to D register CLK

ACIN input to A register CLK

BCIN input to B register CLK

0.26/

0.12

0.30/

0.13

0.37/

0.14

0.37/

0.28

0.45/

0.14

ns

T_{DSPCKD_A_AREG}

T_{DSPDCK_B_BREG}

T_{DSPCKD_B_BREG}

/

0.33/

0.15

0.38/

0.16

0.45/

0.18

0.45/

0.25

0.60/

0.19

T_{DSPDCK_C_CREG}

T_{DSPCKD_C_CREG}

/

0.17/

0.17

0.20/

0.19

0.24/

0.21

0.24/

0.26

0.34/

0.29

T_{DSPDCK_D_DREG}

T_{DSPCKD_D_DREG}

0.25/

0.25

0.32/

0.27

0.42/

0.27

0.42/

0.42

0.54/

0.23

T_{DSPDCK_ACIN_AREG}

T_{DSPCKD_ACIN_AREG}

/

0.23/

0.12

0.27/

0.13

0.32/

0.14

0.32/

0.17

0.36/

0.14

T_{DSPDCK_BCIN_BREG}

T_{DSPCKD_BCIN_BREG}

/

0.25/

0.15

0.29/

0.16

0.36/

0.18

0.36/

0.18

0.41/

0.19

Setup and Hold Times of Data Pins to the Pipeline Register Clock

T_{DSPDCK_ A, B _MREG_MULT}

/

{A, B} input to M register CLK using

multiplier

2.40/

2.76/

3.29/

–0.01

4.31/

–0.07

ns

{

}

T_{DSPCKD_{A, B}_MREG_MULT}

–0.01 –0.01 –0.01

T_{DSPDCK_ A, D _ADREG}

/

{A, D} input to AD register CLK

1.29/ 1.48/ 1.76/

–0.02 –0.02 –0.02

1.76/

–0.02

2.29/

–0.27

{

}

T_{DSPCKD_{A, D}_ADREG}

Setup and Hold Times of Data/Control Pins to the Output Register Clock

T_{DSPDCK_{A, B}_PREG_MULT}

/

{A, B} input to P register CLK using

multiplier

4.02/

4.60/

5.48/

–0.28

6.95/

–0.48

ns

T_{DSPCKD_{A, B} _PREG_MULT}

–0.28 –0.28 –0.28

T_{DSPDCK_D_PREG_MULT}

T_{DSPCKD_D_PREG_MULT}

/

D input to P register CLK using

multiplier

3.93/ 4.50/ 5.35/

–0.73 –0.73 –0.73

5.35/

–0.73

6.73/

–1.68

T_{DSPDCK_{A, B} _PREG}

/

A or B input to P register CLK not using 1.73/

multiplier

1.98/ 2.35/

2.35/

–0.28

2.80/

–0.48

T_{DSPCKD_{A, B} _PREG}

–0.28 –0.28 –0.28

T_{DSPDCK_C_PREG}

T_{DSPCKD_C_PREG}

/

C input to P register CLK not using

multiplier

1.54/ 1.76/ 2.10/

2.10/

–0.26

2.54/

–0.45

–0.26 –0.26 –0.26

1.32/ 1.51/ 1.80/

T_{DSPDCK_PCIN_PREG}

/

PCIN input to P register CLK

1.80/

–0.15

2.13/

–0.25

T_{DSPCKD_PCIN_PREG}

–0.15 –0.15 –0.15

Setup and Hold Times of the CE Pins

T_{DSPDCK_{CEA;CEB}_{AREG;BREG}}

/

{CEA; CEB} input to {A; B} register CLK 0.35/

0.06

0.42/

0.08

0.52/

0.11

0.52/

0.11

0.64/

0.11

ns

T_{DSPCKD_{CEA;CEB}_{AREG;BREG}}

T_{DSPDCK_CEC_CREG}

/

CEC input to C register CLK

CED input to D register CLK

CEM input to M register CLK

CEP input to P register CLK

0.28/

0.10

0.34/

0.11

0.42/

0.13

0.42/

0.13

0.49/

0.16

T_{DSPCKD_CEC_CREG}

T_{DSPDCK_CED_DREG}

T_{DSPCKD_CED_DREG}

0.36/

0.43/

0.52/

–0.03

0.68/

0.14

–0.03 –0.03 –0.03

T_{DSPDCK_CEM_MREG}

T_{DSPCKD_CEM_MREG}

/

0.17/

0.18

0.21/

0.20

0.27/

0.23

0.27/

0.23

0.45/

0.29

T_{DSPDCK_CEP_PREG}

/

0.36/

0.01

0.43/

0.01

0.53/

0.01

0.53/

0.01

0.63/

0.00

T_{DSPCKD_CEP_PREG}

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Product Specification

27

Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Speed Grade

Table 29: DSP48E1 Switching Characteristics (Cont’d)

Symbol

Description

1.0V

-1

0.9V Units

-2L

-3

-2/-2L

-1Q/-1M

Setup and Hold Times of the RST Pins

T_{DSPDCK_{RSTA; RSTB}_{AREG; BREG}}

/

{RSTA, RSTB} input to {A, B} register

CLK

0.41/

0.11

0.46/

0.13

0.55/

0.15

0.55/

0.24

0.63/

0.40

ns

T_{DSPCKD_{RSTA; RSTB}_{AREG; BREG}}

T_{DSPDCK_RSTC_CREG}

/

RSTC input to C register CLK

RSTD input to D register CLK

RSTM input to M register CLK

RSTP input to P register CLK

0.07/

0.10

0.08/

0.11

0.09/

0.12

0.09/

0.25

0.13/

0.11

T_{DSPCKD_RSTC_CREG}

T_{DSPDCK_RSTD_DREG}

T_{DSPCKD_RSTD_DREG}

0.44/

0.07

0.50/

0.08

0.59/

0.09

0.59/

0.09

0.67/

0.08

T_{DSPDCK_RSTM_MREG}

/

0.21/

0.22

0.23/

0.24

0.27/

0.28

0.27/

0.28

0.28/

0.35

T_{DSPCKD_RSTM_MREG}

T_{DSPDCK_RSTP_PREG}

/

0.27/

0.01

0.30/

0.01

0.35/

0.01

0.35/

0.03

0.43/

0.00

T_{DSPCKD_RSTP_PREG}

Combinatorial Delays from Input Pins to Output Pins

T_{DSPDO_A_CARRYOUT_MULT}

A input to CARRYOUT output using

multiplier

3.79

4.35

5.18

6.61

ns

T_{DSPDO_D_P_MULT}

T_{DSPDO_B_P}

D input to P output using multiplier

B input to P output not using multiplier

C input to P output

3.72

1.53

1.33

4.26

1.75

1.53

5.07

2.08

1.82

5.07

2.08

1.82

6.41

2.48

2.22

ns

T_{DSPDO_C_P}

Combinatorial Delays from Input Pins to Cascading Output Pins

T_{DSPDO_{A; B}_{ACOUT; BCOUT}}

{A, B} input to {ACOUT, BCOUT} output 0.55

0.63

4.65

0.74

5.54

0.74

5.54

0.87

7.03

ns

T_{DSPDO_{A, B}_CARRYCASCOUT_MULT}

{A, B} input to CARRYCASCOUT

output using multiplier

4.06

3.97

1.77

1.58

T_{DSPDO_D_CARRYCASCOUT_MULT}

T_{DSPDO_{A, B}_CARRYCASCOUT}

T_{DSPDO_C_CARRYCASCOUT}

D input to CARRYCASCOUT output

using multiplier

4.54

2.03

1.81

5.40

2.41

2.15

5.40

2.41

2.15

6.81

2.88

2.62

ns

{A, B} input to CARRYCASCOUT

output not using multiplier

C input to CARRYCASCOUT output

Combinatorial Delays from Cascading Input Pins to All Output Pins

T_{DSPDO_ACIN_P_MULT}

T_{DSPDO_ACIN_P}

ACIN input to P output using multiplier

3.65

1.37

4.19

1.57

5.00

1.88

5.00

1.88

6.40

2.44

ns

ACIN input to P output not using

multiplier

T_{DSPDO_ACIN_ACOUT}

ACIN input to ACOUT output

0.38

3.90

0.44

4.47

0.53

5.33

0.53

5.33

0.63

6.79

ns

T_{DSPDO_ACIN_CARRYCASCOUT_MULT}

ACIN input to CARRYCASCOUT output

using multiplier

T_{DSPDO_ACIN_CARRYCASCOUT}

ACIN input to CARRYCASCOUT output

not using multiplier

1.61

1.85

2.21

2.84

ns

T_{DSPDO_PCIN_P}

PCIN input to P output

1.11

1.28

1.56

1.52

1.85

1.52

1.85

1.82

2.21

ns

T_{DSPDO_PCIN_CARRYCASCOUT}

PCIN input to CARRYCASCOUT output 1.36

Clock to Outs from Output Register Clock to Output Pins

T_{DSPCKO_P_PREG}

CLK PREG to P output

0.33

0.52

0.37

0.59

0.44

0.69

0.44

0.69

0.54

0.84

ns

T_{DSPCKO_CARRYCASCOUT_PREG}

CLK PREG to CARRYCASCOUT

output

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Product Specification

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Speed Grade

Table 29: DSP48E1 Switching Characteristics (Cont’d)

Symbol

Description

1.0V

-1

0.9V Units

-2L

-3

-2/-2L

-1Q/-1M

Clock to Outs from Pipeline Register Clock to Output Pins

T_{DSPCKO_P_MREG}

CLK MREG to P output

1.68

1.92

1.93

2.21

2.31

2.64

2.31

2.64

2.73

3.12

ns

T_{DSPCKO_CARRYCASCOUT_MREG}

CLK MREG to CARRYCASCOUT

output

T_{DSPCKO_P_ADREG_MULT}

CLK ADREG to P output using

multiplier

2.72

2.96

3.10

3.38

3.69

4.02

3.69

4.02

4.60

4.99

ns

T_{DSPCKO_CARRYCASCOUT_ADREG_MULT}CLK ADREG to CARRYCASCOUT

output using multiplier

Clock to Outs from Input Register Clock to Output Pins

T_{DSPCKO_P_AREG_MULT}

T_{DSPCKO_P_BREG}

CLK AREG to P output using multiplier

3.94

1.64

4.51

1.87

5.37

2.22

5.37

2.22

6.84

2.65

ns

CLK BREG to P output not using

multiplier

T_{DSPCKO_P_CREG}

CLK CREG to P output not using

multiplier

1.69

3.91

1.93

4.48

2.30

5.32

2.30

5.32

2.81

6.77

ns

T_{DSPCKO_P_DREG_MULT}

CLK DREG to P output using multiplier

Clock to Outs from Input Register Clock to Cascading Output Pins

T_{DSPCKO_{ACOUT; BCOUT}_{AREG; BREG}}CLK (ACOUT, BCOUT) to {A,B} register

output

0.64

4.19

0.73

4.79

0.87

5.70

0.87

5.70

1.02

7.24

ns

T_{DSPCKO_CARRYCASCOUT_{AREG,}

CLK (AREG, BREG) to

CARRYCASCOUT output using

multiplier

BREG}_MULT

T_{DSPCKO_CARRYCASCOUT_ BREG}

CLK BREG to CARRYCASCOUT

output not using multiplier

1.88

4.16

1.94

2.15

4.76

2.21

2.55

5.65

2.63

2.55

5.65

2.63

3.04

7.17

3.20

ns

T_{DSPCKO_CARRYCASCOUT_ DREG_MULT}CLK DREG to CARRYCASCOUT

output using multiplier

T_{DSPCKO_CARRYCASCOUT_ CREG}

CLK CREG to CARRYCASCOUT

output

Maximum Frequency

F_MAX

With all registers used

628.93 550.66 464.25 464.25 363.77 MHz

531.63 465.77 392.93 392.93 310.08 MHz

349.28 305.62 257.47 257.47 210.44 MHz

317.26 277.62 233.92 233.92 191.28 MHz

F_{MAX_PATDET}

With pattern detector

F_{MAX_MULT_NOMREG}

F_{MAX_MULT_NOMREG_PATDET}

Two register multiply without MREG

with pattern detect

F_{MAX_PREADD_MULT_NOADREG}

Without ADREG

397.30 346.26 290.44 290.44 223.26 MHz

260.01 227.01 190.69 190.69 150.13 MHz

F_{MAX_PREADD_MULT_NOADREG_PATDET}Without ADREG with pattern detect

F_{MAX_NOPIPELINEREG}

Without pipeline registers (MREG,

ADREG)

F_{MAX_NOPIPELINEREG_PATDET}

Without pipeline registers (MREG,

ADREG) with pattern detect

241.72 211.15 177.43 177.43 140.10 MHz

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Clock Buffers and Networks

Table 30: Global Clock Switching Characteristics (Including BUFGCTRL)

Speed Grade

Symbol

Description

1.0V

-1

0.9V

-2L

Units

-3

-2/-2L

-1Q/-1M

(1)

T_{BCCCK_CE}/T_{BCCKC_CE}

CE pins setup/hold

0.12/0.39 0.13/0.40 0.16/0.41 0.16/0.83 0.31/0.67

ns

(1)

T_{BCCCK_S}/T_{BCCKC_S}

S pins setup/hold

(2)

T_{BCCKO_O}

BUFGCTRL delay from I0/I1 to O

0.08

0.09

0.10

0.14

Maximum Frequency

F_{MAX_BUFG}

Global clock tree (BUFG)

628.00

464.00

394.00

MHz

Notes:

1.

T

and T

must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These

BCCCK_CE

BCCKC_CE

parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are

optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between

clocks.

2.

T

(BUFG delay from I0 to O) values are the same as T

values.

BCCKO_O

BGCKO_O

Table 31: Input/Output Clock Switching Characteristics (BUFIO)

Speed Grade

Symbol

Description

Clock to out delay from I to O

I/O clock tree (BUFIO)

1.0V

-1

0.9V

-2L

Units

ns

-3

-2/-2L

-1Q/-1M

T_{BIOCKO_O}

1.11

1.26

1.54

1.56

Maximum Frequency

F_{MAX_BUFIO}

680.00

600.00

MHz

Table 32: Regional Clock Buffer Switching Characteristics (BUFR)

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

0.76

-1

-1Q/-1M

0.99

T_{BRCKO_O}

Clock to out delay from I to O

0.64

0.34

0.99

0.52

1.24

0.72

ns

Clock to out delay from I to O with

Divide Bypass attribute set

0.39

0.52

T_{BRCKO_O_BYP}

T_{BRDO_O}

Propagation delay from CLR to O

0.81

0.85

1.09

0.96

ns

Maximum Frequency

(1)

F_{MAX_BUFR}

Regional clock tree (BUFR)

420.00

375.00

315.00

MHz

Notes:

1. The maximum input frequency to the BUFR and BUFMR is the BUFIO F

frequency.

MAX

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Table 33: Horizontal Clock Buffer Switching Characteristics (BUFH)

Speed Grade

Symbol

Description

1.0V

-1

0.9V

-2L

Units

-3

-2/-2L

-1Q/-1M

T_{BHCKO_O}

BUFH delay from I to O

CE pin setup and hold

0.10

0.11

0.13

0.16

ns

T_{BHCCK_CE}/T_{BHCKC_CE}

Maximum Frequency

F_{MAX_BUFH}

0.19/0.13 0.22/0.15 0.28/0.21 0.28/0.42 0.35/0.25

Horizontal clock buffer (BUFH)

628.00

464.00

394.00

MHz

Table 34: Duty Cycle Distortion and Clock-Tree Skew

Speed Grade

1.0V

Symbol

Description

Device

0.9V

-2L

Units

-3

-2/-2L

-1

-1Q/-1M

T_{DCD_CLK}

T_CKSKEW

Global clock tree duty-cycle distortion⁽¹⁾

Global clock tree skew⁽²⁾

All

0.20

0.26

0.27

0.40

N/A

0.14

0.03

0.18

0.20

0.26

0.33

0.48

0.20

0.26

0.36

0.54

N/A

0.25

0.33

0.48

0.69

N/A

0.14

0.03

0.18

ns

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

XA7A35T

XA7A50T

XA7A75T

XA7A100T

XQ7A50T

XQ7A100T

XQ7A200T

All

0.33

0.36

0.33

0.48

0.14

0.03

0.18

0.36

0.54

0.14

0.03

0.18

0.36

0.54

0.14

0.03

0.18

T_{DCD_BUFIO}I/O clock tree duty cycle distortion

T_BUFIOSKEWI/O clock tree skew across one clock region All

T_{DCD_BUFR}

Regional clock tree duty cycle distortion

All

Notes:

1. These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to

calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times.

2. The T

value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree

CKSKEW

skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx Timing Analyzer

tools to evaluate clock skew specific to your application.

MMCM Switching Characteristics

Table 35: MMCM Specification

Speed Grade

Symbol

Description

1.0V

-2/-2L

800.00

10.00

0.9V

-2L

Units

-3

-1

MMCM_F_INMAX

MMCM_F_INMIN

MMCM_F_INJITTER

Maximum input clock frequency

Minimum input clock frequency

Maximum input clock period jitter

800.00

10.00

800.00

10.00

800.00

10.00

MHz

< 20ꢀ of clock input period or 1 ns Max

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Speed Grade

Table 35: MMCM Specification (Cont’d)

Symbol

Description

1.0V

-2/-2L

25

0.9V

-2L

Units

-3

25

-1

25

MMCM_F_INDUTY

Allowable input duty cycle: 10—49 MHz

Allowable input duty cycle: 50—199 MHz

Allowable input duty cycle: 200—399 MHz

Allowable input duty cycle: 400—499 MHz

Allowable input duty cycle: >500 MHz

Minimum dynamic phase-shift clock frequency

Maximum dynamic phase-shift clock frequency

Minimum MMCM VCO frequency

25

ꢀ

30

35

ꢀ

40

ꢀ

45

ꢀ

MMCM_F_{MIN_PSCLK}

MMCM_F_{MAX_PSCLK}

MMCM_F_VCOMIN

0.01

550.00

600.00

0.01

500.00

600.00

0.01

450.00

600.00

0.01

450.00

600.00

MHz

ns

MMCM_F_VCOMAX

MMCM_F_BANDWIDTH

Maximum MMCM VCO frequency

1600.00 1440.00 1200.00 1200.00

Low MMCM bandwidth at typical⁽¹⁾

1.00

4.00

0.12

1.00

4.00

0.12

1.00

4.00

1.00

4.00

0.12

High MMCM bandwidth at typical⁽¹⁾

MMCM_T_{STATPHAOFFSET}Static phase offset of the MMCM outputs⁽²⁾

0.12

MMCM_T_OUTJITTER

MMCM_T_OUTDUTY

MMCM_T_LOCKMAX

MMCM_F_OUTMAX

MMCM_F_OUTMIN

MMCM output jitter

Note 3

0.20

MMCM output clock duty-cycle precision⁽⁴⁾

MMCM maximum lock time

0.20

100.00

800.00

4.69

0.20

100.00

800.00

4.69

0.25

100.00

800.00

4.69

ns

µs

100.00

800.00

4.69

MMCM maximum output frequency

MMCM minimum output frequency⁽⁵⁾⁽⁶⁾

External clock feedback variation

Minimum reset pulse width

MHz

MMCM_T_EXTFDVAR

MMCM_RST_MINPULSE

MMCM_F_PFDMAX

< 20ꢀ of clock input period or 1 ns Max

5.00

ns

Maximum frequency at the phase frequency

detector

550.00

500.00

450.00

MHz

MMCM_F_PFDMIN

MMCM_T_FBDELAY

Minimum frequency at the phase frequency

detector

10.00

MHz

Maximum delay in the feedback path

3 ns Max or one CLKIN cycle

MMCM Switching Characteristics Setup and Hold

T_{MMCMDCK_PSEN}Setup and hold of phase-shift enable

/

1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00

ns

T_{MMCMCKD_PSEN}

T_{MMCMDCK_PSINCDEC}

/

Setup and hold of phase-shift increment/decrement 1.04/0.00 1.04/0.00 1.04/0.00 1.04/0.00

T_{MMCMCKD_PSINCDEC}

T_{MMCMCKO_PSDONE}

Phase shift clock-to-out of PSDONE 0.59 0.68 0.81 0.78

Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK

T_{MMCMDCK_DADDR}

/

DADDR setup/hold

1.25/0.15 1.40/0.15 1.63/0.15 1.43/0.00 ns, Min

1.76/0.00 1.97/0.00 2.29/0.00 2.40/0.00 ns, Min

1.25/0.15 1.40/0.15 1.63/0.15 1.43/0.00 ns, Min

T_{MMCMCKD_DADDR}

T_{MMCMDCK_DI}

T_{MMCMCKD_DI}

/

DI setup/hold

T_{MMCMDCK_DEN}

/

DEN setup/hold

DWE setup/hold

CLK to out of DRDY

T_{MMCMCKD_DEN}

T_{MMCMDCK_DWE}

/

T_{MMCMCKD_DWE}

T_{MMCMCKO_DRDY}

0.65

0.72

0.99

ns, Max

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Speed Grade

Table 35: MMCM Specification (Cont’d)

Symbol

Description

1.0V

-2/-2L

200.00

0.9V

-2L

Units

-3

-1

F_DCK

DCLK frequency

200.00

100.00 MHz, Max

Notes:

1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.

2. The static offset is measured between any MMCM outputs with identical phase.

3. Values for this parameter are available in the Clocking Wizard.

See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.

4. Includes global clock buffer.

5. Calculated as F

/128 assuming output duty cycle is 50ꢀ.

VCO

6. When CLKOUT4_CASCADE = TRUE, MMCM_F

is 0.036 MHz.

OUTMIN

PLL Switching Characteristics

Table 36: PLL Specification

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

800.00

19.00

-1

PLL_F_INMAX

Maximum input clock frequency

Minimum input clock frequency

Maximum input clock period jitter

800.00

19.00

800.00

19.00

800.00

19.00

MHz

PLL_F_INMIN

PLL_F_INJITTER

PLL_F_INDUTY

< 20ꢀ of clock input period or 1 ns Max

Allowable input duty cycle: 19—49 MHz

Allowable input duty cycle: 50—199 MHz

Allowable input duty cycle: 200—399 MHz

Allowable input duty cycle: 400—499 MHz

Allowable input duty cycle: >500 MHz

Minimum PLL VCO frequency

25

30

25

30

25

30

25

30

ꢀ

35

ꢀ

40

ꢀ

45

ꢀ

PLL_F_VCOMIN

800.00

MHz

ns

PLL_F_VCOMAX

PLL_F_BANDWIDTH

Maximum PLL VCO frequency

Low PLL bandwidth at typical⁽¹⁾

High PLL bandwidth at typical⁽¹⁾

Static phase offset of the PLL outputs⁽²⁾

PLL output jitter

2133.00 1866.00 1600.00 1600.00

1.00

4.00

0.12

1.00

4.00

0.12

1.00

4.00

1.00

4.00

0.12

PLL_T_{STATPHAOFFSET}

PLL_T_OUTJITTER

PLL_T_OUTDUTY

PLL_T_LOCKMAX

PLL_F_OUTMAX

0.12

Note 3

0.20

PLL output clock duty-cycle precision⁽⁴⁾

PLL maximum lock time

0.20

100.00

800.00

6.25

0.20

100.00

800.00

6.25

0.25

100.00

800.00

6.25

ns

µs

100.00

800.00

6.25

PLL maximum output frequency

PLL minimum output frequency⁽⁵⁾

External clock feedback variation

Minimum reset pulse width

MHz

PLL_F_OUTMIN

PLL_T_EXTFDVAR

PLL_RST_MINPULSE

PLL_F_PFDMAX

< 20ꢀ of clock input period or 1 ns Max

5.00

500.00

19.00

5.00

450.00

19.00

5.00

450.00

19.00

ns

Maximum frequency at the phase frequency detector 550.00

MHz

PLL_F_PFDMIN

Minimum frequency at the phase frequency detector

Maximum delay in the feedback path

19.00

PLL_T_FBDELAY

3 ns Max or one CLKIN cycle

Dynamic Reconfiguration Port (DRP) for PLL Before and After DCLK

T_{PLLDCK_DADDR}Setup and hold of D address

/

1.25/0.15 1.40/0.15 1.63/0.15 1.43/0.00 ns, Min

T_{PLLCKD_DADDR}

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Speed Grade

Table 36: PLL Specification (Cont’d)

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

T_{PLLDCK_DI}/T_{PLLCKD_DI}Setup and hold of D input

1.25/0.15 1.40/0.15 1.63/0.15 1.43/0.00 ns, Min

1.76/0.00 1.97/0.00 2.29/0.00 2.40/0.00 ns, Min

T_{PLLDCK_DEN}

/

Setup and hold of D enable

T_{PLLCKD_DEN}

T_{PLLDCK_DWE}

T_{PLLCKD_DWE}

/

Setup and hold of D write enable

1.25/0.15 1.40/0.15 1.63/0.15 1.43/0.00 ns, Min

T_{PLLCKO_DRDY}

F_DCK

CLK to out of DRDY

DCLK frequency

0.65

0.72

0.99

ns, Max

200.00

100.00 MHz, Max

Notes:

1. The PLL does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.

2. The static offset is measured between any PLL outputs with identical phase.

3. Values for this parameter are available in the Clocking Wizard.

See http://www.xilinx.com/products/intellectual-property/clocking_wizard.htm.

4. Includes global clock buffer.

5. Calculated as F

/128 assuming output duty cycle is 50ꢀ.

VCO

Device Pin-to-Pin Output Parameter Guidelines

Table 37: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Near Clock Region)

Speed Grade

Symbol

Description

Device

1.0V

-2/-2L

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.

0.9V

-2L

Units

-3

-1

-1M/-1Q

T_ICKOF

Clock-capable clock input and OUTFF

without MMCM/PLL (near clock region)

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

XA7A35T

XA7A50T

XA7A75T

XA7A100T

XQ7A50T

XQ7A100T

XQ7A200T

5.10

5.14

5.47

N/A

5.70

5.74

6.11

5.70

5.74

5.70

5.74

6.11

6.61

6.72

7.16

6.61

6.72

6.61

6.72

7.16

N/A

7.56

7.62

8.08

N/A

ns

N/A

6.61

6.72

6.61

6.72

7.16

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible IOB and CLB flip-flops are clocked by the global clock net.

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Table 38: Clock-Capable Clock Input to Output Delay Without MMCM/PLL (Far Clock Region)

Speed Grade

1.0V

Symbol

Description

Device

0.9V Units

-2L

-3

-2/-2L

-1

-1M/-1Q

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, without MMCM/PLL.

T_ICKOFFAR

Clock-capable clock input and OUTFF

without MMCM/PLL (far clock region)

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

XA7A35T

XA7A50T

XA7A75T

XA7A100T

XQ7A50T

XQ7A100T

XQ7A200T

5.10

5.38

6.17

N/A

5.70

6.01

6.89

5.70

6.01

5.70

6.01

6.89

6.61

7.02

8.05

6.61

7.02

6.61

7.02

8.05

N/A

7.57

7.94

9.03

N/A

ns

N/A

6.61

7.02

6.61

7.02

8.05

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible IOB and CLB flip-flops are clocked by the global clock net.

Table 39: Clock-Capable Clock Input to Output Delay With MMCM

Speed Grade

Symbol

Description

Device

1.0V

-2/-2L

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM.

0.9V

-2L

Units

-3

-1

-1M/-1Q

T_ICKOFMMCMCC

Clock-capable clock input and OUTFF

with MMCM

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

XA7A35T

XA7A50T

XA7A75T

XA7A100T

XQ7A50T

XQ7A100T

XQ7A200T

1.00

1.01

N/A

1.00

1.02

1.00

1.02

1.00

1.04

1.00

1.04

N/A

1.78

1.79

1.84

N/A

ns

N/A

1.00

1.04

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible IOB and CLB flip-flops are clocked by the global clock net.

2. MMCM output jitter is already included in the timing calculation.

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Table 40: Clock-Capable Clock Input to Output Delay With PLL

Speed Grade

1.0V

Symbol

Description

Device

0.9V Units

-2L

-3

-2/-2L

-1

-1M/-1Q

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with PLL.

T_ICKOFPLLCC

Clock-capable clock input and OUTFF

with PLL

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

XA7A35T

XA7A50T

XA7A75T

XA7A100T

XQ7A50T

XQ7A100T

XQ7A200T

0.82

0.81

N/A

0.82

0.81

0.82

0.81

0.82

0.81

0.82

0.81

N/A

1.39

1.40

1.45

N/A

ns

N/A

0.82

0.81

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all

accessible IOB and CLB flip-flops are clocked by the global clock net.

2. PLL output jitter is already included in the timing calculation.

Table 41: Pin-to-Pin, Clock-to-Out using BUFIO

Speed Grade

Symbol

Description

1.0V

-2/-2L

SSTL15 Clock-Capable Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with BUFIO.

0.9V

-2L

Units

-3

-1

-1M/-1Q

T_ICKOFCS

Clock to out of I/O clock

5.01

5.61

6.64

7.32

ns

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Device Pin-to-Pin Input Parameter Guidelines

All devices are 100ꢀ functionally tested. Values are expressed in nanoseconds unless otherwise noted.

Table 42: Global Clock Input Setup and Hold Without MMCM/PLL with ZHOLD_DELAY on HR I/O Banks

Speed Grade

Symbol

Description

Device

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

-1M/-1Q

Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.⁽¹⁾

T_PSFD/ T_PHFD

Full delay (legacy delay or

default delay)

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

XA7A35T

XA7A50T

XA7A75T

XA7A100T

XQ7A50T

XQ7A100T

XQ7A200T

2.47/–0.29 2.65/–0.29 3.10/–0.29

2.69/–0.34 2.89/–0.34 3.34/–0.34

3.03/–0.36 3.27/–0.36 3.79/–0.36

N/A

5.10/–0.44

5.66/–0.51

6.66/–0.55

N/A

ns

global clock input and IFF⁽²⁾

without MMCM/PLL with

ZHOLD_DELAY on HR I/O

banks

N/A

2.65/–0.29 3.10/–0.29 3.10/–0.29

2.89/–0.34 3.34/–0.34 3.34/–0.34

2.65/–0.29 3.10/–0.29 3.10/–0.29

2.89/–0.34 3.34/–0.34 3.34/–0.34

3.27/–0.36 3.79/–0.36 3.79/–0.36

N/A

Notes:

1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global

clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global clock input

signal using the fastest process, lowest temperature, and highest voltage.

2. IFF = Input flip-flop or latch.

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Table 43: Clock-Capable Clock Input Setup and Hold With MMCM

Speed Grade

1.0V

Symbol

Description

Device

0.9V

-2L

Units

-3

-2/-2L

-1

-1M/-1Q

Input Setup and Hold Time Relative to Global Clock Input Signal for SSTL15 Standard.⁽¹⁾

T_PSMMCMCC

T_PHMMCMCC

/

No delay clock-capable

clock input and IFF⁽²⁾with

MMCM

XC7A35T

XC7A50T

XC7A75T

2.46/–0.62 2.80/–0.62 3.35/–0.62

2.47/–0.62 2.81/–0.62 3.36/–0.62

N/A

2.14/–0.48

2.15/–0.48

2.32/–0.51

N/A

ns

XC7A100T 2.47/–0.62 2.81/–0.62 3.36/–0.62

XC7A200T 2.59/–0.63 2.95/–0.63 3.52/–0.63

XA7A35T

XA7A50T

XA7A75T

XA7A100T

XQ7A50T

XQ7A100T

XQ7A200T

N/A

2.80/–0.62 3.35/–0.62 3.35/–0.62

2.81/–0.62 3.36/–0.62 3.36/–0.62

2.80/–0.62 3.35/–0.62 3.35/–0.62

2.81/–0.62 3.36/–0.62 3.36/–0.62

2.95/–0.63 3.52/–0.63 3.52/–0.63

N/A

Notes:

1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the

global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global

clock input signal using the fastest process, lowest temperature, and highest voltage.

2. IFF = Input flip-flop or latch

3. Use IBIS to determine any duty-cycle distortion incurred using various standards.

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Table 44: Clock-Capable Clock Input Setup and Hold With PLL

Speed Grade

1.0V

Symbol

Description

Device

0.9V

-2L

Units

-3

-2/-2L

-1

-1M/-1Q

Input Setup and Hold Time Relative to Clock-Capable Clock Input Signal for SSTL15 Standard.⁽¹⁾

T_PSPLLCC

T_PHPLLCC

/

No delay clock-capable

XC7A35T

XC7A50T

XC7A75T

XC7A100T

XC7A200T

XA7A35T

XA7A50T

XA7A75T

XA7A100T

XQ7A50T

XQ7A100T

XQ7A200T

2.77/–0.20 3.15/–0.20 3.77/–0.20

2.78/–0.20 3.15/–0.20 3.78/–0.20

2.91/–0.21 3.29/–0.21 3.94/–0.21

N/A

2.46/–0.59

2.47/–0.59

2.64/–0.62

N/A

ns

clock input and IFF⁽²⁾with PLL

N/A

3.15/–0.20 3.77/–0.20 3.77/–0.20

3.15/–0.20 3.78/–0.20 3.78/–0.20

3.15/–0.20 3.77/–0.20 3.77/–0.20

3.15/–0.20 3.78/–0.20 3.78/–0.20

3.29/–0.21 3.94/–0.21 3.94/–0.21

N/A

Notes:

1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the

global clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the global

clock input signal using the fastest process, lowest temperature, and highest voltage.

2. IFF = Input flip-flop or latch

3. Use IBIS to determine any duty-cycle distortion incurred using various standards.

Table 45: Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO

Speed Grade

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

-1M/-1Q

Input Setup and Hold Time Relative to a Forwarded Clock Input Pin Using BUFIO for SSTL15 Standard.

T

_PSCS/T_PHCS

Setup and hold of I/O clock

–0.38/1.31 –0.38/1.46 –0.38/1.76 –0.38/1.76 –0.16/1.89

ns

Table 46: Sample Window

Speed Grade

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

0.64

-1

-1M/-1Q

0.70

T_SAMP

Sampling error at receiver pins⁽¹⁾

0.59

0.35

0.70

0.46

0.70

0.46

ns

T_{SAMP_BUFIO}

Sampling error at receiver pins using BUFIO⁽²⁾

0.40

0.46

Notes:

1. This parameter indicates the total sampling error of the Artix-7 FPGAs DDR input registers, measured across voltage, temperature, and

process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements

include:

- CLK0 MMCM jitter

- MMCM accuracy (phase offset)

- MMCM phase shift resolution

These measurements do not include package or clock tree skew.

2. This parameter indicates the total sampling error of the Artix-7 FPGAs DDR input registers, measured across voltage, temperature, and

process. The characterization methodology uses the BUFIO clock network and IDELAY to capture the DDR input registers’ edges of

operation. These measurements do not include package or clock tree skew.

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Additional Package Parameter Guidelines

The parameters in this section provide the necessary values for calculating timing budgets for Artix-7 FPGA clock transmitter

and receiver data-valid windows.

Table 47: Package Skew

Symbol

T_PKGSKEW

Description

Package skew⁽¹⁾

Device

XC7A35T

Package

CPG236

CSG324

CSG325

FTG256

FGG484

CPG236

CSG324

CSG325

FTG256

FGG484

CSG324

FTG256

FGG484

FGG676

CSG324

FTG256

FGG484

FGG676

SBG484

FBG484

FBG676

FFG1156

CPG236

CSG324

CSG325

CPG236

CSG324

CSG325

CSG324

FGG484

CSG324

FGG484

CS325

Value

48

Units

ps

104

142

98

97

48

XC7A50T

104

142

98

97

113

120

144

153

113

120

144

153

111

109

121

151

48

XC7A75T

XC7A100T

XC7A200T

XA7A35T

XA7A50T

104

142

48

104

142

113

144

113

144

142

97

XA7A75T

XA7A100T

XQ7A50T

XQ7A100T

FG484

CS324

113

144

FG484

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Table 47: Package Skew (Cont’d)

Symbol

Description

Package skew⁽¹⁾

Device

XQ7A200T

Package

RS484

RB484

RB676

Value

111

Units

ps

T_PKGSKEW

109

ps

121

ps

Notes:

1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from die

pad to ball.

2. Package delay information is available for these device/package combinations. This information can be used to deskew the package.

GTP Transceiver Specifications

GTP Transceiver DC Input and Output Levels

Table 48 summarizes the DC output specifications of the GTP transceivers in Artix-7 FPGAs. Consult UG482: 7 Series

FPGAs GTP Transceiver User Guide for further details.

Table 48: GTP Transceiver DC Specifications

Symbol

DC Parameter

Conditions

Min

Typ

Max

Units

Differential peak-to-peak output Transmitter output swing is set to

–

1000

mV

DV_PPOUT

voltage⁽¹⁾

maximum setting

DC common mode output

voltage

Equation based

V_MGTAVTT– DV_PPOUT/4

mV

V_CMOUTDC

R_OUT

Differential output resistance

–

100

–

Ω

mV

ps

V_CMOUTAC

Common mode output voltage: AC coupled

1/2 V_MGTAVTT

–

Transmitter output pair (TXP and TXN) intra-pair skew

(FFG, FBG, SBG packages)

–

10

12

T_OSKEW

Transmitter output pair (TXP and TXN) intra-pair skew

(FGG, FTG, CSG, CPG packages)

–

ps

Differential peak-to-peak input External AC coupled

voltage

150

2000

mV

DV_PPIN

V_IN

Absolute input voltage

DC coupled V_MGTAVTT= 1.2V

–200

–

2/3 V_MGTAVTT

100

V_MGTAVTT

mV

Ω

V_CMIN

R_IN

Common mode input voltage

Differential input resistance

–

C_EXT

Recommended external AC coupling capacitor⁽²⁾

100

nF

Notes:

1. The output swing and preemphasis levels are programmable using the attributes discussed in UG482: 7 Series FPGAs GTP Transceiver

User Guide and can result in values lower than reported in this table.

2. Other values can be used as appropriate to conform to specific protocols and standards.

X-Ref Target - Figure 1

+V

0

P

N

Single-Ended

Voltage

ds181_01_062811

Figure 1: Single-Ended Peak-to-Peak Voltage

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

X-Ref Target - Figure 2

+V

0

Differential

Voltage

P–N

–V

ds181_02_062811

Figure 2: Differential Peak-to-Peak Voltage

Table 49 summarizes the DC specifications of the clock input of the GTP transceiver. Consult UG482: 7 Series FPGAs GTP

Transceiver User Guide for further details.

Table 49: GTP Transceiver Clock DC Input Level Specification

Symbol

V_IDIFF

DC Parameter

Differential peak-to-peak input voltage

Min

350

–

Typ

–

Max

2000

–

Units

mV

Ω

R_IN

Differential input resistance

100

C_EXT

Required external AC coupling capacitor

–

nF

GTP Transceiver Switching Characteristics

Consult UG482: 7 Series FPGAs GTP Transceiver User Guide for further information.

Table 50: GTP Transceiver Performance

Speed Grade

1.0V

-2/-2L

Package Type

0.9V

-2L

-3

-1

Output

Divider

Symbol

Description

Units

FFG

FBG

SBG

RB

FFG

FBG

SBG

RB

FGG

FTG

CSG

CPG

FGG

FTG

CSG

CPG

FGG

FFG

FBG

SBG

FFG

FBG

SBG

FTG

CSG

CPG

FTG

CSG

CPG

RS

F_GTPMAX

Maximum GTP transceiver data rate

6.6

6.25

6.6

6.25

3.75

Gb/s

F_GTPMIN

Minimum GTP transceiver data rate

1

0.500

0.500 Gb/s

3.2–6.6

1.6–3.3

3.2–6.6

3.2–3.75

1.6–3.2

0.8–1.6

0.5–0.8

1.6–3.3

3.2–3.75

1.6–3.2

Gb/s

GHz

2

1.6–3.3

0.8–1.65

0.5–0.825

1.6–3.3

F_GTPRANGE

PLL line rate range

4

0.8–1.65

0.5–0.825

1.6–3.3

0.8–1.6

0.5–0.8

1.6–3.3

8

F_GTPPLLRANGEGTP transceiver PLL frequency

range

Table 51: GTP Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

F_GTPDRPCLK

GTPDRPCLK maximum frequency

175

156

125

MHz

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Table 52: GTP Transceiver Reference Clock Switching Characteristics

All Speed Grades

Symbol

Description

Conditions

Units

Min

60

–

Typ

–

Max

660

–

F_GCLK

T_RCLK

T_FCLK

T_DCREF

Reference clock frequency range

Reference clock rise time

Reference clock fall time

MHz

ps

20ꢀ – 80ꢀ

200

–

80ꢀ – 20ꢀ

–

ps

Reference clock duty cycle

Transceiver PLL only

40

60

ꢀ

X-Ref Target - Figure 3

T_RCLK

80%

20%

T_FCLK

ds181_03_062811

Figure 3: Reference Clock Timing Parameters

Table 53: GTP Transceiver PLL/Lock Time Adaptation

All Speed Grades

Symbol

Description

Initial PLL lock

Conditions

Units

Min

Typ

Max

T_LOCK

–

1

ms

After the PLL is locked to the

reference clock, this is the time it

takes to lock the clock data

recovery (CDR) to the data

present at the input.

Clock recovery phase acquisition and

adaptation time.

T_DLOCK

–

50,000

2.3 x10⁶

UI

(1)

Table 54: GTP Transceiver User Clock Switching Characteristics

Speed Grade

1.0V

Symbol

Description

Conditions

0.9V

Units

-3

-2/-2L

-1

-2L

F_TXOUT

F_RXOUT

F_TXIN

TXOUTCLK maximum frequency

RXOUTCLK maximum frequency

TXUSRCLK maximum frequency

RXUSRCLK maximum frequency

TXUSRCLK2 maximum frequency

RXUSRCLK2 maximum frequency

412.500

234.375

MHz

16-bit data path

F_RXIN

F_TXIN2

F_RXIN2

Notes:

1. Clocking must be implemented as described in UG482: 7 Series FPGAs GTP Transceiver User Guide.

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Table 55: GTP Transceiver Transmitter Switching Characteristics

Symbol

Description

Serial data rate range

Condition

Min

Typ

–

Max

F_GTPMAX

–

Units

Gb/s

ps

mV

ns

UI

F_GTPTX

T_RTX

0.500

–

TX rise time

20ꢀ–80ꢀ

80ꢀ–20ꢀ

50

–

T_FTX

TX fall time

–

T_LLSKEW

TX lane-to-lane skew⁽¹⁾

Electrical idle amplitude

Electrical idle transition time

Total Jitter⁽²⁾⁽³⁾

Deterministic Jitter⁽²⁾⁽³⁾

Total Jitter⁽²⁾⁽³⁾

Deterministic Jitter⁽²⁾⁽³⁾

Total Jitter⁽²⁾⁽³⁾

Deterministic Jitter⁽²⁾⁽³⁾

Total Jitter⁽²⁾⁽³⁾

Deterministic Jitter⁽²⁾⁽³⁾

Total Jitter⁽²⁾⁽³⁾

Deterministic Jitter⁽²⁾⁽³⁾

Total Jitter⁽²⁾⁽³⁾

Deterministic Jitter⁽²⁾⁽³⁾

Total Jitter⁽²⁾⁽³⁾

Deterministic Jitter⁽²⁾⁽³⁾

Total Jitter⁽²⁾⁽³⁾

–

500

V_TXOOBVDPP

T_{TXOOBTRANSITION}

TJ_6.6

–

20

–

140

–

0.30

0.15

0.30

0.15

0.30

0.15

0.30

0.15

0.2

6.6 Gb/s

5.0 Gb/s

DJ_6.6

–

UI

TJ_5.0

–

UI

DJ_5.0

–

UI

TJ_4.25

–

UI

4.25 Gb/s

3.75 Gb/s

3.20 Gb/s⁽⁴⁾

3.20 Gb/s⁽⁵⁾

2.5 Gb/s⁽⁶⁾

1.25 Gb/s⁽⁷⁾

500 Mb/s

DJ_4.25

TJ_3.75

–

UI

–

UI

DJ_3.75

TJ_3.2

–

UI

–

UI

DJ_3.2

–

0.1

UI

TJ_3.2L

–

0.32

0.16

0.20

0.08

0.15

0.06

0.1

UI

DJ_3.2L

TJ_2.5

–

UI

–

UI

DJ_2.5

–

UI

TJ_1.25

–

UI

DJ_1.25

TJ₅₀₀

Deterministic Jitter⁽²⁾⁽³⁾

Total Jitter⁽²⁾⁽³⁾

Deterministic Jitter⁽²⁾⁽³⁾

–

UI

–

UI

DJ₅₀₀

–

0.03

UI

Notes:

1. Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated GTP Quad).

2. Using PLL[0/1]_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations.

-12

3. All jitter values are based on a bit-error ratio of 1e

4. PLL frequency at 3.2 GHz and TXOUT_DIV = 2.

5. PLL frequency at 1.6 GHz and TXOUT_DIV = 1.

6. PLL frequency at 2.5 GHz and TXOUT_DIV = 2.

7. PLL frequency at 2.5 GHz and TXOUT_DIV = 4.

.

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Table 56: GTP Transceiver Receiver Switching Characteristics

Symbol Description

RX oversampler not enabled

Min

0.500

–

Typ

–

Max

F_GTPMAX

–

Units

Gb/s

ns

F_GTPRX

T_RXELECIDLE

RX_OOBVDPP

Serial data rate

Time for RXELECIDLE to respond to loss or restoration of data

OOB detect threshold peak-to-peak

10

–

60

150

mV

Receiver spread-spectrum

Modulated @ 33 kHz

tracking⁽¹⁾

–5000

–

5000

ppm

RX_SST

RX_RL

Run length (CID)

–

512

UI

RX_PPMTOL

SJ Jitter Tolerance⁽²⁾

JT_SJ_6.6

Data/REFCLK PPM offset tolerance

–1250

1250

ppm

Sinusoidal Jitter⁽³⁾

6.6 Gb/s

0.44

0.45

0.5

–

UI

JT_SJ_5.0

5.0 Gb/s

JT_SJ_4.25

JT_SJ_3.75

JT_SJ_3.2

4.25 Gb/s

3.75 Gb/s

3.2 Gb/s⁽⁴⁾

3.2 Gb/s⁽⁵⁾

2.5 Gb/s⁽⁶⁾

1.25 Gb/s⁽⁷⁾

500 Mb/s

JT_SJ_3.2L

JT_SJ_2.5

JT_SJ_1.25

JT_SJ₅₀₀

0.5

0.4

SJ Jitter Tolerance with Stressed Eye⁽²⁾

JT_TJSE_3.2

3.2 Gb/s

6.6 Gb/s

3.2 Gb/s

6.6 Gb/s

0.70

0.1

–

UI

Total Jitter with Stressed Eye⁽⁸⁾

JT_TJSE_6.6

JT_SJSE_3.2

JT_SJSE_6.6

Sinusoidal Jitter with Stressed

Eye⁽⁸⁾

0.1

Notes:

1. Using RXOUT_DIV = 1, 2, and 4.

2. All jitter values are based on a bit error ratio of 1e

–12

.

3. The frequency of the injected sinusoidal jitter is 10 MHz.

4. PLL frequency at 3.2 GHz and RXOUT_DIV = 2.

5. PLL frequency at 1.6 GHz and RXOUT_DIV = 1.

6. PLL frequency at 2.5 GHz and RXOUT_DIV = 2.

7. PLL frequency at 2.5 GHz and RXOUT_DIV = 4.

8. Composite jitter.

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

GTP Transceiver Protocol Jitter Characteristics

For Table 57 through Table 61, the UG482: 7 Series FPGAs GTP Transceiver User Guide contains recommended settings

for optimal usage of protocol specific characteristics.

Table 57: Gigabit Ethernet Protocol Characteristics

Description

Line Rate (Mb/s)

Min

–

Max

0.24

–

Units

UI

Gigabit Ethernet Transmitter Jitter Generation

Total transmitter jitter (T_TJ)

1250

Gigabit Ethernet Receiver High Frequency Jitter Tolerance

Total receiver jitter tolerance

1250

0.749

UI

Table 58: XAUI Protocol Characteristics

Description

Line Rate (Mb/s)

3125

Min

–

Max

0.35

–

Units

UI

XAUI Transmitter Jitter Generation

Total transmitter jitter (T_TJ)

XAUI Receiver High Frequency Jitter Tolerance

Total receiver jitter tolerance

3125

0.65

UI

(1)

Table 59: PCI Express Protocol Characteristics

Standard

Description

Line Rate (Mb/s)

Min

Max

Units

PCI Express Transmitter Jitter Generation

PCI Express Gen 1

PCI Express Gen 2

Total transmitter jitter

2500

5000

–

0.25

UI

PCI Express Receiver High Frequency Jitter Tolerance

PCI Express Gen 1

Total receiver jitter tolerance

Receiver inherent timing error

2500

5000

0.65

0.40

0.30

–

UI

PCI Express Gen 2⁽²⁾

Receiver inherent deterministic timing error

Notes:

1. Tested per card electromechanical (CEM) methodology.

2. Using common REFCLK.

Table 60: CEI-6G Protocol Characteristics

Description

Line Rate (Mb/s)

Interface

Min

Max

Units

UI

CEI-6G Transmitter Jitter Generation

Total transmitter jitter⁽¹⁾

4976–6375

CEI-6G-SR

–

0.3

–

CEI-6G Receiver High Frequency Jitter Tolerance

Total receiver jitter tolerance⁽¹⁾

4976–6375

0.6

UI

Notes:

1. Tested at most commonly used line rate of 6250 Mb/s using 390.625 MHz reference clock.

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Table 61: CPRI Protocol Characteristics

Description

Line Rate (Mb/s)

Min

Max

Units

CPRI Transmitter Jitter Generation

614.4

1228.8

2457.6

3072.0

4915.2

6144.0

–

0.35

0.3

UI

Total transmitter jitter

0.3

CPRI Receiver Frequency Jitter Tolerance

Total receiver jitter tolerance

614.4

1228.8

0.65

0.60

–

UI

2457.6

3072.0

4915.2⁽¹⁾

6144.0⁽¹⁾

Notes:

1. Tested to CEI-6G-SR.

Integrated Interface Block for PCI Express Designs Switching Characteristics

More information and documentation on solutions for PCI Express designs can be found at:

http://www.xilinx.com/technology/protocols/pciexpress.htm

Table 62: Maximum Performance for PCI Express Designs

Speed Grade

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

250.00

-1

F_PIPECLK

Pipe clock maximum frequency

250.00

MHz

F_USERCLK

F_USERCLK2

F_DRPCLK

User clock maximum frequency

User clock 2 maximum frequency

DRP clock maximum frequency

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47

Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

XADC Specifications

Table 63: XADC Specifications

Parameter

Symbol

Comments/Conditions

Min

Typ

Max

Units

V_CCADC= 1.8V 5ꢀ, V_REFP= 1.25V, V_REFN= 0V, ADCCLK = 26 MHz, –55°C ≤ Tj ≤ 125°C, Typical values at T_j=+40°C

ADC Accuracy⁽¹⁾

Resolution

12

–

3

–

Bits

LSBs

ꢀ

Integral Nonlinearity⁽²⁾

INL

–40°C ≤ T_j≤ 100°C

2

–55°C ≤ T_j< –40°C; 100°C < T_j≤ 125°C

No missing codes, guaranteed monotonic

–40°C ≤ T_j≤ 100°C

–

3

1

Differential Nonlinearity

Offset Error

DNL

–

Unipolar

–

8

–55°C ≤ T_j< –40°C; 100°C < T_j≤ 125°C

–55°C ≤ T_j≤ 125°C

–

12

4

Bipolar

–

Gain Error

–

0.5

4

Offset Matching

Gain Matching

Sample Rate

–

LSBs

ꢀ

–

0.3

1

0.1

60

–

MS/s

dB

Signal to Noise Ratio⁽²⁾

RMS Code Noise

SNR

THD

F_SAMPLE= 500KS/s, F_IN= 20 kHz

External 1.25V reference

–

2

LSBs

dB

On-chip reference

–

Total Harmonic Distortion⁽²⁾

Analog Inputs⁽³⁾

F_SAMPLE= 500KS/s, F_IN= 20 kHz

70

–

ADC Input Ranges

Unipolar operation

0

–

1

V

Bipolar operation

–0.5

0

+0.5

Unipolar common mode range (FS input)

Bipolar common mode range (FS input)

+0.5

–0.1

+0.6

Maximum External Channel Input Ranges

Adjacent analog channels set within these

ranges should not corrupt measurements on

adjacent channels

V_CCADC

Auxiliary Channel Full

Resolution Bandwidth

FRBW

250

–

kHz

On-Chip Sensors

Temperature Sensor Error

–40°C ≤ T_j≤ 100°C

–

4

6

1

2

°C

ꢀ

–55°C ≤ T_j< –40°C; 100°C < T_j≤ 125°C

–40°C ≤ T_j≤ 100°C

Supply Sensor Error

–55°C ≤ T_j< –40°C; 100°C < T_j≤ 125°C

ꢀ

Conversion Rate⁽⁴⁾

Conversion Time - Continuous t_CONV

Number of ADCCLK cycles

Number of CLK cycles

DRP clock frequency

Derived from DCLK

26

–

32

21

Cycles

MHz

ꢀ

Conversion Time - Event

DRP Clock Frequency

ADC Clock Frequency

DCLK Duty Cycle

t_CONV

DCLK

8

250

26

ADCCLK

1

40

60

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48

Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Table 63: XADC Specifications (Cont’d)

Parameter

XADC Reference⁽⁵⁾

External Reference

On-Chip Reference

Symbol

Comments/Conditions

Min

Typ

Max

Units

V_REFP

Externally supplied reference voltage

1.20

1.25

1.30

V

Ground V_REFPpin to AGND,

–40°C ≤ T_j≤ 100°C

1.2375 1.25

1.2625

Ground V_REFPpin to AGND,

1.225 1.25

1.275

V

–55°C ≤ T_j< –40°C; 100°C < T_j≤ 125°C

Notes:

1. Offset and gain errors are removed by enabling the XADC automatic gain calibration feature. The values are specified for when this feature

is enabled.

2. Only specified for bitstream option XADCEnhancedLinearity = ON.

3. See the ADC chapter in the 7 Series FPGAs and Zynq-7000 AP SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter (UG480) for a

detailed description.

4. See the Timing chapter in the 7 Series FPGAs and Zynq-7000 AP SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter (UG480) for

a detailed description.

5. Any variation in the reference voltage from the nominal V

= 1.25V and V

= 0V will result in a deviation from the ideal transfer

REFP

REFN

function. This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external

ratiometric type applications allowing reference to vary by 4ꢀ is permitted.

Configuration Switching Characteristics

Table 64: Configuration Switching Characteristics

Speed Grade

Symbol

Description

1.0V

0.9V

-2L

Units

-3

-2/-2L

-1

Power-up Timing Characteristics

(1)

T_PL

Program latency

5.00

10/50

10/35

250.00

5.00

10/50

10/35

250.00

5.00

10/50

10/35

250.00

5.00

ms, Max

(1)

T_POR

Power-on reset (50 ms ramp rate time)

Power-on reset (1 ms ramp rate time)

Program pulse width

10/50 ms, Min/Max

10/35 ms, Min/Max

T_PROGRAM

CCLK Output (Master Mode)

250.00

ns, Min

T_ICCK

Master CCLK output delay

150.00

40/60

100.00

50.00

3.00

150.00

40/60

100.00

50.00

3.00

150.00

40/60

100.00

50.00

3.00

150.00

40/60

70.00

35.00

3.00

ns, Min

ꢀ, Min/Max

MHz, Max

MHz, Typ

ꢀ, Max

T_MCCKL

T_MCCKH

F_MCCK

Master CCLK clock Low time duty cycle

Master CCLK clock High time duty cycle

Master CCLK frequency

Master CCLK frequency for AES encrypted x16

Master CCLK frequency at start of configuration

F_{MCCK_START}

F_MCCKTOL

Frequency tolerance, master mode with respect to

nominal CCLK

50

CCLK Input (Slave Modes)

T_SCCKL

T_SCCKH

F_SCCK

Slave CCLK clock minimum Low time

2.50

ns, Min

Slave CCLK clock minimum High time

Slave CCLK frequency

100.00

70.00

MHz, Max

EMCCLK Input (Master Mode)

T_EMCCKL

T_EMCCKH

F_EMCCK

External master CCLK Low time

2.50

ns, Min

External master CCLK High time

External master CCLK frequency

100.00

70.00

MHz, Max

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Table 64: Configuration Switching Characteristics (Cont’d)

Speed Grade

1.0V

Symbol

Description

0.9V

-2L

Units

-3

-2/-2L

-1

Internal Configuration Access Port

F_ICAPCK

Internal configuration access port (ICAPE2) clock

frequency

100.00

70.00

MHz, Max

Master/Slave Serial Mode Programming Switching

T_DCCK/T_CCKD

T_CCO

DIN setup/hold

4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.00

8.00 8.00 8.00 9.00

ns, Min

ns, Max

DOUT clock to out

SelectMAP Mode Programming Switching

T_SMDCCK/T_SMCCKDD[31:00] setup/hold

_SMCSCCK/T_SMCCKCSCSI_B setup/hold

4.00/0.00 4.00/0.00 4.00/0.00 4.50/0.00

4.00/0.00 4.00/0.00 4.00/0.00 5.00/0.00

10.00/0.00 10.00/0.00 10.00/0.00 12.00/0.00

ns, Min

ns, Max

T

_SMWCCK/T_SMCCKW

RDWR_B setup/hold

T_SMCKCSO

CSO_B clock to out (330 Ω pull-up resistor

required)

7.00

8.00

T_SMCO

D[31:00] clock to out in readback

Readback frequency

8.00

10.00

70.00

ns, Max

F_RBCCK

100.00

MHz, Max

Boundary-Scan Port Timing Specifications

T_TAPTCK/T_TCKTAP

T_TCKTDO

TMS and TDI setup/hold

TCK falling edge to TDO output

TCK frequency

3.00/2.00 3.00/2.00 3.00/2.00 3.00/2.00

ns, Min

ns, Max

7.00

8.50

F_TCK

66.00

50.00

MHz, Max

BPI Flash Master Mode Programming Switching

(2)

T_BPICCO

A[28:00], RS[1:0], FCS_B, FOE_B, FWE_B,

ADV_B clock to out

8.50

10.00

ns, Max

ns, Min

T

_BPIDCC/T_BPICCD

D[15:00] setup/hold

4.00/0.00 4.00/0.00 4.00/0.00 4.50/0.00

SPI Flash Master Mode Programming Switching

T_SPIDCC/T_SPICCD

T_SPICCM

D[03:00] setup/hold

MOSI clock to out

FCS_B clock to out

3.00/0.00 3.00/0.00 3.00/0.00 3.00/0.00

ns, Min

ns, Max

8.00

9.00

T_SPICCFC

USRCCLK Output

T_USRCCLKO

STARTUPE2 USRCCLKO input to CCLK output

0.50/6.00 0.50/6.70 0.50/7.50 0.50/7.50

ns,

Min/Max

Device DNA Access Port

F_DNACK

DNA access port (DNA_PORT)

100.00

70.00

MHz, Max

Notes:

1. To support longer delays in configuration, use the design solutions described in UG470: 7 Series FPGA Configuration User Guide.

2. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

eFUSE Programming Conditions

Table 65 lists the programming conditions specifically for eFUSE. For more information, see UG470: 7 Series FPGA

Configuration User Guide.

(1)

Table 65: eFUSE Programming Conditions

Symbol

Description

Min

–

Typ

–

Max

115

125

Units

mA

I_FS

T_j

V_CCAUXsupply current

Temperature range

15

–

°C

Notes:

1. The FPGA must not be configured during eFUSE programming.

Revision History

The following table shows the revision history for this document:

Date

Version

1.0

Description

09/26/2011

11/07/2011

Initial Xilinx release.

1.1

Revised the V_OCMspecification in Table 11. Updated the AC Switching Characteristics based upon the

ISE 13.3 software v1.02 speed specification throughout document including Table 13 and Table 14.

Added MMCM_T_FBDELAYwhile adding MMCM_ to the symbol names of a few specifications in

Table 35 and PLL to the symbol names in Table 36. In Table 37 through Table 44, updated the pin-to-

pin description with the SSTL15 standard. Updated units in Table 46.

02/13/2012

1.2

Updated the Artix-7 family of devices listed throughout the entire data sheet. Updated the AC Switching

Characteristics based upon the ISE 13.4 software v1.03 for the -3, -2, and -1 speed grades and v1.00

for the -2L speed grade.

Updated summary description on page 1. In Table 2, revised V_CCOfor the 3.3V HR I/O banks and

updated T_j. Updated the notes in Table 5. Added MGTAVCC and MGTAVTT power supply ramp times

to Table 7. Rearranged Table 8, added Mobile_DDR, HSTL_I_18, HSTL_II_18, HSUL_12,

SSTL135_R, SSTL15_R, and SSTL12 and removed DIFF_SSTL135, DIFF_SSTL18_I,

DIFF_SSTL18_II, DIFF_HSTL_I, and DIFF_HSTL_II. Added Table 9 and Table 10. Revised the

specifications in Table 11. Revised V_INin Table 48. Updated the eFUSE Programming Conditions

section and removed the endurance table. Added the table. Revised F_TXINand F_RXINin Table 54.

Revised I_CCADCand updated Note 1 in Table 63. Revised DDR LVDS transmitter data width in

Table 15. Removed notes from Table 25 as they are no longer applicable. Updated specifications in

Table 64. Updated Note 1 in Table 34.

06/01/2012

1.3

Reorganized entire data sheet including adding Table 41 and Table 45.

Updated T_SOLin Table 1. Updated I_BATTand added R_{IN_TERM}to Table 3. Updated Power-On/Off Power

Supply Sequencing section with regards to GTP transceivers. In Table 8, updated many parameters

including SSTL135 and SSTL135_R. Removed V_OXcolumn and added DIFF_HSUL_12 to Table 10.

Updated V_OLin Table 11. Updated Table 15 and removed notes 2 and 3. Updated Table 16.

Updated the AC Switching Characteristics based upon the ISE 14.1 software v1.03 for the -3, -2, -2L

(1.0V), -1, and v1.01 for the -2L (0.9V) speed specifications throughout the document.

In Table 28, updated Reset Delays section including Note 10 and Note 11. In Table 54, replaced

F

_TXOUTwith F_GLK. Updated many of the XADC specifications in Table 63 and added Note 2. Updated

and moved Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK section from

Table 64 to Table 35 and Table 36.

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Description

Date

Version

09/20/2012

1.4

In Table 1, updated the descriptions, changed V_INand Note 2, and added Note 4. In Table 2, changed

descriptions and notes. Updated parameters in Table 3. Added Table 4. Revised the Power-On/Off

Power Supply Sequencing section. Updated standards and specifications in Table 8, Table 9, and

Table 10. Removed the XC7A350T device from data sheet.

Updated the AC Switching Characteristics section to the ISE 14.2 speed specifications throughout the

document. Updated the IOB Pad Input/Output/3-State discussion and changed Table 18 by adding

T

_{IOIBUFDISABLE}. Removed many of the combinatorial delay specifications and T_CINCK/T_CKCINfrom

Table 25.Changed F_PFDMAXconditions in Table 35 and Table 36. Updated the GTP Transceiver

Specifications section, moved the GTP Transceiver DC characteristics section to the overall DC

Characteristics section, and added the GTP Transceiver Protocol Jitter Characteristics section. In

Table 63, updated Note 1. In Table 64, updated T_POR

.

02/01/2013

1.5

Updated the AC Switching Characteristics based upon the 14.4/2012.4 device pack for ISE 14.4 and

Vivado 2012.4, both at v1.07 for the -3, -2, -2L (1.0V), -1 speed specifications, and v1.05 for the -2L

(0.9V) speed specifications throughout the document. Production changes to Table 13 and Table 14

for -3, -2, -2L (1.0V), -1 speed specifications.

Revised I_DCINand I_DCOUTand added Note 5 in Table 1. Added Note 2 to Table 2. Updated Table 5.

Added minimum current specifications to Table 6. Removed SSTL12 and HSTL_I_12 from Table 8.

Removed DIFF_SSTL12 from Table 10. Updated Table 13. Added a 2:1 memory controller section to

Table 16. Updated Note 1 in Table 32. Revised Table 34. Updated Note 1 and Note 2 in Table 47.

Updated D_VPPINin Table 48. Updated V_IDIFFin Table 49. Removed T_LOCKand T_PHASEand revised

F

_GCLKin Table 52. Updated T_DLOCKin Table 53. Updated Table 54. In Table 55, updated T_RTX, T_FTX,

V_TXOOBVDPP, and revised Note 1 through Note 7. In Table 56, updated RX_SSTand RX_PPMTOLand

revised Note 4 through Note 7. In Table 61, revised and added Note 1.

Revised the maximum external channel input ranges in Table 63. In Table 64, revised F_MCCKand

added the Internal Configuration Access Port section.

04/17/2013

1.6

Updated the AC Switching Characteristics based upon v1.07 of the ISE 14.5 and Vivado 2013.1 for the

-3, -2, -2L (1.0V), and -1 speed specifications, and v1.05 for the -2L (0.9V) speed specifications.

Production changes to Table 13 and Table 14 for -2L (0.9V) speed specifications.

In Table 1, revised V_IN(I/O input voltage) to match values in Table 4 and combined Note 4 with old Note

5 and then added new Note 5. Revised V_INdescription, removed Note 10, and added Note 7 in Table 2.

Updated first 3 rows in Table 4. Also revised PCI33_3 voltage minimum in Table 8 to match values in

Table 1 and Table 4. Added Note 1 to Table 11. Removed Note 1 from Table 14. Updated Table 16 title.

Throughout the data sheet (Table 26, Table 27, and Table 42) removed the obvious note “A Zero “0”

Hold Time listing indicates no hold time or a negative hold time.”

09/04/2013

11/27/2013

1.7

1.8

Added new Artix-7 devices (XC7A35T, XC7A50T, and XC7A75T) throughout. In Table 1, updated I_DCIN

and I_DCOUTfor cases when floating, at V_MGTAVTT, or GND. Added back Note 1 to Table 14. Added CPG

package to Table 48 and Table 50.

Added automotive and expanded temperature range Artix-7 devices throughout. Added -1M and -1Q

speed grades throughout. Added reference to 7 Series FPGAs Overview, Defense-Grade 7 Series

FPGAs Overview, and XA Artix-7 FPGAs Overview in Introduction. In Table 2, added junction

temperature operating ranges for expanded (Q) and military (M) devices, and added Note 3. In Table 3,

removed commercial (C), industrial (I), and extended (E) from descriptions of R_{IN_TERM}. Updated

temperature ranges in Table 4. Removed notes from Table 6. Added T_J= 125°C to Conditions column

for T_VCCO2VCCAUXin Table 7. In AC Switching Characteristics, updated first paragraph, added

Table 12, and added -1Q/-1M speed grades to other tables in this section. In Table 50, added RB and

RS packages, and updated F_GTPMAX. In Table 63, updated ADC Accuracy, On-Chip Sensors, XADC

Reference sections and notes. Added T_USRCCLKOand F_DNACKto Table 64.

01/07/2014

01/23/2014

1.9

In Table 13, promoted all XC7A75T speed grades from Advance to Production and all XQ7A50T speed

grades from Preliminary to Advance. In Table 14, inserted “Vivado tools 2013.3” for the production

XC7A75T speed grades.

1.10

Updated the AC Switching Characteristics based upon ISE 14.7 and Vivado 2013.4. Updated Note 5

in Table 2. Removed pad pull-down @ V_IN= 1.8V for I_RPDin Table 3. Added Note 2 to Table 4.

Removed XQ7A50T fromTable 12, Table 13, and Table 14. In Table 13, changed speed grades for XA

Artix-7 FPGAs and defense-grade Artix-7Q family from -2 to -2I and -1 to -1I, and moved all speed

grades of XA7A100T, and -1I and -2I speed grades of XQ7A100T from Preliminary to Production. In

Table 14, updated production software for XA7A100T and XQ7A100T. Added HSUL_12_F,

DIFF_HSUL_12_F, MOBILE_DDR_S, MOBILE_DDR_F, DIFF_MOBILE_DDR_S, and

DIFF_MOBILE_DDR_F to Table 17. Removed introductory text in Device Pin-to-Pin Output Parameter

Guidelines.

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Artix-7 FPGAs Data Sheet: DC and Switching Characteristics

Description

Date

Version

03/04/2014

1.11

Updated Note 2 in Table 4. In Table 13, moved XQ7A100T -1M speed grade from Preliminary to

Production. In Table 14, added production software for XQ7A100T -1M speed grade.

03/28/2014

1.12

In Table 5, added I_CCINTQ, I_CCOQ, I_CCAUXQ, and I_CCBRAMQvalues for XC7A35T, XC7A50T, XA7A35T,

XA7A50T, and XQ7A50T devices. In Table 6, added power-on current values for XC7A35T, XC7A50T,

XA7A35T, XA7A50T, and XQ7A50T devices. In Table 12, added row for XC7A35T, XC7A50T, and

XC7A75T devices. In Table 13, moved all speed grades of XC7A35T and XC7A50T devices from

Advance to Production, and added XQ7A50T. In Table 14, added XQ7A50T and production software

for XC7A35T and XC7A50T -3, -2, -2L (1.0V), -1, and -2L (0.9V) speed grades. For F_{IDELAYCTRL_REF}

in Table 23, updated REFCLK frequency of 300 MHz, added REFCLK frequency of 400 MHz, and

updated Note 1. In Table 34, added T_CKSKEWdata for XC7A35T and XC7A50T devices. In Table 37,

updated T_ICKOFdata for -1 and -2L (0.9V) speed grades of XC7A35T and XC7A50T devices. In

Table 38, updated T_ICKOFFARdata for -1 and -2L (0.9V) speed grades of XC7A35T and XC7A50T

devices. In Table 39, added T_ICKOFMMCMCCdata for -2L (0.9V) speed grade of XC7A35T and

XC7A50T devices. In Table 40, added T_ICKOFPLLCCdata for -2L (0.9V) speed grade of XC7A35T and

XC7A50T devices. In Table 42, updated T_PSFD/T_PHFDdata for -2/-2L, -1, and -2L (0.9V) speed grades

of XC7A35T and XC7A50T devices. In Table 43, updated T_PSMMCMCC/T_PHMMCMCCdata for -1 and -2L

(0.9V) speed grades of XC7A35T and XC7A50T devices. In Table 44, updated T_PSPLLCC/T_PHPLLCC

data for -1 and -2L (0.9V) speed grades of XC7A35T and XC7A50T devices. In Table 47, added

package skew values for XC7A35T, XC7A50T, XA7A35T, XA7A50T, and XQ7A50T devices.

05/13/2014

1.13

In AC Switching Characteristics, updated to Vivado 2014.1. In Table 12, updated Vivado 2014.1

version numbers and consolidated rows. In Table 13, moved all XA7A75T speed grades from Advance

to Preliminary and all XQ7A200T speed grades from Preliminary to Production. In Table 14, added

production software for XQ7A200T -2, -1, and -1M speed grades. Added timing data for XA7A35T,

XA7A50T, XA7A75T, and XQ7A50T devices to Table 37, Table 38, Table 39, Table 40, Table 42,

Table 43, and Table 44.

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The information disclosed to you hereunder (the "Materials") is provided solely for the selection and use of Xilinx products. To the

maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL

WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF

MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable

(whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related

to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special,

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any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility

of the same. Xilinx assumes no obligation to correct any errors contained in the Materials, or to advise you of any corrections or update.

You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to

the terms and conditions of Xilinx’s limited warranty, please refer to Xilinx’s Terms of Sale which can be viewed at

www.xilinx.com/legal.htm#tos; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx

products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and

liability for use of Xilinx products in such critical applications, please refer to Xilinx’s Terms of Sale which can be viewed at

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AUTOMOTIVE APPLICATIONS DISCLAIMER

XILINX PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE, OR FOR USE IN ANY APPLICATION REQUIRING FAIL-

SAFE PERFORMANCE, SUCH AS APPLICATIONS RELATED TO: (I) THE DEPLOYMENT OF AIRBAGS, (II) CONTROL OF A

VEHICLE, UNLESS THERE IS A FAIL-SAFE OR REDUNDANCY FEATURE (WHICH DOES NOT INCLUDE USE OF SOFTWARE IN

THE XILINX DEVICE TO IMPLEMENT THE REDUNDANCY) AND A WARNING SIGNAL UPON FAILURE TO THE OPERATOR, OR (III)

USES THAT COULD LEAD TO DEATH OR PERSONAL INJURY. CUSTOMER ASSUMES THE SOLE RISK AND LIABILITY OF ANY

USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.

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53


型号：	XC7A200T-2SB484C
厂家：	XILINX, INC
描述：	Field Programmable Gate Array, PBGA484, 19 X 19 MM, 0.80 MM PITCH, BGA-484 栅可编程逻辑
文件：	总53页 (文件大小：617K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XC7A200T-2SB484C [XILINX]

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