XC6SLX100-3FGG676I_技术文档

89

Spartan-6 FPGA Data Sheet:

DC and Switching Characteristics

DS162 (v3.1.1) January 30, 2015

Product Specification

Spartan-6 FPGA Electrical Characteristics

Spartan®-6 LX and LXT FPGAs are available in various speed grades, with -3 having the highest performance. The DC and

AC electrical parameters of the Automotive XA Spartan-6 FPGAs and Defense-grade Spartan-6Q FPGAs devices are

equivalent to the commercial specifications except where noted. The timing characteristics of the commercial (XC) -2 speed

grade industrial device are the same as for a -2 speed grade commercial device. The -2Q and -3Q speed grades are

exclusively for the expanded (Q) temperature range. The timing characteristics are equivalent to those shown for the -2 and

-3 speed grades for the Automotive and Defense-grade devices.

Spartan-6 FPGA DC and AC characteristics are specified for commercial (C), industrial (I), and expanded (Q) temperature

ranges. Only selected speed grades and/or devices might be available in the industrial or expanded temperature ranges for

Automotive and Defense-grade devices. References to device names refer to all available variations of that part number (for

example, LX75 could denote XC6SLX75, XA6SLX75, or XQ6SLX75). The Spartan-6 FPGA -3N speed grade designates

devices that do not support MCB functionality.

All supply voltage and junction temperature specifications are representative of worst-case conditions. The parameters

included are common to popular designs and typical applications.

Available device and package combinations can be found at:

•

DS160: Spartan-6 Family Overview

DS170: Automotive XA Spartan-6 Family Overview

DS172: Defense-Grade Spartan-6Q Family Overview

This Spartan-6 FPGA data sheet, part of an overall set of documentation on the Spartan-6 family of FPGAs, is available on

the Xilinx website at http://www.xilinx.com/support/documentation/spartan-6.htm.

Spartan-6 FPGA DC Characteristics

(1)

Table 1: Absolute Maximum Ratings

Symbol

V_CCINT

V_CCAUX

V_CCO

Description

Units

Internal supply voltage relative to GND

Auxiliary supply voltage relative to GND

Output drivers supply voltage relative to GND

–0.5 to 1.32

–0.5 to 3.75

V

V_BATT

Key memory battery backup supply (LX75, LX75T, LX100, LX100T, LX150, and LX150T only) –0.5 to 4.05

External voltage supply for eFUSE programming (LX75, LX75T, LX100, LX100T, LX150, and

LX150T only)⁽²⁾

–0.5 to 3.75

V_FS

V_REF

Input reference voltage

–0.5 to 3.75

V

States and other countries. All other trademarks are the property of their respective owners.

DS162 (v3.1.1) January 30, 2015

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Product Specification

1

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 1: Absolute Maximum Ratings (Cont’d)

Symbol

Description

Units

V

DC

–0.60 to 4.10

–0.75 to 4.25

Commercial 20% overshoot duration

V

8% overshoot duration⁽⁵⁾–0.75 to 4.40

V

DC

–0.60 to 3.95

V

All user and dedicated

I/Os

Industrial

20% overshoot duration

4% overshoot duration⁽⁵⁾–0.75 to 4.40

–0.75 to 4.15

V

DC

–0.60 to 3.95

V

Expanded (Q) 20% overshoot duration

–0.75 to 4.15

V

4% overshoot duration⁽⁵⁾–0.75 to 4.40

20% overshoot duration –0.75 to 4.35

Commercial 15% overshoot duration⁽⁵⁾–0.75 to 4.40

V

I/O input voltage or voltage

applied to 3-state output,

relative to GND⁽⁴⁾

(3)

V_INand V_TS

V

10% overshoot duration

20% overshoot duration

10% overshoot duration

–0.75 to 4.45

–0.75 to 4.25

–0.75 to 4.35

V

Restricted to

maximum of 100 user Industrial

I/Os

V

8% overshoot duration⁽⁵⁾–0.75 to 4.40

V

20% overshoot duration

–0.75 to 4.25

V

Expanded (Q) 10% overshoot duration

–0.75 to 4.35

V

8% overshoot duration⁽⁵⁾–0.75 to 4.40

V

T_STG

Storage temperature (ambient)

–65 to 150

+260

°C

Maximum soldering temperature⁽⁶⁾

(TQG144, CPG196, CSG225, CSG324, CSG484, and FTG256)

T_SOL

Maximum soldering temperature⁽⁶⁾(Pb-free packages: FGG484, FGG676, and FGG900)

Maximum soldering temperature⁽⁶⁾(Pb packages: CS484, FT256, FG484, FG676, and FG900)

Maximum junction temperature⁽⁶⁾

+250

+220

+125

°C

T_j

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.

Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.

2. When programming eFUSE, V ≤ V

. Requires up to 40 mA current. For read mode, V can be between GND and 3.45 V.

FS

CCAUX

FS

3. I/O absolute maximum limit applied to DC and AC signals. Overshoot duration is the percentage of a data period that the I/O is stressed

beyond 3.45V.

4. For I/O operation, refer to UG381: Spartan-6 FPGA SelectIO Resources User Guide.

5. Maximum percent overshoot duration to meet 4.40V maximum.

6.

T

is the maximum soldering temperature for component bodies. For soldering guidelines and thermal considerations,

SOL

see UG385: Spartan-6 FPGA Packaging and Pinout Specification.

DS162 (v3.1.1) January 30, 2015

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Product Specification

2

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 2: Recommended Operating Conditions

Symbol

Description

-3, -3N, -2

Min

1.14

1.2

Typ

1.2

1.23

1.0

2.5

3.3

–

Max

1.26

Units

V

Standard performance⁽²⁾

Extended performance⁽²⁾

Standard performance⁽²⁾

V_CCINT

Internal supply voltage relative to GND -3, -2

-1L

1.26

V

0.95

2.375

3.15

1.1

1.05

V

_CCAUX= 2.5V⁽⁵⁾

2.625

3.45

V

(3)(4)

V_CCAUX

Auxiliary supply voltage relative to GND

Output supply voltage relative to GND

V_CCAUX= 3.3V

V

(6)(7)(8)

V_CCO

3.45

V

Commercial temperature (C) –0.5

–

4.0

V

All I/O

standards

(except PCI)

Industrial temperature (I)

Expanded (Q) temperature

–0.5

–

3.95

V

V_IN

Input voltage relative to GND

–

3.95

V

PCI I/O standard⁽⁹⁾

–

V_CCO+ 0.5

V

Maximum current through pin using PCI I/O standard

when forward biasing the clamp diode.⁽⁹⁾

Commercial (C) and

Industrial temperature (I)

–

10

mA

(10)

I_IN

Expanded (Q) temperature

–

7

mA

Maximum current through pin when forward biasing the ground clamp diode.

10

Battery voltage relative to GND, T_j= 0°C to +85°C

(LX75, LX75T, LX100, LX100T, LX150, and LX150T only)

(11)

V_BATT

1.0

–

3.6

V

Commercial (C) range

0

–

85

°C

T_j

Junction temperature operating range

Industrial temperature (I) range

Expanded (Q) temperature range

–40

100

125

Notes:

1. All voltages are relative to ground.

2. See Interface Performances for Memory Interfaces in Table 25. The extended performance range is specified for designs not using the

standard V

voltage range. The standard V

voltage range is used for:

CCINT

•

Designs that do not use an MCB

LX4 devices

Devices in the TQG144 or CPG196 packages

Devices with the -3N speed grade

3. Recommended maximum voltage droop for V

is 10 mV/ms.

must be 2.5V.

CCAUX

4. During configuration, if V

is 1.8V, then V

CCO_2

CCAUX

5. The -1L devices require V

= 2.5V when using the LVDS_25, LVDS_33, BLVDS_25, LVPECL_25, RSDS_25, RSDS_33, PPDS_25,

CCAUX

and PPDS_33 I/O standards on inputs. LVPECL_33 is not supported in the -1L devices.

6. Configuration data is retained even if V drops to 0V.

CCO

7. Includes V

of 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V.

CCO

8. For PCI systems, the transmitter and receiver should have common supplies for V

9. Devices with a -1L speed grade do not support Xilinx PCI IP.

10. Do not exceed a total of 100 mA per bank.

.

CCO

11. V

is required to maintain the battery backed RAM (BBR) AES key when V

is not applied. Once V

is applied, V

can be

BATT

CCAUX

BATT

unconnected. When BBR is not used, Xilinx recommends connecting to V

or GND. However, V

can be unconnected.

CCAUX

BATT

DS162 (v3.1.1) January 30, 2015

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Product Specification

3

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 3: eFUSE Programming Conditions

Symbol

Description

Min

3.2

–

Typ Max Units

(2)

V_FS

External voltage supply

V_FSsupply current

3.3

–

3.4

40

V

mA

V

I_FS

V_CCAUXAuxiliary supply voltage relative to GND

3.2

3.3

3.45

(3)

R_FUSE

External resistor from R_FUSEpin to GND

1129 1140 1151

Ω

V_CCINTInternal supply voltage relative to GND

1.14

15

1.2

–

1.26

85

V

t_j

Temperature range

°C

Notes:

1. These specifications apply during programming of the eFUSE AES key. Programming is only supported through JTAG.The AES key is only

supported in the following devices: LX75, LX75T, LX100, LX100T, LX150, and LX150T.

2. When programming eFUSE, V must be less than or equal to V

. When not programming or when eFUSE is not used, Xilinx

FS

CCAUX

recommends connecting V to GND. However, V can be between GND and 3.45 V.

FS

3. An R

resistor is required when programming the eFUSE AES key. When not programming or when eFUSE is not used, Xilinx

FUSE

recommends connecting the R

pin to V

or GND. However, R

can be unconnected.

FUSE

CCAUX

FUSE

DS162 (v3.1.1) January 30, 2015

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Product Specification

4

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 4: DC Characteristics Over Recommended Operating Conditions

Symbol

V_DRINT

V_DRAUX

Description

Min

0.8

Typ

–

Max Units

Data retention V_CCINTvoltage (below which configuration data might be lost)

Data retention V_CCAUXvoltage (below which configuration data might be lost)

V_REFleakage current per pin for commercial (C) and industrial (I) devices

V_REFleakage current per pin for expanded (Q) devices

–

V

2.0

–

V

–10

–15

–

10

15

10

µA

I_REF

–

Input or output leakage current per pin (sample-tested) for commercial (C) and industrial –10

(I) devices

–

I_L

Input or output leakage current per pin (sample-tested) for expanded (Q) devices

–15

–20

–

15

20

µA

All pins except PROGRAM_B, DONE, and

JTAG pins when HSWAPEN = 1

Leakage current on pins during hot

I_HS

socketing with FPGA unpowered

PROGRAM_B, DONE, and JTAG pins, or other

I_{HS(HSWAPEN = 1)}

I_RPU

+

µA

pins when HSWAPEN = 0

(1)

C_IN

Die input capacitance at the pad

–

200

120

60

40

12

200

140

–

10

500

350

200

150

100

550

400

150

–

pF

µA

nA

Ω

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 3.3V or V_CCAUX= 3.3V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 2.5V or V_CCAUX= 2.5V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 1.8V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 1.5V

Pad pull-up (when selected) @ V_IN= 0V, V_CCO= 1.2V

Pad pull-down (when selected) @ V_IN= V_CCO, V_CCAUX= 3.3V

Pad pull-down (when selected) @ V_IN= V_CCO, V_CCAUX= 2.5V

Battery supply current

–

I_RPU

–

I_RPD

–

(2)

I_BATT

–

(3)

R_DT

Resistance of optional input differential termination circuit, V_CCAUX= 3.3V

–

100

25

Thevenin equivalent resistance of programmable input termination to V_CCO

(UNTUNED_SPLIT_25) for commercial (C) and industrial (I) devices

23

55

Ω

Thevenin equivalent resistance of programmable input termination to V_CCO

(UNTUNED_SPLIT_25) for expanded (Q) devices

20

39

32

56

47

25

50

75

55

72

Ω

Thevenin equivalent resistance of programmable input termination to V_CCO

(UNTUNED_SPLIT_50) for commercial (C) and industrial (I) devices

(5)

R_{IN_TERM}

Thevenin equivalent resistance of programmable input termination to V_CCO

(UNTUNED_SPLIT_50) for expanded (Q) devices

74

Thevenin equivalent resistance of programmable input termination to V_CCO

(UNTUNED_SPLIT_75) for commercial (C) and industrial (I) devices

109

115

Thevenin equivalent resistance of programmable input termination to V_CCO

(UNTUNED_SPLIT_75) for expanded (Q) devices

Thevenin equivalent resistance of programmable output termination (UNTUNED_25)

11

21

29

25

50

75

52

96

Ω

R_{OUT_TERM}Thevenin equivalent resistance of programmable output termination (UNTUNED_50)

Thevenin equivalent resistance of programmable output termination (UNTUNED_75)

145

Notes:

1. The C measurement represents the die capacitance at the pad, not including the package.

IN

2. Maximum value specified for worst case process at 25°C. LX75, LX75T, LX100, LX100T, LX150, and LX150T only.

3. Refer to IBIS models for R variation and for values at V = 2.5V. IBIS values for R are valid for all temperature ranges.

DT

CCAUX

DT

4.

V

is not required for data retention. The minimum V

for power-on reset and configuration is 1.65V.

CCO2

5. Termination resistance to a V

/2 level.

CCO

DS162 (v3.1.1) January 30, 2015

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Product Specification

5

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Quiescent Current

Typical values for quiescent supply current are specified at nominal voltage, 25°C junction temperatures (T). Quiescent

j

supply current is specified by speed grade for Spartan-6 devices. Xilinx recommends analyzing static power consumption

using the Xilinx Power Estimator (XPE) tool (download at http://www.xilinx.com/power) for conditions other than those

specified in Table 5.

Table 5: Typical Quiescent Supply Current

Speed Grade

Symbol

Description

Device

Units

-3

-3N

4.0

-2

-1L

2.4

I_CCINTQ

Quiescent V_CCINTsupply current

LX4

4.0

mA

LX9

4.0

2.4

LX16

6.0

4.0

LX25

11.0

15.0

29.0

36.0

51.0

1.0

11.0

15.0

29.0

36.0

51.0

1.0

11.0

15.0

29.0

36.0

51.0

1.0

6.6

LX25T

LX45

N/A

9.0

LX45T

LX75

N/A

17.4

N/A

21.6

N/A

31.0

N/A

1.0

LX75T

LX100

LX100T

LX150

LX150T

LX4

I_CCOQ

Quiescent V_CCOsupply current

LX9

1.0

LX16

2.0

LX25

2.0

LX25T

LX45

2.0

N/A

3.0

LX45T

LX75

3.0

N/A

4.0

LX75T

LX100

LX100T

LX150

LX150T

4.0

N/A

5.0

N/A

7.0

N/A

DS162 (v3.1.1) January 30, 2015

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Product Specification

6

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Speed Grade

Table 5: Typical Quiescent Supply Current (Cont’d)

Symbol

Description

Device

Units

-3

2.5

3.0

4.0

5.0

7.0

9.0

12.0

-3N

2.5

3.0

4.0

5.0

7.0

9.0

12.0

-2

2.5

3.0

4.0

5.0

7.0

9.0

12.0

-1L

2.5

I_CCAUXQ

Quiescent V_CCAUXsupply current

LX4

mA

LX9

2.5

LX16

3.0

LX25

4.0

LX25T

LX45

N/A

5.0

LX45T

LX75

N/A

7.0

LX75T

LX100

LX100T

LX150

LX150T

N/A

9.0

N/A

12.0

N/A

Notes:

1. Typical values are specified at nominal voltage, 25°C junction temperatures (Tj). Industrial (I) grade devices have the same typical values as

commercial (C) grade devices at 25°C, but higher values at 100°C. Use the XPE tool to calculate 100°C values. Nominal V is 1.20V;

CCINT

use the XPE tool to calculate 1.23V values for the nominal V

of the extended performance range.

CCINT

2. Typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all I/O pins are 3-state and

floating.

3. If differential signaling is used, more accurate quiescent current estimates can be obtained by using the Xilinx Power Estimator (XPE) or

Xilinx Power Analyzer (XPA) tools.

Table 6: Power Supply Ramp Time

Symbol

V_CCINTR

Description

Speed Grade

Ramp Time

0.20 to 50.0

0.20 to 40.0

0.20 to 50.0

Units

ms

Internal supply voltage ramp time

-3, -3N, -2

-1L

All

ms

(1)

V_CCO2

Output drivers bank 2 supply voltage ramp time

Auxiliary supply voltage ramp time

ms

V_CCAUXR

All

ms

Notes:

1. The minimum V

for power-on reset and configuration is 1.65V.

CCO2

2. Spartan-6 FPGAs require a certain amount of supply current during power-on to insure proper device initialization. The actual current

consumed depends on the power-on ramp rate of the power supply. Use the Xilinx Power Estimator (XPE) or Xilinx Power Analyzer (XPA)

tools to estimate current drain on these supplies. Spartan-6 devices do not have a required power-on sequence.

DS162 (v3.1.1) January 30, 2015

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Product Specification

7

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

SelectIO™ Interface DC Input and Output Levels

Table 7: Recommended Operating Conditions for User I/Os Using Single-Ended Standards

V

_CCOfor Drivers⁽¹⁾

V_REFfor Inputs

V, Nom

I/O Standard

V, Min

3.0

2.3

1.65

1.4

1.1

3.0

2.7

3.0

1.7

1.4

1.7

3.0

2.3

1.7

1.425

V, Nom

3.3

2.5

1.8

1.5

1.2

3.3

3.0

3.3

1.8

1.5

1.8

3.3

2.5

1.8

1.5

V, Max

3.45

2.7

V, Min

V, Max

LVTTL

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS18_JEDEC

LVCMOS15

LVCMOS15_JEDEC

LVCMOS12

LVCMOS12_JEDEC

PCI33_3⁽²⁾

PCI66_3⁽²⁾

I2C

1.95

1.6

1.3

V_REFis not used for these I/O standards

1.3

3.45

1.9

SMBUS

SDIO

MOBILE_DDR

HSTL_I

1.6

0.68

–

0.75

0.9

HSTL_II

1.6

HSTL_III

1.6

–

HSTL_I_18

HSTL_II_18

HSTL_III_18

SSTL3_I

1.9

0.8

0.9

1.1

1.9

–

0.9

–

1.9

–

1.1

–

3.45

2.7

1.3

1.5

1.7

SSTL3_II

1.3

1.5

1.7

SSTL2_I

1.13

0.833

0.69

1.25

0.9

1.38

0.969

0.81

SSTL2_II

2.7

SSTL18_I

1.9

SSTL18_II

SSTL15_II

1.9

0.9

1.575

0.75

Notes:

1.

V

range required when using I/O standard for an output. Also required for MOBILE_DDR, PCI33_3, LVCMOS18_JEDEC,

CCO

LVCMOS15_JEDEC, and LVCMOS12_JEDEC inputs, and for LVCMOS25 inputs when V

= 3.3V.

CCAUX

2. For PCI systems, the transmitter and receiver should have common supplies for V

.

CCO

DS162 (v3.1.1) January 30, 2015

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Product Specification

8

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 8: Recommended Operating Conditions for User I/Os Using Differential Signal Standards

V_CCOfor Drivers

I/O Standard

V, Min

3.0

V, Nom

V, Max

3.45

LVDS_33

3.3

LVDS_25

2.25

3.0

2.5

2.75

BLVDS_25

2.5

2.75

MINI_LVDS_33

MINI_LVDS_25

LVPECL_33⁽¹⁾

LVPECL_25

3.3

3.45

2.25

2.5

2.75

N/A–Inputs Only

RSDS_33

3.0

2.25

3.14

3.0

3.3

2.5

3.3

2.5

1.8

1.5

1.8

3.3

2.5

1.8

1.5

3.45

2.75

3.45

2.75

2.7

RSDS_25

TMDS_33⁽¹⁾

PPDS_33

PPDS_25

2.25

2.3

DISPLAY_PORT

DIFF_MOBILE_DDR

DIFF_HSTL_I

DIFF_HSTL_II

DIFF_HSTL_III

DIFF_HSTL_I_18

DIFF_HSTL_II_18

DIFF_HSTL_III_18

DIFF_SSTL3_I

DIFF_SSTL3_II

DIFF_SSTL2_I

DIFF_SSTL2_II

DIFF_SSTL18_I

DIFF_SSTL18_II

DIFF_SSTL15_II

1.7

1.9

1.4

1.6

1.4

1.6

1.4

1.6

1.7

1.9

1.7

1.9

1.7

1.9

3.0

3.45

2.7

3.0

2.3

2.7

1.7

1.9

1.7

1.9

1.425

1.575

Notes:

1. LVPECL_33 and TMDS_33 inputs require V

= 3.3V nominal.

CCAUX

DS162 (v3.1.1) January 30, 2015

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Product Specification

9

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

In Table 9 and Table 10, values for V and V are recommended input voltages. Values for I and I are guaranteed over

IL

IH

OL

OH

the recommended operating conditions at the V and V test points. Only selected standards are tested. These are

OL

OH

chosen to ensure that all standards meet their specifications. The selected standards are tested at a minimum V

with the

CCO

respective V and V voltage levels shown. Other standards are sample tested.

OL

OH

Table 9: Single-Ended I/O Standard DC Input and Output Levels

V_ILV_IH

V_OL

V, Max

0.4

V_OH

V, Min

I_OL

I_OH

mA

I/O Standard

V, Min

–0.5

V, Max

0.8

V, Min

2.0

V, Max

4.1

mA

Note 2

Note 3

Note 4

1.5

LVTTL

2.4

Note 2

Note 3

Note 4

–0.5

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS18 (-1L)

LVCMOS18_JEDEC

LVCMOS15

LVCMOS15 (-1L)

LVCMOS15_JEDEC

LVCMOS12

LVCMOS12 (-1L)

LVCMOS12_JEDEC

PCI33_3

0.8

2.0

4.1

0.4

V_CCO– 0.4

0.7

1.7

4.1

0.4

0.38

0.33

0.8

4.1

0.45

V

_CCO– 0.45

V_CCO– 0.45

75% V_CCO

0.71

4.1

0.45

35% V_CCO

0.38

65% V_CCO

0.8

4.1

0.45

4.1

25% V_CCO

0.4

0.33

0.71

4.1

35% V_CCO

0.38

65% V_CCO

0.8

4.1

V_CCO– 0.4

0.33

0.71

4.1

0.4

V_CCO– 0.4

90% V_CCO

–

35% V_CCO

30% V_CCO

25% V_CCO

0.8

65% V_CCO

50% V_CCO

70% V_CCO

2.1

4.1

0.4

V_CCO+ 0.5

4.1

10% V_CCO

20% V_CCO

0.4

PCI66_3

1.5

–0.5

I2C

3

–

SMBUS

4.1

–

4

–

SDIO

12.5% V_CCO

20% V_CCO

75% V_CCO

80% V_CCO

V_REF+ 0.1

V_REF+ 0.2

4.1

12.5% V_CCO

10% V_CCO

0.4

75% V_CCO

90% V_CCO

V_CCO– 0.4

V_TT+ 0.6

V_TT+ 0.8

V_TT+ 0.61

V_TT+ 0.81

V_TT+ 0.47

V_TT+ 0.60

V_TT+ 0.4

0.1

–0.1

MOBILE_DDR

HSTL_I

4.1

0.1

–0.1

V

_REF– 0.1

4.1

8

–8

HSTL_II

V_REF– 0.1

4.1

0.4

16

–16

HSTL_III

V

_REF– 0.1

_REF– 0.2

4.1

0.4

24

–8

HSTL_I_18

HSTL_II_18

HSTL_III_18

SSTL3_I

4.1

0.4

11

–11

4.1

0.4

22

–22

4.1

0.4

30

–11

4.1

V_TT– 0.6

V_TT– 0.8

V_TT– 0.61

V_TT– 0.81

V_TT– 0.47

V_TT– 0.60

V_TT– 0.4

8

–8

SSTL3_II

V_REF– 0.2

4.1

16

–16

SSTL2_I

V

_REF– 0.15

V_REF+ 0.15

V_REF+ 0.125

V_REF+ 0.1

4.1

8.1

–8.1

SSTL2_II

V

4.1

16.2

6.7

–16.2

–6.7

SSTL18_I

V_REF– 0.125

_REF– 0.125

V_REF– 0.1

4.1

SSTL18_II

SSTL15_II

V

4.1

13.4

–13.4

4.1

Notes:

1. Tested according to relevant specifications.

2. Using drive strengths of 2, 4, 6, 8, 12, 16, or 24 mA.

3. Using drive strengths of 2, 4, 6, 8, 12, or 16 mA.

4. Using drive strengths of 2, 4, 6, 8, or 12 mA.

5. For more information, refer to UG381: Spartan-6 FPGA SelectIO Resources User Guide.

DS162 (v3.1.1) January 30, 2015

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Product Specification

10

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 10: Differential I/O Standard DC Input and Output Levels

V_IDV_ICMV_OD

V_OCM

V_OH

V_OL

mV,

Min

mV,

V, Min V, Max mV, Min

V, Min

V, Max

V, Min

V, Max

I/O Standard

LVDS_33⁽²⁾⁽³⁾

LVDS_25⁽²⁾⁽³⁾

BLVDS_25⁽²⁾⁽³⁾

MINI_LVDS_33

MINI_LVDS_25

LVPECL_33⁽²⁾⁽³⁾

LVPECL_25⁽²⁾⁽³⁾

RSDS_33⁽²⁾⁽³⁾

RSDS_25⁽²⁾⁽³⁾

TMDS_33

Max

100

200

100

150

100

190

600

–

0.3

2.7

0.2

0.3

0.78

0.68

0.8

1.0

0.7

0.55

2.35

1.95

2.8⁽¹⁾

1.95

1.5

247

240

300

454

460

600

1.125

1.375

–

Typical 50% V_CCO

600

1000

–

1.0

1.4

Inputs only

1.4

100

400

100

–

400

800

400

–

1.0

–

1.5

1200

400

1260

–

3.23⁽¹⁾

2.3

V_CCO– 0.405 V_CCO– 0.190

PPDS_33⁽²⁾⁽³⁾

PPDS_25⁽²⁾⁽³⁾

DISPLAY_PORT

0.5

1.4

2.3

2.35

1.02

0.9

Typical 50% V_CCO

DIFF_MOBILE_DDR 100

–

90% V_CCO10% V_CCO

DIFF_HSTL_I

100

–

V_CCO– 0.4

0.4

DIFF_HSTL_II

–

0.9

–

DIFF_HSTL_III

DIFF_HSTL_I_18

DIFF_HSTL_II_18

DIFF_HSTL_III_18

DIFF_SSTL3_I

DIFF_SSTL3_II

DIFF_SSTL2_I

DIFF_SSTL2_II

DIFF_SSTL18_I

DIFF_SSTL18_II

DIFF_SSTL15_II

–

0.9

–

V

_CCO– 0.4

–

1.1

–

1.1

–

V_CCO– 0.4

_CCO– 0.4

–

1.1

–

V

–

1.9

–

V

_TT+ 0.6 V_TT– 0.6

–

1.9

–

V_TT+ 0.8 V_TT– 0.8

–

1.5

–

V

_TT+ 0.61 V_TT– 0.61

_TT+ 0.81 V_TT– 0.81

_TT+ 0.47 V_TT– 0.47

–

1.5

–

V

–

1.1

–

1.1

–

V

_TT+ 0.6 V_TT– 0.6

–

0.95

–

V_TT+ 0.4 V_TT– 0.4

Notes:

1. LVPECL_33 and TMDS_33 maximum V

is the lower of V (maximum) or V

– (V /2)

ICM

CCAUX ID

2. When V

= 3.3V, the DCD can be higher than 5% for V

< 0.7V when using these I/O standards: LVDS_25, LVDS_33, BLVDS_25,

CCAUX

ICM

LVPECL_25, LVPECL_33, RSDS_25, RSDS_33, PPDS_25, and PPDS_33.

3. The -1L devices require V = 2.5V when using the LVDS_25, LVDS_33, BLVDS_25, LVPECL_25, RSDS_25, RSDS_33, PPDS_25,

CCAUX

and PPDS_33 I/O standards on inputs. LVPECL_33 is not supported in the -1L devices.

DS162 (v3.1.1) January 30, 2015

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Product Specification

11

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

eFUSE Read Endurance

Table 11 lists the minimum guaranteed number of read cycle operations for Device DNA and for the AES eFUSE key. For

more information, see UG380: Spartan-6 FPGA Configuration User Guide.

Table 11: eFUSE Read Endurance

Speed Grade

Units

Symbol

Description

(Min)

-3

-3N

-2

-1L

DNA_CYCLES

Number of DNA_PORT READ operations or JTAG ISC_DNA read

command operations. Unaffected by SHIFT operations.

Read

Cycles

30,000,000

AES_CYCLES

Number of JTAG FUSE_KEY or FUSE_CNTL read command operations.

Unaffected by SHIFT operations.

Read

Cycles

GTP Transceiver Specifications

GTP transceivers are available in the Spartan-6 LXT devices. See DS160: Spartan-6 Family Overview for more information.

GTP Transceiver DC Characteristics

(1)

Table 12: Absolute Maximum Ratings for GTP Transceivers

Symbol

Description

MIn

Max

Units

MGTAVCC

Analog supply voltage for the GTP transmitter and receiver circuits relative to

GND

–0.5

1.32

V

MGTAVTTTX

MGTAVTTRX

MGTAVCCPLL

Analog supply voltage for the GTP transmitter termination circuit relative to GND

Analog supply voltage for the GTP receiver termination circuit relative to GND

–0.5

1.32

V

Analog supply voltage for the GTP transmitter and receiver PLL circuits relative to

GND

MGTAVTTRCAL Analog supply voltage for the resistor calibration circuit of the GTP transceiver

bank (top or bottom)

–0.5

1.32

V

V_IN

Receiver (RXP/RXN) and Transmitter (TXP/TXN) absolute input voltage

Reference clock absolute input voltage

–0.5

1.32

V

V_MGTREFCLK

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to

Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.

(1)(2)(3)

Table 13: Recommended Operating Conditions for GTP Transceivers

Symbol

Description

Min

Typ

1.20

Max

1.26

Units

MGTAVCC

Analog supply voltage for the GTP transmitter and receiver circuits relative to GND 1.14

V

MGTAVTTTX

MGTAVTTRX

Analog supply voltage for the GTP transmitter termination circuit relative to GND

Analog supply voltage for the GTP receiver termination circuit relative to GND

1.14

MGTAVCCPLL Analog supply voltage for the GTP transmitter and receiver PLL circuits relative to 1.14

GND

MGTAVTTRCAL Analog supply voltage for the resistor calibration circuit of the GTP transceiver

bank (top or bottom)

1.14

1.20

1.26

V

Notes:

1. Each voltage listed requires the filter circuit described in UG386: Spartan-6 FPGA GTP Transceivers User Guide.

2. Voltages are specified for the temperature range of T_j= –40°C to +125°C.

3. The voltage level of MGTAVCCPLL must not exceed the voltage level of MGTAVCC +10mV. The voltage level of MGTAVCC must not exceed the

voltage level of MGTAVCCPLL.

DS162 (v3.1.1) January 30, 2015

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Product Specification

12

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 14: GTP Transceiver Current Supply (per Lane)

Symbol

I_MGTAVCC

Description

Typ⁽¹⁾

40.4

27.4

13.6

28.7

Max

Units

mA

Ω

GTP transceiver internal analog supply current

GTP transmitter termination supply current

I_MGTAVTTTX

I_MGTAVTTRX

I_MGTAVCCPLL

R_MGTRREF

Note 2

GTP receiver termination supply current

GTP transmitter and receiver PLL supply current

Precision reference resistor for internal calibration termination

50.0 1%

tolerance

Notes:

1. Typical values are specified at nominal voltage, 25°C, with a 2.5 Gb/s line rate, with a shared PLL use mode.

2. Values for currents of other transceiver configurations and conditions can be obtained by using the Xilinx Power Estimator (XPE) or Xilinx Power

Analyzer (XPA) tools.

(1)(2)(3)(4)

Table 15: GTP Transceiver Quiescent Supply Current (per Lane)

Symbol

Description

Quiescent MGTAVCC supply current

Typ⁽⁵⁾

1.7

Max

Units

mA

I_MGTAVCCQ

I_MGTAVTTTXQQuiescent MGTAVTTTX supply current

I_MGTAVTTRXQQuiescent MGTAVTTRX supply current

I_MGTAVCCPLLQQuiescent MGTAVCCPLL supply current

0.1

mA

Note 2

1.2

mA

1.0

mA

Notes:

1. Device powered and unconfigured.

2. Currents for conditions other than values specified in this table can be obtained by using the Xilinx Power Estimator (XPE) or Xilinx Power Analyzer

(XPA) tools.

3. GTP transceiver quiescent supply current for an entire device can be calculated by multiplying the values in this table by the number of available GTP

transceivers.

4. Does not include power-up MGTAVTTRCAL supply current during device configuration.

5. Typical values are specified at nominal voltage, 25°C.

DS162 (v3.1.1) January 30, 2015

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Product Specification

13

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

GTP Transceiver DC Input and Output Levels

Table 16 summarizes the DC output specifications of the GTP transceivers in Spartan-6 FPGAs. Figure 1 shows the single-

ended output voltage swing. Figure 2 shows the peak-to-peak differential output voltage.

Consult UG386: Spartan-6 FPGA GTP Transceivers User Guide for further details.

Table 16: GTP Transceiver DC Specifications

Symbol

DC Parameter

Conditions

Min

Typ

Max

Units

Differential peak-to-peak input External AC coupled

voltage

140

–

2000

mV

DV_PPIN

Absolute input voltage

DC coupled

MGTAVTTRX = 1.2V

–400

–

MGTAVTTRX mV

V_IN

Common mode input voltage

DC coupled

MGTAVTTRX = 1.2V

3/4

–

mV

V_CMIN

MGTAVTTRX

Differential peak-to-peak output Transmitter output swing is set

voltage⁽¹⁾

to maximum setting

1000

–

DV_PPOUT

V_SEOUT

V_CMOUTDC

R_IN

Single-ended output voltage swing⁽¹⁾

Common mode output voltage Equation based

Differential input resistance

–

500

mV

Ω

MGTAVTTTX – V_SEOUT/2

80

–

100

–

130

R_OUT

Differential output resistance

130

15

Ω

T_OSKEW

C_EXT

Transmitter output skew

ps

nF

Recommended external AC coupling capacitor⁽²⁾

75

100

200

Notes:

1. The output swing and preemphasis levels are programmable using the attributes discussed in UG386: Spartan-6 FPGA GTP Transceivers User

Guide and can result in values lower than reported in this table. DV_PPOUTis the minimum guaranteed value at the maximum setting. Refer to UG386:

Spartan-6 FPGA GTP Transceivers User Guide for nominal values.

2. Other values can be used as appropriate to conform to specific protocols and standards.

X-Ref Target - Figure 1

+V

0

P

N

Single-Ended

Voltage

ds162_01_112009

Figure 1: Single-Ended Peak-to-Peak Voltage

X-Ref Target - Figure 2

+V

0

Differential

Voltage

P–N

–V

ds162_02_112009

Figure 2: Differential Peak-to-Peak Voltage

Table 17 summarizes the DC specifications of the clock input of the GTP transceiver. Consult UG386: Spartan-6 FPGA GTP

Transceivers User Guide for further details.

DS162 (v3.1.1) January 30, 2015

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Product Specification

14

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 17: GTP Transceiver Clock DC Input Level Specification

Symbol

V_IDIFF

R_IN

DC Parameter

Differential peak-to-peak input voltage

Min

200

80

Typ

800

100

Max

2000

120

–

Units

mV

Ω

Differential input resistance

C_EXT

Required external AC coupling capacitor

–

nF

GTP Transceiver Switching Characteristics

Consult UG386: Spartan-6 FPGA GTP Transceivers User Guide for further information.

Table 18: GTP Transceiver Performance

Speed Grade

Symbol

Description

Units

-3

3.2

-3N

-2

-1L

N/A

F_GTPMAX

Maximum GTP transceiver data rate

3.2

2.7

Gb/s

F_GTPRANGE1

F_GTPRANGE2

F_GTPRANGE3

GTP transceiver data rate range when

PLL_TXDIVSEL_OUT = 1

1.88 to 3.2

1.88 to 2.7

GTP transceiver data rate range when

PLL_TXDIVSEL_OUT = 2

0.94 to 1.62 0.94 to 1.62 0.94 to 1.62

N/A

Gb/s

GTP transceiver data rate range when

PLL_TXDIVSEL_OUT = 4

0.6 to 0.81

F_GPLLMAX

F_GPLLMIN

Maximum PLL frequency

Minimum PLL frequency

1.62

0.94

1.62

0.94

1.62

0.94

N/A

GHz

Table 19: GTP Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics

Speed Grade

Symbol

Description

Units

-3

-3N

-2

-1L

F_GTPDRPCLK

GTP transceiver DCLK (DRP clock) maximum frequency

125

100

N/A

MHz

Table 20: GTP Transceiver Reference Clock Switching Characteristics

All LXT Speed Grades

Symbol

Description

Conditions

Units

Min

Typ

–

Max

F_GCLK

T_RCLK

T_FCLK

Reference clock frequency range

Reference clock rise time

Reference clock fall time

60

–

160

–

MHz

ps

20% – 80%

80% – 20%

200

50

–

ps

T_DCREFReference clock duty cycle

Transceiver PLL only

45

–

55

1

%

T_LOCKClock recovery frequency acquisition Initial PLL lock

ms

time

T_PHASEClock recovery phase acquisition time Lock to data after PLL has locked to

the reference clock

–

200

µs

X-Ref Target - Figure 3

T_RCLK

80%

20%

T_FCLK

ds162_05_042109

Figure 3: Reference Clock Timing Parameters

DS162 (v3.1.1) January 30, 2015

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Product Specification

15

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 21: GTP Transceiver User Clock Switching Characteristics

Speed Grade

Symbol

Description

Conditions

Units

-3

320

-3N

320

-2

-1L

N/A

F_TXOUT

F_RXREC

T_RX

TXOUTCLK maximum frequency

RXRECCLK maximum frequency

RXUSRCLK maximum frequency

RXUSRCLK2 maximum frequency

270

125

67.5

270

125

67.5

MHz

320

T_RX2

1 byte interface

2 byte interface

4 byte interface

156.25

160

156.25

160

80

T_TX

TXUSRCLK maximum frequency

TXUSRCLK2 maximum frequency

320

T_TX2

1 byte interface

2 byte interface

4 byte interface

156.25

160

156.25

160

80

Notes:

1. Clocking must be implemented as described in UG386: Spartan-6 FPGA GTP Transceivers User Guide.

Table 22: GTP Transceiver Transmitter Switching Characteristics

Symbol

T_RTX

Description

Condition

20%–80%

80%–20%

Min

–

Typ

Max

–

Units

ps

mV

ns

UI

TX Rise time

TX Fall time

140

120

–

T_FTX

–

T_LLSKEW

V_TXOOBVDPP

T_{TXOOBTRANSITION}

T_J3.125

TX lane-to-lane skew⁽¹⁾

Electrical idle amplitude

Electrical idle transition time

Total Jitter⁽²⁾

Deterministic Jitter⁽²⁾

Total Jitter⁽²⁾

Deterministic Jitter⁽²⁾

Total Jitter⁽²⁾

Deterministic Jitter⁽²⁾

Total Jitter⁽²⁾

–

400

20

–

50

3.125 Gb/s

2.5 Gb/s

–

0.35

0.15

0.33

0.15

0.20

0.10

0.20

0.10

0.05

D_J3.125

T_J2.5

–

UI

–

UI

D_J2.5

–

UI

T_J1.62

1.62 Gb/s

1.25 Gb/s

614 Mb/s

–

UI

D_J1.62

–

UI

T_J1.25

–

UI

D_J1.25

Deterministic Jitter⁽²⁾

Total Jitter⁽²⁾

Deterministic Jitter⁽²⁾

–

UI

T_J614

–

UI

D_J614

–

UI

Notes:

1. Using same REFCLK input with TXENPMAPHASEALIGN enabled for up to four consecutive GTP transceiver sites.

2. Using PLL_DIVSEL_FB = 2, INTDATAWIDTH = 1. These values are NOT intended for protocol specific compliance determinations.

DS162 (v3.1.1) January 30, 2015

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Product Specification

16

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 23: GTP Transceiver Receiver Switching Characteristics

Symbol

T_RXELECIDLE

R_XOOBVDPP

R_XSST

Description

Min

–

Typ

75

–

Max

–

Units

ns

Time for RXELECIDLE to respond to loss or restoration of data

OOB detect threshold peak-to-peak

60

150

0

mV

Receiver spread-spectrum tracking⁽¹⁾

Modulated @ 33 KHz

Internal AC capacitor bypassed

CDR 2^nd-order loop disabled

–5000

–

ppm

UI

R_XRL

Run length (CID)

–

150

200

2000

1000

–200

–

ppm

PLL_RXDIVSEL_OUT = 1 –2000

PLL_RXDIVSEL_OUT = 2 –2000

PLL_RXDIVSEL_OUT = 4 –1000

–

Data/REFCLK PPM offset

tolerance

CDR 2^nd-order

loop enabled

R_XPPMTOL

–

SJ Jitter Tolerance⁽²⁾

JT_SJ_3.125

JT_SJ_2.5

Sinusoidal Jitter⁽³⁾

3.125 Gb/s

2.5 Gb/s

0.4

0.5

–

UI

JT_SJ_1.62

1.62 Gb/s

1.25 Gb/s

614 Mb/s

JT_SJ_1.25

JT_SJ₆₁₄

SJ Jitter Tolerance with Stressed Eye⁽²⁾⁽⁵⁾

JT_TJSE_3.125

JT_SJSE_3.125

JT_TJSE_2.7

JT_SJSE_2.7

Total Jitter with stressed eye⁽⁴⁾

3.125 Gb/s

2.7 Gb/s

0.65

0.1

–

UI

Sinusoidal Jitter with stressed eye

Total Jitter with stressed eye⁽⁴⁾

0.65

0.1

Sinusoidal Jitter with stressed eye

2.7 Gb/s

Notes:

1. Using PLL_RXDIVSEL_OUT = 1, 2, and 4.

2. All jitter values are based on a Bit Error Ratio of 1e^–12

.

3. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.

4. Composed of 0.37 UI DJ in the form of ISI and 0.18 UI RJ.

5. Measured using PRBS7 data pattern.

Endpoint Block for PCI Express Designs Switching Characteristics

The Endpoint block for PCI Express is available in the Spartan-6 LXT devices. Consult the Spartan-6 FPGA Integrated

Endpoint Block for PCI Express for further information.

Table 24: Maximum Performance for PCI Express Designs

Speed Grade

Symbol

Description

User clock maximum frequency

Units

-3

-3N

-2

-1L

F_PCIEUSER

62.5

N/A

MHz

DS162 (v3.1.1) January 30, 2015

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Product Specification

17

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Performance Characteristics

This section provides the performance characteristics of some common functions and designs implemented in

Spartan-6 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values

are subject to the same guidelines as the Switching Characteristics, page 19.

Table 25: Interface Performances

Speed Grade

Clock

Buffer

Data

Width

Description

I/O Resource

Units

-3

-3N

-2

-1L

Networking Applications⁽¹⁾

SDR LVDS transmitter or receiver

DDR LVDS transmitter or receiver

IOB SDR register

BUFG

–

400

800

400

800

375

750

500

750

950

500

750

950

500

750

950

500

750

950

250

500

250

375

500

250

375

500

—

Mb/s

ODDR2/IDDR2 register

2 BUFGs

2

500

SDR LVDS transmitter

DDR LVDS transmitter

SDR LVDS receiver

DDR LVDS receiver

OSERDES2

BUFPLL

2 BUFIO2s

BUFPLL

3

750

4-8

2

1080

500

1050

500

3

750

4-8

2

1080

500

1050

500

ISERDES2 in RETIMED mode

3

750

—

4-8

2

1080

500

1050

500

—

ISERDES2 in RETIMED mode 2 BUFIO2s

3

750

—

4-8

1080

1050

—

Memory Interfaces (Implemented using the Spartan-6 FPGA Memory Controller Block)⁽²⁾

Standard Performance (Standard V_CCINT

)

DDR

400 Note 4 400

667 Note 4 625

800 Note 4 667

400 Note 4 400

350

400

—

Mb/s

DDR2

DDR3

LPDDR (Mobile_DDR)

350

(3)

Extended Performance (Requires Extended Performance V_CCINT

)

DDR2

800 Note 4 667

—

Mb/s

Notes:

1. Refer to XAPP1064, Source-Synchronous Serialization and Deserialization (up to 1050 Mb/s) and UG381, Spartan-6 FPGA SelectIO

Resources User Guide.

2. Refer to UG388, Spartan-6 FPGA Memory Controller User Guide.

3. Extended Memory Controller block performance for DDR2 can be achieved using the extended performance V

range from Table 2.

CCINT

4. The LX4 device, all devices in the TQG144 and CPG196 packages, and the -3N speed grade do not support a Memory Controller Block.

DS162 (v3.1.1) January 30, 2015

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Product Specification

18

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Switching Characteristics

All values represented in this data sheet are based on these

speed specifications: v1.20 for -3, -3N, and -2; and v1.08 for

-1L. Switching characteristics are specified on a per-speed-

grade basis and can be designated as Advance,

Preliminary, or Production. Each designation is defined as

follows:

Table 26: Spartan-6 Device Speed Grade Designations

Speed Grade Designations

Device

Advance

Preliminary

Production

-3, -2, -1L

-3, -3N, -2, -1L

-3, -3N, -2

-3, -3N, -2, -1L

-3, -3N, -2

-3, -3N, -2, -1L

-3, -3N, -2

-3, -3N, -2, -1L

-3, -3N, -2

-3, -3N, -2, -1L

-3, -3N, -2

-3, -2

XC6SLX4⁽¹⁾

XC6SLX9

Advance

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

These specifications are based on simulations only and are

typically available soon after device design specifications

are frozen. Although speed grades with this designation are

considered relatively stable and conservative, some under-

reporting might still occur.

Preliminary

These specifications are based on complete ES

(engineering sample) silicon characterization. Devices and

speed grades with this designation are intended to give a

better indication of the expected performance of production

silicon. The probability of under-reporting delays is greatly

reduced as compared to Advance data.

Production

XA6SLX9

-3, -2

These specifications are released once enough production

silicon of a particular device family member has been

characterized to provide full correlation between

specifications and devices over numerous production lots.

There is no under-reporting of delays, and customers

receive formal notification of any subsequent changes.

Typically, the slowest speed grades transition to Production

before faster speed grades.

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

XQ6SLX75

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

-3, -2

All specifications are always representative of worst-case

supply voltage and junction temperature conditions.

-3, -2

-2

Since individual family members are produced at different

times, the migration from one category to another depends

completely on the status of the fabrication process for each

device.

-2, -1L

-3, -2

-2, -1L

The -1L speed grade refers to the lower-power Spartan-6

devices. The -3N speed grade refers to the Spartan-6

devices that do not support MCB functionality.

-3, -2

Notes:

1. The XC6SLX4 is not available in the -3N speed grade.

Table 26 correlates the current status of each Spartan-6

device on a per speed grade basis.

Testing of Switching Characteristics

All devices are 100% functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed

below are representative values.

For more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and

back-annotated to the simulation net list. Unless otherwise noted, values apply to all Spartan-6 devices.

DS162 (v3.1.1) January 30, 2015

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Product Specification

19

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Production Silicon and ISE Software Status

In some cases, a particular family member (and speed grade) is released to production before a speed specification is

released with the correct label (Advance, Preliminary, Production). Any labeling discrepancies are corrected in subsequent

speed specification releases. Table 27 lists the production released Spartan-6 family member, speed grade, and the

minimum corresponding supported speed specification version and ISE® software revisions. The ISE software and speed

specifications listed are the minimum releases required for production. All subsequent releases of software and speed

specifications are valid.

(1)

Table 27: Spartan-6 Device Production Software and Speed Specification Release

Speed Grade Designations⁽²⁾

Device

-3⁽³⁾

-3N

-2⁽⁴⁾

-1L

XC6SLX4

ISE 12.4 v1.15

ISE 12.1 v1.08

ISE 12.2 v1.11⁽⁶⁾

ISE 12.1 v1.08

ISE 12.2 v1.11⁽⁶⁾

ISE 13.2 v1.19

N/A

ISE 12.3 v1.12⁽⁵⁾

ISE 11.5 v1.06

ISE 12.2 v1.11⁽⁶⁾

ISE 11.5 v1.07

ISE 12.1 v1.08

ISE 12.2 v1.11⁽⁶⁾

ISE 13.2 v1.19

ISE 13.3 v1.20

ISE 13.2 v1.07

XC6SLX9

ISE 13.1 Update v1.18⁽⁷⁾

ISE 13.2 v1.07

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

ISE 13.1 Update v1.18⁽⁷⁾

ISE 13.2 v1.07

ISE 13.1 Update v1.18⁽⁷⁾

ISE 13.2 v1.07

ISE 13.1 Update v1.18⁽⁷⁾

N/A

ISE 13.1 Update v1.18⁽⁷⁾

ISE 13.1 v1.06

ISE 13.1 Update v1.18⁽⁷⁾

N/A

ISE 13.1 Update v1.18⁽⁷⁾

ISE 13.2 v1.07

ISE 13.1 Update v1.18⁽⁷⁾

N/A

ISE 13.1 Update v1.18⁽⁷⁾

ISE 13.1 v1.06

ISE 13.1 Update v1.18⁽⁷⁾

N/A

ISE 13.1 v1.06

N/A

ISE 13.1 Update v1.18⁽⁷⁾

N/A

XA6SLX9

N/A

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

N/A

DS162 (v3.1.1) January 30, 2015

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Product Specification

20

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 27: Spartan-6 Device Production Software and Speed Specification Release (Cont’d)

Speed Grade Designations⁽²⁾

Device

-3⁽³⁾

N/A

-3N

N/A

-2⁽⁴⁾

-1L

ISE 13.2 v1.07

N/A

XQ6SLX75

ISE 13.2 v1.19

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

ISE 13.2 v1.19

N/A

ISE 13.2 v1.07

N/A

ISE 13.2 v1.19

Notes:

1. ISE 13.3 software with v1.20 for -3, -3N, and -2; and v1.08 for -1L speed specification reflects the changes outlined in

XCN11028: Spartan-6 FPGA Speed File Changes.

2. As marked with an N/A, LXT devices and all XA devices are not available with a -1L speed grade; LX4 devices and all XA and XQ devices

are not available with a -3N speed grade.

3. Improved -3 specifications reflected in this data sheet require ISE 12.4 software with v1.15 speed specification.

4. Improved -2 specifications reflected in this data sheet require ISE 12.4 software and the 12.4 Speed Files Patch which contains the v1.17

speed specification available on the Xilinx Download Center.

5. ISE 12.3 software with v1.12 speed specification is available using ISE 12.3 software and the 12.3 Speed Files Patch available on the

Xilinx Download Center.

6. ISE 12.2 software with v1.11 speed specification is available using ISE 12.2 software and the 12.2 Speed Files Patch available on the

Xilinx Download Center.

7. ISE 13.1 software with v1.18 speed specification is available using ISE 13.1 software and the 13.1 Update available on the

Xilinx Download Center. See XCN11012: Speed File Change for -3N Devices.

IOB Pad Input/Output/3-State Switching Characteristics

Table 28 (for commercial (XC) Spartan-6 devices) and Table 29 (for Automotive XA Spartan-6 and Defense-grade

Spartan-6Q devices) summarizes the values of standard-specific data input delays, output delays terminating at pads

(based on standard), and 3-state delays.

•

T

is described as the delay from IOB pad through the input buffer to the I-pin of an IOB pad. The delay varies

IOPI

depending on the capability of the SelectIO input buffer.

T

is described as the delay from the O pin to the IOB pad through the output buffer of an IOB pad. The delay varies

IOOP

depending on the capability of the SelectIO output buffer.

T

is described as the delay from the T pin to the IOB pad through the output buffer of an IOB pad, when 3-state is

IOTP

disabled. The delay varies depending on the SelectIO capability of the output buffer.

See the TRACE report for further information on delays when using an I/O standard with UNTUNED termination on inputs

or outputs.

Table 28: IOB Switching Characteristics for the Commercial (XC) Spartan-6 Devices

T_IOPI

T_IOOP

T_IOTP

I/O Standard

Speed Grade

Units

-3

-3N

-2 -1L⁽¹⁾

-3

-3N

-2

-1L⁽¹⁾

-3

-3N

-2

-1L⁽¹⁾

LVDS_33

LVDS_25

BLVDS_25

1.17 1.29 1.42 1.68 1.55 1.69 1.89 2.42 3000 3000 3000 3000

1.01 1.13 1.26 1.57 1.65 1.79 1.99 2.47 3000 3000 3000 3000

1.02 1.14 1.27 1.57 1.72 1.86 2.06 2.68 1.72 1.86 2.06 2.68

1.17 1.29 1.42 1.68 1.57 1.71 1.91 2.41 3000 3000 3000 3000

1.01 1.13 1.26 1.57 1.65 1.79 1.99 2.47 3000 3000 3000 3000

ns

MINI_LVDS_33

MINI_LVDS_25

LVPECL_33

1.18 1.30 1.43 1.68

1.02 1.14 1.27 1.57

N/A

LVPECL_25

RSDS_33 (point to point)

RSDS_25 (point to point)

TMDS_33

1.17 1.29 1.42 1.68 1.57 1.71 1.91 2.42 3000 3000 3000 3000

1.01 1.13 1.26 1.56 1.65 1.79 1.99 2.47 3000 3000 3000 3000

1.21 1.33 1.46 1.71 1.54 1.68 1.88 2.50 3000 3000 3000 3000

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Product Specification

21

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 28: IOB Switching Characteristics for the Commercial (XC) Spartan-6 Devices (Cont’d)

T_IOPI

T_IOOP

T_IOTP

I/O Standard

Speed Grade

Units

-3

-3N

-2 -1L⁽¹⁾

-3

-3N

-2

-1L⁽¹⁾

-3

-3N

-2

-1L⁽¹⁾

PPDS_33

PPDS_25

PCI33_3

PCI66_3

1.17 1.29 1.42 1.68 1.57 1.71 1.91 2.43 3000 3000 3000 3000

1.01 1.13 1.26 1.56 1.68 1.82 2.02 2.47 3000 3000 3000 3000

ns

1.07 1.19 1.32 1.57⁽²⁾3.51 3.65 3.85 4.38⁽²⁾3.51 3.65 3.85 4.38⁽¹⁾ns

1.07 1.19 1.32 1.57⁽²⁾3.53 3.67 3.87 4.39⁽²⁾3.53 3.67 3.87 4.39⁽¹⁾ns

DISPLAY_PORT

I2C

1.02 1.14 1.27 1.56 3.15 3.29 3.49 4.08 3.15 3.29 3.49 4.08

1.33 1.45 1.58 1.82 11.56 11.70 11.90 12.52 11.56 11.70 11.90 12.52

1.36 1.48 1.61 1.84 2.64 2.78 2.98 3.60 2.64 2.78 2.98 3.60

0.94 1.06 1.19 1.43 2.35 2.49 2.69 3.31 2.35 2.49 2.69 3.31

0.90 1.02 1.15 1.39 1.66 1.80 2.00 2.62 1.66 1.80 2.00 2.62

0.91 1.03 1.16 1.40 1.72 1.86 2.06 2.68 1.72 1.86 2.06 2.68

0.95 1.07 1.20 1.44 1.67 1.81 2.01 2.61 1.67 1.81 2.01 2.61

0.94 1.06 1.19 1.43 1.77 1.91 2.11 2.73 1.77 1.91 2.11 2.73

0.94 1.06 1.19 1.43 1.85 1.99 2.19 2.81 1.85 1.99 2.19 2.81

0.99 1.11 1.24 1.47 1.79 1.93 2.13 2.72 1.79 1.93 2.13 2.72

1.58 1.70 1.83 2.16 1.83 1.97 2.17 2.72 1.83 1.97 2.17 2.72

1.58 1.70 1.83 2.16 2.01 2.15 2.35 2.94 2.01 2.15 2.35 2.94

1.30 1.42 1.55 1.87 1.77 1.91 2.11 2.69 1.77 1.91 2.11 2.69

1.30 1.42 1.55 1.88 1.86 2.00 2.20 2.82 1.86 2.00 2.20 2.82

0.92 1.04 1.17 1.41 1.63 1.77 1.97 2.59 1.63 1.77 1.97 2.59

0.92 1.04 1.17 1.41 1.66 1.80 2.00 2.62 1.66 1.80 2.00 2.62

0.92 1.04 1.17 1.41 1.67 1.81 2.01 2.63 1.67 1.81 2.01 2.63

0.94 1.06 1.19 1.46 1.77 1.91 2.11 2.62 1.77 1.91 2.11 2.62

0.93 1.05 1.18 1.45 1.72 1.86 2.06 2.54 1.72 1.86 2.06 2.54

0.93 1.05 1.18 1.46 1.69 1.83 2.03 2.53 1.69 1.83 2.03 2.53

0.97 1.09 1.22 1.50 1.79 1.93 2.13 2.63 1.79 1.93 2.13 2.63

0.97 1.09 1.22 1.49 1.69 1.83 2.03 2.51 1.69 1.83 2.03 2.51

0.97 1.09 1.22 1.50 1.69 1.83 2.03 2.53 1.69 1.83 2.03 2.53

1.18 1.30 1.43 1.68 1.81 1.95 2.15 2.64 1.81 1.95 2.15 2.64

1.19 1.31 1.44 1.68 1.80 1.94 2.14 2.63 1.80 1.94 2.14 2.63

1.02 1.14 1.27 1.57 1.80 1.94 2.14 2.62 1.80 1.94 2.14 2.62

1.02 1.14 1.27 1.57 1.76 1.90 2.10 2.57 1.76 1.90 2.10 2.57

0.97 1.09 1.22 1.51 1.72 1.86 2.06 2.56 1.72 1.86 2.06 2.56

0.98 1.10 1.23 1.50 1.68 1.82 2.02 2.52 1.68 1.82 2.02 2.52

0.94 1.06 1.19 1.46 1.67 1.81 2.01 2.50 1.67 1.81 2.01 2.50

0.97 1.09 1.22 1.51 1.75 1.89 2.09 2.57 1.75 1.89 2.09 2.57

ns

SMBUS

SDIO

MOBILE_DDR

HSTL_I

HSTL_II

HSTL_III

HSTL_I _18

HSTL_II _18

HSTL_III _18

SSTL3_I

SSTL3_II

SSTL2_I

SSTL2_II

SSTL18_I

SSTL18_II

SSTL15_II

DIFF_HSTL_I

DIFF_HSTL_II

DIFF_HSTL_III

DIFF_HSTL_I_18

DIFF_HSTL_II_18

DIFF_HSTL_III_18

DIFF_SSTL3_I

DIFF_SSTL3_II

DIFF_SSTL2_I

DIFF_SSTL2_II

DIFF_SSTL18_I

DIFF_SSTL18_II

DIFF_SSTL15_II

DIFF_MOBILE_DDR

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Product Specification

22

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 28: IOB Switching Characteristics for the Commercial (XC) Spartan-6 Devices (Cont’d)

T_IOPI

T_IOOP

T_IOTP

I/O Standard

Speed Grade

Units

-3

-3N

-2 -1L⁽¹⁾

-3

-3N

-2

-1L⁽¹⁾

-3

-3N

-2

-1L⁽¹⁾

LVTTL, QUIETIO, 2 mA

LVTTL, QUIETIO, 4 mA

LVTTL, QUIETIO, 6 mA

LVTTL, QUIETIO, 8 mA

LVTTL, QUIETIO, 12 mA

LVTTL, QUIETIO, 16 mA

LVTTL, QUIETIO, 24 mA

LVTTL, Slow, 2 mA

1.35 1.47 1.60 1.82 5.39 5.53 5.73 6.37 5.39 5.53 5.73 6.37

1.35 1.47 1.60 1.82 4.29 4.43 4.63 5.22 4.29 4.43 4.63 5.22

1.35 1.47 1.60 1.82 3.75 3.89 4.09 4.69 3.75 3.89 4.09 4.69

1.35 1.47 1.60 1.82 3.23 3.37 3.57 4.20 3.23 3.37 3.57 4.20

1.35 1.47 1.60 1.82 3.28 3.42 3.62 4.22 3.28 3.42 3.62 4.22

1.35 1.47 1.60 1.82 2.94 3.08 3.28 3.92 2.94 3.08 3.28 3.92

1.35 1.47 1.60 1.82 2.69 2.83 3.03 3.67 2.69 2.83 3.03 3.67

1.35 1.47 1.60 1.82 4.36 4.50 4.70 5.30 4.36 4.50 4.70 5.30

1.35 1.47 1.60 1.82 3.17 3.31 3.51 4.16 3.17 3.31 3.51 4.16

1.35 1.47 1.60 1.82 2.76 2.90 3.10 3.75 2.76 2.90 3.10 3.75

1.35 1.47 1.60 1.82 2.59 2.73 2.93 3.55 2.59 2.73 2.93 3.55

1.35 1.47 1.60 1.82 2.58 2.72 2.92 3.54 2.58 2.72 2.92 3.54

1.35 1.47 1.60 1.82 2.39 2.53 2.73 3.40 2.39 2.53 2.73 3.40

1.35 1.47 1.60 1.82 2.28 2.42 2.62 3.24 2.28 2.42 2.62 3.24

1.35 1.47 1.60 1.82 3.78 3.92 4.12 4.74 3.78 3.92 4.12 4.74

1.35 1.47 1.60 1.82 2.49 2.63 2.83 3.45 2.49 2.63 2.83 3.45

1.35 1.47 1.60 1.82 2.44 2.58 2.78 3.40 2.44 2.58 2.78 3.40

1.35 1.47 1.60 1.82 2.32 2.46 2.66 3.28 2.32 2.46 2.66 3.28

1.35 1.47 1.60 1.82 1.83 1.97 2.17 2.79 1.83 1.97 2.17 2.79

1.34 1.46 1.59 1.82 5.40 5.54 5.74 6.37 5.40 5.54 5.74 6.37

1.34 1.46 1.59 1.82 4.03 4.17 4.37 5.01 4.03 4.17 4.37 5.01

1.34 1.46 1.59 1.82 3.51 3.65 3.85 4.47 3.51 3.65 3.85 4.47

1.34 1.46 1.59 1.82 3.37 3.51 3.71 4.33 3.37 3.51 3.71 4.33

1.34 1.46 1.59 1.82 2.94 3.08 3.28 3.93 2.94 3.08 3.28 3.93

1.34 1.46 1.59 1.82 2.77 2.91 3.11 3.78 2.77 2.91 3.11 3.78

1.34 1.46 1.59 1.82 2.59 2.73 2.93 3.58 2.59 2.73 2.93 3.58

1.34 1.46 1.59 1.82 4.37 4.51 4.71 5.28 4.37 4.51 4.71 5.28

1.34 1.46 1.59 1.82 2.98 3.12 3.32 3.94 2.98 3.12 3.32 3.94

1.34 1.46 1.59 1.82 2.58 2.72 2.92 3.61 2.58 2.72 2.92 3.61

1.34 1.46 1.59 1.82 2.65 2.79 2.99 3.61 2.65 2.79 2.99 3.61

1.34 1.46 1.59 1.82 2.39 2.53 2.73 3.31 2.39 2.53 2.73 3.31

1.34 1.46 1.59 1.82 2.31 2.45 2.65 3.27 2.31 2.45 2.65 3.27

1.34 1.46 1.59 1.82 2.28 2.42 2.62 3.24 2.28 2.42 2.62 3.24

1.34 1.46 1.59 1.82 3.76 3.90 4.10 4.70 3.76 3.90 4.10 4.70

1.34 1.46 1.59 1.82 2.48 2.62 2.82 3.44 2.48 2.62 2.82 3.44

1.34 1.46 1.59 1.82 2.32 2.46 2.66 3.28 2.32 2.46 2.66 3.28

ns

LVTTL, Slow, 4 mA

LVTTL, Slow, 6 mA

LVTTL, Slow, 8 mA

LVTTL, Slow, 12 mA

LVTTL, Slow, 16 mA

LVTTL, Slow, 24 mA

LVTTL, Fast, 2 mA

LVTTL, Fast, 4 mA

LVTTL, Fast, 6 mA

LVTTL, Fast, 8 mA

LVTTL, Fast, 12 mA

LVTTL, Fast, 16 mA

LVTTL, Fast, 24 mA

LVCMOS33, QUIETIO, 2 mA

LVCMOS33, QUIETIO, 4 mA

LVCMOS33, QUIETIO, 6 mA

LVCMOS33, QUIETIO, 8 mA

LVCMOS33, QUIETIO, 12 mA

LVCMOS33, QUIETIO, 16 mA

LVCMOS33, QUIETIO, 24 mA

LVCMOS33, Slow, 2 mA

LVCMOS33, Slow, 4 mA

LVCMOS33, Slow, 6 mA

LVCMOS33, Slow, 8 mA

LVCMOS33, Slow, 12 mA

LVCMOS33, Slow, 16 mA

LVCMOS33, Slow, 24 mA

LVCMOS33, Fast, 2 mA

LVCMOS33, Fast, 4 mA

LVCMOS33, Fast, 6 mA

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Product Specification

23

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 28: IOB Switching Characteristics for the Commercial (XC) Spartan-6 Devices (Cont’d)

T_IOPI

T_IOOP

T_IOTP

I/O Standard

Speed Grade

Units

-3

-3N

-2 -1L⁽¹⁾

-3

-3N

-2

-1L⁽¹⁾

-3

-3N

-2

-1L⁽¹⁾

LVCMOS33, Fast, 8 mA

1.34 1.46 1.59 1.82 2.07 2.21 2.41 3.03 2.07 2.21 2.41 3.03

1.34 1.46 1.59 1.82 1.65 1.79 1.99 2.62 1.65 1.79 1.99 2.62

0.82 0.94 1.07 1.31 4.81 4.95 5.15 5.79 4.81 4.95 5.15 5.79

0.82 0.94 1.07 1.31 3.70 3.84 4.04 4.66 3.70 3.84 4.04 4.66

0.82 0.94 1.07 1.31 3.46 3.60 3.80 4.38 3.46 3.60 3.80 4.38

0.82 0.94 1.07 1.31 3.20 3.34 3.54 4.12 3.20 3.34 3.54 4.12

0.82 0.94 1.07 1.31 2.83 2.97 3.17 3.75 2.83 2.97 3.17 3.75

0.82 0.94 1.07 1.31 2.64 2.78 2.98 3.64 2.64 2.78 2.98 3.64

0.82 0.94 1.07 1.31 2.45 2.59 2.79 3.42 2.45 2.59 2.79 3.42

0.82 0.94 1.07 1.31 3.78 3.92 4.12 4.76 3.78 3.92 4.12 4.76

0.82 0.94 1.07 1.31 2.79 2.93 3.13 3.73 2.79 2.93 3.13 3.73

0.82 0.94 1.07 1.31 2.73 2.87 3.07 3.66 2.73 2.87 3.07 3.66

0.82 0.94 1.07 1.31 2.48 2.62 2.82 3.42 2.48 2.62 2.82 3.42

0.82 0.94 1.07 1.31 2.01 2.15 2.35 2.95 2.01 2.15 2.35 2.95

0.82 0.94 1.07 1.31 2.01 2.15 2.35 2.94 2.01 2.15 2.35 2.94

0.82 0.94 1.07 1.31 3.35 3.49 3.69 4.31 3.35 3.49 3.69 4.31

0.82 0.94 1.07 1.31 2.25 2.39 2.59 3.22 2.25 2.39 2.59 3.22

0.82 0.94 1.07 1.31 2.09 2.23 2.43 3.05 2.09 2.23 2.43 3.05

0.82 0.94 1.07 1.31 2.02 2.16 2.36 2.98 2.02 2.16 2.36 2.98

0.82 0.94 1.07 1.31 1.56 1.70 1.90 2.52 1.56 1.70 1.90 2.52

1.18 1.30 1.43 2.04 5.92 6.06 6.26 6.80 5.92 6.06 6.26 6.80

1.18 1.30 1.43 2.04 4.74 4.88 5.08 5.63 4.74 4.88 5.08 5.63

1.18 1.30 1.43 2.04 4.05 4.19 4.39 4.96 4.05 4.19 4.39 4.96

1.18 1.30 1.43 2.04 3.71 3.85 4.05 4.63 3.71 3.85 4.05 4.63

1.18 1.30 1.43 2.04 3.35 3.49 3.69 4.27 3.35 3.49 3.69 4.27

1.18 1.30 1.43 2.04 3.20 3.34 3.54 4.14 3.20 3.34 3.54 4.14

1.18 1.30 1.43 2.04 2.96 3.10 3.30 3.98 2.96 3.10 3.30 3.98

1.18 1.30 1.43 2.04 4.62 4.76 4.96 5.54 4.62 4.76 4.96 5.54

1.18 1.30 1.43 2.04 3.69 3.83 4.03 4.60 3.69 3.83 4.03 4.60

1.18 1.30 1.43 2.04 3.00 3.14 3.34 3.94 3.00 3.14 3.34 3.94

1.18 1.30 1.43 2.04 2.19 2.33 2.53 3.17 2.19 2.33 2.53 3.17

1.18 1.30 1.43 2.04 1.99 2.13 2.33 2.95 1.99 2.13 2.33 2.95

ns

LVCMOS33, Fast, 12 mA

LVCMOS33, Fast, 16 mA

LVCMOS33, Fast, 24 mA

LVCMOS25, QUIETIO, 2 mA

LVCMOS25, QUIETIO, 4 mA

LVCMOS25, QUIETIO, 6 mA

LVCMOS25, QUIETIO, 8 mA

LVCMOS25, QUIETIO, 12 mA

LVCMOS25, QUIETIO, 16 mA

LVCMOS25, QUIETIO, 24 mA

LVCMOS25, Slow, 2 mA

LVCMOS25, Slow, 4 mA

LVCMOS25, Slow, 6 mA

LVCMOS25, Slow, 8 mA

LVCMOS25, Slow, 12 mA

LVCMOS25, Slow, 16 mA

LVCMOS25, Slow, 24 mA

LVCMOS25, Fast, 2 mA

LVCMOS25, Fast, 4 mA

LVCMOS25, Fast, 6 mA

LVCMOS25, Fast, 8 mA

LVCMOS25, Fast, 12 mA

LVCMOS25, Fast, 16 mA

LVCMOS25, Fast, 24 mA

LVCMOS18, QUIETIO, 2 mA

LVCMOS18, QUIETIO, 4 mA

LVCMOS18, QUIETIO, 6 mA

LVCMOS18, QUIETIO, 8 mA

LVCMOS18, QUIETIO, 12 mA

LVCMOS18, QUIETIO, 16 mA

LVCMOS18, QUIETIO, 24 mA

LVCMOS18, Slow, 2 mA

LVCMOS18, Slow, 4 mA

LVCMOS18, Slow, 6 mA

LVCMOS18, Slow, 8 mA

LVCMOS18, Slow, 12 mA

LVCMOS18, Slow, 16 mA

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Product Specification

24

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 28: IOB Switching Characteristics for the Commercial (XC) Spartan-6 Devices (Cont’d)

T_IOPI

T_IOOP

T_IOTP

I/O Standard

Speed Grade

Units

-3

-3N

-2 -1L⁽¹⁾

-3

-3N

-2

-1L⁽¹⁾

-3

-3N

-2

-1L⁽¹⁾

LVCMOS18, Slow, 24 mA

LVCMOS18, Fast, 2 mA

LVCMOS18, Fast, 4 mA

LVCMOS18, Fast, 6 mA

LVCMOS18, Fast, 8 mA

LVCMOS18, Fast, 12 mA

LVCMOS18, Fast, 16 mA

LVCMOS18, Fast, 24 mA

1.18 1.30 1.43 2.04 1.99 2.13 2.33 2.95 1.99 2.13 2.33 2.95

1.18 1.30 1.43 2.04 3.59 3.73 3.93 4.53 3.59 3.73 3.93 4.53

1.18 1.30 1.43 2.04 2.39 2.53 2.73 3.35 2.39 2.53 2.73 3.35

1.18 1.30 1.43 2.04 1.88 2.02 2.22 2.84 1.88 2.02 2.22 2.84

1.18 1.30 1.43 2.04 1.81 1.95 2.15 2.77 1.81 1.95 2.15 2.77

1.18 1.30 1.43 2.04 1.71 1.85 2.05 2.67 1.71 1.85 2.05 2.67

ns

LVCMOS18_JEDEC, QUIETIO, 2 mA 0.94 1.06 1.19 1.41 5.91 6.05 6.25 6.79 5.91 6.05 6.25 6.79

LVCMOS18_JEDEC, QUIETIO, 4 mA 0.94 1.06 1.19 1.41 4.75 4.89 5.09 5.64 4.75 4.89 5.09 5.64

LVCMOS18_JEDEC, QUIETIO, 6 mA 0.94 1.06 1.19 1.41 4.04 4.18 4.38 4.96 4.04 4.18 4.38 4.96

LVCMOS18_JEDEC, QUIETIO, 8 mA 0.94 1.06 1.19 1.41 3.71 3.85 4.05 4.62 3.71 3.85 4.05 4.62

LVCMOS18_JEDEC, QUIETIO, 12 mA 0.94 1.06 1.19 1.41 3.35 3.49 3.69 4.28 3.35 3.49 3.69 4.28

LVCMOS18_JEDEC, QUIETIO, 16 mA 0.94 1.06 1.19 1.41 3.20 3.34 3.54 4.13 3.20 3.34 3.54 4.13

LVCMOS18_JEDEC, QUIETIO, 24 mA 0.94 1.06 1.19 1.41 2.96 3.10 3.30 3.98 2.96 3.10 3.30 3.98

LVCMOS18_JEDEC, Slow, 2 mA

LVCMOS18_JEDEC, Slow, 4 mA

LVCMOS18_JEDEC, Slow, 6 mA

LVCMOS18_JEDEC, Slow, 8 mA

LVCMOS18_JEDEC, Slow, 12 mA

LVCMOS18_JEDEC, Slow, 16 mA

LVCMOS18_JEDEC, Slow, 24 mA

LVCMOS18_JEDEC, Fast, 2 mA

LVCMOS18_JEDEC, Fast, 4 mA

LVCMOS18_JEDEC, Fast, 6 mA

LVCMOS18_JEDEC, Fast, 8 mA

LVCMOS18_JEDEC, Fast, 12 mA

LVCMOS18_JEDEC, Fast, 16 mA

LVCMOS18_JEDEC, Fast, 24 mA

LVCMOS15, QUIETIO, 2 mA

LVCMOS15, QUIETIO, 4 mA

LVCMOS15, QUIETIO, 6 mA

LVCMOS15, QUIETIO, 8 mA

LVCMOS15, QUIETIO, 12 mA

LVCMOS15, QUIETIO, 16 mA

LVCMOS15, Slow, 2 mA

0.94 1.06 1.19 1.41 4.59 4.73 4.93 5.54 4.59 4.73 4.93 5.54

0.94 1.06 1.19 1.41 3.69 3.83 4.03 4.60 3.69 3.83 4.03 4.60

0.94 1.06 1.19 1.41 3.00 3.14 3.34 3.94 3.00 3.14 3.34 3.94

0.94 1.06 1.19 1.41 2.19 2.33 2.53 3.18 2.19 2.33 2.53 3.18

0.94 1.06 1.19 1.41 1.99 2.13 2.33 2.95 1.99 2.13 2.33 2.95

0.94 1.06 1.19 1.41 3.57 3.71 3.91 4.52 3.57 3.71 3.91 4.52

0.94 1.06 1.19 1.41 2.39 2.53 2.73 3.35 2.39 2.53 2.73 3.35

0.94 1.06 1.19 1.41 1.88 2.02 2.22 2.84 1.88 2.02 2.22 2.84

0.94 1.06 1.19 1.41 1.80 1.94 2.14 2.76 1.80 1.94 2.14 2.76

0.94 1.06 1.19 1.41 1.72 1.86 2.06 2.68 1.72 1.86 2.06 2.68

0.98 1.10 1.23 1.79 5.47 5.61 5.81 6.38 5.47 5.61 5.81 6.38

0.98 1.10 1.23 1.79 4.61 4.75 4.95 5.51 4.61 4.75 4.95 5.51

0.98 1.10 1.23 1.79 4.07 4.21 4.41 4.97 4.07 4.21 4.41 4.97

0.98 1.10 1.23 1.79 3.91 4.05 4.25 4.81 3.91 4.05 4.25 4.81

0.98 1.10 1.23 1.79 3.53 3.67 3.87 4.51 3.53 3.67 3.87 4.51

0.98 1.10 1.23 1.79 3.32 3.46 3.66 4.31 3.32 3.46 3.66 4.31

0.98 1.10 1.23 1.79 4.18 4.32 4.52 5.11 4.18 4.32 4.52 5.11

0.98 1.10 1.23 1.79 3.42 3.56 3.76 4.34 3.42 3.56 3.76 4.34

0.98 1.10 1.23 1.79 2.29 2.43 2.63 3.24 2.29 2.43 2.63 3.24

LVCMOS15, Slow, 4 mA

LVCMOS15, Slow, 6 mA

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Product Specification

25

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 28: IOB Switching Characteristics for the Commercial (XC) Spartan-6 Devices (Cont’d)

T_IOPI

T_IOOP

T_IOTP

I/O Standard

Speed Grade

Units

-3

-3N

-2 -1L⁽¹⁾

-3

-3N

-2

-1L⁽¹⁾

-3

-3N

-2

-1L⁽¹⁾

LVCMOS15, Slow, 8 mA

LVCMOS15, Slow, 12 mA

LVCMOS15, Slow, 16 mA

LVCMOS15, Fast, 2 mA

LVCMOS15, Fast, 4 mA

LVCMOS15, Fast, 6 mA

LVCMOS15, Fast, 8 mA

LVCMOS15, Fast, 12 mA

LVCMOS15, Fast, 16 mA

0.98 1.10 1.23 1.79 2.30 2.44 2.64 3.25 2.30 2.44 2.64 3.25

0.98 1.10 1.23 1.79 2.03 2.17 2.37 2.99 2.03 2.17 2.37 2.99

0.98 1.10 1.23 1.79 2.01 2.15 2.35 2.97 2.01 2.15 2.35 2.97

0.98 1.10 1.23 1.79 3.29 3.43 3.63 4.24 3.29 3.43 3.63 4.24

0.98 1.10 1.23 1.79 2.27 2.41 2.61 3.22 2.27 2.41 2.61 3.22

0.98 1.10 1.23 1.79 1.78 1.92 2.12 2.74 1.78 1.92 2.12 2.74

0.98 1.10 1.23 1.79 1.73 1.87 2.07 2.69 1.73 1.87 2.07 2.69

0.98 1.10 1.23 1.79 1.73 1.87 2.07 2.64 1.73 1.87 2.07 2.64

ns

LVCMOS15_JEDEC, QUIETIO, 2 mA 1.03 1.15 1.28 1.49 5.49 5.63 5.83 6.37 5.49 5.63 5.83 6.37

LVCMOS15_JEDEC, QUIETIO, 4 mA 1.03 1.15 1.28 1.49 4.61 4.75 4.95 5.51 4.61 4.75 4.95 5.51

LVCMOS15_JEDEC, QUIETIO, 6 mA 1.03 1.15 1.28 1.49 4.07 4.21 4.41 4.97 4.07 4.21 4.41 4.97

LVCMOS15_JEDEC, QUIETIO, 8 mA 1.03 1.15 1.28 1.49 3.92 4.06 4.26 4.81 3.92 4.06 4.26 4.81

LVCMOS15_JEDEC, QUIETIO, 12 mA 1.03 1.15 1.28 1.49 3.54 3.68 3.88 4.51 3.54 3.68 3.88 4.51

LVCMOS15_JEDEC, QUIETIO, 16 mA 1.03 1.15 1.28 1.49 3.33 3.47 3.67 4.31 3.33 3.47 3.67 4.31

LVCMOS15_JEDEC, Slow, 2 mA

LVCMOS15_JEDEC, Slow, 4 mA

LVCMOS15_JEDEC, Slow, 6 mA

LVCMOS15_JEDEC, Slow, 8 mA

LVCMOS15_JEDEC, Slow, 12 mA

LVCMOS15_JEDEC, Slow, 16 mA

LVCMOS15_JEDEC, Fast, 2 mA

LVCMOS15_JEDEC, Fast, 4 mA

LVCMOS15_JEDEC, Fast, 6 mA

LVCMOS15_JEDEC, Fast, 8 mA

LVCMOS15_JEDEC, Fast, 12 mA

LVCMOS15_JEDEC, Fast, 16 mA

LVCMOS12, QUIETIO, 2 mA

LVCMOS12, QUIETIO, 4 mA

LVCMOS12, QUIETIO, 6 mA

LVCMOS12, QUIETIO, 8 mA

LVCMOS12, QUIETIO, 12 mA

LVCMOS12, Slow, 2 mA

1.03 1.15 1.28 1.49 4.18 4.32 4.52 5.13 4.18 4.32 4.52 5.13

1.03 1.15 1.28 1.49 3.42 3.56 3.76 4.35 3.42 3.56 3.76 4.35

1.03 1.15 1.28 1.49 2.29 2.43 2.63 3.25 2.29 2.43 2.63 3.25

1.03 1.15 1.28 1.49 2.30 2.44 2.64 3.26 2.30 2.44 2.64 3.26

1.03 1.15 1.28 1.49 2.01 2.15 2.35 2.97 2.01 2.15 2.35 2.97

1.03 1.15 1.28 1.49 3.28 3.42 3.62 4.22 3.28 3.42 3.62 4.22

1.03 1.15 1.28 1.49 2.27 2.41 2.61 3.23 2.27 2.41 2.61 3.23

1.03 1.15 1.28 1.49 1.78 1.92 2.12 2.74 1.78 1.92 2.12 2.74

1.03 1.15 1.28 1.49 1.73 1.87 2.07 2.69 1.73 1.87 2.07 2.69

1.03 1.15 1.28 1.49 1.73 1.87 2.07 2.63 1.73 1.87 2.07 2.63

0.91 1.03 1.16 1.51 6.40 6.54 6.74 7.30 6.40 6.54 6.74 7.30

0.91 1.03 1.16 1.51 4.98 5.12 5.32 5.90 4.98 5.12 5.32 5.90

0.91 1.03 1.16 1.51 4.65 4.79 4.99 5.55 4.65 4.79 4.99 5.55

0.91 1.03 1.16 1.51 4.23 4.37 4.57 5.21 4.23 4.37 4.57 5.21

0.91 1.03 1.16 1.51 3.98 4.12 4.32 4.94 3.98 4.12 4.32 4.94

0.91 1.03 1.16 1.51 4.98 5.12 5.32 5.91 4.98 5.12 5.32 5.91

0.91 1.03 1.16 1.51 2.84 2.98 3.18 3.81 2.84 2.98 3.18 3.81

0.91 1.03 1.16 1.51 2.77 2.91 3.11 3.72 2.77 2.91 3.11 3.72

0.91 1.03 1.16 1.51 2.34 2.48 2.68 3.31 2.34 2.48 2.68 3.31

0.91 1.03 1.16 1.51 2.08 2.22 2.42 3.06 2.08 2.22 2.42 3.06

LVCMOS12, Slow, 4 mA

LVCMOS12, Slow, 6 mA

LVCMOS12, Slow, 8 mA

LVCMOS12, Slow, 12 mA

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Product Specification

26

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 28: IOB Switching Characteristics for the Commercial (XC) Spartan-6 Devices (Cont’d)

T_IOPI

T_IOOP

T_IOTP

I/O Standard

Speed Grade

Units

-3

-3N

-2 -1L⁽¹⁾

-3

-3N

-2

-1L⁽¹⁾

-3

-3N

-2

-1L⁽¹⁾

LVCMOS12, Fast, 2 mA

LVCMOS12, Fast, 4 mA

LVCMOS12, Fast, 6 mA

LVCMOS12, Fast, 8 mA

LVCMOS12, Fast, 12 mA

0.91 1.03 1.16 1.51 3.46 3.60 3.80 4.44 3.46 3.60 3.80 4.44

0.91 1.03 1.16 1.51 2.35 2.49 2.69 3.30 2.35 2.49 2.69 3.30

0.91 1.03 1.16 1.51 1.79 1.93 2.13 2.75 1.79 1.93 2.13 2.75

0.91 1.03 1.16 1.51 1.68 1.82 2.02 2.64 1.68 1.82 2.02 2.64

0.91 1.03 1.16 1.51 1.66 1.80 2.00 2.62 1.66 1.80 2.00 2.62

ns

LVCMOS12_JEDEC, QUIETIO, 2 mA 1.50 1.62 1.75 1.88 6.39 6.53 6.73 7.31 6.39 6.53 6.73 7.31

LVCMOS12_JEDEC, QUIETIO, 4 mA 1.50 1.62 1.75 1.88 4.98 5.12 5.32 5.88 4.98 5.12 5.32 5.88

LVCMOS12_JEDEC, QUIETIO, 6 mA 1.50 1.62 1.75 1.88 4.67 4.81 5.01 5.54 4.67 4.81 5.01 5.54

LVCMOS12_JEDEC, QUIETIO, 8 mA 1.50 1.62 1.75 1.88 4.23 4.37 4.57 5.22 4.23 4.37 4.57 5.22

LVCMOS12_JEDEC, QUIETIO, 12 mA 1.50 1.62 1.75 1.88 3.99 4.13 4.33 4.94 3.99 4.13 4.33 4.94

LVCMOS12_JEDEC, Slow, 2 mA

LVCMOS12_JEDEC, Slow, 4 mA

LVCMOS12_JEDEC, Slow, 6 mA

LVCMOS12_JEDEC, Slow, 8 mA

LVCMOS12_JEDEC, Slow, 12 mA

LVCMOS12_JEDEC, Fast, 2 mA

LVCMOS12_JEDEC, Fast, 4 mA

LVCMOS12_JEDEC, Fast, 6 mA

LVCMOS12_JEDEC, Fast, 8 mA

LVCMOS12_JEDEC, Fast, 12 mA

1.50 1.62 1.75 1.88 5.00 5.14 5.34 5.90 5.00 5.14 5.34 5.90

1.50 1.62 1.75 1.88 2.85 2.99 3.19 3.80 2.85 2.99 3.19 3.80

1.50 1.62 1.75 1.88 2.76 2.90 3.10 3.72 2.76 2.90 3.10 3.72

1.50 1.62 1.75 1.88 2.35 2.49 2.69 3.30 2.35 2.49 2.69 3.30

1.50 1.62 1.75 1.88 2.09 2.23 2.43 3.05 2.09 2.23 2.43 3.05

1.50 1.62 1.75 1.88 3.46 3.60 3.80 4.42 3.46 3.60 3.80 4.42

1.50 1.62 1.75 1.88 2.35 2.49 2.69 3.31 2.35 2.49 2.69 3.31

1.50 1.62 1.75 1.88 1.79 1.93 2.13 2.76 1.79 1.93 2.13 2.76

1.50 1.62 1.75 1.88 1.69 1.83 2.03 2.65 1.69 1.83 2.03 2.65

1.50 1.62 1.75 1.88 1.66 1.80 2.00 2.62 1.66 1.80 2.00 2.62

Notes:

1. The -1L values listed in this table are also applicable to the Spartan-6Q devices.

2. Devices with a -1L speed grade do not support Xilinx PCI IP.

DS162 (v3.1.1) January 30, 2015

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Product Specification

27

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 29: IOB Switching Characteristics for the Automotive XA Spartan-6 and the Spartan-6Q Devices

T_IOPI

T_IOOP

T_IOTP

I/O Standard

Speed Grade

Units

-3

-2

-3

-2

-3

-2

LVDS_33

LVDS_25

BLVDS_25

1.24

1.08

1.09

1.25

1.08

1.25

1.09

1.24

1.08

1.29

1.25

1.08

1.14

1.09

1.40

1.43

1.01

1.07

1.05

1.13

1.65

1.37

0.99

1.00

1.01

1.00

1.04

1.42

1.26

1.27

1.43

1.26

1.43

1.27

1.42

1.26

1.47

1.43

1.26

1.32

1.27

1.58

1.61

1.19

1.25

1.23

1.31

1.83

1.55

1.17

1.18

1.19

1.18

1.22

1.69

1.79

1.86

1.71

1.79

N/A

1.89

1.99

2.06

1.91

1.99

N/A

3000

1.86

3000

N/A

3000

2.06

3000

N/A

ns

MINI_LVDS_33

MINI_LVDS_25

LVPECL_33

LVPECL_25

RSDS_33 (point to point)

RSDS_25 (point to point)

TMDS_33

N/A

1.71

1.79

1.68

1.71

1.82

3.81

3.29

11.70

2.78

2.50

1.80

1.86

1.81

1.91

1.99

1.93

1.97

2.15

1.91

2.00

1.77

1.80

1.81

1.91

1.86

1.83

1.93

1.83

1.91

1.99

1.88

1.91

2.02

4.01

3.49

11.90

2.98

2.70

2.00

2.06

2.01

2.11

2.19

2.13

2.17

2.35

2.11

2.20

1.97

2.00

2.01

2.11

2.06

2.03

2.13

2.03

3000

3.81

3.29

11.70

2.78

2.50

1.80

1.86

1.81

1.91

1.99

1.93

1.97

2.15

1.91

2.00

1.77

1.80

1.81

1.91

1.86

1.83

1.93

1.83

3000

4.01

3.49

11.90

2.98

2.70

2.00

2.06

2.01

2.11

2.19

2.13

2.17

2.35

2.11

2.20

1.97

2.00

2.01

2.11

2.06

2.03

2.13

2.03

PPDS_33

PPDS_25

PCI33_3

PCI66_3

DISPLAY_PORT

I2C

SMBUS

SDIO

MOBILE_DDR

HSTL_I

HSTL_II

HSTL_III

HSTL_I _18

HSTL_II _18

HSTL_III _18

SSTL3_I

SSTL3_II

SSTL2_I

SSTL2_II

SSTL18_I

SSTL18_II

SSTL15_II

DIFF_HSTL_I

DIFF_HSTL_II

DIFF_HSTL_III

DIFF_HSTL_I_18

DIFF_HSTL_II_18

DIFF_HSTL_III_18

DS162 (v3.1.1) January 30, 2015

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Product Specification

28

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 29: IOB Switching Characteristics for the Automotive XA Spartan-6 and the Spartan-6Q Devices (Cont’d)

T_IOPI

T_IOOP

T_IOTP

I/O Standard

Speed Grade

Units

-3

-2

-3

-2

-3

-2

DIFF_SSTL3_I

1.26

1.09

1.04

1.05

1.01

1.04

1.42

1.41

1.44

1.27

1.22

1.23

1.19

1.22

1.60

1.59

1.95

1.94

1.90

1.86

1.82

1.81

1.89

5.64

4.46

3.92

3.37

3.42

3.09

2.83

4.58

3.38

2.95

2.73

2.72

2.53

2.42

4.04

2.66

2.58

2.46

1.97

5.65

4.20

3.65

3.51

3.09

2.91

2.73

4.59

3.14

2.15

2.14

2.10

2.06

2.02

2.01

2.09

5.84

4.66

4.12

3.57

3.62

3.29

3.03

4.78

3.58

3.15

2.93

2.92

2.73

2.62

4.24

2.86

2.78

2.66

2.17

5.85

4.40

3.85

3.71

3.29

3.11

2.93

4.79

3.34

1.95

1.94

1.90

1.86

1.82

1.81

1.89

5.64

4.46

3.92

3.37

3.42

3.09

2.83

4.58

3.38

2.95

2.73

2.72

2.53

2.42

4.04

2.66

2.58

2.46

1.97

5.65

4.20

3.65

3.51

3.09

2.91

2.73

4.59

3.14

2.15

2.14

2.10

2.06

2.02

2.01

2.09

5.84

4.66

4.12

3.57

3.62

3.29

3.03

4.78

3.58

3.15

2.93

2.92

2.73

2.62

4.24

2.86

2.78

2.66

2.17

5.85

4.40

3.85

3.71

3.29

3.11

2.93

4.79

3.34

ns

DIFF_SSTL3_II

DIFF_SSTL2_I

DIFF_SSTL2_II

DIFF_SSTL18_I

DIFF_SSTL18_II

DIFF_SSTL15_II

DIFF_MOBILE_DDR

LVTTL, QUIETIO, 2 mA

LVTTL, QUIETIO, 4 mA

LVTTL, QUIETIO, 6 mA

LVTTL, QUIETIO, 8 mA

LVTTL, QUIETIO, 12 mA

LVTTL, QUIETIO, 16 mA

LVTTL, QUIETIO, 24 mA

LVTTL, Slow, 2 mA

LVTTL, Slow, 4 mA

LVTTL, Slow, 6 mA

LVTTL, Slow, 8 mA

LVTTL, Slow, 12 mA

LVTTL, Slow, 16 mA

LVTTL, Slow, 24 mA

LVTTL, Fast, 2 mA

LVTTL, Fast, 4 mA

LVTTL, Fast, 6 mA

LVTTL, Fast, 8 mA

LVTTL, Fast, 12 mA

LVTTL, Fast, 16 mA

LVTTL, Fast, 24 mA

LVCMOS33, QUIETIO, 2 mA

LVCMOS33, QUIETIO, 4 mA

LVCMOS33, QUIETIO, 6 mA

LVCMOS33, QUIETIO, 8 mA

LVCMOS33, QUIETIO, 12 mA

LVCMOS33, QUIETIO, 16 mA

LVCMOS33, QUIETIO, 24 mA

LVCMOS33, Slow, 2 mA

LVCMOS33, Slow, 4 mA

DS162 (v3.1.1) January 30, 2015

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Product Specification

29

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 29: IOB Switching Characteristics for the Automotive XA Spartan-6 and the Spartan-6Q Devices (Cont’d)

T_IOPI

T_IOOP

T_IOTP

I/O Standard

Speed Grade

Units

-3

-2

-3

-2

-3

-2

LVCMOS33, Slow, 6 mA

LVCMOS33, Slow, 8 mA

LVCMOS33, Slow, 12 mA

LVCMOS33, Slow, 16 mA

LVCMOS33, Slow, 24 mA

LVCMOS33, Fast, 2 mA

LVCMOS33, Fast, 4 mA

LVCMOS33, Fast, 6 mA

LVCMOS33, Fast, 8 mA

LVCMOS33, Fast, 12 mA

LVCMOS33, Fast, 16 mA

LVCMOS33, Fast, 24 mA

LVCMOS25, QUIETIO, 2 mA

LVCMOS25, QUIETIO, 4 mA

LVCMOS25, QUIETIO, 6 mA

LVCMOS25, QUIETIO, 8 mA

LVCMOS25, QUIETIO, 12 mA

LVCMOS25, QUIETIO, 16 mA

LVCMOS25, QUIETIO, 24 mA

LVCMOS25, Slow, 2 mA

LVCMOS25, Slow, 4 mA

LVCMOS25, Slow, 6 mA

LVCMOS25, Slow, 8 mA

LVCMOS25, Slow, 12 mA

LVCMOS25, Slow, 16 mA

LVCMOS25, Slow, 24 mA

LVCMOS25, Fast, 2 mA

LVCMOS25, Fast, 4 mA

LVCMOS25, Fast, 6 mA

LVCMOS25, Fast, 8 mA

LVCMOS25, Fast, 12 mA

LVCMOS25, Fast, 16 mA

LVCMOS25, Fast, 24 mA

LVCMOS18, QUIETIO, 2 mA

LVCMOS18, QUIETIO, 4 mA

LVCMOS18, QUIETIO, 6 mA

LVCMOS18, QUIETIO, 8 mA

LVCMOS18, QUIETIO, 12 mA

1.41

0.89

1.25

1.59

1.07

1.43

2.79

2.53

2.45

2.42

4.05

2.66

2.46

2.21

1.80

5.00

3.85

3.60

3.34

2.98

2.79

2.64

3.96

2.96

2.88

2.63

2.15

3.52

2.43

2.23

2.16

1.70

6.11

4.88

4.20

3.86

3.49

2.99

2.73

2.65

2.62

4.25

2.86

2.66

2.41

2.00

5.20

4.05

3.80

3.54

3.18

2.99

2.84

4.16

3.16

3.08

2.83

2.35

3.72

2.63

2.43

2.36

1.90

6.31

5.08

4.40

4.06

3.69

2.79

2.53

2.45

2.42

4.05

2.66

2.46

2.21

1.80

5.00

3.85

3.60

3.34

2.98

2.79

2.64

3.96

2.96

2.88

2.63

2.15

3.52

2.43

2.23

2.16

1.70

6.11

4.88

4.20

3.86

3.49

2.99

2.73

2.65

2.62

4.25

2.86

2.66

2.41

2.00

5.20

4.05

3.80

3.54

3.18

2.99

2.84

4.16

3.16

3.08

2.83

2.35

3.72

2.63

2.43

2.36

1.90

6.31

5.08

4.40

4.06

3.69

ns

DS162 (v3.1.1) January 30, 2015

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Product Specification

30

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 29: IOB Switching Characteristics for the Automotive XA Spartan-6 and the Spartan-6Q Devices (Cont’d)

T_IOPI

T_IOOP

T_IOTP

I/O Standard

Speed Grade

Units

-3

-2

-3

-2

-3

-2

LVCMOS18, QUIETIO, 16 mA

LVCMOS18, QUIETIO, 24 mA

LVCMOS18, Slow, 2 mA

1.25

1.01

1.43

1.19

3.34

3.18

4.79

3.84

3.17

2.37

2.13

3.78

2.54

2.02

1.95

1.85

6.09

4.89

4.20

3.87

3.49

3.34

3.17

4.79

3.84

3.18

2.37

2.13

3.75

2.54

2.02

1.94

1.86

3.54

3.38

4.99

4.04

3.37

2.57

2.33

3.98

2.74

2.22

2.15

2.05

6.29

5.09

4.40

4.07

3.69

3.54

3.37

4.99

4.04

3.38

2.57

2.33

3.95

2.74

2.22

2.14

2.06

3.34

3.18

4.79

3.84

3.17

2.37

2.13

3.78

2.54

2.02

1.95

1.85

6.09

4.89

4.20

3.87

3.49

3.34

3.17

4.79

3.84

3.18

2.37

2.13

3.75

2.54

2.02

1.94

1.86

3.54

3.38

4.99

4.04

3.37

2.57

2.33

3.98

2.74

2.22

2.15

2.05

6.29

5.09

4.40

4.07

3.69

3.54

3.37

4.99

4.04

3.38

2.57

2.33

3.95

2.74

2.22

2.14

2.06

ns

LVCMOS18, Slow, 4 mA

LVCMOS18, Slow, 6 mA

LVCMOS18, Slow, 8 mA

LVCMOS18, Slow, 12 mA

LVCMOS18, Slow, 16 mA

LVCMOS18, Slow, 24 mA

LVCMOS18, Fast, 2 mA

LVCMOS18, Fast, 4 mA

LVCMOS18, Fast, 6 mA

LVCMOS18, Fast, 8 mA

LVCMOS18, Fast, 12 mA

LVCMOS18, Fast, 16 mA

LVCMOS18, Fast, 24 mA

LVCMOS18_JEDEC, QUIETIO, 2 mA

LVCMOS18_JEDEC, QUIETIO, 4 mA

LVCMOS18_JEDEC, QUIETIO, 6 mA

LVCMOS18_JEDEC, QUIETIO, 8 mA

LVCMOS18_JEDEC, QUIETIO, 12 mA

LVCMOS18_JEDEC, QUIETIO, 16 mA

LVCMOS18_JEDEC, QUIETIO, 24 mA

LVCMOS18_JEDEC, Slow, 2 mA

LVCMOS18_JEDEC, Slow, 4 mA

LVCMOS18_JEDEC, Slow, 6 mA

LVCMOS18_JEDEC, Slow, 8 mA

LVCMOS18_JEDEC, Slow, 12 mA

LVCMOS18_JEDEC, Slow, 16 mA

LVCMOS18_JEDEC, Slow, 24 mA

LVCMOS18_JEDEC, Fast, 2 mA

LVCMOS18_JEDEC, Fast, 4 mA

LVCMOS18_JEDEC, Fast, 6 mA

LVCMOS18_JEDEC, Fast, 8 mA

LVCMOS18_JEDEC, Fast, 12 mA

LVCMOS18_JEDEC, Fast, 16 mA

LVCMOS18_JEDEC, Fast, 24 mA

DS162 (v3.1.1) January 30, 2015

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Product Specification

31

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 29: IOB Switching Characteristics for the Automotive XA Spartan-6 and the Spartan-6Q Devices (Cont’d)

T_IOPI

T_IOOP

T_IOTP

I/O Standard

Speed Grade

Units

-3

-2

-3

-2

-3

-2

LVCMOS15, QUIETIO, 2 mA

LVCMOS15, QUIETIO, 4 mA

LVCMOS15, QUIETIO, 6 mA

LVCMOS15, QUIETIO, 8 mA

LVCMOS15, QUIETIO, 12 mA

LVCMOS15, QUIETIO, 16 mA

LVCMOS15, Slow, 2 mA

1.05

1.10

0.98

1.23

1.28

1.16

5.63

4.75

4.21

4.05

3.74

3.52

4.32

3.58

2.45

2.46

2.17

2.15

3.43

2.42

1.92

1.87

5.64

4.75

4.21

4.06

3.75

3.53

4.32

3.56

2.44

2.47

2.15

3.43

2.42

1.92

1.87

6.54

5.12

5.83

4.95

4.41

4.25

3.94

3.72

4.52

3.78

2.65

2.66

2.37

2.35

3.63

2.62

2.12

2.07

5.84

4.95

4.41

4.26

3.95

3.73

4.52

3.76

2.64

2.67

2.35

3.63

2.62

2.12

2.07

6.74

5.32

5.63

4.75

4.21

4.05

3.74

3.52

4.32

3.58

2.45

2.46

2.17

2.15

3.43

2.42

1.92

1.87

5.64

4.75

4.21

4.06

3.75

3.53

4.32

3.56

2.44

2.47

2.15

3.43

2.42

1.92

1.87

6.54

5.12

5.83

4.95

4.41

4.25

3.94

3.72

4.52

3.78

2.65

2.66

2.37

2.35

3.63

2.62

2.12

2.07

5.84

4.95

4.41

4.26

3.95

3.73

4.52

3.76

2.64

2.67

2.35

3.63

2.62

2.12

2.07

6.74

5.32

ns

LVCMOS15, Slow, 4 mA

LVCMOS15, Slow, 6 mA

LVCMOS15, Slow, 8 mA

LVCMOS15, Slow, 12 mA

LVCMOS15, Slow, 16 mA

LVCMOS15, Fast, 2 mA

LVCMOS15, Fast, 4 mA

LVCMOS15, Fast, 6 mA

LVCMOS15, Fast, 8 mA

LVCMOS15, Fast, 12 mA

LVCMOS15, Fast, 16 mA

LVCMOS15_JEDEC, QUIETIO, 2 mA

LVCMOS15_JEDEC, QUIETIO, 4 mA

LVCMOS15_JEDEC, QUIETIO, 6 mA

LVCMOS15_JEDEC, QUIETIO, 8 mA

LVCMOS15_JEDEC, QUIETIO, 12 mA

LVCMOS15_JEDEC, QUIETIO, 16 mA

LVCMOS15_JEDEC, Slow, 2 mA

LVCMOS15_JEDEC, Slow, 4 mA

LVCMOS15_JEDEC, Slow, 6 mA

LVCMOS15_JEDEC, Slow, 8 mA

LVCMOS15_JEDEC, Slow, 12 mA

LVCMOS15_JEDEC, Slow, 16 mA

LVCMOS15_JEDEC, Fast, 2 mA

LVCMOS15_JEDEC, Fast, 4 mA

LVCMOS15_JEDEC, Fast, 6 mA

LVCMOS15_JEDEC, Fast, 8 mA

LVCMOS15_JEDEC, Fast, 12 mA

LVCMOS15_JEDEC, Fast, 16 mA

LVCMOS12, QUIETIO, 2 mA

LVCMOS12, QUIETIO, 4 mA

DS162 (v3.1.1) January 30, 2015

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Product Specification

32

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 29: IOB Switching Characteristics for the Automotive XA Spartan-6 and the Spartan-6Q Devices (Cont’d)

T_IOPI

T_IOOP

T_IOTP

I/O Standard

Speed Grade

Units

-3

-2

-3

-2

-3

-2

LVCMOS12, QUIETIO, 6 mA

LVCMOS12, QUIETIO, 8 mA

LVCMOS12, QUIETIO, 12 mA

LVCMOS12, Slow, 2 mA

0.98

1.57

1.16

1.75

4.79

4.43

4.18

5.12

3.00

2.91

2.51

2.25

3.60

2.49

1.94

1.82

1.80

6.53

5.12

4.81

4.44

4.20

5.14

2.99

2.90

2.50

2.26

3.60

2.49

1.94

1.83

1.80

4.99

4.63

4.38

5.32

3.20

3.11

2.71

2.45

3.80

2.69

2.14

2.02

2.00

6.73

5.32

5.01

4.64

4.40

5.34

3.19

3.10

2.70

2.46

3.80

2.69

2.14

2.03

2.00

4.79

4.43

4.18

5.12

3.00

2.91

2.51

2.25

3.60

2.49

1.94

1.82

1.80

6.53

5.12

4.81

4.44

4.20

5.14

2.99

2.90

2.50

2.26

3.60

2.49

1.94

1.83

1.80

4.99

4.63

4.38

5.32

3.20

3.11

2.71

2.45

3.80

2.69

2.14

2.02

2.00

6.73

5.32

5.01

4.64

4.40

5.34

3.19

3.10

2.70

2.46

3.80

2.69

2.14

2.03

2.00

ns

LVCMOS12, Slow, 4 mA

LVCMOS12, Slow, 6 mA

LVCMOS12, Slow, 8 mA

LVCMOS12, Slow, 12 mA

LVCMOS12, Fast, 2 mA

LVCMOS12, Fast, 4 mA

LVCMOS12, Fast, 6 mA

LVCMOS12, Fast, 8 mA

LVCMOS12, Fast, 12 mA

LVCMOS12_JEDEC, QUIETIO, 2 mA

LVCMOS12_JEDEC, QUIETIO, 4 mA

LVCMOS12_JEDEC, QUIETIO, 6 mA

LVCMOS12_JEDEC, QUIETIO, 8 mA

LVCMOS12_JEDEC, QUIETIO, 12 mA

LVCMOS12_JEDEC, Slow, 2 mA

LVCMOS12_JEDEC, Slow, 4 mA

LVCMOS12_JEDEC, Slow, 6 mA

LVCMOS12_JEDEC, Slow, 8 mA

LVCMOS12_JEDEC, Slow, 12 mA

LVCMOS12_JEDEC, Fast, 2 mA

LVCMOS12_JEDEC, Fast, 4 mA

LVCMOS12_JEDEC, Fast, 6 mA

LVCMOS12_JEDEC, Fast, 8 mA

LVCMOS12_JEDEC, Fast, 12 mA

Notes:

1. The Spartan-6Q FPGA -1L values are listed in Table 28.

Table 30 summarizes the value of T

. T

is described as the delay from the T pin to the IOB pad through the

IOTPHZ IOTPHZ

output buffer of an IOB pad, when 3-state is enabled (i.e., a high impedance state). These delays are measured using

LVCMOS25, Fast, 12 mA.

Table 30: IOB 3-state ON Output Switching Characteristics (T

)

IOTPHZ

Speed Grade

Symbol

T_IOTPHZ

Description

T input to Pad high-impedance

Units

-3

-3N

-2

-1L

1.39

1.59

1.91

ns

DS162 (v3.1.1) January 30, 2015

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Product Specification

33

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

I/O Standard Measurement Methodology

Input Delay Measurements

Table 31 shows the test setup parameters used for measuring input delay.

Table 31: Input Delay Measurement Methodology

(1)

(3)(4)

(2)(4)

Description

LVTTL (Low-Voltage Transistor-Transistor Logic)

LVCMOS (Low-Voltage CMOS), 3.3V

LVCMOS, 2.5V

I/O Standard Attribute

LVTTL

V_L

V_H

3.0

V_MEAS

V_REF

0

1.4

–

LVCMOS33

3.3

1.65

1.25

0.9

LVCMOS25

2.5

LVCMOS, 1.8V

LVCMOS18

1.8

LVCMOS, 1.5V

LVCMOS15

1.5

1.2

0.75

0.6

LVCMOS, 1.2V

LVCMOS12

PCI (Peripheral Component Interface),

33 MHz and 66 MHz, 3.3V

PCI33_3, PCI66_3

Per PCI Specification

HSTL (High-Speed Transceiver Logic),

Class I & II

HSTL_I, HSTL_II

V

_REF– 0.5

V_REF+ 0.5

V_REF

0.75

HSTL, Class III

HSTL_III

V_REF– 0.5

_REF– 0.5

V_REF– 0.5

V_REF+ 0.5

V_REF

0.90

1.1

HSTL, Class I & II, 1.8V

HSTL, Class III 1.8V

HSTL_I_18, HSTL_II_18

HSTL_III_18

V

SSTL (Stub Terminated Transceiver Logic),

Class I & II, 3.3V

SSTL3_I, SSTL3_II

V_REF– 0.75 V_REF+ 0.75

1.5

SSTL, Class I & II, 2.5V

SSTL, Class I & II, 1.8V

SSTL, Class II, 1.5V

SSTL2_I, SSTL2_II

SSTL18_I, SSTL18_II

SSTL15_II

V

_REF– 0.75 V_REF+ 0.75

V_REF

0⁽⁵⁾

1.25

0.90

0.75

–

V

_REF– 0.5

_REF– 0.2

V_REF+ 0.5

V_REF+ 0.2

V

LVDS (Low-Voltage Differential Signaling),

2.5V & 3.3V

LVDS_25, LVDS_33

1.25 – 0.125 1.25 + 0.125

LVPECL (Low-Voltage Positive Emitter-Coupled

Logic), 2.5V & 3.3V

LVPECL_25, LVPECL_33

BLVDS_25

1.2 – 0.3

1.2 + 0.3

0⁽⁵⁾

–

BLVDS (Bus LVDS), 2.5V

Mini-LVDS, 2.5V & 3.3V

1.3 – 0.125

1.2 – 0.125

1.3 + 0.125

1.2 + 0.125

0⁽⁵⁾

–

MINI_LVDS_25,

MINI_LVDS_33

RSDS (Reduced Swing Differential Signaling),

2.5V & 3.3V

RSDS_25, RSDS_33

1.2 – 0.1

3.0 – 0.1

1.25 – 0.1

1.2 + 0.1

3.0 + 0.1

1.25 + 0.1

0⁽⁵⁾

–

TMDS (Transition Minimized Differential Signaling),

3.3V

TMDS_33

PPDS (Point-to-Point Differential Signaling,

2.5V & 3.3V

PPDS_25, PPDS_33

Notes:

1. Input waveform switches between V_Land V_H.

2. Measurements are made at typical, minimum, and maximum V_REFvalues. Reported delays reflect worst case of these measurements. V_REFvalues

listed are typical.

3. Input voltage level from which measurement starts.

4. This is an input voltage reference that bears no relation to the V_REF/ V_MEASparameters found in IBIS models and/or noted in Figure 4.

5. The value given is the differential input voltage.

DS162 (v3.1.1) January 30, 2015

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Product Specification

34

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Output Delay Measurements

X-Ref Target - Figure 5

FPGA Output

Output delays are measured using a Tektronix P6245

TDS500/600 probe (< 1 pF) across approximately 4" of FR4

microstrip trace. Standard termination was used for all

testing. The propagation delay of the 4" trace is

+

C_REF

R_REFV_MEAS

characterized separately and subtracted from the final

measurement, and is therefore not included in the

generalized test setups shown in Figure 4 and Figure 5.

–

ds162_07_011309

X-Ref Target - Figure 4

Figure 5: Differential Test Setup

V_REF

Measurements and test conditions are reflected in the IBIS

models except where the IBIS format precludes it.

Parameters V

, R

, C

, and V

fully describe

R_REF

REF

MEAS

FPGA Output

the test conditions for each I/O standard. The most accurate

prediction of propagation delay in any given application can

be obtained through IBIS simulation, using the following

method:

V_MEAS

(voltage level when taking

delay measurement)

1. Simulate the output driver of choice into the generalized

test setup, using values from Table 32.

C_REF

(probe capacitance)

2. Record the time to V

.

MEAS

ds162_06_011309

3. Simulate the output driver of choice into the actual PCB

trace and load, using the appropriate IBIS model or

capacitance value to represent the load.

Figure 4: Single-Ended Test Setup

4. Record the time to V

.

MEAS

5. Compare the results of steps 2 and 4. The increase or

decrease in delay yields the actual propagation delay of

the PCB trace.

Table 32: Output Delay Measurement Methodology

(1)

I/O Standard

Attribute

R_REFC_REF

V_MEASV_REF

Description

(Ω)

1M

25

(pF)

(V)

LVTTL (Low-Voltage Transistor-Transistor Logic)

LVCMOS (Low-Voltage CMOS), 3.3V

LVCMOS, 2.5V

LVTTL (all)

0

1.4

0

LVCMOS33

0

1.65

1.25

0.9

0

LVCMOS25

0

LVCMOS, 1.8V

LVCMOS18

0

LVCMOS, 1.5V

LVCMOS15

0

0.75

0.6

0

LVCMOS, 1.2V

LVCMOS12

0

PCI33_3, PCI66_3 (rising edge)

PCI33_3, PCI66_3 (falling edge)

HSTL_I

10⁽²⁾

0.94

2.03

V_REF

0.9

0

PCI (Peripheral Component Interface)

33 MHz and 66 MHz, 3.3V

25

10⁽²⁾

3.3

0.75

1.5

0.9

1.8

0.9

1.25

HSTL (High-Speed Transceiver Logic), Class I

HSTL, Class II

50

0

HSTL_II

25

HSTL, Class III

HSTL_III

50

HSTL, Class I, 1.8V

HSTL_I_18

50

V_REF

1.1

HSTL, Class II, 1.8V

HSTL_II_18

25

HSTL, Class III, 1.8V

HSTL_III_18

SSTL18_I

50

SSTL (Stub Series Terminated Logic), Class I, 1.8V

SSTL, Class II, 1.8V

50

V_REF

SSTL18_II

25

SSTL, Class I, 2.5V

SSTL2_I

50

DS162 (v3.1.1) January 30, 2015

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Product Specification

35

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 32: Output Delay Measurement Methodology (Cont’d)

(1)

I/O Standard

Attribute

R_REFC_REF

V_MEASV_REF

Description

(Ω)

(pF)

(V)

V_REF

0⁽³⁾

(V)

1.25

0.75

–

SSTL, Class II, 2.5V

SSTL, Class II, 1.5V

SSTL2_II

25

0

SSTL15_II

25

LVDS (Low-Voltage Differential Signaling), 2.5V & 3.3V

BLVDS (Bus LVDS), 2.5V

LVDS_25, LVDS_33

BLVDS_25

100

Note 4

100

0⁽³⁾

–

Mini-LVDS, 2.5V & 3.3V

MINI_LVDS_25, MINI_LVDS_33

0⁽³⁾

–

RSDS (Reduced Swing Differential Signaling), 2.5V & 3.3V RSDS_25, RSDS_33

100

0⁽³⁾

–

TMDS (Transition Minimized Differential Signaling), 3.3V

PPDS (Point-to-Point Differential Signaling, 2.5V & 3.3V

TMDS_33

Note 5

100

0⁽³⁾

–

PPDS_25, PPDS_33

0⁽³⁾

–

Notes:

1.

C_REFis the capacitance of the probe, nominally 0 pF.

2. Per PCI specifications.

3. The value given is the differential output voltage.

4. See the BLVDS Output Termination section in UG381, Spartan-6 FPGA SelectIO Resources User Guide.

5. See the TMDS_33 Termination section in UG381, Spartan-6 FPGA SelectIO Resources User Guide.

Simultaneously Switching Outputs

Due to package electrical parasitics, a given package supports a limited number of simultaneous switching outputs (SSOs)

when using fast, high-drive outputs. Table 33 and Table 34 provide guidelines for the recommended maximum allowable

number of SSOs. These guidelines describe the maximum number of user I/O pins of an output signal standard that should

simultaneously switch in the same direction, while maintaining a safe level of switching noise for that particular signal

standard. Meeting these guidelines for the stated test conditions ensures that the FPGA operates free from the adverse

effects of GND and power bounce.

For each device/package combination, Table 33 provides the number of equivalent V

/GND pairs per bank. For each

CCO

output signal standard and drive strength, Table 34 recommends the maximum number of SSOs, switching in the same

direction, allowed per V /GND pair within an I/O bank. The guidelines are categorized by package style, slew rate, and

CCO

output drive current. The number of SSOs are also specified by I/O bank. Multiply the appropriate numbers from each table

to calculate the maximum number of SSOs allowed within an I/O bank. The guidelines assume that all pins within a bank use

the same I/O standard. Although in general lower DRIVE settings improve SSO characteristics, in some instances higher

DRIVE settings improve SSO values because they also improve noise margin. Analysis using the PlanAhead tool supports

mixed standards within a bank. Exceeding these SSO guidelines can result in increased power or GND bounce, degraded

signal integrity, or increased system jitter. For a given I/O standard, if the SSO limit per pair in Table 34 is greater than the

maximum I/O per pair in Table 33, then there is no SSO limit for the exclusive use of that I/O standard.

The recommended maximum SSO values assume that the FPGA is soldered on a printed circuit board and that the board

uses sound design practices. Due to the additional inductance introduced by the socket, the SSO values do not apply for

FPGAs mounted in sockets. The SSO values assume that the V

is powered at 3.3V. Setting V

to 2.5V provides

CCAUX

better SSO characteristics. For more detail, see UG381: Spartan-6 FPGA SelectIO Resources User Guide.

SSO analysis does not take relative pin locations into account. The PlanAhead tool supports simultaneous switching noise

(SSN) analysis, which is based on relative pin locations, allowing the optimal choice of package pins. For more information,

see UG792: Pin Planning Methodology Guide.

There are also restrictions on using SelectIO resources in proximity to GTP transceivers. For more information, see

UG386: Spartan-6 FPGA GTP Transceivers User Guide.

DS162 (v3.1.1) January 30, 2015

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Product Specification

36

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 33: Spartan-6 FPGA V

/GND Pairs per Bank

CCO

Package

Devices

Description

Bank 0

Bank 1

Bank 2

2

Bank 3

3

Bank 4

N/A

6

Bank 5

N/A

6

V

_CCO/GND Pairs

3

8

3

8

TQG144

LX

Maximum I/O per Pair

VCCO/GND Pairs

Maximum I/O per Pair

V_CCO/GND Pairs

13

4

8

4

6

CPG196

CSG225

FT(G)256

LX

6

4

7

4

LX

Maximum I/O per Pair

V_CCO/GND Pairs

10

5

10

6

9

10

5

4

LX

Maximum I/O per Pair

V_CCO/GND Pairs

8

9

10

6

LX

Maximum I/O per Pair

V_CCO/GND Pairs

10

4

9

10

6

9

CSG324

6

LXT

LX

Maximum I/O per Pair

V_CCO/GND Pairs

4

9

10

8

9

8

13

8

13

8

Maximum I/O per Pair

V_CCO/GND Pairs

7

CS(G)484

FG(G)484

7

12

8

13

8

LXT

LX

Maximum I/O per Pair

V_CCO/GND Pairs

5

6

10

6

10

8

11

9

11

8

Maximum I/O per Pair

V_CCO/GND Pairs

6

10

8

11

7

10

8

LXT

LX45

Maximum I/O per Pair

V_CCO/GND Pairs

7

12

3

15

7

10

8

16

7

Maximum I/O per Pair

V_CCO/GND Pairs

12

9

10

9

10

9

FG(G)676

FG(G)900

LX75, LX100, LX150

Maximum I/O per Pair

V_CCO/GND Pairs

10

8

9

10

8

10

8

7

LXT

LX

Maximum I/O per Pair

7

8

7

V

_CCO/GND Pairs

17

7

14

6

17

7

14

8

7

8

Maximum I/O per Pair

V_CCO/GND Pairs

7

6

15

7

14

6

13

8

14

8

7

8

LXT

Maximum I/O per Pair

7

6

DS162 (v3.1.1) January 30, 2015

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Product Specification

37

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

SSO Limit per V_CCO/GND Pair

Table 34: SSO Limit per V

/GND Pair

CCO

All TQG144, CPG196,

CSG225, FT(G)256, and

LX devices in CSG324

All CS(G)484, FG(G)484,

FG(G)676, FG(G)900, and

LXT devices in CSG324

V_CCO

I/O Standard

Drive

Slew

Bank 0/2

30 ⁽¹⁾

51

Bank 1/3

35

Bank 0/2

30

Bank 1/3/4/5

Fast

35

52

70

19

22

32

14

17

24

12

13

19

4

2

4

Slow

55

51

QuietIO

Fast

71

58

71

17

Slow

23

25

23

QuietIO

Fast

35

32

35

13

15

13

1.2V

LVCMOS12, LVCMOS12_JEDEC

6

Slow

19

20

19

QuietIO

Fast

26

24

26

N/A

12

N/A

8

Slow

15

QuietIO

Fast

20

5

12

Slow

8

5

QuietIO

11

10

DS162 (v3.1.1) January 30, 2015

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Product Specification

38

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

SSO Limit per V_CCO/GND Pair

Table 34: SSO Limit per V

/GND Pair (Cont’d)

CCO

All TQG144, CPG196,

CSG225, FT(G)256, and

LX devices in CSG324

All CS(G)484, FG(G)484,

FG(G)676, FG(G)900, and

LXT devices in CSG324

V_CCO

I/O Standard

Drive

Slew

Bank 0/2

33

Bank 1/3

40

62

67

21

30

33

16

19

24

13

16

20

5

Bank 0/2

33

Bank 1/3/4/5

Fast

41

56

66

21

24

30

16

17

21

12

14

17

4

2

4

Slow

57

QuietIO

Fast

70

19

Slow

30

QuietIO

Fast

38

14

6

Slow

18

QuietIO

Fast

27

LVCMOS15, LVCMOS15_JEDEC

11

8

Slow

16

QuietIO

Fast

23

N/A

9

N/A

9

1.5V

12

16

Slow

8

5

QuietIO

Fast

10

5

9

4

Slow

8

QuietIO

10

5

9

HSTL_I

10

6

HSTL_II

N/A

7

N/A

7

HSTL_III

9

DIFF_HSTL_I

DIFF_HSTL_II

DIFF_HSTL_III

SSTL_15_II ⁽³⁾

DIFF_SSTL_15_II ⁽³⁾

27

30

15

27

5

27

30

18

27

4

N/A

21

N/A

21

N/A

15

12

DS162 (v3.1.1) January 30, 2015

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Product Specification

39

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

SSO Limit per V_CCO/GND Pair

Table 34: SSO Limit per V

/GND Pair (Cont’d)

CCO

All TQG144, CPG196,

CSG225, FT(G)256, and

LX devices in CSG324

All CS(G)484, FG(G)484,

FG(G)676, FG(G)900, and

LXT devices in CSG324

V_CCO

I/O Standard

Drive

Slew

Bank 0/2

39

65

80

22

38

45

16

27

30

13

16

25

5

Bank 1/3

46

75

80

25

36

40

18

25

28

15

18

22

7

Bank 0/2

39

65

80

22

38

45

16

27

30

13

16

25

5

Bank 1/3/4/5

Fast

47

74

85

25

29

35

17

19

23

14

16

18

5

2

4

Slow

QuietIO

Fast

Slow

QuietIO

Fast

6

Slow

QuietIO

Fast

LVCMOS18, LVCMOS18_JEDEC

8

Slow

QuietIO

Fast

12

16

24

Slow

7

8

7

6

QuietIO

Fast

11

4

10

5

11

4

8

4

1.8V

Slow

7

8

7

5

QuietIO

Fast

11

N/A

9

10

5

11

N/A

9

8

3

Slow

8

QuietIO

10

5

8

HSTL_I_18

9

HSTL_II_18

N/A

9

N/A

9

6

HSTL_III_18

10

30

15

30

14

42

10

5

11

27

18

33

14

42

10

4

DIFF_HSTL_I_18

DIFF_HSTL_II_18

DIFF_HSTL_III_18

MOBILE_DDR ⁽³⁾

DIFF_MOBILE_DDR ⁽³⁾

SSTL_18_I ⁽³⁾

SSTL_18_II ⁽³⁾

DIFF_SSTL_18_I ⁽³⁾

DIFF_SSTL_18_II ⁽³⁾

27

N/A

27

12

36

9

27

N/A

27

12

36

9

N/A

27

N/A

27

N/A

30

15

30

12

DS162 (v3.1.1) January 30, 2015

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Product Specification

40

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

SSO Limit per V_CCO/GND Pair

Table 34: SSO Limit per V

/GND Pair (Cont’d)

CCO

All TQG144, CPG196,

CSG225, FT(G)256, and

LX devices in CSG324

All CS(G)484, FG(G)484,

FG(G)676, FG(G)900, and

LXT devices in CSG324

V_CCO

I/O Standard

Drive

Slew

Bank 0/2

38

46

57

21

26

33

15

19

25

12

15

21

1

Bank 1/3

Bank 0/2

38

46

57

21

26

33

15

19

25

12

15

21

1

Bank 1/3/4/5

Fast

43

52

64

24

31

32

17

22

23

15

18

19

3

43

48

59

23

27

30

16

19

14

16

1

2

4

Slow

QuietIO

Fast

Slow

QuietIO

Fast

6

Slow

QuietIO

Fast

LVCMOS25

8

Slow

QuietIO

Fast

2.5V

12

16

24

Slow

2

7

2

4

QuietIO

Fast

3

8

3

8

1

3

1

Slow

3

7

3

QuietIO

Fast

4

9

4

8

N/A

10

N/A

30

N/A

3

N/A

10

N/A

30

N/A

1

Slow

5

2

QuietIO

8

6

SSTL_2_I ⁽³⁾

SSTL_2_II ⁽³⁾

DIFF_SSTL_2_I ⁽³⁾

DIFF_SSTL_2_II ⁽³⁾

11

7

11

7

33

21

33

24

DS162 (v3.1.1) January 30, 2015

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Product Specification

41

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

SSO Limit per V_CCO/GND Pair

Table 34: SSO Limit per V

/GND Pair (Cont’d)

CCO

All TQG144, CPG196,

CSG225, FT(G)256, and

LX devices in CSG324

All CS(G)484, FG(G)484,

FG(G)676, FG(G)900, and

LXT devices in CSG324

V_CCO

I/O Standard

Drive

Slew

Bank 0/2

Bank 1/3

Bank 0/2

Bank 1/3/4/5

Fast

42

50

60

21

32

39

14

19

29

11

15

25

1

46

55

68

27

37

42

19

25

30

15

20

24

3

42

50

60

21

32

39

14

19

29

11

15

25

1

44

49

60

25

32

37

17

22

25

14

18

20

1

2

4

Slow

QuietIO

Fast

Slow

QuietIO

Fast

6

Slow

QuietIO

Fast

3.3V

LVCMOS33

8

Slow

QuietIO

Fast

12

16

24

Slow

2

5

2

QuietIO

Fast

4

9

4

7

1

2

1

Slow

1

5

1

QuietIO

Fast

3

10

2

3

8

1

Slow

2

5

2

1

QuietIO

7

9

7

DS162 (v3.1.1) January 30, 2015

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Product Specification

42

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

SSO Limit per V_CCO/GND Pair

Table 34: SSO Limit per V

/GND Pair (Cont’d)

CCO

All TQG144, CPG196,

CSG225, FT(G)256, and

LX devices in CSG324

All CS(G)484, FG(G)484,

FG(G)676, FG(G)900, and

LXT devices in CSG324

V_CCO

I/O Standard

Drive

Slew

Bank 0/2

Bank 1/3

65

80

89

30

41

49

21

28

39

16

22

28

3

Bank 0/2

Bank 1/3/4/5

Fast

53

70

79

23

34

44

16

21

34

12

16

27

1

53

70

79

23

34

44

16

21

34

12

16

27

1

62

73

91

27

37

46

20

25

34

15

19

24

1

2

4

Slow

QuietIO

Fast

Slow

QuietIO

Fast

6

Slow

QuietIO

Fast

LVTTL

8

Slow

QuietIO

Fast

12

16

24

Slow

2

5

2

4

3.3V

QuietIO

Fast

2

10

3

2

8

1

Slow

1

7

1

2

QuietIO

Fast

3

11

2

3

8

1

Slow

2

5

2

QuietIO

8

9

8

PCI33_3

PCI66_3

SSTL_3_I

SSTL_3_II

18

5

19

8

18

5

19

8

3

5

3

DIFF_SSTL_3_I

DIFF_SSTL_3_II

SDIO

15

9

24

15

18

15

9

24

9

17

15

DS162 (v3.1.1) January 30, 2015

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Product Specification

43

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

SSO Limit per V_CCO/GND Pair

Table 34: SSO Limit per V

/GND Pair (Cont’d)

CCO

All TQG144, CPG196,

CSG225, FT(G)256, and

LX devices in CSG324

All CS(G)484, FG(G)484,

FG(G)676, FG(G)900, and

LXT devices in CSG324

V_CCO

I/O Standard

Drive

Slew

Bank 0/2

16

Bank 1/3

N/A

48

Bank 0/2

16

Bank 1/3/4/5

N/A

20

LVDS_33

LVDS_25

BLVDS_25

20

MINI_LVDS_33

MINI_LVDS_25

RSDS_33

13

N/A

40

13

N/A

30

18

12

Various RSDS_25

TMDS_33

15

83

PPDS_33

12

PPDS_25

16

DISPLAY_PORT

42

I2C

47

55

47

42

SMBUS

44

52

44

40

Notes:

1. SSO limits greater than the number of I/O per V

/GND pair (Table 33) indicate No Limit for the given I/O standard. They are provided in

CCO

this table to calculate limits when using multiple I/O standards in a bank.

2. Not available (N/A) indicates that the I/O standard is not available in the given bank.

3. When used with the MCB, these signals are exempt from SSO analysis due to the known activity of the MCB switching patterns. SSO

performance is validated for all MCB instances. MCB outputs can, in some cases, exceed the SSO limits.

DS162 (v3.1.1) January 30, 2015

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Product Specification

44

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Input/Output Logic Switching Characteristics

Table 35: ILOGIC2 Switching Characteristics

Speed Grade

Symbol Description

Units

-3

-3N

-2

-1L

Setup/Hold

T_ICE0CK/T_ICKCE0

CE0 pin Setup/Hold with respect to CLK

0.56/

–0.30

0.56/

–0.25

0.79/

–0.22

1.21/

–0.52

ns

T_ISRCK/T_ICKSR

_IDOCK/T_IOCKD

SR pin Setup/Hold with respect to CLK

0.74/

–0.23

0.74/

–0.22

0.98/

–0.20

1.31/

–0.45

T

D pin Setup/Hold with respect to CLK without Delay

DDLY pin Setup/Hold with respect to CLK (using IODELAY2)

1.19/

–0.83

1.36/

–0.83

1.73/

–0.83

2.18/

–1.77

T_IDOCKD/T_IOCKDD

0.31/

0.00

0.47/

0.00

0.54/

0.00

0.63/

–0.39

Combinatorial

T_IDI

D pin to O pin propagation delay, no Delay

0.95

0.23

1.28

0.39

1.53

0.44

2.25

0.74

ns

T_IDID

DDLY pin to O pin propagation delay (using IODELAY2)

Sequential Delays

T_IDLO

D pin to Q pin using flip-flop as a latch without Delay

DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY2)

CLK to Q outputs for XC devices⁽¹⁾

1.56

0.68

1.03

1.38

1.81

1.86

0.97

1.24

N/A

2.39

1.20

1.43

1.78

2.50

3.49

1.94

2.11

3.05

ns

T_IDLOD

T_ICKQ

CLK to Q outputs for XA and XQ devices

SR pin to Q outputs

T_{RQ_ILOGIC2}

1.81

Notes:

1. For IDDR2 configuration; see TRACE reports for SDR timing.

Table 36: OLOGIC2 Switching Characteristics

Speed Grade

Symbol

Description

Units

-3

-3N

-2

-1L

Setup/Hold

T_ODCK/T_OCKD

D1/D2 pins Setup/Hold with respect to CLK

OCE pin Setup/Hold with respect to CLK

SR pin Setup/Hold with respect to CLK

T1/T2 pins Setup/Hold with respect to CLK

TCE pin Setup/Hold with respect to CLK

0.81/

–0.05

0.86/

–0.05

1.18/

0.00

1.73/

–0.27

ns

T_OOCECK/T_OCKOCE

T_OSRCK/T_OCKSR

_OTCK/T_OCKT

0.75/

–0.10

0.75/

–0.10

1.01/

–0.05

1.66/

–0.23

0.70/

–0.28

0.79/

–0.28

1.03/

–0.23

1.39/

–0.47

T

0.24/

–0.08

0.56/

–0.06

0.83/

–0.01

0.99/

–0.19

T_OTCECK/T_OCKTCE

0.58/

–0.06

0.72/

–0.06

1.18/

–0.01

1.51/

–0.13

Sequential Delays

T_OCKQ

CLK to OQ/TQ out for XC devices⁽¹⁾

CLK to OQ/TQ out for XA and XQ devices

SR pin to OQ/TQ out

0.48

0.85

1.81

0.51

N/A

0.74

1.16

2.50

0.74

3.05

ns

T_{RQ_OLOGIC2}

1.81

Notes:

1. For ODDR2 configuration; see TRACE reports for SDR timing.

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Product Specification

45

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Input Serializer/Deserializer Switching Characteristics

Table 37: ISERDES2 Switching Characteristics

Speed Grade

Symbol

Description

Units

-3

-3N

-2

-1L

Setup/Hold for Control Lines

T_{ISCCK_BITSLIP}/ T_{ISCKC_BITSLIP}

BITSLIP pin Setup/Hold with respect to CLKDIV

CE pin Setup/Hold with respect to CLK

0.16/

–0.09

0.20/

–0.09

0.31/

–0.09

0.34/

–0.14

ns

T_{ISCCK_CE}/ T_{ISCKC_CE}

0.71/

–0.47

0.71/

–0.42

0.97/

–0.42

1.39/

–0.71

Setup/Hold for Data Lines

T

_{ISDCK_D}/T_{ISCKD_D}

D pin Setup/Hold with respect to CLK

0.24/

–0.15

0.25/

–0.05

0.29/

–0.05

0.09/

–0.05

ns

T

_{ISDCK_DDLY}/T_{ISCKD_DDLY}

DDLY pin Setup/Hold with respect to CLK (using

IODELAY2)

–0.25/ –0.25/ –0.25/ –0.54/

0.30 0.42 0.56 0.67

T_{ISDCK_D_DDR}/T_{ISCKD_D_DDR}

D pin Setup/Hold with respect to CLK at DDR mode

–0.03/ –0.03/ –0.03/ –0.05/

0.04 0.16 0.18 0.12

T_{ISDCK_DDLY_DDR}

T_{ISCKD_DDLY_DDR}

/

D pin Setup/Hold with respect to CLK at DDR mode

(using IODELAY2)

–0.40/ –0.40/ –0.40/ –0.71/

0.48

0.53

0.71

0.86

Sequential Delays

T_{ISCKO_Q}

CLKDIV to out at Q pin

1.30

270

1.44

2.02

250

2.22

125

ns

F_CLKDIV

CLKDIV maximum frequency

262.5

MHz

Output Serializer/Deserializer Switching Characteristics

Table 38: OSERDES2 Switching Characteristics

Speed Grade

-3N -2

Symbol

Description

Units

-3

-1L

Setup/Hold

T_{OSDCK_D}/T_{OSCKD_D}

D input Setup/Hold with respect to CLKDIV

T input Setup/Hold with respect to CLK

OCE input Setup/Hold with respect to CLK

TCE input Setup/Hold with respect to CLK

–0.03/

1.02

–0.03/ –0.03/ –0.02/

1.17 1.27 0.23

ns

(1)

T_{OSDCK_T}/T_{OSCKD_T}

_{OSCCK_OCE}/T_{OSCKC_OCE}

–0.05/ –0.05/ –0.05/ –0.05/

1.03

1.13

1.23

0.24

T

0.12/

–0.03

0.15/

–0.03

0.24/

–0.03

0.28/

–0.17

T_{OSCCK_TCE}/T_{OSCKC_TCE}

0.14/

–0.08

0.17/

–0.08

0.27/

–0.08

0.31/

–0.16

Sequential Delays

T_{OSCKO_OQ}

T_{OSCKO_TQ}

Clock to out from CLK to OQ

Clock to out from CLK to TQ

CLKDIV maximum frequency

0.94

270

1.11

1.51

250

1.89

1.91

125

ns

F_CLKDIV

262.5

MHz

Notes:

1.

T_{OSDCK_T2}/T_{OSCKD_T2}(T input setup/hold with respect to CLKDIV) are reported as T_{OSDCK_T}/T_{OSCKD_T}in TRACE report.

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Product Specification

46

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Input/Output Delay Switching Characteristics

Table 39: IODELAY2 Switching Characteristics

Speed Grade

Symbol

Description

Units

-3

-3N

-2

-1L⁽³⁾

T_{IODCCK_CAL}/ T_{IODCKC_CAL}

_{IODCCK_CE}/ T_{IODCKC_CE}

T_{IODCCK_INC}/ T_{IODCKC_INC}

T_{IODCCK_RST}/ T_{IODCKC_RST}

CAL pin Setup/Hold with respect to CK

CE pin Setup/Hold with respect to CK

INC pin Setup/Hold with respect to CK

RST pin Setup/Hold with respect to CK

0.28/

–0.13

0.33/

–0.13

0.48/

–0.13

N/A

ns

T

0.17/

–0.03

0.17/

–0.03

0.25/

–0.02

N/A

ns

0.10/

0.02

0.12/

0.03

0.18/

0.06

0.12/

–0.02

0.15/

–0.02

0.22/

–0.01

(2)

T_TAP1

Maximum tap 1 delay

Maximum tap 2 delay

Maximum tap 3 delay

Maximum tap 4 delay

Maximum tap 5 delay

Maximum tap 6 delay

Maximum tap 7 delay

Maximum tap 8 delay

8

14

16

N/A

ps

T_TAP2

T_TAP3

T_TAP4

T_TAP5

T_TAP6

T_TAP7

T_TAP8

F_MINCAL

40

66

77

95

120

141

194

249

276

341

188

140

166

231

292

343

424

188

ps

108

171

207

212

322

188

ps

Minimum allowed bit rate for calibration in variable

mode: VARIABLE_FROM_ZERO,

Mb/s

VARIABLE_FROM_HALF_MAX, and

DIFF_PHASE_DETECTOR.

T_{IODDO_IDATAIN}

T_{IODDO_ODATAIN}

Propagation delay through IODELAY2

Note 1 Note 1 Note 1 Note 3

–

Notes:

1. Delay depends on IODELAY2 tap setting. See TRACE report for actual values.

+ T (where n equals the remainder). For minimum delay consult the TRACE

2. Maximum tap delay = integer (number of taps/8) × T

TAP8

TAPn

setup and hold report. Minimum delay is typically greater than 30% of the maximum delay. Tap delays can vary by device and overall

conditions. See TRACE report for actual values.

3. Spartan-6 -1L devices only support tap 0. See TRACE report for actual values.

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Product Specification

47

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

CLB Switching Characteristics (SLICEM Only)

Table 40: CLB Switching Characteristics (SLICEM Only)

Speed Grade

Symbol

Description

Units

-3

-3N

-2

-1L

Combinatorial Delays

T_ILO

An – Dn LUT inputs to A to D outputs

0.21

0.37

0.26

0.43

0.26

0.43

0.46

0.77

ns, Max

An – Dn LUT inputs through F7AMUX/F7BMUX to

AMUX/CMUX output

T_OPAB

An – Dn LUT inputs through F7AMUX or F7BMUX and F8MUX

to BMUX output

0.37

0.46

0.84

ns, Max

T_ITO

An – Dn LUT inputs through latch to AQ – DQ outputs

An – Dn LUT inputs to AQ – DQ outputs (latch as logic)

An LUT inputs to COUT output

Bn LUT inputs to COUT output

Cn LUT inputs to COUT output

Dn LUT inputs to COUT output

AX input to COUT output

0.82

0.38

0.28

0.21

0.13

0.10

0.09

0.08

0.21

0.30

0.29

0.31

0.95

0.48

0.49

0.33

0.35

0.26

0.16

0.12

0.11

0.10

0.22

0.31

0.32

0.95

0.48

0.49

0.33

0.35

0.26

0.16

0.12

0.11

0.10

0.22

0.31

0.32

1.64

0.69

0.71

0.55

0.52

0.36

0.18

0.09

0.06

0.47

0.57

0.58

0.68

ns, Max

T_{TITO_LOGIC}

T_OPCYA

T_OPCYB

T_OPCYC

T_OPCYD

T_AXCY

T_BXCY

BX input to COUT output

T_CXCY

CX input to COUT output

T_DXCY

DX input to COUT output

T_BYP

CIN input to COUT output

T_CINA

CIN input to AMUX output

T_CINB

CIN input to BMUX output

T_CINC

CIN input to CMUX output

T_CIND

CIN input to DMUX output

Sequential Delays

T_CKO

Clock to AQ – DQ outputs

0.45

0.53

0.74

ns, Max

Setup and Hold Times of CLB Flip-Flops Before/After Clock CLK

T

_DICK/T_CKDI

AX – DX input to CLK on A – D flip-flops

0.42/

0.28

0.47/

0.39

0.47/

0.39

0.90/

0.56

ns, Min

T

_CECK/T_CKCE

CE input to CLK on A – D flip-flops

0.31/

–0.07

0.37/

–0.07

0.37/

–0.07

0.59/

–0.27

T_SRCK/T_CKSR

SR input to CLK on A – D flip-flops for XC devices

SR input to CLK on A – D flip-flops for XA and XQ devices

CIN input to CLK on A – D flip-flops

0.41/

0.02

0.42/

0.02

0.42/

0.02

0.68/

–0.29

0.41/

0.02

N/A

0.44/

0.02

0.68/

–0.29

T

_CINCK/T_CKCIN

0.31/

–0.17

0.31/

–0.13

0.31/

–0.13

0.81/

–0.42

Set/Reset

T_RPW

T_RQ

SR input minimum pulse width

0.41

0.60

862

0.48

0.70

0.65

806

0.48

0.70

0.65

667

1.37

0.88

0.90

500

ns, Min

ns, Max

MHz

Delay from SR input to AQ – DQ flip-flops

Delay from CE input to AQ – DQ flip-flops

Toggle frequency (for export control)

T_CEO

F_TOG

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Product Specification

48

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

CLB Distributed RAM Switching Characteristics (SLICEM Only)

Table 41: CLB Distributed RAM Switching Characteristics (SLICEM Only)

Speed Grade

Symbol

Description

Units

-3

-3N

-2

-1L

Sequential Delays

T_SHCKO

Clock to A – D outputs

Clock to A – D outputs (direct output path)

Setup and Hold Times Before/After Clock CLK

1.26

0.96

1.55

1.20

1.55

1.20

2.35

1.87

ns, Max

T

_DS/T_DH

AX – DX or AI – DI inputs to CLK

Address An inputs to clock for XC devices

Address An inputs to clock for XA and XQ devices

WE input to clock

0.59/

0.17

0.73/

0.22

0.73/

0.22

1.17/

0.33

ns, Min

T_AS/T_AH

0.28/

0.35

0.32/

0.42

0.32/

0.42

0.26/

0.71

0.28/

0.51

N/A

0.32/

0.51

0.26/

0.71

T

_WS/T_WH

0.31/

–0.08

0.37/

–0.08

0.37/

–0.08

0.59/

–0.27

T_CECK/T_CKCE

CE input to CLK

0.31/

–0.08

0.37/

–0.08

0.37/

–0.08

0.59/

–0.27

CLB Shift Register Switching Characteristics (SLICEM Only)

Table 42: CLB Shift Register Switching Characteristics

Speed Grade

Symbol

Description

Units

-3

-3N

-2

-1L

Sequential Delays

T_REG

Clock to A – D outputs

Clock to A – D outputs (direct output path)

Setup and Hold Times Before/After Clock CLK

1.35

1.24

1.78

1.65

1.78

1.65

2.74

2.48

ns, Max

T

_WS/T_WH

WE input to CLK

0.20/

–0.07

0.24/

–0.07

0.24/

–0.07

0.29/

–0.27

ns, Min

T_CECK/T_CKCE

CE input to CLK for XC devices

CE input to CLK for XA and XQ devices

AX – DX or AI – DI inputs to CLK

0.30/

0.30

0.30/

0.38

0.30/

0.38

0.82/

–0.41

0.32/

0.30

N/A

0.40/

0.38

0.82/

–0.41

T_DS/T_DH

0.07/

0.11

0.09/

0.14

0.09/

0.14

0.11/

0.23

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Product Specification

49

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Block RAM Switching Characteristics

Table 43: Block RAM Switching Characteristics

Speed Grade

Symbol

Description

Units

-3

-3N

-2

-1L

Block RAM Clock to Out Delays

T_{RCKO_DO}

Clock CLK to DOUT output (without output register)⁽¹⁾1.85

2.10

1.75

2.10

1.75

3.50 ns, Max

2.30 ns, Max

Clock CLK to DOUT output (with output register)⁽²⁾

1.60

T_{RCKO_DO_REG}

Setup and Hold Times Before/After Clock CLK

T_{RCCK_ADDR}/T_{RCKC_ADDR}

ADDR inputs for XC devices⁽³⁾

0.35/

0.10

0.40/

0.12

0.40/

0.12

0.50/ ns, Min

0.15

ADDR inputs for XA and XQ devices⁽³⁾

DIN inputs⁽⁴⁾

0.35/

0.17

N/A

0.40/

0.17

0.50/ ns, Min

0.15

T_{RDCK_DI}/T_{RCKD_DI}

_{RCCK_EN}/T_{RCKC_EN}

T_{RCCK_REGCE}/T_{RCKC_REGCE}

T_{RCCK_WE}/T_{RCKC_WE}

0.30/

0.10

0.30/

0.10

0.30/

0.10

0.40/ ns, Min

0.15

T

Block RAM Enable (EN) input

CE input of output register

Write Enable (WE) input

0.22/

0.05

0.25/

0.06

0.25/

0.06

0.44/ ns, Min

0.10

0.20/

0.10

0.20/

0.10

0.20/

0.10

0.28/ ns, Min

0.15

0.25/

0.10

0.33/

0.10

0.33/

0.10

0.28/ ns, Min

0.15

Maximum Frequency

F_MAX

Block RAM in all modes

320

280

150

MHz

Notes:

1.

2.

T

_{RCKO_DO}includes T_{RCKO_DOA}and T_{RCKO_DOPA}as well as the B port equivalent timing parameters.

_{RCKO_DO_REG}includes T_{RCKO_DOA_REG}and T_{RCKO_DOPA_REG}as well as the B port equivalent timing parameters.

3. The ADDR setup and hold must be met when EN is asserted (even when WE is deasserted). Otherwise, block RAM data corruption is possible.

4. _{RDCK_DI}includes both A and B inputs as well as the parity inputs of A and B.

T

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Product Specification

50

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

DSP48A1 Switching Characteristics

Table 44: DSP48A1 Switching Characteristics

Speed Grade

-3N -2

Pre-

adder

Post-

adder

Symbol

Description

Multiplier

Units

-3

-1L

Setup and Hold Times of Data/Control Pins to the Input Register Clock

T_{DSPDCK_A_A1REG}

/

A input to A1 register CLK

N/A

0.15/ 0.17/ 0.17/ 0.32/

0.09 0.09 0.09 0.09

ns

T_{DSPCKD_A_A1REG}

T_{DSPDCK_D_B1REG}

T_{DSPCKD_D_B1REG}

/

D input to B1 register CLK

Yes

1.90/ 1.95/ 1.95/ 2.82/

–0.07 –0.07 –0.07 –0.07

C input to C register CLK

for XC devices

0.11/ 0.13/ 0.13/ 0.24/

0.15

0.09

T_{DSPDCK_C_CREG}

T_{DSPCKD_C_CREG}

/

N/A

ns

C input to C register CLK

for XA and XQ devices

0.11/

0.19

0.13/ 0.24/

0.23 0.09

N/A

D input to D register CLK

for XC devices

0.09/ 0.10/ 0.10/ 0.19/

0.15

0.12

T_{DSPDCK_D_DREG}

T_{DSPCKD_D_DREG}

/

N/A

ns

D input to D register CLK

for XA and XQ devices

0.09/

0.23

0.10/ 0.19/

0.27 0.12

N/A

T_{DSPDCK_OPMODE_B1REG}

T_{DSPCKD_OPMODE_B1REG}

/

OPMODE input to B1 register CLK Yes

1.97/ 2.00/ 2.00/ 2.85/

0.01 0.01 0.01 0.01

OPMODE input to OPMODE

register CLK for XC devices

0.18/ 0.21/ 0.21/ 0.40/

0.12

T_{DSPDCK_OPMODE_OPMODEREG}

T_{DSPCKD_OPMODE_OPMODEREG}

/

N/A

ns

OPMODE input to OPMODE

register CLK for XA and XQ

devices

0.18/

0.16

0.21/ 0.40/

0.22 0.12

N/A

Setup and Hold Times of Data Pins to the Pipeline Register Clock

T_{DSPDCK_A_MREG}

/

A input to M register CLK

B input to M register CLK

D input to M register CLK

OPMODE to M register CLK

N/A

Yes

No

Yes

N/A

3.06/ 3.51/ 3.51/ 3.97/

–0.40 –0.40 –0.40 –0.40

ns

T_{DSPCKD_A_MREG}

T_{DSPDCK_B_MREG}

T_{DSPCKD_B_MREG}

/

3.96/ 4.58/ 4.58/ 7.00/

–0.68 –0.68 –0.68 –0.68

T_{DSPDCK_D_MREG}

T_{DSPCKD_D_MREG}

/

4.23/ 4.80/ 4.80/ 6.84/

–0.56 –0.56 –0.56 –0.56

T_{DSPDCK_OPMODE_MREG}

T_{DSPCKD_OPMODE_MREG}

/

4.18/ 4.80/ 4.80/ 6.88/

–0.48 –0.48 –0.48 –0.48

2.37/ 2.70/ 2.70/ 4.28/

–0.48 –0.48 –0.48 –0.48

Setup and Hold Times of Data/Control Pins to the Output Register Clock

T_{DSPDCK_A_PREG}

/

A input to P register CLK

N/A

Yes

No

Yes

N/A

Yes

4.32/ 5.06/ 5.06/ 7.52/

–0.76 –0.76 –0.76 –0.76

ns

T_{DSPCKD_A_PREG}

T_{DSPDCK_B_PREG}

T_{DSPCKD_B_PREG}

/

B input to P register CLK

5.87/ 6.87/ 6.87/ 10.55/ ns

–0.59 –0.59 –0.59 –0.59

4.14/ 4.68/ 4.68/ 8.12/

–0.93 –0.93 –0.93 –0.93

ns

T_{DSPDCK_C_PREG}

T_{DSPCKD_C_PREG}

/

C input to P register CLK

D input to P register CLK

N/A

Yes

2.20/ 2.25/ 2.25/ 3.27/

–0.23 –0.23 –0.23 –0.23

ns

T_{DSPDCK_D_PREG}

T_{DSPCKD_D_PREG}

5.90/ 6.91/ 6.91/ 10.39/ ns

–0.92 –0.92 –0.92 –0.92

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Product Specification

51

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 44: DSP48A1 Switching Characteristics (Cont’d)

Speed Grade

-3N -2

Pre-

Post-

Symbol

Description

Multiplier

Yes

Units

adder

-3

-1L

T_{DSPDCK_OPMODE_PREG}

T_{DSPCKD_OPMODE_PREG}

/

OPMODE input to P register CLK

Yes

No

Yes

6.21/ 7.27/ 7.27/ 10.43/ ns

–0.84 –0.84 –0.84 –0.84

Yes

1.69/ 1.98/ 1.98/ 3.62/

–0.87 –0.87 –0.87 –0.87

ns

No

2.09/ 2.30/ 2.30/ 3.79/

–0.22 –0.22 –0.22 –0.22

ns

Clock to Out from Output Register Clock to Output Pin

T_{DSPCKO_P_PREG}CLK (PREG) to P output

Clock to Out from Pipeline Register Clock to Output Pins

T_{DSPCKO_P_MREG}CLK (MREG) to P output

Clock to Out from Input Register Clock to Output Pins

N/A

Yes

1.20

3.38

1.34

3.95

1.34

3.95

1.90

5.83

ns

T_{DSPCKO_P_A1REG}

T_{DSPCKO_P_B1REG}

T_{DSPCKO_P_CREG}

T_{DSPCKO_P_DREG}

CLK (A1REG) to P output

CLK (B1REG) to P output

CLK (CREG) to P output

CLK (DREG) to P output

N/A

Yes

N/A

Yes

5.02

3.12

6.77

5.87

3.64

7.92

5.87

3.64

9.65

9.63

5.24

ns

7.92 12.53 ns

Combinatorial Delays from Input Pins to Output Pins

T_{DSPDO_A_P}

A input to P output

N/A

Yes

N/A

Yes

No

Yes

No

Yes

2.85

3.33

3.93

5.22

3.76

6.54

7.34

3.15

7.38

7.52

5.66

3.49

3.33

3.93

5.22

3.76

6.54

4.73

6.74

8.94

5.55

9.76

ns

No⁽²⁾3.35

Yes 4.56

T_{DSPDO_B_P}

B input to P output

No⁽²⁾3.22

No⁽²⁾6.01

Yes

N/A

Yes

No

Yes

6.27

2.69

6.31

6.43

4.84

3.11

7.34 11.96 ns

3.15 4.68 ns

T_{DSPDO_C_P}

C input to P output

T_{DSPDO_D_P}

D input to P output

7.38 11.81 ns

7.52 11.84 ns

T_{DSPDO_OPMODE_P}

OPMODE input to P output

5.66

3.49

9.25

5.03

ns

No

Maximum Frequency

F_MAX

All registers used

Yes

390

333

213 MHz

Notes:

1. A Yes signifies that the component is in the path. A No signifies that the component is being bypassed. N/A signifies not applicable because

no path exists.

2. Implemented in the post-adder by adding to zero.

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Product Specification

52

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 45: Device DNA Interface Port Switching Characteristics

Speed Grade

-3N -2

Symbol

Description

Units

-3

-1L

T_DNASSU

(T_{DNADCK_SHIFT}

Setup time on SHIFT before the rising edge of CLK

7

1

7

ns, Min

)

T_DNASH

(T_{DNACKD_SHIFT}

Hold time on SHIFT after the rising edge of CLK

Setup time on DIN before the rising edge of CLK

Hold time on DIN after the rising edge of CLK

)

T_DNADSU

(T_{DNADCK_DIN}

)

T_DNADH

(T_{DNACKD_DIN}

1

7

)

ns, Min

ns, Max

T_DNARSU

(T_{DNADCK_READ}

Setup time on READ before the rising edge of CLK

Hold time on READ after the rising edge of CLK

Clock-to-output delay on DOUT after rising edge of CLK

)

1,000

1

T_DNARH

(T_{DNACKD_READ}

ns, Min

)

0.5

6

ns, Min

ns, Max

MHz, Max

ns, Min

T_DNADCKO

(T_{DNACKO_DOUT}

)

(2)

T_DNACLKF

CLK frequency

CLK Low time

CLK High time

2

T_DNACLKL

T_DNACLKH

50

ns, Min

Notes:

1. The minimum READ pulse width is 8 ns, the maximum READ pulse width is 1 µs.

2. Also applies to TCK when reading DNA through the boundary-scan port.

Table 46: Suspend Mode Switching Characteristics

Symbol

Entering Suspend Mode

T_{SUSPENDHIGH_AWAKE}

T_{SUSPENDFILTER}

Description

Min

Max

Units

Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter

Adjustment to SUSPEND pin rising edge parameters when glitch filter enabled

2.5

31

–

14

430

15

ns

T_{SUSPEND_GWE}

Rising edge of SUSPEND pin until FPGA output pins drive their defined

SUSPEND constraint behavior (without glitch filter)

T_{SUSPEND_GTS}

Rising edge of SUSPEND pin to write-protect lock on all writable clocked

elements (without glitch filter)

–

15

ns

T_{SUSPEND_DISABLE}

Rising edge of the SUSPEND pin to FPGA input pins and interconnect

disabled (without glitch filter)

1500

Exiting Suspend Mode

T_{SUSPENDLOW_AWAKE}

Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does not

include DCM or PLL lock time.

7

–

7

75

41

µs

ns

µs

ns

µs

T_{SUSPEND_ENABLE}

T_{AWAKE_GWE1}

T_{AWAKE_GWE512}

T_{AWAKE_GTS1}

Falling edge of the SUSPEND pin to FPGA input pins and interconnect re-

enabled

Rising edge of the AWAKE pin until write-protect lock released on all writable

clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1.

80

Rising edge of the AWAKE pin until write-protect lock released on all writable

clocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512.

20.5

80

Rising edge of the AWAKE pin until outputs return to the behavior described in

the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1.

T_{AWAKE_GTS512}

T_{SCP_AWAKE}

Rising edge of the AWAKE pin until outputs return to the behavior described in

the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:512.

20.5

75

Rising edge of SCP pins to rising edge of AWAKE pin

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53

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Configuration Switching Characteristics

(1)

Table 47: Configuration Switching Characteristics

Speed Grade

Symbol

Description

Units

-3

-3N

-2

-1L

Power-up Timing Characteristics

(2)

T_PL

PROGRAM_B Latency

4

5

ms, Max

ms, Min/Max

ns, Min

(2)

T_POR

Power-on reset (50 ms ramp time)⁽³⁾

Power-on reset (10 ms ramp time)

PROGRAM_B Pulse Width

5/30

5/25

500

5/34

5/29

500

5/40

5/35

500

5/40

500

T_PROGRAM

Slave Serial Mode Programming Switching

T

_DCCK/T_CCKD

DIN Setup/Hold, slave mode

CCLK to DOUT

6.0/1.0 6.0/1.0 6.0/1.0 8.0/2.0

ns, Min

ns, Max

T_CCO

12

80

12

80

12

80

17

50

F_SCCK

Slave mode external CCLK

MHz, Max

Slave SelectMAP Mode Programming Switching

T_SMDCCK/T_SMCCKDSelectMAP Data Setup/Hold

_SMCSCCK/T_SMCCKCSCSI_B Setup/Hold

6.0/1.0 6.0/1.0 6.0/1.0 8.0/2.0

7.0/0.0 7.0/0.0 7.0/0.0 9.0/2.0

17.0/1.0 17.0/1.0 17.0/1.0 27.0/2.0

ns, Min

T

T_SMWCCK/T_SMCCKW

T_SMCKCSO

T_SMCO

RDWR_B Setup/Hold

ns, Min

CSO_B clock to out

16

13

12

50

16

13

12

50

16

13

12

50

26

25

17

25

ns, Max

MHz, Max

CCLK to DATA out in readback

CCLK to BUSY out in readback

T_SMCKBY

Maximum CCLK frequency (LX4, LX9, LX16, LX25,

LX25T, LX45, LX45T, LX75, and LX75T only)

Maximum CCLK frequency (LX100 and LX100T in x8

mode, LX150, and LX150T only)

40

35

20

40

35

20

40

35

20

4

MHz, Max

F_SMCCK

Maximum CCLK frequency (LX100 and LX100T in x16

mode only)

Maximum Readback CCLK frequency, including block

RAM (LX4, LX9, LX16, LX25, LX25T, LX45, LX45T,

LX75, and LX75T only)

Maximum Readback CCLK frequency, ignoring block

RAM (POST_CRC) (LX4, LX9, LX16, LX25, LX25T,

LX45, LX45T, LX75, and LX75T only)

50

30

MHz, Max

F_RBCCK

Maximum Readback CCLK frequency, including block

RAM (LX100, LX100T, LX150, and LX150T only)

12

35

12

35

12

35

4

MHz, Max

Maximum Readback CCLK frequency, ignoring block

RAM (POST_CRC) (LX100, LX100T, LX150, and

LX150T only)

20

Boundary-Scan Port Timing Specifications

T_TAPTCK

T_TCKTAP

T_TCKTDO

T_TCKH

TMS and TDI Setup time before TCK

10

5.5

6.5

12

33

2

10

5.5

6.5

12

33

2

10

5.5

6.5

12

33

2

17

5.5

8

ns, Min

TMS and TDI Hold time after TCK

TCK falling edge to TDO output valid

TCK clock minimum High time

ns, Max

ns, Min

21

18

2

T_TCKL

TCK clock minimum Low time

ns, Min

F_TCK

Maximum configuration TCK clock frequency

Maximum boundary-scan TCK clock frequency

Maximum AES key TCK clock frequency

MHz, Max

F_TCKB

F_TCKAES

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54

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 47: Configuration Switching Characteristics (Cont’d)

Speed Grade

Symbol Description

Units

-3

-3N

-2

-1L

BPI Master Flash Mode Programming Switching⁽⁴⁾

(5)

T_BPICCO

A[25:0], FCS_B, FOE_B, FWE_B, LDC outputs valid

after CCLK falling edge

15

20

ns, Max

T_BPIICCK

_BPIDCC/T_BPICCD

Master BPI CCLK (output) delay

Setup/Hold on D[15:0] data input pins

10/100 10/100 10/100 10/130 µs, Min/Max

T

5.0/1.0 5.0/1.0 5.0/1.0 6.0/2.0

ns, Min

SPI Master Flash Mode Programming Switching⁽⁶⁾

T_SPIDCC/T_SPIDCCD

DIN, MISO0, MISO1, MISO2, MISO3, Setup/Hold

5.0/1.0 5.0/1.0 5.0/1.0 7.0/1.0

ns, Min

before/after the rising CCLK edge

Master SPI CCLK (output) delay

MOSI clock to out

T_SPIICCK

T_SPICCM

T_SPICCFC

0.4/7.0 0.4/7.0 0.4/7.0 0.4/10.0 µs, Min/Max

13

16

13

16

13

16

19

26

ns, Max

CSO_B clock to out

CCLK Output (Master Modes)

T_MCCKL

T_MCCKH

F_MCCK

Master CCLK clock duty cycle Low

40/60

%, Min/Max

MHz, Max

Master CCLK clock duty cycle High

Maximum frequency, serial mode (Master Serial/SPI)

All devices

40

30

25

Maximum frequency, parallel mode (Master

SelectMAP/BPI)

MHz, Max

LX9, LX16, LX25, LX25T, LX45, LX45T, LX75, and

LX75T

Maximum frequency, parallel mode (Master

SelectMAP/BPI)

LX100 and LX100T in x8 mode, LX150, and LX150T

40

35

40

35

40

35

20

50

MHz, Max

%

Maximum frequency, parallel mode (Master

SelectMAP/BPI)

LX100 and LX100T in x16 mode

F_MCCKTOL

Frequency Tolerance, master mode

50

CCLK Input (Slave Modes)

T_SCCKL

Slave CCLK clock minimum Low time

5

8

ns, Min

T_SCCKH

Slave CCLK clock minimum High time

USERCCLK Input

T_USERCCLKL

T_USERCCLKH

F_USERCCLK

USERCCLK clock minimum Low time

USERCCLK clock minimum High time

Maximum USERCCLK frequency

12

40

12

40

12

40

16

30

ns, Min

MHz, Max

Notes:

1. Maximum frequency and setup/hold timing parameters are for 3.3V and 2.5V configuration voltages.

2. To support longer delays in configuration, use the design solutions described in UG380: Spartan-6 FPGA Configuration User Guide.

3. Table 6 specifies the power supply ramp time.

4. BPI mode is not supported in:

•

LX4, LX25, or LX25T devices

LX9 devices in the TQG144 package

LX9 or LX16 devices in the CPG196 package.

5. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.

6. Defense-grade Spartan-6Q -2Q devices configure in single default SPI Master (x1) mode at T_j= –55°C. During operation and when using all other

configuration functions, the minimum operating temperature is –40°C.

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55

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Clock Buffers and Networks

Table 48: Global Clock Switching Characteristics (BUFGMUX)

Speed Grade

Symbol

T_GSI(T_GSI0, T_GSI1

Description

Devices

Units

-3

-3N

0.31

0.21

-2

-1L

0.48

N/A

0.21

N/A

)

S pin Setup to I0/I1 inputs

LX devices

0.25

0.21

0.48

0.21

ns

LXT devices

LX devices

LXT devices

T_GIO(T_GI0O, T_GI1O

)

BUFGMUX delay from I0/I1 to O

Global clock tree (BUFGMUX)⁽¹⁾

values also apply to BUFH.

Maximum Frequency

F_MAX

LX devices

400

375

250

N/A

MHz

LXT devices

Notes:

1. The BUFGMUX F

MAX

Table 49: Input/Output Clock Switching Characteristics (BUFIO2)

Speed Grade

Symbol

Description

Devices

Units

-3

-3N

0.82

-2

-1L

1.50

N/A

(1)

T_{BUFCKO_O}

Clock to out delay from I to O

LX devices

0.67

1.09

ns

LXT devices

Maximum Frequency

F_MAX

I/O clock tree (BUFIO2)

LX devices

540

525

500

300

N/A

MHz

LXT devices

Notes:

1.

T

reflects the longest delay of T

, T

, and T

. See TRACE reports for specific values.

BUFCKO_O

BUFCKO_IOCLK BUFCKO_DIVCLK

BUFCKO_SSTROBE

Table 50: Input/Output Clock Switching Characteristics (BUFIO2FB)

Speed Grade

Units

Symbol

Description

Devices

-3

-3N

-2

-1L

Maximum Frequency

F_MAX

I/O clock tree (BUFIO2FB)

LX devices

1080

1050

950

500

N/A

MHz

LXT devices

Table 51: Input/Output Clock Switching Characteristics (BUFPLL)

Speed Grade

Symbol

Description

Devices

Units

-3

-3N

-2

-1L

Maximum Frequency

F_MAX

BUFPLL clock tree (BUFPLL)

LX devices

LXT devices

1080

1050

950

500

N/A

MHz

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

PLL Switching Characteristics

Table 52: PLL Specification

Speed Grade

Symbol

F_INMAX

Description

Device⁽¹⁾

Units

-3

-3N

525

400

19

-2

-1L

300

N/A

250

N/A

19

Maximum Input Clock Frequency from I/O Clock

(BUFIO2)

LX devices

LXT devices

LX devices

LXT devices

LX devices

LXT devices

All

540

400

19

450

375

19

MHz

Maximum Input Clock Frequency from Global Clock

Buffer (BUFGMUX)

F_INMIN

Minimum Input Clock Frequency

19

N/A

F_INJITTER

Maximum Input Clock Period Jitter: 19–200 MHz

Maximum Input Clock Period Jitter: > 200 MHz

Allowable Input Duty Cycle: 19—199 MHz

Allowable Input Duty Cycle: 200—299 MHz

Allowable Input Duty Cycle: > 300 MHz

Minimum PLL VCO Frequency

1 ns Maximum

<20% of clock input period Maximum

All

F_INDUTY

All

25/75

35/65

45/55

%

All

%

All

%

F_VCOMIN

LX devices

LXT devices

LX devices

400

1000

1

400

N/A

1000

N/A

1

MHz

ns

F_VCOMAX

Maximum PLL VCO Frequency

1080

1050

1

LXT devices 1080

F_BANDWIDTH

Low PLL Bandwidth at Typical⁽³⁾

High PLL Bandwidth at Typical⁽³⁾

Static Phase Offset of the PLL Outputs

PLL Output Jitter⁽³⁾

All

1

4

All

4

T_STAPHAOFFSET

T_OUTJITTER

T_OUTDUTY

All

0.12

Note 2

0.20

100

375

950

3.125

0.15

All

PLL Output Clock Duty Cycle Precision⁽⁴⁾

PLL Maximum Lock Time

All

0.15

100

0.15

100

0.25

100

ns

T_LOCKMAX

All

µs

LX devices

LXT devices

LX devices

400

250

MHz

PLL Maximum Output Frequency for BUFGMUX

PLL Maximum Output Frequency for BUFPLL

400

N/A

F_OUTMAX

1080

1050

3.125

500

LXT devices 1080

N/A

F_OUTMIN

PLL Minimum Output Frequency⁽⁵⁾

All

3.125

T_EXTFDVAR

External Clock Feedback Variation: 19–200 MHz

External Clock Feedback Variation: > 200 MHz

Minimum Reset Pulse Width

1 ns Maximum

< 20% of clock input period Maximum

RST_MINPULSE

5

ns

(6)

F_PFDMAX

Maximum Frequency at the Phase Frequency Detector LX devices

500

19

500

19

400

19

300

N/A

19

MHz

LXT devices

Minimum Frequency at the Phase Frequency Detector LX devices

LXT devices

F_PFDMIN

19

N/A

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Product Specification

57

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Speed Grade

Table 52: PLL Specification (Cont’d)

Symbol Description

Maximum Delay in the Feedback Path

Device⁽¹⁾

Units

-3

-3N

-2

-1L

T_FBDELAY

Notes:

All

3 ns Max or one CLKIN cycle

1. LXT devices are not available with a -1L speed grade.

2. Values for this parameter are available in the Clocking Wizard.

3. The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies.

4. Includes global clock buffer.

5. Calculated as F

/128 assuming output duty cycle is 50%.

VCO

6. When using CLK_FEEDBACK = CLKOUT0 with BUFIO2 feedback, the feedback frequency will be higher than the phase frequency detector

frequency. F = F / CLKFBOUT_MULT

PFDMAX

CLKFB

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

DCM Switching Characteristics

(1)

Table 53: Operating Frequency Ranges and Conditions for the Delay-Locked Loop (DLL)

Speed Grade

Symbol

Description

-3

-3N

Max

-2

-1L

Min Max

Units

Min

Max

Min

Max

Input Frequency Ranges

CLKIN_FREQ_DLL

Frequency of the CLKIN clock

input when the CLKDV output is

not used.

5⁽²⁾280⁽³⁾5⁽²⁾280⁽³⁾5⁽²⁾250⁽³⁾5⁽²⁾175⁽³⁾MHz

Frequency of the CLKIN clock

input when using the CLKDV

output.

5⁽²⁾280⁽³⁾5⁽²⁾280⁽³⁾5⁽²⁾250⁽³⁾5⁽²⁾133⁽³⁾MHz

Input Pulse Requirements

CLKIN_PULSE

CLKIN pulse width as a

percentage of the CLKIN period

for

40

45

60

55

40

45

60

55

40

45

60

55

40

45

60

55

%

CLKIN_FREQ_DLL < 150 MHz

CLKIN pulse width as a

percentage of the CLKIN period

for

CLKIN_FREQ_DLL > 150 MHz

Input Clock Jitter Tolerance and Delay Path Variation⁽⁴⁾

CLKIN_CYC_JITT_DLL_LF Cycle-to-cycle jitter at the CLKIN

input for

CLKIN_FREQ_DLL < 150 MHz

–

300

150

–

300

150

–

300

150

–

300

150

ps

CLKIN_CYC_JITT_DLL_HF

Cycle-to-cycle jitter at the CLKIN

input for

CLKIN_FREQ_DLL > 150 MHz.

CLKIN_PER_JITT_DLL

Period jitter at the CLKIN input.

–

1

–

1

–

1

–

1

ns

CLKFB_DELAY_VAR_EXT

Allowable variation of the off-chip

feedback delay from the DCM

output to the CLKFB input.

Notes:

1. DLL specifications apply when using any of the DLL outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV.

2. When operating independently of the DLL, the DFS supports lower CLKIN_FREQ_DLL frequencies. See Table 55.

3. The CLKIN_DIVIDE_BY_2 attribute increases the effective input frequency range. When set to TRUE, the input clock frequency is divided by two as

it enters the DCM. Input clock frequencies for the clock buffer being used can be increased up to the F_MAX(see Table 48 and Table 49 for BUFGMUX

and BUFIO2 limits). When used with CLK_FEEDBACK=2X, the input clock frequency matches the frequency for CLK2X, and is limited to

CLKOUT_FREQ_2X.

4. CLKIN_FREQ_DLL input jitter beyond these limits can cause the DCM to lose LOCK, indicated by the LOCKED output deasserting. The user must

then reset the DCM.

5. When using both DCMs in a CMT, both DCMs must be LOCKED.

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 54: Switching Characteristics for the Delay-Locked Loop (DLL)

Speed Grade

-3N -2

Min Max Min Max Min Max Min Max

Symbol

Description

-3

-1L

Units

Output Frequency Ranges

CLKOUT_FREQ_CLK0

Frequency for the CLK0 and

CLK180 outputs.

5

280

200

5

280

200

5

250

200

5

175 MHz

CLKOUT_FREQ_CLK90

CLKOUT_FREQ_2X

Frequency for the CLK90 and

CLK270 outputs.

Frequency for the CLK2X and

CLK2X180 outputs.

10

375

186

10

375

186

10

334

166

10

250 MHz

88.6 MHz

0.3125

CLKOUT_FREQ_DV

Frequency for the CLKDV output.

Output Clock Jitter^(2)(3)(4)

CLKOUT_PER_JITT_0

CLKOUT_PER_JITT_90

CLKOUT_PER_JITT_180

CLKOUT_PER_JITT_270

CLKOUT_PER_JITT_2X

Period jitter at the CLK0 output.

Period jitter at the CLK90 output.

Period jitter at the CLK180 output.

Period jitter at the CLK270 output.

–

100

150

–

100

150

–

100

150

–

100

150

ps

Period jitter at the CLK2X and

CLK2X180 outputs.

Maximum = [0.5% of CLKIN period + 100]

150 150 150

ps

CLKOUT_PER_JITT_DV1

CLKOUT_PER_JITT_DV2

Period jitter at the CLKDV output

when performing integer division.

–

150

Period jitter at the CLKDV output

when performing non-integer

division.

Maximum = [0.5% of CLKIN period + 100]

ps

Duty Cycle⁽⁴⁾

CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0,

CLK90, CLK180, CLK270, CLK2X,

CLK2X180, and CLKDV outputs,

Typical = [1% of CLKIN period + 350]

ps

including the BUFGMUX and clock

tree duty-cycle distortion.

Phase Alignment⁽⁴⁾

CLKIN_CLKFB_PHASE

Phase offset between the CLKIN

and CLKFB inputs

(CLK_FEEDBACK = 1X).

–

150

250

–

150

250

–

150

250

–

250

350

ps

Phase offset between the CLKIN

and CLKFB inputs

(CLK_FEEDBACK = 2X).⁽⁶⁾

CLKOUT_PHASE_DLL

Phase offset between DLL outputs

for CLK0 to CLK2X (not CLK2X180).

Maximum = [1% of CLKIN period + 100]

ps

Phase offset between DLL outputs

for all others.

Maximum =

[1% of

Maximum = [1% of CLKIN period + 150]

CLKIN

period + 200]

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60

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 54: Switching Characteristics for the Delay-Locked Loop (DLL) (Cont’d)

Speed Grade

-3N -2

Min Max Min Max Min Max Min Max

Symbol

Description

-3

-1L

Units

LOCK_DLL⁽³⁾

When using the DLL alone: The time

from deassertion at the DCM’s reset

input to the rising transition at its

LOCKED output. When the DCM is

locked, the CLKIN and CLKFB

signals are in phase.

–

5

–

5

–

5

–

5

ms

CLKIN_FREQ_DLL < 50 MHz.

When using the DLL alone: The time

from deassertion at the DCM’s reset

input to the rising transition at its

LOCKED output. When the DCM is

locked, the CLKIN and CLKFB

signals are in phase.

–

0.60

40

–

0.60

40

–

0.60

40

–

0.60

40

ms

ps

CLKIN_FREQ_DLL > 50 MHz

Delay Lines

DCM_DELAY_STEP⁽⁵⁾

Finest delay resolution, averaged

over all steps.

10

Notes:

1. The values in this table are based on the operating conditions described in Table 2 and Table 53.

2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.

3. For optimal jitter tolerance and faster LOCK time, use the CLKIN_PERIOD attribute.

4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, this data sheet specifies a maximum jitter of

(1% of CLKIN period + 150 ps). Assuming that the CLKIN frequency is 100 MHz, the equivalent CLKIN period is 10 ns. Since 1% of 10 ns is 0.1 ns

or 100 ps, the maximum jitter is (100 ps + 150 ps) = 250 ps.

5. A typical delay step size is 23 ps.

6. The timing analysis tools use the CLK_FEEDBACK = 1X condition for the CLKIN_CLKFB_PHASE value (reported as phase error). When using

CLK_FEEDBACK = 2X, add 100 ps to the phase error for the CLKIN_CLKFB_PHASE value (as shown in this table).

(1)

Table 55: Recommended Operating Conditions for the Digital Frequency Synthesizer (DFS)

Speed Grade

Symbol

Description

-3

-3N

-2

-1L

Units

Min Max Min Max Min Max Min Max

Input Frequency Ranges⁽²⁾

CLKIN_FREQ_FX

Frequency for the CLKIN input. Also

(3)

0.5 375

0.5 333

0.5 200

MHz

ps

described as F_CLKIN

.

Input Clock Jitter Tolerance⁽⁴⁾

CLKIN_CYC_JITT_FX_LF Cycle-to-cycle jitter at the CLKIN input,

based on CLKFX output frequency:

–

300

–

300

–

300

–

300

FCLKFX < 150 MHz.

CLKIN_CYC_JITT_FX_HF Cycle-to-cycle jitter at the CLKIN input,

based on CLKFX output frequency:

–

150

–

150

–

150

–

150

ps

ns

FCLKFX > 150 MHz.

CLKIN_PER_JITT_FX

Period jitter at the CLKIN input.

1

Notes:

1. DFS specifications apply when using either of the DFS outputs (CLKFX or CLKFX180).

2. When using both DFS and DLL outputs on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 53.

3. The CLKIN_DIVIDE_BY_2 attribute increases the effective input frequency range. When set to TRUE, the input clock frequency is divided by two as

it enters the DCM. Input clock frequencies for the clock buffer being used can be increased up to the F_MAX(see Table 48 and Table 49 for BUFGMUX

and BUFIO2 limits).

4. CLKIN input jitter beyond these limits can cause the DCM to lose LOCK.

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 56: Switching Characteristics for the Digital Frequency Synthesizer (DFS) for DCM_SP

Speed Grade

-3N -2

Min Max Min Max Min Max Min Max

Symbol

Description

-3

-1L

Units

Output Frequency Ranges

CLKOUT_FREQ_FX

Frequency for the CLKFX and

CLKFX180 outputs

5

375

5

375

5

333

5

200 MHz

Output Clock Jitter⁽²⁾⁽³⁾

Period jitter at the CLKFX and

CLKFX180 outputs. When

CLKIN < 20 MHz

Use the Clocking Wizard

ps

CLKOUT_PER_JITT_FX

Period jitter at the CLKFX and

CLKFX180 outputs. When

CLKIN > 20 MHz

Typical = (1% of CLKFX period + 100)

Maximum = (1% of CLKFX period + 350)

Duty Cycle⁽⁴⁾⁽⁵⁾

Duty cycle precision for the CLKFX

and CLKFX180 outputs including the

BUFGMUX and clock tree duty-cycle

distortion

CLKOUT_DUTY_CYCLE_FX

ps

Phase Alignment (Phase Error)⁽⁵⁾

Phase offset between the DFS

CLKFX output and the DLL CLK0

output when both the DFS and DLL

are used

CLKOUT_PHASE_FX

–

200

–

200

–

200

–

250

ps

Phase offset between the DFS

CLKFX180 output and the DLL CLK0

output when both the DFS and DLL

are used

CLKOUT_PHASE_FX180

Maximum = (1% of CLKFX period + 200)

LOCKED Time

When FCLKIN < 50 MHz, the time

from deassertion at the DCM’s reset

input to the rising transition at its

LOCKED output. The DFS asserts

LOCKED when the CLKFX and

CLKFX180 signals are valid. When

using both the DLL and the DFS, use

the longer locking time.

–

5

–

5

–

5

–

5

ms

LOCK_FX⁽²⁾

When FCLKIN > 50 MHz, the time

from deassertion at the DCM’s reset

input to the rising transition at its

LOCKED output. The DFS asserts

LOCKED when the CLKFX and

CLKFX180 signals are valid. When

using both the DLL and the DFS, use

the longer locking time.

0.45

0.60

Notes:

1. The values in this table are based on the operating conditions described in Table 2 and Table 55.

2. For optimal jitter tolerance and a faster LOCK time, use the CLKIN_PERIOD attribute.

3. Output jitter is characterized with no input jitter. Output jitter strongly depends on the environment, including the number of SSOs, the output drive

strength, CLB utilization, CLB switching activities, switching frequency, power supply, and PCB design. The actual maximum output jitter depends on

the system application.

4. The CLKFX, CLKFXDV, and CLKFX180 outputs have a duty cycle of approximately 50%.

5. Some duty cycle and alignment specifications include a percentage of the CLKFX output period. For example, this data sheet specifies a maximum

CLKFX jitter of (1% of CLKFX period + 200 ps). Assuming that the CLKFX output frequency is 100 MHz, the equivalent CLKFX period is 10 ns, and

1% of 10 ns is 0.1 ns or 100 ps. Accordingly, the maximum jitter is (100 ps + 200 ps) = 300 ps.

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Product Specification

62

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 57: Switching Characteristics for the Digital Frequency Synthesizer DFS (DCM_CLKGEN)

Speed Grade

-3N -2

Symbol

Description

-3

-1L

Units

Min

Max

Min

Max

Min

Max

Min

Max

Output Frequency Ranges (DCM_CLKGEN)

CLKOUT_FREQ_FX

Frequency for the CLKFX and

CLKFX180 outputs

5

375

5

375

5

333

5

200 MHz

100 MHz

CLKOUT_FREQ_FXDV

Frequency for the CLKFXDV

output

0.15625

166.5

187.5

Output Clock Jitter⁽²⁾⁽³⁾

CLKOUT_PER_JITT_FX

Period jitter at the CLKFX and

CLKFX180 outputs.

Typical = [0.2% of CLKFX period + 100]

ps

CLKOUT_PER_JITT_FXDV Period jitter at the CLKFXDV

output.

CLKFX period change in free

running oscillator mode at the

same temperature.

Maximum = 3% of CLKFX period

Maximum = 5% of CLKFX period

ps

FCLKFX > 50 MHz

CLKFX_FREEZE_VAR

CLKFX period change in free

running oscillator mode at the

same temperature.

FCLKFX < 50 MHz

CLKFX_FREEZE_TEMP

_SLOPE

CLKFX period will change in

free_oscillator mode over

temperature. Add to

CLKFX_FREEZE_VAR to

determine total CLKFX period

change. Percentage change for

CLKFX period over 1°C.

Maximum = 0.1

%/°C

Duty Cycle⁽⁴⁾⁽⁵⁾

CLKOUT_DUTY_CYCLE_ Duty cycle precision for the

FX

CLKFX and CLKFX180 outputs,

including the BUFGMUX and

clock tree duty-cycle distortion

Maximum = [1% of CLKFX period + 350]

ps

CLKOUT_DUTY_CYCLE_ Duty cycle precision for the

FXDV

CLKFXDV outputs, including the

BUFGMUX and clock tree

duty-cycle distortion

Lock Time

LOCK_FX⁽²⁾⁽⁷⁾

The time from deassertion at the

DCM’s Reset input to the rising

transition at its LOCKED output.

The DFS asserts LOCKED when

the CLKFX, CLKFX180, and

CLKFXDV signals are valid.

–

50

5

–

50

5

–

50

5

–

50

5

ms

Lock time requires

CLKFX_DIVIDE < F_IN/(0.50

MHz)

when: F_CLKIN< 50 MHz

when: F_CLKIN> 50 MHz

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Product Specification

63

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 57: Switching Characteristics for the Digital Frequency Synthesizer DFS (DCM_CLKGEN) (Cont’d)

Speed Grade

Symbol

Description

-3

-3N

-2

-1L

Units

Min

Max

Min

Max

Min

Max

Min

Max

Spread Spectrum

F_{CLKIN_FIXED_SPREAD_}

SPECTRUM

Frequency of the CLKIN input for

fixed spread spectrum

(SPREAD_SPECTRUM =

CENTER_LOW_SPREAD/

CENTER_HIGH_SPREAD)

30

200

30

200

30

200

30

200 MHz

(6)

T_{CENTER_LOW_SPREAD}

T_{CENTER_HIGH_SPREAD}

F_{MOD_FIXED_SPREAD_}

Spread at the CLKFX output for

fixed spread spectrum

(SPREAD_SPECTRUM =

CENTER_LOW_SPREAD)

100

Typical = ------------------------------------------

CLKFX_DIVIDE

ps

Maximum = 250

(6)

240

Typical = ------------------------------------------

CLKFX_DIVIDE

Spread at the CLKFX output for

fixed spread spectrum

(SPREAD_SPECTRUM=

CENTER_HIGH_SPREAD)

Maximum = 400

Average modulation frequency

when using fixed spread

spectrum

(SPREAD_SPECTRUM =

CENTER_LOW_SPREAD /

CENTER_HIGH_SPREAD)

(6)

SPECTRUM

Typical = F_IN/1024

MHz

Notes:

1. The values in this table are based on the operating conditions described in Table 2 and Table 55.

2. For optimal jitter tolerance and a faster LOCK time, use the CLKIN_PERIOD attribute.

3. Output jitter is characterized with no input jitter. Output jitter strongly depends on the environment, including the number of SSOs, the output drive

strength, CLB utilization, CLB switching activities, switching frequency, power supply, and PCB design. The actual maximum output jitter depends on

the system application.

4. The CLKFX, CLKFXDV, and CLKFX180 outputs have a duty cycle of approximately 50%.

5. Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, this data sheet specifies a maximum

CLKFX jitter of (1% of CLKFX period + 200 ps). Assuming that the CLKFX output frequency is 100 MHz, the equivalent CLKFX period is 10 ns, and

1% of 10 ns is 0.1 ns or 100 ps. Accordingly, the maximum jitter is (100 ps + 200 ps) = 300 ps.

6. When using CENTER_LOW_SPREAD, CENTER_HIGH_SPREAD, the valid values for CLKFX_MULTIPLY are limited to 2 through 32, and the valid

values for CLKFX_DIVIDE are limited to 1 through 4, with the resulting CLKFX or CLKFX180 output frequency limited to a minimum of 50 MHz.

7. When using dynamic frequency synthesis, LOCK_FX does not apply.

Table 58: Recommended Operating Conditions for the Phase-Shift Clock in Variable Phase Mode (DCM_SP) or

Dynamic Frequency Synthesis (DCM_CLKGEN)

Speed Grade

Symbol

Description

-3

-3N

-2

-1L

Units

Min

Max

Min

Max

Min

Max

Min

Max

Operating Frequency Ranges

PSCLK_FREQ

Frequency for the PSCLK

(DCM_SP) or PROGCLK

(DCM_CLKGEN) input.

1

167

1

167

1

167

1

100

MHz

Input Pulse Requirements

PSCLK_PULSE

PSCLK (DCM_SP) or PROGCLK

(DCM_CLKGEN) pulse width as a

percentage of the clock period.

40

60

40

60

40

60

40

60

%

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Product Specification

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

(1)

Table 59: Switching Characteristics for the Phase-Shift Clock in Variable Phase Mode

Symbol

Description

Amount of Phase Shift

Units

Phase Shifting Range

When CLKIN < 60 MHz, the maximum allowed

number of DCM_DELAY_STEP steps for a

given CLKIN clock period, where T = CLKIN

clock period in ns. When using

(INTEGER(10 x (TCLKIN – 3 ns)))

steps

CLKIN_DIVIDE_BY_2 = TRUE, double the

clock-effective clock period.

MAX_STEPS⁽²⁾

When CLKIN ≥ 60 MHz, the maximum allowed

number of DCM_DELAY_STEP steps for a

given CLKIN clock period, where T = CLKIN

clock period in ns. When using

(INTEGER(15 x (TCLKIN – 3 ns)))

steps

CLKIN_DIVIDE_BY_2 = TRUE, double the

clock-effective clock period.

Minimum guaranteed delay for variable phase

shifting.

(MAX_STEPS x DCM_DELAY_STEP_MIN)

(MAX_STEPS x DCM_DELAY_STEP_MAX)

ps

FINE_SHIFT_RANGE_MIN

Maximum guaranteed delay for variable phase

shifting

FINE_SHIFT_RANGE_MAX

Notes:

1. The values in this table are based on the operating conditions described in Table 53 and Table 58.

2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM has no initial fixed-phase shifting, that is, the PHASE_SHIFT

attribute is set to 0.

3. The DCM_DELAY_STEP values are provided at the end of Table 54.

(1)

Table 60: Miscellaneous DCM Timing Parameters

Symbol

Description

Min

Max

Units

DCM_RST_PW_MIN

Minimum duration of a RST pulse width

3

–

CLKIN cycles

Notes:

1. This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV). The DCM

DFS outputs (CLKFX, CLKFXDV, CLKFX180) are unaffected.

Table 61: Frequency Synthesis

Attribute

CLKFX_MULTIPLY (DCM_SP)

Min

2

Max

32

CLKFX_DIVIDE (DCM_SP)

1

32

CLKDV_DIVIDE (DCM_SP)

1.5

2

16

CLKFX_MULTIPLY (DCM_CLKGEN)

CLKFX_DIVIDE (DCM_CLKGEN)

CLKFXDV_DIVIDE (DCM_CLKGEN)

256

32

1

2

Table 62: DCM Switching Characteristics

Symbol

Speed Grade

Description

PSEN Setup/Hold

PSINCDEC Setup/Hold

Clock to out of PSDONE

Units

-3

-3N

-2

-1L

T_{DMCCK_PSEN}/ T_{DMCKC_PSEN}

1.50/

0.00

1.50/

0.00

1.50/

0.00

1.50/

0.00

ns

T

_{DMCCK_PSINCDEC}/ T_{DMCKC_PSINCDEC}

1.50/

0.00

1.50/

0.00

1.50/

0.00

1.50/

0.00

ns

T_{DMCKO_PSDONE}

1.50

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Product Specification

65

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Spartan-6 Device Pin-to-Pin Output Parameter Guidelines

All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are

listed in Table 63 through Table 69. Values are expressed in nanoseconds unless otherwise noted.

Table 63: Global Clock Input to Output Delay Without DCM or PLL

Speed Grade

Symbol

Description

Device

Units

-3

-3N

-2

-1L

LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without DCM or PLL

T_ICKOF

Global Clock and OUTFF without DCM or PLL XC6SLX4

6.12

5.98

6.20

6.37

6.39

6.59

6.98

6.44

6.30

6.52

6.69

6.89

N/A

6.51

6.42

6.69

6.88

6.99

7.18

7.68

N/A

7.68

7.48

7.84

8.10

8.16

8.41

8.80

7.68

7.48

7.84

8.12

8.16

8.36

8.16

8.80

9.41

9.10

9.44

N/A

ns

XC6SLX9

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

9.61

N/A

10.18

N/A

10.31

N/A

10.62

N/A

XA6SLX9

N/A

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

XQ6SLX75

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

N/A

10.18

N/A

6.89

N/A

10.62

N/A

7.61

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible

IOB and CLB flip-flops are clocked by the global clock net.

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 64: Global Clock Input to Output Delay With DCM in System-Synchronous Mode

Speed Grade

-3N -2

LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in System-Synchronous Mode.

Symbol

Description

Device

Units

-3

-1L

T_ICKOFDCM

Global Clock and OUTFF with DCM

XC6SLX4

4.23

4.28

3.95

4.37

3.90

3.86

3.90

4.03

4.55

4.62

4.27

4.69

4.22

N/A

5.17

4.57

4.18

4.70

4.23

4.16

4.33

N/A

6.11

5.34

4.59

5.50

4.77

4.66

4.83

6.11

5.33

4.59

4.69

5.50

4.77

5.34

4.77

4.96

6.60

6.36

6.91

N/A

6.85

N/A

6.31

N/A

7.25

N/A

6.63

N/A

6.31

N/A

6.63

N/A

ns

XC6SLX9

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

XA6SLX9

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

XQ6SLX75

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

N/A

4.22

N/A

4.62

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible

IOB and CLB flip-flops are clocked by the global clock net.

2. DCM output jitter is already included in the timing calculation.

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Product Specification

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 65: Global Clock Input to Output Delay With DCM in Source-Synchronous Mode

Speed Grade

-3N -2

LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in Source-Synchronous Mode.

Symbol

Description

Device

Units

-3

-1L

T_{ICKOFDCM_0}

Global Clock and OUTFF with DCM

XC6SLX4

5.03

5.08

4.81

5.26

4.77

4.72

4.76

4.90

5.35

5.42

5.13

5.58

5.09

N/A

6.13

5.51

5.13

5.69

5.18

5.11

5.30

N/A

7.21

6.44

5.69

6.63

5.88

5.76

5.93

7.21

6.44

5.69

5.79

6.63

5.87

6.44

5.87

6.06

8.05

7.96

7.94

N/A

7.92

N/A

7.95

N/A

8.59

N/A

7.93

N/A

7.95

N/A

7.93

N/A

ns

XC6SLX9

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

XA6SLX9

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

XQ6SLX75

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

N/A

5.09

N/A

5.50

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible

IOB and CLB flip-flops are clocked by the global clock net.

2. DCM output jitter is already included in the timing calculation.

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Product Specification

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 66: Global Clock Input to Output Delay With PLL in System-Synchronous Mode

Speed Grade

-3N -2

LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in System-Synchronous Mode.

Symbol

Description

Device

Units

-3

-1L

T_ICKOFPLL

Global Clock and OUTFF with PLL

XC6SLX4

4.57

4.41

4.03

4.63

4.01

4.02

4.06

3.65

4.88

4.74

4.43

4.94

4.32

N/A

5.25

4.64

4.32

4.96

4.30

4.33

3.98

N/A

6.25

5.39

4.91

5.75

4.88

4.90

4.58

6.13

5.27

4.78

4.88

5.62

4.77

5.41

4.77

4.60

7.34

6.92

7.64

N/A

7.36

N/A

7.15

N/A

7.37

N/A

6.94

N/A

7.15

N/A

6.94

N/A

ns

XC6SLX9

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

XA6SLX9

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

XQ6SLX75

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

N/A

4.32

N/A

4.35

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible

IOB and CLB flip-flops are clocked by the global clock net.

2. PLL output jitter is included in the timing calculation.

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 67: Global Clock Input to Output Delay With PLL in Source-Synchronous Mode

Speed Grade

-3N -2

LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with PLL in Source-Synchronous Mode.

Symbol

Description

Device

Units

-3

-1L

T_{ICKOFPLL_0}

Global Clock and OUTFF with PLL

XC6SLX4

5.49

5.23

5.00

5.59

4.96

4.97

5.01

4.59

5.79

5.56

5.40

5.89

5.27

N/A

6.29

5.77

5.35

6.03

5.41

5.42

5.06

N/A

7.44

6.79

6.10

7.02

6.22

6.21

5.86

7.32

6.66

5.97

6.07

6.90

6.12

6.80

6.12

5.88

8.55

8.21

8.54

N/A

8.39

N/A

8.32

N/A

9.08

N/A

8.13

N/A

8.32

N/A

8.13

N/A

ns

XC6SLX9

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

XA6SLX9

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

XQ6SLX75

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

N/A

5.27

N/A

5.21

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible

IOB and CLB flip-flops are clocked by the global clock net.

2. PLL output jitter is included in the timing calculation.

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 68: Global Clock Input to Output Delay With DCM and PLL in System-Synchronous Mode

Speed Grade

-3N -2

Symbol

Description

Device

Units

-3

-1L

LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in System-Synchronous Mode

and PLL in DCM2PLL Mode.

T_{ICKOFDCM_PLL}

Global Clock and OUTFF with DCM and PLL

XC6SLX4

4.78

4.70

4.63

4.68

4.72

4.76

4.44

5.07

5.22

5.01

4.93

4.94

N/A

5.24

5.12

5.09

4.98

5.04

5.07

4.73

N/A

6.32

5.94

5.92

5.83

5.88

5.92

5.31

6.18

5.77

5.80

5.90

5.67

5.70

5.77

5.70

5.31

7.09

6.63

7.30

N/A

7.26

N/A

6.90

N/A

7.77

N/A

6.96

N/A

6.90

N/A

6.96

N/A

ns

XC6SLX9

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

XA6SLX9

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

XQ6SLX75

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

N/A

4.94

N/A

5.02

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible

IOB and CLB flip-flops are clocked by the global clock net.

2. DCM and PLL output jitter are already included in the timing calculation.

DS162 (v3.1.1) January 30, 2015

www.xilinx.com

Product Specification

71

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 69: Global Clock Input to Output Delay With DCM and PLL in Source-Synchronous Mode

Speed Grade

-3N -2

Symbol

Description

Device

Units

-3

-1L

LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM in Source-Synchronous Mode

and PLL in DCM2PLL Mode.

T_{ICKOFDCM0_PLL}

Global Clock and OUTFF with DCM and PLL

XC6SLX4

5.58

5.50

5.57

5.53

5.55

5.58

5.62

5.32

5.87

6.02

5.88

5.82

5.81

N/A

6.19

6.06

6.04

5.97

6.00

6.03

5.70

N/A

7.42

7.05

7.02

6.96

6.99

7.02

6.41

7.28

6.87

6.90

7.00

6.81

6.80

6.88

6.80

6.41

8.54

8.24

8.33

N/A

8.32

N/A

8.54

N/A

9.11

N/A

8.26

N/A

8.54

N/A

8.26

N/A

ns

XC6SLX9

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

XA6SLX9

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

XQ6SLX75

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

N/A

5.81

N/A

5.90

Notes:

1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible

IOB and CLB flip-flops are clocked by the global clock net.

2. DCM and PLL output jitter are already included in the timing calculation.

DS162 (v3.1.1) January 30, 2015

www.xilinx.com

Product Specification

72

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Spartan-6 Device Pin-to-Pin Input Parameter Guidelines

All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are

listed in Table 70 through Table 77. Values are expressed in nanoseconds unless otherwise noted.

Table 70: Global Clock Setup and Hold Without DCM or PLL (No Delay)

Speed Grade

Symbol

Description

Device

Units

-3

-3N

-2

-1L

Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾

T

_PSND/ T_PHND

No Delay Global Clock and IFF⁽³⁾

without DCM or PLL

XC6SLX4

0.10/1.56

0.12/1.42

0.18/1.64

N/A

0.10/1.83

0.10/1.84

0.12/1.64

0.18/1.99

0.07/2.54

0.13/2.19

0.11/2.57

N/A

ns

XC6SLX9

0.10/1.57

0.12/1.48

0.18/1.75

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

–0.08/1.80 –0.08/1.95 –0.08/2.27 –0.17/2.74

–0.08/1.80 –0.08/1.95 –0.08/2.27 N/A

0.13/2.27 –0.12/3.30

0.13/2.27 N/A

0.13/1.81

0.13/2.06

–0.14/2.03 –0.14/2.24 –0.14/2.56 –0.17/3.44

–0.14/2.03 –0.14/2.24 –0.14/2.56 N/A

–0.24/2.42 –0.24/2.74 –0.24/2.95 –0.60/3.75

–0.24/2.42 –0.24/2.74 –0.24/2.95

N/A

0.10/1.57

0.12/1.43

0.18/1.65

–0.08/1.82

0.13/2.02

N/A

0.10/1.84

0.12/1.64

0.18/1.99

–0.08/2.27

0.13/2.32

0.10/2.51

XA6SLX9

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

XQ6SLX75

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

N/A

0.13/2.32 –0.12/3.30

0.13/2.32 N/A

–0.24/2.95 –0.60/3.75

–0.24/2.95 N/A

0.13/2.02

N/A

–0.24/2.74

Notes:

1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock

input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using

the fastest process, lowest temperature, and highest voltage.

2. IFF = Input Flip-Flop or Latch.

DS162 (v3.1.1) January 30, 2015

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Product Specification

73

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 71: Global Clock Setup and Hold Without DCM or PLL (Default Delay)

Speed Grade

Symbol

Description

Device

Units

-3

-3N

-2

-1L

Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾

T_PSFD/ T_PHFD

Default Delay⁽²⁾Global Clock and

IFF⁽³⁾without DCM or PLL

XC6SLX4

0.66/1.17

0.87/1.16

0.68/0.77

0.40/1.05

0.41/1.11

0.39/1.12

0.23/1.54

0.73/1.18

0.90/1.20

0.70/0.81

0.76/0.81

0.40/1.06

0.41/1.24

N/A

0.75/1.17

0.93/1.16

0.81/0.81

0.42/1.17

0.41/1.13

0.39/1.23

0.23/1.62

N/A

1.05/0.79

1.05/1.17

0.96/1.16

0.87/0.82

0.64/1.20

0.80/1.14

0.39/1.28

0.23/1.62

1.05/0.80

0.96/0.75

0.87/0.91

1.03/0.91

0.64/1.20

0.80/1.18

0.86/1.55

0.80/1.18

0.28/1.57

2.09/1.05

1.86/1.06

2.21/1.33

N/A

ns

XC6SLX9

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

1.61/1.67

N/A

1.23/1.82

N/A

1.13/1.94

N/A

1.14/2.05

N/A

XA6SLX9

N/A

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

XQ6SLX75

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

N/A

1.23/1.82

N/A

0.41/1.24

N/A

1.14/2.05

N/A

0.28/1.78

N/A

Notes:

1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the

Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global

Clock input signal using the fastest process, lowest temperature, and highest voltage.

2. Default delay uses IODELAY2 tap 0.

3. IFF = Input Flip-Flop or Latch.

DS162 (v3.1.1) January 30, 2015

www.xilinx.com

Product Specification

74

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 72: Global Clock Setup and Hold With DCM in System-Synchronous Mode

Speed Grade

Symbol

Description

Device

Units

-3

-3N

-2

-1L

Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾

T_PSDCM/ T_PHDCM

No Delay Global Clock and IFF⁽²⁾

with DCM in System-Synchronous

Mode

XC6SLX4

1.54/0.06

N/A

1.75/0.12

2.84/0.27

ns

XC6SLX9

1.63/0.12

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

1.72/–0.18 1.87/–0.17 2.13/–0.17 2.31/0.26

1.70/–0.03 1.78/–0.02 2.00/–0.02 2.88/0.20

1.70/0.07

1.78/0.08

2.00/0.08

N/A

1.74/–0.03 1.84/–0.02 2.02/–0.02 2.64/0.52

1.74/–0.01 1.84/0.00

2.02/0.00

2.20/0.12

1.97/0.08

1.97/0.10

1.82/0.40

1.75/0.26

2.13/0.03

2.05/0.17

2.13/0.17

2.02/0.13

2.20/0.12

2.46/0.24

2.20/0.12

1.82/0.56

N/A

2.96/0.58

N/A

1.86/0.11

1.64/0.07

1.64/0.09

1.53/0.39

1.65/0.16

1.88/0.02

1.80/0.16

1.75/0.12

1.87/0.11

N/A

1.98/0.12

1.72/0.08

1.72/0.10

1.62/0.40

N/A

2.70/0.99

N/A

2.75/1.00

N/A

XA6SLX9

N/A

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

XQ6SLX75

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

N/A

2.96/0.58

N/A

1.87/0.11

N/A

2.75/1.00

N/A

1.65/0.55

N/A

Notes:

1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock

input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using

the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter.

2. IFF = Input Flip-Flop or Latch

3. Use IBIS to determine any duty-cycle distortion incurred using various standards.

DS162 (v3.1.1) January 30, 2015

www.xilinx.com

Product Specification

75

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 73: Global Clock Setup and Hold With DCM in Source-Synchronous Mode

Speed Grade

Symbol

Description

Device

Units

-3

-3N

-2

-1L

Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾

T_PSDCM0/ T_PHDCM0No Delay Global Clock and IFF⁽²⁾

with DCM in Source-Synchronous

Mode

XC6SLX4

0.71/0.65

0.71/0.69

0.86/0.52

0.84/0.58

0.85/0.70

1.00/0.62

1.00/0.71

0.81/0.68

0.68/0.98

0.81/0.74

1.01/0.56

0.94/0.76

0.86/0.74

1.02/0.71

N/A

0.71/1.19

0.92/0.57

0.90/0.59

0.90/0.76

1.06/0.63

1.06/0.72

0.81/0.69

0.69/0.99

N/A

0.72/1.22

0.72/1.36

1.04/0.60

1.01/0.59

0.98/0.79

1.15/0.63

1.15/0.72

0.94/0.69

0.79/0.99

0.72/1.36

1.04/0.60

1.06/0.77

1.14/0.77

0.98/0.78

1.15/0.72

1.37/0.75

1.15/0.72

0.79/1.15

1.58/1.18

1.02/1.06

1.58/1.07

N/A

ns

XC6SLX9

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

1.34/1.34

N/A

1.65/1.46

N/A

1.42/2.07

N/A

1.45/1.60

N/A

XA6SLX9

N/A

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

XQ6SLX75

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

N/A

1.65/1.46

N/A

1.02/0.71

N/A

1.45/1.60

N/A

0.73/1.15

N/A

Notes:

1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock

input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using

the fastest process, lowest temperature, and highest voltage. These measurements include DCM CLK0 jitter.

2. IFF = Input Flip-Flop or Latch

3. Use IBIS to determine any duty-cycle distortion incurred using various standards.

DS162 (v3.1.1) January 30, 2015

www.xilinx.com

Product Specification

76

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 74: Global Clock Setup and Hold With PLL in System-Synchronous Mode

Speed Grade

Symbol

Description

Device

Units

-3

-3N

-2

-1L

Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾

T_PSPLL/ T_PHPLL

No Delay Global Clock and IFF⁽²⁾

with PLL in System-Synchronous

Mode

XC6SLX4

1.37/0.25

1.37/0.21

N/A

1.52/0.41

1.52/0.26

2.07/0.69

ns

XC6SLX9

1.48/0.21

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

1.33/–0.03 1.53/–0.02 1.60/–0.02 1.57/0.48

1.65/0.28

1.55/0.18

1.77/0.21

1.44/0.32

1.39/0.49

1.61/0.10

1.89/–0.08

1.85/0.16

1.58/0.07

1.80/0.06

N/A

1.71/0.28

1.64/0.18

1.89/0.21

1.52/0.32

1.48/0.49

N/A

1.91/0.28

1.75/0.18

2.13/0.21

1.70/0.32

1.67/0.49

1.64/0.28

1.72/–0.08

2.08/0.16

2.17/0.16

1.87/0.03

2.25/0.06

2.34/0.14

2.25/0.06

1.79/0.37

2.44/0.76

N/A

2.02/0.90

N/A

2.46/0.53

N/A

1.78/0.86

N/A

1.94/0.94

N/A

XA6SLX9

N/A

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

XQ6SLX75

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

N/A

2.46/0.53

N/A

1.80/0.06

N/A

1.94/0.94

N/A

1.43/0.37

N/A

Notes:

1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock

input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using

the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.

2. IFF = Input Flip-Flop or Latch

3. Use IBIS to determine any duty-cycle distortion incurred using various standards.

DS162 (v3.1.1) January 30, 2015

www.xilinx.com

Product Specification

77

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 75: Global Clock Setup and Hold With PLL in Source-Synchronous Mode

Speed Grade

Symbol

Description

Device

Units

-3

-3N

-2

-1L

Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾

T_PSPLL0/ T_PHPLL0

No Delay Global Clock and IFF⁽²⁾

with PLL in Source-Synchronous

Mode

XC6SLX4

0.47/1.08

0.37/0.75

0.69/1.06

0.57/1.05

0.57/1.06

0.86/1.04

0.53/1.13

0.50/1.31

0.71/0.93

0.92/0.69

0.99/0.94

0.63/1.02

0.88/0.89

N/A

0.47/1.35

0.37/0.82

0.69/1.06

0.65/1.10

0.87/1.04

0.54/1.13

0.51/1.31

N/A

0.47/1.60

0.51/0.94

0.69/1.06

0.65/1.18

0.90/1.04

0.55/1.13

0.52/1.31

0.62/1.47

0.63/0.82

0.96/0.94

1.04/0.94

0.72/1.05

1.02/0.89

1.25/0.96

1.02/0.89

0.63/1.19

1.15/1.68

0.57/1.31

1.86/1.67

N/A

ns

XC6SLX9

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

1.02/1.65

N/A

1.34/1.55

N/A

0.89/2.39

N/A

1.02/1.72

N/A

XA6SLX9

N/A

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

XQ6SLX75

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

N/A

1.34/1.55

N/A

0.88/0.89

N/A

1.02/1.72

N/A

0.60/1.19

N/A

Notes:

1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock

input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using

the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.

2. IFF = Input Flip-Flop or Latch

3. Use IBIS to determine any duty-cycle distortion incurred using various standards.

DS162 (v3.1.1) January 30, 2015

www.xilinx.com

Product Specification

78

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 76: Global Clock Setup and Hold With DCM and PLL in System-Synchronous Mode

Speed Grade

Symbol

Description

Device

Units

-3

-3N

-2

-1L

Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾

T_PSDCMPLL

/

No Delay Global Clock and IFF⁽²⁾

with DCM in System-Synchronous

Mode and PLL in DCM2PLL Mode.

XC6SLX4

1.16/0.49

1.16/0.44

N/A

1.39/0.49

1.39/0.44

2.36/0.59

ns

T_PHDCMPLL

XC6SLX9

1.37/0.44

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

1.44/–0.08 1.49/–0.04 1.62/–0.04 2.06/0.55

1.52/0.42

1.54/0.39

1.72/0.41

1.34/0.51

1.30/0.60

1.58/0.37

2.67/0.35

1.74/0.27

1.58/0.29

1.74/0.24

N/A

1.65/0.42

1.59/0.39

1.80/0.41

1.46/0.51

1.40/0.60

N/A

1.83/0.42

1.75/0.39

1.99/0.41

1.64/0.51

1.55/0.60

1.58/0.37

2.67/0.17

1.95/0.27

2.03/0.27

1.87/0.29

2.11/0.24

2.64/0.82

2.11/0.24

1.67/0.70

2.52/0.43

N/A

2.48/0.76

N/A

2.60/0.75

N/A

2.12/0.90

N/A

2.57/0.97

N/A

XA6SLX9

N/A

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

XQ6SLX75

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

N/A

2.60/0.75

N/A

1.74/0.24

N/A

2.57/0.97

N/A

1.50/0.70

N/A

Notes:

1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock

input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using

the fastest process, lowest temperature, and highest voltage. These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0

driving BUFG.

2. IFF = Input Flip-Flop or Latch

3. Use IBIS to determine any duty-cycle distortion incurred using various standards.

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 77: Global Clock Setup and Hold With DCM and PLL in Source-Synchronous Mode

Speed Grade

-3N -2

Symbol

Description

Device

Units

-3

-1L

Example Data Input Set-Up and Hold Times Relative to a Forwarded Clock Input Pin,⁽¹⁾Using DCM, PLL, and Global Clock Buffer for

the LVCMOS25 standard.

T_{PSDCMPLL_0}

/

No Delay Global Clock and IFF⁽²⁾

with DCM in Source-Synchronous

Mode and PLL in DCM2PLL Mode.

XC6SLX4

0.43/1.07

0.43/1.03

0.74/0.93

0.67/1.02

0.65/0.99

0.65/1.00

0.86/1.01

0.50/1.10

0.45/1.28

0.74/1.00

1.81/1.15

0.89/1.01

0.69/0.95

0.88/0.94

N/A

0.45/1.14

0.74/1.12

0.76/1.11

0.65/1.04

0.88/1.06

0.56/1.10

0.47/1.28

N/A

0.43/1.43

0.45/1.43

0.74/1.21

0.84/1.18

0.71/1.12

0.94/1.14

0.61/1.17

0.52/1.28

0.74/1.43

1.81/1.03

0.96/1.05

1.04/1.15

0.83/0.96

1.06/0.96

1.55/1.33

1.06/0.96

0.64/1.30

1.10/1.67

0.77/1.35

1.23/1.46

N/A

ns

T_{PHDCMPLL_0}

XC6SLX9

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

1.18/1.58

N/A

1.29/1.67

N/A

0.84/2.24

N/A

1.27/1.56

N/A

XA6SLX9

N/A

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

XQ6SLX75

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

N/A

1.29/1.67

N/A

0.88/0.94

N/A

1.27/1.56

N/A

0.58/1.30

N/A

Notes:

1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the Global Clock

input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global Clock input signal using

the fastest process, lowest temperature, and highest voltage. The timing values were measured using the fine-phase adjustment feature of the DCM.

These measurements include CMT jitter; DCM CLK0 driving PLL, PLL CLKOUT0 driving BUFG. Package skew is not included in these

measurements.

2. IFF = Input Flip-Flop

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Source-Synchronous Switching Characteristics

The parameters in this section provide the necessary values for calculating timing budgets for Spartan-6 FPGA

source-synchronous transmitter and receiver data-valid windows.

Table 78: Duty Cycle Distortion and Clock-Tree Skew

Speed Grade

Symbol

Description

Device⁽¹⁾

LX4

Units

-3

-3N

N/A

-2

-1L

0.35

N/A

0.35

N/A

0.35

N/A

0.35

N/A

0.35

N/A

0.29

0.22

0.41

N/A

0.28

N/A

0.50

N/A

0.21

N/A

0.35

N/A

0.50

N/A

T_{DCD_CLK}

Global Clock Tree Duty Cycle Distortion⁽²⁾

0.20

0.35

0.25

0.15

0.26

0.20

0.56

0.22

N/A

0.20

0.35

0.25

0.15

0.26

0.20

0.56

0.22

0.43

0.22

0.48

0.25

ns

LX9

0.20

0.35

N/A

LX16

LX25

LX25T

LX45

LX45T

LX75

LX75T

LX100

LX100T

LX150

LX150T

LX4

T_CKSKEW

Global Clock Tree Skew⁽³⁾

LX9

0.25

0.15

0.26

0.20

0.56

0.22

N/A

LX16

LX25

LX25T

LX45

LX45T

LX75

LX75T

XC6SLX100⁽⁴⁾

XA6SLX100⁽⁴⁾

LX100T

LX150

LX150T

LX devices

LXT devices

0.22

0.48

0.25

0.22

0.48

0.25

T_{DCD_BUFIO2}I/O clock tree duty cycle distortion

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 78: Duty Cycle Distortion and Clock-Tree Skew (Cont’d)

Symbol Description

Device⁽¹⁾

LX4

Speed Grade

Units

-3

-3N

N/A

-2

-1L

0.07

N/A

0.07

N/A

0.07

N/A

0.07

N/A

0.07

N/A

T_BUFIOSKEWI/O clock tree skew across one clock region

0.06

ns

LX9

0.06

LX16

LX25

LX25T

LX45

LX45T

LX75

LX75T

LX100

LX100T

LX150

LX150T

Notes:

1. LXT devices are not available with a -1L speed grade. The LX4 is not available in -3N speed grade.

2. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where

other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times.

3. The T_CKSKEWvalue represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists

for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA Editor and Timing Analyzer

tools to evaluate clock skew specific to your application.

4. The T_CKSKEWis 0.43 ns for the XA6SLX100 device using a -2 speed grade and 0.22 ns for the XC6SLX100 devices using the -2 speed grade.

Table 79: Package Skew

Symbol

T_PKGSKEW

Description

Package Skew⁽¹⁾

Device

Package⁽²⁾

TQG144

CPG196

CSG225

TQG144

CPG196

CSG225

FT(G)256

CSG324

CPG196

CSG225

FT(G)256

CSG324

FT(G)256

CSG324

FG(G)484

CSG324

FG(G)484

Value

N/A

23

Units

ps

LX4

LX9

58

N/A

23

58

88

64

19

70

LX16

71

54

90

LX25

61

84

48

LX25T

112

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 79: Package Skew (Cont’d)

Symbol

Description

Package Skew⁽¹⁾

Device

Package⁽²⁾

CSG324

Value

70

Units

ps

T_PKGSKEW

CS(G)484

FG(G)484

FG(G)676

CSG324

99

LX45

109

138

75

LX45T

LX75

CS(G)484

FG(G)484

CS(G)484

FG(G)484

FG(G)676

CS(G)484

FG(G)484

FG(G)676

CS(G)484

FG(G)484

FG(G)676

CS(G)484

FG(G)484

FG(G)676

FG(G)900

CS(G)484

FG(G)484

FG(G)676

FG(G)900

CS(G)484

FG(G)484

FG(G)676

FG(G)900

100

95

101

107

161

107

110

134

95

LX75T

LX100

155

144

88

111

147

134

84

LX100T

LX150

103

115

121

83

88

LX150T

141

120

Notes:

1. These values represent the worst-case skew between any two SelectIO resources in the package: shortest delay to longest delay from Pad to Ball.

2. Some of the devices are available in both Pb and Pb-free (additional G) packages as standard ordering options. See DS160: Spartan-6 Family

Overview for more information.

Table 80: Sample Window

Speed Grade

Symbol

Description

Device⁽¹⁾

Units

-3

-3N

510

430

-2

-1L

740

590

T_SAMP

Sampling Error at Receiver Pins⁽²⁾

All

510

430

530

450

ps

T_{SAMP_BUFIO2}

Sampling Error at Receiver Pins using

BUFIO2⁽³⁾

Notes:

1. LXT devices are not available with a -1L speed grade.

2. This parameter indicates the total sampling error of Spartan-6 FPGA DDR input registers, measured across voltage, temperature, and process. The

characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:

- CLK0 DCM jitter

- DCM accuracy (phase offset)

- DCM phase shift resolution

These measurements do not include package or clock tree skew.

3. This parameter indicates the total sampling error of Spartan-6 FPGA DDR input registers, measured across voltage, temperature, and process. The

characterization methodology uses the BUFIO2 clock network and IODELAY2 to capture the DDR input registers’ edges of operation. These

measurements do not include package or clock tree skew.

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 81: Source-Synchronous Pin-to-Pin Setup/Hold and Clock-to-Out Using BUFIO2

Speed Grade

Symbol

Description

Device

Units

-3

-3N

-2

-1L

Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO2

T_PSCS/T_PHCS

IFF setup/hold using BUFIO2 clock XC6SLX4

XC6SLX9

0.57/0.94

0.40/0.95

0.48/0.74

0.28/1.02

0.42/1.19

0.38/1.48

0.06/1.48

0.04/1.73

0.64/0.96

0.44/0.99

0.50/0.78

0.28/1.04

0.43/1.21

0.38/1.49

N/A

0.50/0.96

0.55/0.75

0.28/1.12

0.44/1.29

0.38/1.63

0.06/1.63

0.04/1.75

N/A

0.95/1.12

0.60/1.12

0.69/0.83

0.28/1.24

0.50/1.40

0.38/1.84

0.27/1.56

1.27/1.31

0.15/1.78

N/A

ns

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

0.12/1.83

N/A

XC6SLX45T

XC6SLX75

0.05/2.78

N/A

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

0.06/1.87 –0.03/2.72

0.06/1.87 N/A

0.04/1.98 –0.08/3.07

0.04/1.98

0.97/1.12

0.62/1.16

0.69/0.83

0.28/1.25

0.50/1.40

0.38/1.84

1.01/1.63

0.38/1.84

N/A

XA6SLX9

N/A

XA6SLX16

N/A

XA6SLX25

N/A

XA6SLX25T

XA6SLX45

N/A

XA6SLX45T

XA6SLX75

N/A

XA6SLX75T

XA6SLX100

XQ6SLX75

N/A

0.05/2.78

N/A

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

0.38/1.49

N/A

0.04/1.98 –0.08/3.07

0.04/1.98 N/A

0.04/1.75

N/A

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Table 81: Source-Synchronous Pin-to-Pin Setup/Hold and Clock-to-Out Using BUFIO2 (Cont’d)

Speed Grade

Symbol

Description

Device

Units

-3

-3N

-2

-1L

Pin-to-Pin Clock-to-Out Using BUFIO2

T_ICKOFCSOFF clock-to-out using BUFIO2

XC6SLX4

5.51

5.31

5.53

5.76

5.94

6.09

6.29

5.83

5.65

5.85

6.07

6.26

N/A

5.89

5.70

6.00

6.18

6.46

6.53

6.69

N/A

6.95

6.67

7.02

7.22

7.57

7.60

7.81

6.95

6.68

7.03

7.25

7.57

7.48

7.57

7.81

8.45

8.21

8.72

N/A

8.77

N/A

9.72

N/A

9.66

N/A

9.94

N/A

9.72

N/A

9.94

N/A

ns

clock

XC6SLX9

XC6SLX16

XC6SLX25

XC6SLX25T

XC6SLX45

XC6SLX45T

XC6SLX75

XC6SLX75T

XC6SLX100

XC6SLX100T

XC6SLX150

XC6SLX150T

XA6SLX4

XA6SLX9

XA6SLX16

XA6SLX25

XA6SLX25T

XA6SLX45

XA6SLX45T

XA6SLX75

XA6SLX75T

XA6SLX100

XQ6SLX75

XQ6SLX75T

XQ6SLX150

XQ6SLX150T

N/A

6.26

N/A

6.62

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Revision History

The following table shows the revision history for this document.

Date

Version

1.0

Description of Revisions

06/24/09

08/26/09

Initial Xilinx release.

Added V_FSto Table 1and Table 2. Added R_FUSEto Table 2. Added XC6SLX75 and XC6SLX75T to

_BATTand I_BATTin Table 1, Table 2, and Table 4. Corrected the quiescent supply current for the

1.1

V

XC6SLX4 in Table 5. Updated Table 11. Removed DV_PPINfrom Figure 2. Removed F_PCIECOREfrom

Table 24 and added values to F_PCIEUSER. Added more networking applications to Table 25. Updated

values for T_{SUSPENDLOW_AWAKE}, T_{SUSPEND_ENABLE}, and T_{SCP_AWAKE}in Table 46. Numerous changes

to Table 47, page 54 including the addition of new values to various specifications, revising the

T

_SMCKCSOdescription, and changing the units of T_POR. Also, removed Dynamic Reconfiguration Port

(DRP) for DCM and PLL Before and After DCLK section from Table 47 and updated all the notes. In

Table 52, added to F_INMAX, revised F_OUTMAX, and removed PLL Maximum Output Frequency for

BUFIO2. Revised values for DCM_DELAY_STEP in Table 54. Updated CLKIN_FREQ_FX values in

Table 55.

01/04/10

1.2

Added -4 speed grade to entire document. Updated speed specification of -4, -3, -2 speed grades to

version 1.03. Added -1L speed grade numbers per speed specification 1.00. Updated T_SOLin Table 1.

Added -1L rows for LVCMOS12, LVCMOS15, and LVCMOS18 in Table 9. Revised much of the detail

in GTP Transceiver Specifications in Table 12 through Table 23. Added -2 data to Table 25. Updated

F

_MAXin Table 44. Updated descriptions for T_DNACLKLand T_DNACLKHin Table 45 and revised values for

all parameters. Removed T_INITADDRfrom Table 47 and added new data. Updated values in Table 48

through Table 62. Added Table 51 (BUFPLL) and Table 57 (DCM_CLKGEN). Removed

T

_LOCKMAXnote from Table 52. Updated note 3 in Table 53. In Table 79: removed XC6SLX75CSG324

and XC6SLX75TCSG324; added XC6SLX75FG(G)484 and XC6SLX75FG(G)484.

02/22/10

1.3

Production release of XC6SLX16 -2 speed grade devices. The changes to Table 26 and Table 27

includes updating this data sheet to the data in ISE v11.5 software with speed specification v1.06.

Updated maximum of V_INand V_TSand note 2 in Table 1. In Table 2, changed V_IN, added I_INand note

5, revised notes 1, 6, and 7, and added note 8 to R_FUSE. In Table 4, removed previous note 1 and added

data to I_RPU, I_RPD, and I_BATT, changed C_IN, added R_DTand R_{IN_TERM}, and added note 2 and 3. Updated

V_CCO2in Table 6. Added Table 7 and Table 8. Removed PCI66_3 from Table 9. Updated PCI33_3 and

I2C in Table 9. Updated the description of Table 11. Completely updated Table 25. Updated Table 28

including adding values for PCI33_3. Updated V_REFvalue for HSTL_III_18 in Table 31. Updates

missing V_REFvalues in Table 32. Added Simultaneously Switching Outputs, page 36. Removed T_GSRQ

and T_RPWfrom Table 35 and Table 36. Also removed T_DOQfrom Table 36. Removed T_{ISDO_DO}and

note 1 from Table 37. Removed T_{OSCCK_S}and combinatorial section from Table 38. In Table 39,

removed T_{IODDO_T}and added new tap parameters and note 2. In Table 40, Table 41, and Table 42,

made typographical edits and removed notes. Removed clock CLK section in Table 41. Removed clock

CLK section and T_{REG_MUX}and T_{REG_M31}in Table 42. Added block RAM F_MAXvalues to Table 43.

Updated values and added note 2 to Table 45. Added values to Table 46 and removed note 1.

Numerous changes to Table 47. Completely updated Table 57. Revised data in Table 62. Removed

note 3 from Table 71. Added values to Table 79. Added data to Table 80 and Table 81.

03/10/10

1.4

Production release of XC6SLX45 -2 speed grade devices, which includes changes to Table 26 and

Table 27 updating this data sheet to the data in ISE v11.5 software with speed specification v1.07.

Fixed R_{IN_TERM}description in Table 4. Added PCI66_3 to Table 7 and replaced note 1. Corrected note

1 and the V, Max for TMDS_33 in Table 8. In Table 10, added note 1 to LVPECL_33 and TMDS_33.

Also updated specifications for TMDS_33. Updated the GTP Transceiver Specifications section

including adding values to Table 16, Table 17, and Table 20 through Table 23. Added PCI66_3 back

into Table 9, Table 28, Table 31, Table 32, and Table 34. Updated note 3 on Table 32. In Table 34,

corrected some typographical errors and fixed SSO limits for bank1/3 in FG(G)484 package. Corrected

T_{OSCKC_OCE}in Table 38. In Table 57, updated CLKFX_FREEZE_VAR and

CLKFX_FREEZE_TEMP_SLOPE and added typical values to T_{CENTER_LOW_SPREAD}and

T_{CENTER_HIGH_SPREAD}. Updated and added values to Table 63 through Table 78, and Table 81. In

Table 79, revised the XC6SLX16-CSG324 and the XC6SLX45-CSG484 and FG(G)484 values.

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Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Description of Revisions

Date

Version

06/14/10

1.5

In Table 2, added note 5 and added temperature range to V_FSand R_FUSE. Removed speed grade

delineation, revised I_RPDdescription, and updated note 2 in Table 4. Added note 2 to Table 7. Added

DIFF_MOBILE_DDR to Table 8 and Table 10. Added note 4 to Table 15. Changed minimum DV_PPINin

Table 16. Updated F_GTPDRPCLKin Table 19. Increased maximum T_LLSKEWin Table 22. Updated

descriptions and added data to Table 23. Removed note 1 and added new data to the Networking

Applications section in Table 25. Updated Table 26 and Table 27 to the data in ISE v12.1 software with

speed specification v1.08. In Table 28, added DIFF_MOBILE_DDR and updated -4 speed grade data.

Updated the maximum I/O pairs per bank in Table 33. Updated note 2 on Table 39. Revised the F_MAX

in Table 44. In Table 47, updated description for T_SMCKCSO, revised values for T_PORand added Min

value, added T_BPIICCKand T_SPIICCK. Also in Table 47, added device dependencies to F_SMCCKand

F

_RBCCK. Updated and added data to Table 63 through Table 78, and Table 81. In Table 79, added data

on the XC6SLX45-FG(G)676 and revised the XC6SLX45T and XC6SLX150T values.

The following changes to this specification are addressed in the product change notice

XCN10024, MCB Performance and JTAG Revision Code for Spartan-6 LX16 and LX45 FPGAs.

In Table 2, revised the V_CCINTto add the memory controller block extended performance

specifications. In Table 25, changed the standard specifications and added extended performance

specifications for the memory controller block and note 2. Added note 4 and updated values in

Table 34.

06/24/10

1.6

Production release of XC6SLX45T (-2 and -3 speed grades), XC6SLX16 and XC6SLX45 (-3 speed

grade) devices which includes changes to Table 26 and Table 27 (ISE v12.1 software with speed

specification v1.08).

Added the -3N speed grade, which designates Spartan-6 devices that do not support MCB

functionality. This includes changes to Table 2 (note 2), Table 25 (note 4), and Switching

Characteristics (Table 26).

Updated Simultaneously Switching Outputs discussion. Added -3 speed grade values for T_TAPand

F_MINCALvalues in Table 39. In Table 40, updated T_RPW(-2 and -3 speed grade) values and F_TOG(-3

speed grade) values. In Table 48, updated T_GIO(-2 and -3 speed grade) values. Updated -3 values in

spread spectrum section of Table 57.

07/16/10

07/26/10

1.7

1.8

Production release of specific devices listed in Table 26 and Table 27 using ISE v12.2 software with

speed specification v1.11. Added note 4 advising designers of the patch which contains v1.11. Also

updated the -1L speed specification to v1.04. Updated numerous -4 and -1L values. Added -4 T_TAP

values and F_MINCALto Table 39. Revised T_CINCK/T_CKCINin Table 40. In Table 41, revised T_SHCKO. In

Table 42, revised T_REG. Added new -1L values to Table 47. Added and updated values in Table 79.

Production release of XC6SLX25, XC6SLX25T, XC6SLX100 and XC6SLX100T in the specific speed

grades listed in Table 26 and Table 27 using ISE v12.2 software with speed specification v1.11. Added

note 7 to Table 2 and moved V_FSand R_FUSEto a new Table 3. Added I_HSand note 4 to Table 4. Added

note 1 to Table 28. Added and updated SSO limits per V_CCO/GND pairs in Table 34. Added note 3 to

Table 47. In Table 54, removed -1L specifications for CLKOUT_PER_JITT_DV1/2 and revised

CLKIN_CLKFB_PHASE and CLKOUT_PHASE_DLL values. Updated note 3 in both Table 56 and

Table 57.

08/23/10

11/05/10

1.9

Updated values for F_GTPRANGE1, F_GTPRANGE2, and F_GPLLMINin Table 18. Revised -3 and -4 values in

Table 21. Removed the -1L speed grade readback support restriction and note 3 in Table 47.

1.10

Production release of XC6SLX4 and XC6SLX9 in the specific speed grades listed in Table 26 and

Table 27 using ISE v12.3 software with speed specification v1.12 for the -2 speed grade available in

the 12.3 Speed Files Patch. Added note 3 advising designers of the patch which contains v1.12.

In Table 2, added note 4. In Table 4, added note 2. In Table 10, added notes 2 and 3. In Table 44, added

note 2. In Table 47, updated symbol for T_SMWCCK/T_SMCCKW, changed -1L values for T_USERCCLKHand

T_USERCCLKL, and added and revised the modes for F_MCCKand F_SMCCK. In Table 53, redefined and

expanded description for CLKIN_FREQ_DLL and rewrote note 3. Updated title of Table 58. Also in

Table 78, revised T_{DCD_CLK}for XC6SLX150 and XC6SLX150T. Changed description of T_PSFD/ T_PHFD

in Table 71.

For the -1L speed grade, updated data sheet to ISE 12.3 software with speed specification v1.05 which

revised the values in the following tables: Table 25, Table 28, Table 35, Table 36, Table 37, Table 40

through Table 43, Table 48 through Table 56, Table 62 through Table 78, Table 80, and Table 81.

Updated Notice of Disclaimer.

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Product Specification

87

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Description of Revisions

Date

Version

01/10/11

1.11

Production release of XC6SLX4 and XC6SLX9 in the specific speed grades listed in Table 26 and

Table 27 using ISE v12.4 software with speed specification v1.15 for the -4, -3, -3N, and -2 speed

grades. Added note 3 to Table 27. Also updated the -1L speed grade requirements to ISE v12.4

software with speed specification v1.06. Revised -3N definition throughout the document.

Added note 4 to Table 2 and updated note 5. Added information on V_CCINTto note 1 in Table 5.

Updated Networking Applications -3 values in Table 25 to match improvements made in ISE v12.4. In

Table 28, added note 1 and revised the T_IOTPvalues for LVDS_33, LVDS_25, MINI_LVDS_33,

MINI_LVDS_25, RSDS_33, RSDS_25, TMDS_33. PPDS_33, and PPDS_25. Added note 3 to

Table 55.

02/11/11

1.12

As described in XCN11008: Product Discontinuation Notice For Spartan-6 LXT -4 Devices, the -4

speed specifications have been discontinued. As outlined in page 2 of the XCN, designers currently

using -4 speed specifications should rerun timing analysis using the new -3 speed specifications before

moving to a replacement device.

Updated the networking applications section of Table 25. Updated -2 speed specifications throughout

document and added note 3 to Table 27 advising designers to use the -2 speed specification update

(v1.17) with the ISE 12.4 software patch. Added F_CLKDIVto Table 37 and Table 38. Updated note 2 in

Table 39. Updated units for T_SMCKCSOand T_BPICCOin Table 47. Updated -1L in Table 71. Removed

Note 2: Package delay information is available for these device/package combinations. This

information can be used to deskew the package from Table 79.

03/31/11

05/20/11

2.0

2.1

Production release of XC6SLX45 in the -1L speed grades listed in Table 26 and Table 27 using ISE

v13.1 software with -1L speed specification v1.06.

In Table 39, removed values in the -1L column and added note 3 as IODELAY2 only supports Tap0 for

lower-power devices. Updated copyright page 1 and Notice of Disclaimer.

Production release of XC6SLX100 and XC6SLX150 in the specific speed grades listed in Table 26 and

Table 27 using ISE v13.1 software with -1L speed specification v1.06. Updated Table 27 and Note 7

with changes per XCN11012: Speed File Change for -3N Devices. Revised Switching Characteristics

section for speed specifications: v1.18 for -3, -3N, and -2; including improvements in Table 73 through

Table 77 and Table 81.

Removed Memory Controller Block from the performance heading in Table 2 and revised Note 2. In

Table 4, added Note 1 to C_INand updated the description of R_{IN_TERM}. Updated Note 1 in Table 5.

Updated Note 1 of Table 7. In Table 25, added and removed -1L specifications, increased the standard

performance DDR3 specifications, removed the extended performance DDR3 row and updated Note 3

and Note 4. Clarified the introductory information for Table 28 and Table 30.

In Table 32: Revised V_MEASvalue for LVCMOS12; revised V_REFfor LVDS_25, LVDS_33,

BLVDS_25,MINI_LVDS_25, MINI_LVDS_33, RSDS_25, and RSDS_33; revised R_REFfor BLVDS_25

and TMDS_33; and added Note 4 and Note 5. Updated Note 2 and Note 3 in Table 39.

In Table 47, revised the values and description of T_PORincluding adding Note 3. Also in Table 47,

augmented the description and added specifications for F_RBCCKand removed XC6SLX4 from F_MCCK

(maximum frequency, parallel mode (Master SelectMAP/BPI). Added BUFGMUX to Table 48 title.

Added Table 50.

In Table 52, revised specifications for T_EXTFDVARand F_INJITTER. In Table 54 removed the 5 MHz <

CLKIN_FREQ_DLL parameter in the LOCK_DLL description. In both Table 56 and Table 57, removed

the 5 MHz < F_CLKINparameter in the LOCK_FX description. In Table 58, updated description for

PSCLK_FREQ and PSCLK_PULSE.

Revised title and symbol of Table 70, added new speed specifications for -1L, and added Note 2.

Added Table 71.

07/11/11

2.2

Added the Automotive XA Spartan-6 and Defense-grade Spartan-6Q devices to all appropriate tables

while sometimes removing the XC6S nomenclature. Added expanded temperature range (Q) to all

appropriate tables. Updated T_SOLpackages in Table 1. Added R_{OUT_TERM}to Table 4. Updated Note 2

on Table 13.

Production release of the XC6SLX4, XC6SLX9, XC6SLX16, XC6SLX25, XC6SLX75, XQ6SLX75, and

XQ6SLX150 in Table 26 and Table 27 using ISE v13.2 software with -1L speed specification v1.07.

Production release of the XA6SLX16, XA6SLX25T, XA6SLX45, XA6SLX45T, XQ6SLX75,

XQ6SLX75T, XQ6SLX150, and XQ6SLX150T in Table 26 and Table 27 using ISE v13.2 software with

-2 and -3 speed specification v1.19.

Added Table 29: IOB Switching Characteristics for the Automotive XA Spartan-6 and the Spartan-6Q

Devices(1). Updated CS(G)484 from CSG484 throughout data sheet. Clarified Note 3 in Table 39.

08/08/11

2.3

Production release of the XA6SLX25, XA6SLX75, and XA6SLX75T in Table 26 and Table 27 using ISE

v13.2 software with -2 and -3 speed specification v1.19.

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Product Specification

88

Spartan-6 FPGA Data Sheet: DC and Switching Characteristics

Description of Revisions

Date

Version

09/14/11

2.4

Production release of the XA6SLX4 and XA6SLX9 devices in Table 26 and Table 27 using ISE v13.2

software with -2 and -3 speed specification v1.19. Added production released version of the

XA6SLX100 to Table 26 and Table 27 using ISE v13.3 software with -2 speed specification v1.20.

Updated R_{OUT_TERM}description in Table 4. Fixed the LVPECL V_Herror in Table 31. Updated

introduction in Simultaneously Switching Outputs. Added the XA6SLX100 to Table 63 through

Table 78, and Table 81. Added Note 4 to Table 78 because the T_CKSKEWfor the XC6SLX100 is not the

same as the T_CKSKEWfor the XA6SLX100.

Revised the revision history for version 1.6 dated 06/24/10. Removed the parenthetical statement

about the -3N speed grade: (specifications are identical to the -3 speed grade).

10/17/11

06/27/14

3.0

3.1

Changed the data sheet from Preliminary Product Specification to Product Specification.

Updated the Switching Characteristics, page 19 speed specification version ISE v13.3 software

to -2 and -3 speed specification v1.20 and -1L speed specification of v1.08. Also updated Note 1 in

Table 27.

In Table 43, Block RAM Switching Characteristics, the F_MAXvalue for the -2 speed grade has been

changed from 260 MHz to 280 MHz.

In Table 54, Switching Characteristics for the DLL, a Note 6 was added and linked to

CLKIN_CLKFB_PHASE.

Added definition of T_SOLto Note 6 in Table 1. Added maximum current condition through ground clamp

diode to I_INin Table 2. Added (HSWAPEN = 1) to I_HSin Table 4. Replaced XPOWER with Xilinx Power

throughout. In Table 16, moved value of 1000 mV from Max to Min column and added sentence about

DV_PPOUTbeing the minimum guaranteed value at the maximum setting to Note 1. Updated

introductory paragraphs in Simultaneously Switching Outputs. Added Note 1 to Table 35. Added

Note 1 to Table 36. Corrected Note 2 in Table 39 to say “Maximum tap delay.” Added alternate symbols

to Table 45. In Table 48, updated symbols for T_GSIand T_GIOand added Note 1. Added Note 1 to

Table 49. Updated descriptions of F_INMAXin Table 52. Replaced BUFG with BUFGMUX in Note 3 of

Table 53 and Note 3 of Table 54. In Table 56, updated subheading to “Phase Alignment (Phase Error).”

In Table 57, updated Note 6 and added Note 7.

01/30/15

3.1.1

Corrected table note reference in Table 52.

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USE OF XILINX PRODUCTS IN SUCH APPLICATIONS.

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Product Specification

89


型号：	XC6SLX100-3FGG676I
厂家：	XILINX, INC
描述：	Field Programmable Gate Array, 7911 CLBs, 862MHz, 101261-Cell, CMOS, PBGA676, 27 X 27 MM, 1 MM PITCH, LEAD FREE, FBGA-676 时钟栅可编程逻辑
文件：	总89页 (文件大小：1826K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XC6SLX100-3FGG676I [XILINX]

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