XC3S5000-4FG320I_技术文档

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Spartan-3 FPGA Family:

Complete Data Sheet

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DS099 July 13, 2004

Advance Product Specification

This document includes all four modules of the Spartan™-3 FPGA data sheet.

Module 1:

Introduction and Ordering Information

Module 3:

DC and Switching Characteristics

DS099-1 (v1.2) December 24, 2003

6 pages

DS099-3 (v1.3) March 4, 2004

40 pages

•

Introduction

•

DC Electrical Characteristics

-

Absolute Maximum Ratings

Supply Voltage Specifications

Recommended Operating Conditions

DC Characteristics

Features

Architectural Overview

Product Availability

User I/O Chart

•

Switching Characteristics

Ordering Information

-

I/O Timing

Core Logic Timing

DCM Timing

Module 2:

Functional Description

DS099-2 (v1.2) July 11, 2003

40 pages

Configuration and JTAG Timing

Module 4:

Pinout Descriptions

DS099-4 (v1.5) July 13, 2004

106 pages

•

IOBs

-

IOB Overview

SelectIO™ Signal Standards

•

CLB Overview

•

Pin Descriptions

Pin Behavior During Configuration

Block RAM

Dedicated Multipliers

Digital Clock Manager (DCM)

-

•

Package Overview

Pinout Tables

-

Clock Network

-

Footprints

•

Configuration

IMPORTANT NOTE: The Spartan-3 FPGA data sheet is created and published in separate modules. This complete version

is provided for easy downloading and searching of the complete document. Page, figure, and table numbers begin at 1 for

each module, and each module has its own Revision History at the end. Use the PDF "Bookmarks" for easy navigation in

this volume.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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06

Spartan-3 FPGA Family:

Introduction and Ordering

Information

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DS099-1 (v1.2) December 24, 2003

Advance Product Specification

-

Densities as high as 74,880 logic cells

326 MHz system clock rate

Three power rails: for core (1.2V), I/Os (1.2V to

3.3V), and auxiliary purposes (2.5V)

Introduction

The Spartan™-3 family of Field-Programmable Gate Arrays

is specifically designed to meet the needs of high volume,

cost-sensitive consumer electronic applications. The

eight-member family offers densities ranging from 50,000 to

five million system gates, as shown in Table 1.

•

SelectIO™ signaling

-

Up to 784 I/O pins

622 Mb/s data transfer rate per I/O

Seventeen single-ended signal standards

Seven differential signal standards including LVDS

Termination by Digitally Controlled Impedance

Signal swing ranging from 1.14V to 3.45V

Double Data Rate (DDR) support

The Spartan-3 family builds on the success of the earlier

Spartan-IIE family by increasing the amount of logic

resources, the capacity of internal RAM, the total number of

I/Os, and the overall level of performance as well as by

improving clock management functions. Numerous

enhancements derive from state-of-the-art Virtex™-II tech-

nology. These Spartan-3 enhancements, combined with

advanced process technology, deliver more functionality

and bandwidth per dollar than was previously possible, set-

ting new standards in the programmable logic industry.

•

Logic resources

-

Abundant logic cells with shift register capability

Wide multiplexers

Fast look-ahead carry logic

Dedicated 18 x 18 multipliers

JTAG logic compatible with IEEE 1149.1/1532

specifications

Because of their exceptionally low cost, Spartan-3 FPGAs

are ideally suited to a wide range of consumer electronics

applications, including broadband access, home network-

ing, display/projection and digital television equipment.

•

SelectRAM™ hierarchical memory

-

The Spartan-3 family is a superior alternative to mask pro-

grammed ASICs. FPGAs avoid the high initial cost, the

lengthy development cycles, and the inherent inflexibility of

conventional ASICs. Also, FPGA programmability permits

design upgrades in the field with no hardware replacement

necessary, an impossibility with ASICs.

Up to 1,872 Kbits of total block RAM

Up to 520 Kbits of total distributed RAM

Digital Clock Manager (up to four DCMs)

-

Clock skew elimination

Frequency synthesis

High resolution phase shifting

•

Eight global clock lines and abundant routing

Fully supported by Xilinx ISE development system

Features

•

Revolutionary 90-nanometer process technology

-

Synthesis, mapping, placement and routing

•

Very low cost, high-performance logic solution for

high-volume, consumer-oriented applications

•

MicroBlaze processor, PCI, and other cores

Table 1: Summary of Spartan-3 FPGA Attributes

CLB Array

(One CLB = Four Slices)

Maximum

Maximum Differential

System

Gates

Logic

Cells

Distributed BlockRAM

Dedicated

Multipliers

1

Device

XC3S50

Rows Columns Total CLBs RAM (bits )

(bits )

DCMs

User I/O

I/O Pairs

50K

200K

400K

1M

1,728

4,320

16

24

32

48

64

80

96

104

12

20

28

40

52

64

72

80

192

480

12K

30K

72K

216K

288K

432K

576K

720K

1,728K

1,872K

4

12

16

24

32

40

96

104

2

4

124

56

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

Notes:

173

76

8,064

896

56K

264

116

175

221

270

312

344

17,280

29,952

46,080

62,208

74,880

1,920

3,328

5,120

6,912

8,320

120K

208K

320K

432K

520K

391

1.5M

2M

487

565

4M

712

5M

784

1. By convention, one Kb is equivalent to 1,024 bits.

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Spartan-3 FPGA Family: Introduction and Ordering Information

Architectural Overview

The Spartan-3 family architecture consists of five funda-

mental programmable functional elements:

•

Multiplier blocks accept two 18-bit binary numbers as

inputs and calculate the product.

Digital Clock Manager (DCM) blocks provide

self-calibrating, fully digital solutions for distributing,

delaying, multiplying, dividing, and phase shifting clock

signals.

•

Configurable Logic Blocks (CLBs) contain RAM-based

Look-Up Tables (LUTs) to implement logic and storage

elements that can be used as flip-flops or latches.

CLBs can be programmed to perform a wide variety of

logical functions as well as to store data.

These elements are organized as shown in Figure 1. A ring

of IOBs surrounds a regular array of CLBs. The XC3S50

has a single column of block RAM embedded in the array.

Those devices ranging from the XC3S200 to the XC3S2000

have two columns of block RAM. The XC3S4000 and

XC3S5000 devices have four RAM columns. Each column

is made up of several 18K-bit RAM blocks; each block is

associated with a dedicated multiplier. The DCMs are posi-

tioned at the ends of the outer block RAM columns.

•

Input/Output Blocks (IOBs) control the flow of data

between the I/O pins and the internal logic of the

device. Each IOB supports bidirectional data flow plus

3-state operation. Twenty-four different signal

standards,

including

seven

high-performance

differential standards, are available as shown in

Table 2. Double Data-Rate (DDR) registers are

included. The Digitally Controlled Impedance (DCI)

feature provides automatic on-chip terminations,

simplifying board designs.

The Spartan-3 family features a rich network of traces and

switches that interconnect all five functional elements,

transmitting signals among them. Each functional element

has an associated switch matrix that permits multiple con-

nections to the routing.

•

Block RAM provides data storage in the form of 18-Kbit

dual-port blocks.

DS099-1_01_032703

Notes:

1. The two additional block RAM columns of the XC3S4000 and XC3S5000

devices are shown with dashed lines. The XC3S50 has only the block RAM

column on the far left.

Figure 1: Spartan-3 Family Architecture

2

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Spartan-3 FPGA Family: Introduction and Ordering Information

which includes the XCF00S PROMs for serial configuration

and the higher density XCF00P PROMs for parallel or serial

configuration.

Configuration

Spartan-3 FPGAs are programmed by loading configuration

data into robust static memory cells that collectively control

all functional elements and routing resources. Before pow-

ering on the FPGA, configuration data is stored externally in

a PROM or some other nonvolatile medium either on or off

the board. After applying power, the configuration data is

written to the FPGA using any of five different modes: Mas-

ter Parallel, Slave Parallel, Master Serial, Slave Serial and

Boundary Scan (JTAG). The Master and Slave Parallel

modes use an 8-bit wide SelectMAP™ port.

I/O Capabilities

The SelectIO feature of Spartan-3 devices supports 17 sin-

gle-ended standards and seven differential standards as

listed in Table 2. Many standards support the DCI feature,

which uses integrated terminations to eliminate unwanted

signal reflections. Table 3 shows the number of user I/Os as

well as the number of differential I/O pairs available for each

device/package combination.

The recommended memory for storing the configuration

data is the low-cost Xilinx Platform Flash PROM family,

Table 2: Signal Standards Supported by the Spartan-3 Family

Standard

Category

V_CCO

(V)

DCI

Option

Description

Gunning Transceiver Logic

High-Speed Transceiver Logic

Class

Symbol

Single-Ended

GTL

N/A

1.5

1.8

Terminated

GTL

Yes

No

Plus

GTLP

HSTL

I

III

HSTL_I

HSTL_III

HSTL_I_18

HSTL_II_18

HSTL_III_18

LVCMOS12

LVCMOS15

LVCMOS18

LVCMOS25

LVCMOS33

LVTTL

I

II

III

LVCMOS

Low-Voltage CMOS

1.2

1.5

1.8

2.5

3.3

3.0

1.8

2.5

N/A

33 MHz

N/A

I

Yes

No

LVTTL

PCI

Low-Voltage Transistor-Transistor Logic

Peripheral Component Interconnect

Stub Series Terminated Logic

PCI33_3

No

SSTL

SSTL18_I

SSTL2_I

Yes

II

SSTL2_II

Differential

LDT

Lightning Data Transport

(HyperTransport™)

2.5

N/A

LDT_25

No

LVDS

Low-Voltage Differential Signaling

Standard

Bus

LVDS_25

Yes

No

Yes

No

BLVDS_25

LVDSEXT_25

ULVDS_25

LVPECL_25

Extended Mode

Ultra

LVPECL

RSDS

Low-Voltage Positive Emitter-Coupled

Logic

2.5

N/A

Reduced-Swing Differential Signaling

N/A

RSDS_25

No

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Spartan-3 FPGA Family: Introduction and Ordering Information

Table 3: Spartan-3 I/O Chart

Available User I/Os and Differential (Diff) I/O Pairs

PQ208 FT256 FG320 FG456 FG676

User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff User Diff

VQ100

TQ144

FG900

FG1156

Device

XC3S50

63

-

29

-

97

-

46

-

124

56

62

-

76

-

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

Notes:

141

173

141

173

221 100 264 116

-

173

221 100 333 149 391 175

221 100 333 149 487 221

-

489 221 565 270

-

633 300 712 312

633 300 784 344

-

1. All device options listed in a given package column are pin-compatible.

Product Ordering and Availability

Table 4 shows all valid device ordering combinations of

device density, speed grade, package, and temperature

range parameters for the Spartan-3 family as well as the

availability status of those combinations.

Table 4: Spartan-3 Device Availability

Package Type⁽¹⁾

:

VQFP

TQFP

PQFP

FTBGA

FBGA

FG676

Code: VQ100

TQ144

PQ208

FT256

FG320

FG456

FG900

FG1156

Device

XC3S50

(C, I)

-

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

Notes:

(C, I)

-

(C, I)

-

(C, I)

-

(C, I)

-

(C, I)

-

(C, I)

-

1. Package types are explained in Ordering Information, page 5.

2. Commercial devices are offered in the -4 and -5 speed grades; industrial devices are only in the -4 speed grade.

3. C = Commercial, T_J= 0° to +85°C; I = Industrial, T_J= –40°C to +100°C.

4. Parentheses indicate that a given device is not yet released to production. Contact your local sales office for availability information.

4

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Spartan-3 FPGA Family: Introduction and Ordering Information

Ordering Information

Example:

XC3S50 -4 PQ208 C

Device Type

Temperature Range

Package Type / Number of Pins

Speed Grade

Device

XC3S50

Speed Grade

Package Type / Number of Pins

Temperature Range (T_J)

-4 Standard Performance VQ100 100-pin Very Thin Quad Flat Pack (VQFP)

C Commercial (0°C to 85°C)

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

-5 High Performance

TQ144 144-pin Thin Quad Flat Pack (TQFP)

I

Industrial (–40°C to 100°C)

PQ208 208-pin Plastic Quad Flat Pack (PQFP)

FT256 256-ball Fine-Pitch Thin Ball Grid Array (FTBGA)

FG320 320-ball Fine-Pitch Ball Grid Array (FBGA)

FG456 456-ball Fine-Pitch Ball Grid Array (FBGA)

FG676 676-ball Fine-Pitch Ball Grid Array (FBGA)

FG900 900-ball Fine-Pitch Ball Grid Array (FBGA)

FG1156 1156-ball Fine-Pitch Ball Grid Array (FBGA)

Package Marking

R

SPARTAN

Device Type

XC3S50^TM

PQ208xxx0350

xxxxxxxxx

4C

Date Code

Lot Code

Package

Speed Grade

Operating Range

ds099-1_02_122403

Revision History

Date

Version No.

Description

04/11/03

04/24/03

12/24/03

1.0

1.1

1.2

Initial Xilinx release.

Updated block RAM, DCM, and multiplier counts for the XC3S50.

Added the FG320 package.

The Spartan-3 Family Data Sheet

DS099-1, Spartan-3 FPGA Family: Introduction and Ordering Information (Module 1)

DS099-2, Spartan-3 FPGA Family: Functional Description (Module 2)

DS099-3, Spartan-3 FPGA Family: DC and Switching Characteristics (Module 3)

DS099-4, Spartan-3 FPGA Family: Pinout Descriptions (Module 4)

DS099-1 (v1.2) December 24, 2003

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Spartan-3 1.2V FPGA Family:

Functional Description

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DS099-2 (v1.2) July 11, 2003

Advance Product Specification

IOBs

the FPGA’s internal logic through a multiplexer to the

output driver. In addition to this direct path, the

multiplexer provides the option to insert a pair of

storage elements.

IOB Overview

The Input/Output Block (IOB) provides a programmable,

bidirectional interface between an I/O pin and the FPGA’s

internal logic.

•

All signal paths entering the IOB, including those

associated with the storage elements, have an inverter

option. Any inverter placed on these paths is

automatically absorbed into the IOB.

A simplified diagram of the IOB’s internal structure appears

in Figure 1. There are three main signal paths within the

IOB: the output path, input path, and 3-state path. Each

path has its own pair of storage elements that can act as

either registers or latches. For more information, see the

Storage Element Functions section. The three main signal

paths are as follows:

Storage Element Functions

There are three pairs of storage elements in each IOB, one

pair for each of the three paths. It is possible to configure

each of these storage elements as an edge-triggered

D-type flip-flop (FD) or a level-sensitive latch (LD).

•

The input path carries data from the pad, which is

bonded to a package pin, through an optional

programmable delay element directly to the I line. After

the delay element, there are alternate routes through a

pair of storage elements to the IQ1 and IQ2 lines. The

IOB outputs I, IQ1, and IQ2 all lead to the FPGA’s

internal logic. The delay element can be set to ensure a

hold time of zero.

The storage-element-pair on either the Output path or the

Three-State path can be used together with a special multi-

plexer to produce Double-Data-Rate (DDR) transmission.

This is accomplished by taking data synchronized to the

clock signal’s rising edge and converting them to bits syn-

chronized on both the rising and the falling edge. The com-

bination of two registers and a multiplexer is referred to as a

Double-Data-Rate D-type flip-flop (FDDR).

•

The output path, starting with the O1 and O2 lines,

carries data from the FPGA’s internal logic through a

multiplexer and then a three-state driver to the IOB

pad. In addition to this direct path, the multiplexer

provides the option to insert a pair of storage elements.

See Double-Data-Rate Transmission, page 3 for more

information.

The 3-state path determines when the output driver is

high impedance. The T1 and T2 lines carry data from

The signal paths associated with the storage element are

described in Table 1.

Table 1: Storage Element Signal Description

Storage

Element

Signal

Description

Data input

Function

D

Data at this input is stored on the active edge of CK enabled by CE. For latch operation when the

input is enabled, data passes directly to the output Q.

Q

Data output

The data on this output reflects the state of the storage element. For operation as a latch in

transparent mode, Q will mirror the data at D.

CK

CE

SR

Clock input

A signal’s active edge on this input with CE asserted, loads data into the storage element.

When asserted, this input enables CK. If not connected, CE defaults to the asserted state.

Clock Enable input

Set/Reset

Forces storage element into the state specified by the SRHIGH/SRLOW attributes. The

SYNC/ASYNC attribute setting determines if the SR input is synchronized to the clock or not.

REV

Reverse

Used together with SR. Forces storage element into the state opposite from what SR does.

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Spartan-3 1.2V FPGA Family: Functional Description

T

TFF1

T1

D

Q

CE

CK

SR

REV

Q

DDR

MUX

TCE

T2

D

TFF2

CE

CK

SR

REV

Three-state Path

V

CCO

OFF1

O1

D

Q

CE

CK

Weak

ESD

OTCLK1

Pull-Up

SR

REV

Q

DDR

MUX

I/O

OCE

O2

Weak

Pull-

Down

Program-

mable

Output

Driver

D

DCI

OFF2

CE

OTCLK2

CK

SR

REV

Weak

Keeper

Latch

Output Path

LVCMOS, LVTTL, PCI

Single-ended Standards

IQ1

I

Fixed

Delay

D

Q

IFF1

using V

REF

CE

CK

V

REF

ICLK1

ICE

SR

REV

Q

Differential Standards

IQ2

I/O Pin

from

D

Adjacent

IOB

IFF2

CE

CK

ICLK2

SR

REV

SR

REV

Input Path

Note: All IOB signals communicating with the FPGA's internal logic have the option of inverting polarity.

DS099_01_040703

Figure 1: Simplified IOB Diagram

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Spartan-3 1.2V FPGA Family: Functional Description

According to Figure 1, the clock line OTCLK1 connects the

CK inputs of the upper registers on the output and

three-state paths. Similarly, OTCLK2 connects the CK

inputs for the lower registers on the output and three-state

paths. The upper and lower registers on the input path have

independent clock lines: ICLK1 and ICLK2.

path and ICE does the same for the register pair on the

input path.

The Set/Reset (SR) line entering the IOB is common to all

six registers, as is the Reverse (REV) line.

Each storage element supports numerous options in addi-

tion to the control over signal polarity described in the IOB

Overview section. These are described in Table 2.

The enable line OCE connects the CE inputs of the upper

and lower registers on the output path. Similarly, TCE con-

nects the CE inputs for the register pair on the three-state

Table 2: Storage Element Options

Option Switch

Function

Specificity

FF/Latch

Chooses between an edge-sensitive flip-flop or Independent for each storage element.

a level-sensitive latch

SYNC/ASYNC

Determines whether SR is synchronous or

asynchronous

Independent for each storage element.

SRHIGH/SRLOW Determines whether SR acts as a Set, which

forces the storage element to a logic “1"

Independent for each storage element, except

when using FDDR. In the latter case, the selection

(SRHIGH) or a Reset, which forces a logic “0” for the upper element (OFF1 or TFF2) will apply to

(SRLOW).

both elements.

INIT1/INIT0

In the event of a Global Set/Reset, after

Independent for each storage element, except

configuration or upon activation of the GTS net, when using FDDR. In the latter case, selecting

this switch decides whether to set or reset a INIT0 for one element applies to both elements

storage element. By default, choosing SRLOW (even though INIT1 is selected for the other).

also selects INIT0; choosing SRHIGH also

selects INIT1.

The storage-element-pair on the Three-State path (TFF1

Double-Data-Rate Transmission

and TFF2) can also be combined with a local multiplexer to

form an FDDR primitive. This permits synchronizing the out-

put enable to both the rising and falling edges of a clock.

This DDR operation is realized in the same way as for the

output path.

Double-Data-Rate (DDR) transmission describes the tech-

nique of synchronizing signals to both the rising and falling

edges of the clock signal. Spartan-3 devices use regis-

ter-pairs in all three IOB paths to perform DDR operations.

The pair of storage elements on the IOB’s Output path

(OFF1 and OFF2), used as registers, combine with a spe-

cial multiplexer to form a DDR D-type flip-flop (FDDR). This

primitive permits DDR transmission where output data bits

are synchronized to both the rising and falling edges of a

clock. It is possible to access this function by placing either

an FDDRRSE or an FDDRCPE component or symbol into

the design. DDR operation requires two clock signals (50%

duty cycle), one the inverted form of the other. These sig-

nals trigger the two registers in alternating fashion, as

shown in Figure 2. Commonly, the Digital Clock Manager

(DCM) generates the two clock signals by mirroring an

incoming signal, then shifting it 180 degrees. This approach

ensures minimal skew between the two signals.

The storage-element-pair on the input path (IFF1 and IFF2)

allows an I/O to receive a DDR signal. An incoming DDR

clock signal triggers one register and the inverted clock sig-

nal triggers the other register. In this way, the registers take

turns capturing bits of the incoming DDR data signal.

Aside from high bandwidth data transfers, DDR can also be

used to reproduce, or “mirror”, a clock signal on the output.

This approach is used to transmit clock and data signals

together. A similar approach is used to reproduce a clock

signal at multiple outputs. The advantage for both

approaches is that skew across the outputs will be minimal.

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Spartan-3 1.2V FPGA Family: Functional Description

clamp diodes are always connected to the pad, regardless

of the signal standard selected. The presence of diodes lim-

its the ability of Spartan-3 I/Os to tolerate high signal volt-

ages. The V_INabsolute maximum rating in Table 1 in

Module 3: DC and Switching Characteristics specifies the

voltage range that I/Os can tolerate.

DCM

180˚ 0˚

FDDR

D1

Slew Rate Control and Drive Strength

Q1

Two options, FAST and SLOW, control the output slew rate.

The FAST option supports output switching at a high rate.

The SLOW option reduces bus transients. These options are

only available when using one of the LVCMOS or LVTTL

standards, which also provide up to seven different levels of

current drive strength: 2, 4, 6, 8, 12, 16, and 24 mA. Choos-

ing the appropriate drive strength level is yet another means

to minimize bus transients.

CLK1

DDR MUX

Q

D2

Table 3 shows the drive strengths that the LVCMOS and

LVTTL standards support. The Fast option is indicated by

appending an "F" attribute after the output buffer symbol

OBUF or the bidirectional buffer symbol IOBUF. The Slow

option appends an "S" attribute. The drive strength in milliam-

peres follows the slew rate attribute. For example,

OBUF_LVCMOS18_S_6 or IOBUF_LVCMOS25_F_16.

Q2

CLK2

DS099-2_02_070303

Figure 2: Clocking the DDR Register

Table 3: Programmable Output Drive Current

Current Drive (mA)

Signal

Pull-Up and Pull-Down Resistors

Standard

LVCMOS12

LVCMOS15

LVCMOS18

LVCMOS25

LVCMOS33

LVTTL

2

4

6

8

12

16

-

24

-

The optional pull-up and pull-down resistors are intended to

establish High and Low levels, respectively, at unused I/Os.

The weak pull-up resistor optionally connects each IOB pad

to V_CCO. A weak pull-down resistor optionally connects

each pad to GND. These resistors are placed in a design

using the PULLUP and PULLDOWN symbols in a sche-

matic, respectively. They can also be instantiated as com-

ponents, set as constraints or passed as attributes in HDL

code. These resistors can also be selected for all unused

I/O using the Bitstream Generator (BitGen) option Unused-

Pin. A Low logic level on HSWAP_EN activates the pull-up

resistors on all I/Os during configuration.

3

-

3

-

3

-

3

Boundary-Scan Capability

All Spartan-3 IOBs support boundary-scan testing compat-

ible with IEEE 1149.1 standards. See Boundary-Scan

(JTAG) Mode, page 36 for more information.

Weak-Keeper Circuit

SelectIO Signal Standards

Each I/O has an optional weak-keeper circuit that retains

the last logic level on a line after all drivers have been turned

off. This is useful to keep bus lines from floating when all

connected drivers are in a high-impedance state. This func-

tion is placed in a design using the KEEPER symbol.

Pull-up and pull-down resistors override the weak-keeper

circuit.

The IOBs support 17 different single-ended signal stan-

dards, as listed in Table 4. Furthermore, the majority of

IOBs can be used in specific pairs supporting any of six dif-

ferential signal standards, as shown in Table 5. The desired

standard is selected by placing the appropriate I/O library

symbol or component into the FPGA design. For example,

the symbol named IOBUF_LVCMOS15_F_8 represents a

bidirectional I/O to which the 1.5V LVCMOS signal standard

has been assigned. The slew rate and current drive are set

to Fast and 8 mA, respectively.

ESD Protection

Clamp diodes protect all device pads against damage from

Electro-Static Discharge (ESD) as well as excessive voltage

transients. Each I/O has two clamp diodes: One diode

extends P-to-N from the pad to V_CCOand a second diode

extends N-to-P from the pad to GND. During operation,

these diodes are normally biased in the off state. These

Together with placing the appropriate I/O symbol, two exter-

nally applied voltage levels, V_CCOand V_REFselect the

desired signal standard. The V_CCOlines provide current to

the output driver. The voltage on these lines determines the

4

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Spartan-3 1.2V FPGA Family: Functional Description

output voltage swing for all standards except GTL and

GTLP.

Table 4: Single-Ended I/O Standards (Values in Volts)

V_CCO

Board

All single-ended standards except the LVCMOS modes

require a Reference Voltage (V_REF) to bias the input-switch-

ing threshold. Once a configuration data file is loaded into

the FPGA that calls for the I/Os of a given bank to use such

a signal standard, a few specifically reserved I/O pins on the

same bank automatically convert to V_REFinputs. When

using one of the LVCMOS standards, these pins remain

I/Os because the V_CCOvoltage biases the input-switching

threshold, so there is no need for V_REF. Select the V_CCOand

V_REFlevels to suit the desired single-ended standard

according to Table 4.

Signal

Standard

For

V_REFfor

Termination

Outputs Inputs Inputs⁽¹⁾Voltage(V_TT

)

PCI33_3

SSTL18_I

SSTL2_I

SSTL2_II

Notes:

3.0

1.8

2.5

3.0

-

0.9

1.25

1. Banks 4 and 5 of any Spartan-3 device in a VQ100 package

do not support signal standards using V_REF

.

2. The V_CCOlevel used for the GTL and GTLP standards must

be no lower than the termination voltage (V_TT), nor can it be

lower than the voltage at the I/O pad.

Differential standards employ a pair of signals, one the

opposite polarity of the other. The noise canceling (e.g.,

Common-Mode Rejection) properties of these standards

permit exceptionally high data transfer rates. This section

introduces the differential signaling capabilities of Spartan-3

devices.

3. See Table 6 for a listing of the single-ended DCI standards.

Table 5: Differential I/O Standards

V_CCO(Volts)

For For

Outputs Inputs

V_OD⁽¹⁾(mV)

V_REFfor

Inputs

(Volts)

Signal

Standard

Min.

430

250

330

430

100

Max.

670

400

450

700

670

400

Each device-package combination designates specific I/O

pairs that are specially optimized to support differential

standards. A unique “L-number”, part of the pin name, iden-

tifies the line-pairs associated with each bank (see Module

4: Pinout Descriptions). For each pair, the letters “P” and

“N” designate the true and inverted lines, respectively. For

example, the pin names IO_L43P_7 and IO_L43N_7 indi-

cate the true and inverted lines comprising the line pair L43

on Bank 7. The differential Output Voltage (V_OD) parameter

measures the voltage difference the High and Low logic lev-

els that a pair of differential outputs drive. The V_ODrange for

each of the differential standards is listed in Table 5. The

V_CCOlines provide current to the outputs. The V_REFlines

are not used. Select the V_CCOlevel to suit the desired differ-

ential standard according to Table 5.

LDT_25

2.5

-

LVDS_25

BLVDS_25

LVDSEXT_25

ULVDS_25

RSDS_25

Notes:

1. Measured with a termination resistor value (RT) of 100

Ohms.

2. See Table 6 for a listing of the differential DCI standards.

The need to supply V_REFand V_CCOimposes constraints on

which standards can be used in the same bank. See The

Organization of IOBs into Banks section for additional

guidelines concerning the use of the V_CCOand V_REFlines.

Table 4: Single-Ended I/O Standards (Values in Volts)

V_CCO

Board

Termination

Digitally Controlled Impedance (DCI)

Signal

Standard

For

V_REFfor

When the round-trip delay of an output signal — i.e., from

output to input and back again — exceeds rise and fall

times, it is common practice to add termination resistors to

the line carrying the signal. These resistors effectively

match the impedance of a device’s I/O to the characteristic

impedance of the transmission line, thereby preventing

reflections that adversely affect signal integrity. However,

with the high I/O counts supported by modern devices, add-

ing resistors requires significantly more components and

board area. Furthermore, for some packages — e.g., ball

grid arrays — it may not always be possible to place resis-

tors close to pins.

Outputs Inputs Inputs⁽¹⁾Voltage (V_TT

)

GTL

Note 2

1.5

Note 2

0.8

1.2

1.5

0.75

1.5

0.9

1.8

-

GTLP

Note 2

1

HSTL_I

-

0.75

HSTL_III

1.5

-

0.9

HSTL_I_18

HSTL_II_18

HSTL_III_18

LVCMOS12

LVCMOS15

LVCMOS18

LVCMOS25

LVCMOS33

LVTTL

1.8

-

0.9

1.8

-

0.9

1.8

-

1.1

1.2

1.5

1.8

2.5

3.3

-

1.5

-

DCI answers these concerns by providing two kinds of

on-chip terminations: Parallel terminations make use of an

integrated resistor network. Series terminations result from

controlling the impedance of output drivers. DCI actively

adjusts both parallel and series terminations to accurately

1.8

-

2.5

-

3.3

-

3.3

-

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Spartan-3 1.2V FPGA Family: Functional Description

match the characteristic impedance of the transmission line.

This adjustment process compensates for differences in I/O

impedance that can result from normal variation in the

ambient temperature, the supply voltage and the manufac-

turing process. When the output driver turns off, the series

termination, by definition, approaches a very high imped-

ance; in contrast, parallel termination resistors remain at the

targeted values.

DCI is available only for certain I/O standards, as listed in

Table 6. DCI is selected by applying the appropriate I/O

standard extensions to symbols or components. There are

five basic ways to configure terminations, as shown in

Table 7. The DCI I/O standard determines which of these

terminations is put into effect.

Table 6: DCI I/O Standards

V

_CCO(V)

Termination Type

Category of Signal

Standard

For

Outputs

For

Inputs

V_REFfor

Inputs (V)

Signal Standard

At Output

At Input

Single-Ended

Gunning

Transceiver Logic

GTL_DCI

1.2

1.5

1.8

1.5

1.8

2.5

3.3

1.5

1.8

2.5

3.3

1.8

2.5

1.2

1.5

1.8

1.5

1.8

2.5

3.3

1.5

1.8

2.5

3.3

1.8

2.5

0.8

1.0

0.75

0.9

1.1

-

Single

GTLP_DCI

High-Speed

Transceiver Logic

HSTL_I_DCI

None

Split

Single

Split

HSTL_III_DCI

HSTL_I_DCI_18

HSTL_II_DCI_18

HSTL_III_DCI_18

None

Single

None

Low-Voltage CMOS LVDCI_15

LVDCI_18

Controlled impedance

driver

-

LVDCI_25

-

LVDCI_33

-

LVDCI_DV2_15

-

Controlled driver with

half-impedance

LVDCI_DV2_18

LVDCI_DV2_25

LVDCI_DV2_33

SSTL18_I_DCI

SSTL2_I_DCI

SSTL2_II_DCI

-

Stub Series

Terminated Logic

0.9

1.25

25-Ohm driver

Split

Split with 25-Ohm driver

Differential

Low-Voltage

Differential

Signalling

LVDS_25_DCI

2.5

-

None

Split on

each line

of pair

LVDSEXT_25_DCI

Notes:

1. Bank 5 of any Spartan-3 device in a VQ100 or TQ144 package does not support DCI signal standards.

6

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Spartan-3 1.2V FPGA Family: Functional Description

Table 7: DCI Terminations

Termination

Schematic⁽¹⁾

I/O Standards

LVDCI_15

Controlled impedance output driver

IOB

LVDCI_18

LVDCI_25

LVDCI_33

R

Z

0

Controlled output driver with half impedance

LVDCI_DV2_15

LVDCI_DV2_18

LVDCI_DV2_25

LVDCI_DV2_33

IOB

R/2

Z

0

Single resistor

GTL_DCI

V

CCO

IOB

GTLP_DCI

HSTL_III_DCI⁽²⁾

HSTL_III_DCI_18⁽²⁾

R

Z

0

Split resistors

HSTL_I_DCI⁽²⁾

V

CCO

IOB

HSTL_I_DCI_18⁽²⁾

HSTL_II_DCI_18

LVDS_25_DCI

2R

Z

0

LVDSEXT_25_DCI

2R

Split resistors with output driver impedance

fixed to 25Ω

SSTL18_I_DCI⁽³⁾

SSTL2_I_DCI⁽³⁾

SSTL2_II_DCI

V

CCO

IOB

25Ω

2R

Z

0

Notes:

1. The value of R is equivalent to the characteristic impedance of the line connected to the I/O. It is also equal to half the value of R_REF

for the DV2 standards and R_REFfor all other DCI standards.

2. For DCI using HSTL Classes I and III, terminations only go into effect at inputs (not at outputs).

3. For DCI using SSTL Class I, the split termination only goes into effect at inputs (not at outputs).

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Spartan-3 1.2V FPGA Family: Functional Description

The DCI feature operates independently for each of the

device’s eight banks. Each bank has an "N" reference pin

(VRN) and a "P" reference pin, (VRP), to calibrate driver

and termination resistance. Only when using a DCI stan-

dard on a given bank do these two pins function as VRN

and VRP. When not using a DCI standard, the two pins func-

tion as user I/Os. As shown in Figure 3, add an external ref-

erence resistor to pull the VRN pin up to V_CCOand another

reference resistor to pull the VRP pin down to GND. Both

resistors have the same value — commonly 50 Ohms —

with one-percent tolerance, which is either the characteristic

impedance of the line or twice that, depending on the DCI

standard in use. Standards having a symbol name that con-

tains the letters “DV2” use a reference resistor value that is

twice the line impedance. DCI adjusts the output driver

impedance to match the reference resistors’ value or half

that, according to the standard. DCI always adjusts the

on-chip termination resistors to directly match the reference

resistors’ value.

Spartan-3 devices in these packages support eight inde-

pendent V_CCOsupplies.

Bank 0

Bank 1

Bank 5

Bank 4

DS099-2_03_060102

Figure 4: Spartan-3 I/O Banks (top view)

In contrast, the 144-pin Thin Quad Flat Pack (TQ144) pack-

age ties V^CCOtogether internally for the pair of banks on

each side of the device. For example, the V^CCOBank 0 and

the V_CCOBank 1 lines are tied together. The interconnected

bank-pairs are 0/1, 2/3, 4/5, and 6/7. As a result, Spartan-3

devices in the TQ144 package support four independent

One of eight

I/O Banks

V

CCO

R

(1%)

REF

VRN

VRP

V

_CCOsupplies.

R

REF

Spartan-3 Compatibility

Within the Spartan-3 family, all devices are pin-compatible

by package. When the need for future logic resources out-

grows the capacity of the Spartan-3 device in current use, a

larger device in the same package can serve as a direct

replacement. Larger devices may add extra V_REFand V_CCO

lines to support a greater number of I/Os. In the larger

device, more pins can convert from user I/Os to V_REFlines.

Also, additional V_CCOlines are bonded out to pins that were

“not connected” in the smaller device. Thus, it is important

to plan for future upgrades at the time of the board’s initial

design by laying out connections to the extra pins.

DS099-2_04_091602

Figure 3: Connection of Reference Resistors (R_REF

)

The rules guiding the use of DCI standards on banks are as

follows:

1. No more than one DCI I/O standard with a Single

Termination is allowed per bank.

2. No more than one DCI I/O standard with a Split

Termination is allowed per bank.

3. Single Termination, Split Termination, Controlled-

Impedance Driver, and Controlled-Impedance Driver

with Half Impedance can co-exist in the same bank.

The Spartan-3 family is not pin-compatible with any previ-

ous Xilinx FPGA family.

See also The Organization of IOBs into Banks, page 8.

Rules Concerning Banks

When assigning I/Os to banks, it is important to follow the

following V_CCOrules:

The Organization of IOBs into Banks

IOBs are allocated among eight banks, so that each side of

the device has two banks, as shown in Figure 4. For all

packages, each bank has independent V_REFlines. For

example, V_REFBank 3 lines are separate from the V_REF

lines going to all other banks.

1. Leave no V_CCOpins unconnected on the FPGA.

2. Set all V_CCOlines associated with the (interconnected)

bank to the same voltage level.

3. The V_CCOlevels used by all standards assigned to the

I/Os of the (interconnected) bank(s) must agree. The

Xilinx development software checks for this. Tables 4, 5,

and 6 describe how different standards use the V_CCO

supply.

For the Very Thin Quad Flat Pack (VQ), Plastic Quad Flat

Pack (PQ), Fine Pitch Thin Ball Grid Array (FT), and Fine

Pitch Ball Grid Array (FG) packages, each bank has dedi-

cated V_CCOlines. For example, the V_CCOBank 7 lines are

separate from the V_CCOlines going to all other banks. Thus,

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Spartan-3 1.2V FPGA Family: Functional Description

4. If none of the standards assigned to the I/Os of the

(interconnected) bank(s) use V_CCO, tie all associated

The I/Os During Power-On, Configuration, and

User Mode

V_CCOlines to 2.5V.

With no power applied to the FPGA, all I/Os are in a

high-impedance state. The V_CCINT(1.2V), V_CCAUX(2.5V),

and V_CCOsupplies may be applied in any order. Before

power-on can finish, V_CCINT, V_CCOBank 4, and V_CCAUX

must have reached their respective minimum recom-

mended operating levels (see Table 2 in Module 3: DC and

Switching Characteristics). At this time, all I/O drivers

also will be in a high-impedance state. V_CCOBank 4,

5. In general, apply 2.5V to V_CCOBank 4 from power-on to

the end of configuration. Apply the same voltage to

V_CCOBank 5 during parallel configuration or a

Readback operation. For information on how to

program the FPGA using 3.3V signals and power, see

the 3.3V-Tolerant Configuration Interface section.

If any of the standards assigned to the Inputs of the bank

use V_REF, then observe the following additional rules:

V

_CCINT, and V_CCAUXserve as inputs to the internal

Power-On Reset circuit (POR).

1. Leave no V_REFpins unconnected on any bank.

A Low level applied to HSWAP_EN input enables weak

pull-up resistors on User I/Os from power-on throughout

configuration. A High level on HSWAP_EN disables the

pull-up resistors, allowing the I/Os to float. As soon as

power is applied, the FPGA begins initializing its configura-

tion memory. At the same time, the FPGA internally asserts

the Global Set-Reset (GSR), which asynchronously resets

all IOB storage elements to a Low state.

2. Set all V_REFlines associated with the bank to the same

voltage level.

3. The V_REFlevels used by all standards assigned to the

Inputs of the bank must agree. The Xilinx development

software checks for this. Tables 4 and 6 describe how

different standards use the V_REFsupply.

If none of the standards assigned to the Inputs of a bank

use V_REFfor biasing input switching thresholds, all associ-

ated V_REFpins function as User I/Os.

Upon the completion of initialization, INIT_B goes High,

sampling the M0, M1, and M2 inputs to determine the con-

figuration mode. At this point, the configuration data is

loaded into the FPGA. The I/O drivers remain in a

high-impedance state (with or without pull-up resistors, as

determined by the HSWAP_EN input) throughout configura-

tion.

Exceptions to Banks Supporting I/O

Standards

Bank 5 of any Spartan-3 device in a VQ100 or TQ144 pack-

age does not support DCI signal standards. In this case,

bank 5 has neither VRN nor VRP pins.

The Global Three State (GTS) net is released during

Start-Up, marking the end of configuration and the begin-

ning of design operation in the User mode. At this point,

those I/Os to which signals have been assigned go active

while all unused I/Os remain in a high-impedance state. The

release of the GSR net, also part of Start-up, leaves the IOB

registers in a Low state by default, unless the loaded design

reverses the polarity of their respective RS inputs.

Furthermore, banks 4 and 5 of any Spartan-3 device in a

VQ100 package do not support signal standards using

V_REF(see Table 4). In this case, the two banks do not have

any V_REFpins.

Supply Voltages for the IOBs

Three different supplies power the IOBs:

In User mode, all weak, internal pull-up resistors on the I/Os

are disabled and HSWAP_EN becomes a “don’t care” input.

If it is desirable to have weak pull-up or pull-down resistors

on I/Os carrying signals, the appropriate symbol — e.g.,

PULLUP, PULLDOWN — must be placed at the appropriate

pads in the design. The Bitstream Generator (Bitgen) option

UnusedPin available in the Xilinx development software

determines whether unused I/Os collectively have pull-up

resistors, pull-down resistors, or no resistors in User mode.

1. The V_CCOsupplies, one for each of the FPGA’s I/O

banks, power the output drivers, except when using the

GTL and GTLP signal standards. The voltage on the

V

_CCOpins determines the voltage swing of the output

signal.

_CCINTis the main power supply for the FPGA’s internal

logic.

2.

V

3. The V_CCAUXis an auxiliary source of power, primarily to

optimize the performance of various FPGA functions

such as I/O switching.

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Spartan-3 1.2V FPGA Family: Functional Description

.

Left-Hand SLICEM

(Logic or Distributed RAM

or Shift Register)

Right-Hand SLICEL

(Logic Only)

COUT

CLB

SLICE

X1Y1

SLICE

X1Y0

COUT

Switch

Interconnect

to Neighbors

Matrix

SLICE

X0Y1

CIN

SHIFTOUT

SHIFTIN

SLICE

X0Y0

CIN

DS099-2_05_040703

Figure 5: Arrangement of Slices within the CLB

ROM functions. Besides these, the left-hand pair supports

two additional functions: storing data using Distributed RAM

and shifting data with 16-bit registers. Figure 6 is a diagram

of the left-hand slice; therefore, it represents a superset of

the elements and connections to be found in all slices. See

Function Generator, page 12 for more information.

CLB Overview

The Configurable Logic Blocks (CLBs) constitute the main

logic resource for implementing synchronous as well as

combinatorial circuits. Each CLB comprises four intercon-

nected slices, as shown in Figure 5. These slices are

grouped in pairs. Each pair is organized as a column with an

independent carry chain.

The RAM-based function generator — also known as a

Look-Up Table or LUT — is the main resource for imple-

menting logic functions. Furthermore, the LUTs in each

left-hand slice pair can be configured as Distributed RAM or

a 16-bit shift register. For information on the former, see

XAPP464: Using Look-Up Tables as Distributed RAM in

Spartan-3 FPGAs; for information on the latter, refer to

XAPP465: Using Look-Up Tables as Shift Registers (SRL16)

in Spartan-3 FPGAs. The function generators located in the

upper and lower portions of the slice are referred to as the

"G" and "F", respectively.

The nomenclature that the FPGA Editor — part of the Xilinx

development software — uses to designate slices is as fol-

lows: The letter "X" followed by a number identifies columns

of slices. The "X" number counts up in sequence from the

left side of the die to the right. The letter "Y" followed by a

number identifies the position of each slice in a pair as well

as indicating the CLB row. The "Y" number counts slices

starting from the bottom of the die according to the

sequence: 0, 1, 0, 1 (the first CLB row); 2, 3, 2, 3 (the sec-

ond CLB row); etc. Figure 5 shows the CLB located in the

lower left-hand corner of the die. Slices X0Y0 and X0Y1

make up the column-pair on the left where as slices X1Y0

and X1Y1 make up the column-pair on the right. For each

CLB, the term “left-hand” (or SLICEM) is used to indicated

the pair of slices labeled with an even "X" number, such as

X0, and the term “right-hand” (or SLICEL) designates the

pair of slices with an odd "X" number, e.g., X1.

The storage element, which is programmable as either a

D-type flip-flop or a level-sensitive latch, provides a means

for synchronizing data to a clock signal, among other uses.

The storage elements in the upper and lower portions of the

slice are called FFY and FFX, respectively.

Wide-function multiplexers effectively combine LUTs in

order to permit more complex logic operations. Each slice

has two of these multiplexers with F5MUX in the lower por-

tion of the slice and FXMUX in the upper portion. Depend-

ing on the slice, FXMUX takes on the name F6MUX,

F7MUX, or F8MUX. For more details on the multiplexers,

see XAPP466: Using Dedicated Multiplexers in Spartan-3

FPGAs.

Elements Within a Slice

All four slices have the following elements in common: two

logic function generators, two storage elements, wide-func-

tion multiplexers, carry logic, and arithmetic gates, as

shown in Figure 6. Both the left-hand and right-hand slice

pairs use these elements to provide logic, arithmetic, and

10

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Spartan-3 1.2V FPGA Family: Functional Description

Notes:

1. Options to invert signal polarity as well as other options that enable lines for various functions are not shown.

2. The index i can be 6, 7, or 8, depending on the slice. In this position, the upper right-hand slice has an F8MUX,

and the upper left-hand slice has an F7MUX. The lower right-hand and left-hand slices both have an F6MUX.

Figure 6: Simplified Diagram of the Left-Hand SLICEM

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Spartan-3 1.2V FPGA Family: Functional Description

The carry chain, together with various dedicated arithmetic

logic gates, support fast and efficient implementations of

math operations. The carry chain enters the slice as CIN

and exits as COUT. Five multiplexers control the chain:

CYINIT, CY0F, and CYMUXF in the lower portion as well as

CY0G and CYMUXG in the upper portion. The dedicated

arithmetic logic includes the exclusive-OR gates XORF and

XORG (upper and lower portions of the slice, respectively)

as well as the AND gates GAND and FAND (upper and

lower portions, respectively).

5. Drives the DI input of the LUT. See Distributed RAM

section.

6. BY can control the REV inputs of both the FFY and FFX

storage elements. See Storage Element Section.

7. Finally, the DIG_MUX multiplexer can switch BY onto to

the DIG line, which exits the slice.

Other slice signals shown in Figure 6, page 11 are dis-

cussed in the sections that follow.

Function Generator

Main Logic Paths

Each of the two LUTs (F and G) in a slice have four logic

inputs (A1-A4) and a single output (D). This permits any

four-variable Boolean logic operation to be programmed

into them. Furthermore, wide function multiplexers can be

used to effectively combine LUTs within the same CLB or

across different CLBs, making logic functions with still more

input variables possible.

Central to the operation of each slice are two nearly identi-

cal data paths, distinguished using the terms top and bot-

tom. The description that follows uses names associated

with the bottom path. (The top path names appear in paren-

theses.) The basic path originates at an interconnect-switch

matrix outside the CLB. Four lines, F1 through F4 (or G1

through G4 on the upper path), enter the slice and connect

directly to the LUT. Once inside the slice, the lower 4-bit

path passes through a function generator "F" (or "G") that

performs logic operations. The function generator’s Data

output, "D", offers five possible paths:

The LUTs in both the right-hand and left-hand slice-pairs

not only support the logic functions described above, but

also can function as ROM that is initialized with data at the

time of configuration.

The LUTs in the left-hand slice-pair (even-numbered col-

umns such as X0 in Figure 5) of each CLB support two

additional functions that the right-hand slice-pair (odd-num-

bered columns such as X1) do not.

1. Exit the slice via line "X" (or "Y") and return to

interconnect.

2. Inside the slice, "X" (or "Y") serves as an input to the

DXMUX (DYMUX) which feeds the data input, "D", of

the FFY (FFX) storage element. The "Q" output of the

storage element drives the line XQ (or YQ) which exits

the slice.

First, it is possible to program the “left-hand LUTs” as dis-

tributed RAM. This type of memory affords moderate

amounts of data buffering anywhere along a data path. One

left-hand LUT stores 16 bits. Multiple left-hand LUTs can be

combined in various ways to store larger amounts of data. A

dual port option combines two LUTs so that memory access

is possible from two independent data lines. A Distributed

ROM option permits pre-loading the memory with data dur-

ing FPGA configuration For more information, see the Dis-

tributed RAM section.

3. Control the CYMUXF (or CYMUXG) multiplexer on the

carry chain.

4. With the carry chain, serve as an input to the XORF (or

XORG) exclusive-OR gate that performs arithmetic

operations, producing a result on "X" (or "Y").

5. Drive the multiplexer F5MUX to implement logic

functions wider than four bits. The "D" outputs of both

the F-LUT and G-LUT serve as data inputs to this

multiplexer.

Second, it is possible to program each left-hand LUT as a

16-bit shift register. Used in this way, each LUT can delay

serial data anywhere from one to 16 clock cycles. The four

left-hand LUTs of a single CLB can be combined to produce

delays up to 64 clock cycles. The SHIFTIN and SHIFTOUT

lines cascade LUTs to form larger shift registers. It is also

possible to combine shift registers across more than one

CLB. The resulting programmable delays can be used to

balance the timing of data pipelines.

In addition to the main logic paths described above, there

are two bypass paths that enter the slice as BX and BY.

Once inside the FPGA, BX in the bottom half of the slice (or

BY in the top half) can take any of several possible

branches:

1. Bypass both the LUT and the storage element, then exit

the slice as BXOUT (or BYOUT) and return to

interconnect.

Block RAM Overview

All Spartan-3 devices support block RAM, which is orga-

nized as configurable, synchronous 18Kbit blocks. Block

RAM stores relatively large amounts of data more efficiently

than the distributed RAM feature described earlier. (The lat-

ter is better suited for buffering small amounts of data any-

where along signal paths.) This section describes basic

Block RAM functions. For more information, see XAPP463:

Using Block RAM in Spartan-3 FPGAs.

2. Bypass the LUT, then pass through a storage element

via the D input before exiting as XQ (or YQ).

3. Control the wide function multiplexer F5MUX (or

F6MUX).

4. Via multiplexers, serve as an input to the carry chain.

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Spartan-3 1.2V FPGA Family: Functional Description

The aspect ratio — i.e., width vs. depth — of each block

RAM is configurable. Furthermore, multiple blocks can be

cascaded to create still wider and/or deeper memories.

The Internal Structure of the Block RAM

The block RAM has a dual port structure. The two identical

data ports called A and B permit independent access to the

common RAM block, which has a maximum capacity of

18,432 bits — or 16,384 bits when no parity lines are used.

Each port has its own dedicated set of data, control and

clock lines for synchronous read and write operations.

There are four basic data paths, as shown in Figure 7: (1)

write to and read from Port A, (2) write to and read from Port

B, (3) data transfer from Port A to Port B, and (4) data trans-

fer from Port B to Port A.

A choice among primitives determines whether the block

RAM functions as dual- or single-port memory. A name of

the form RAM16_S[w_A]_S[w_B] calls out the dual-port primi-

tive, where the integers w_Aand w_Bspecify the total data

path width at ports w_Aand w_B, respectively. Thus, a

RAM16_S9_S18 is a dual-port RAM with a 9-bit-wide Port A

and an 18-bit-wide Port B. A name of the form RAM16_S[w]

identifies the single-port primitive, where the integer w

specifies the total data path width of the lone port. A

RAM16_S18 is a single-port RAM with an 18-bit-wide port.

Other memory functions — e.g., FIFOs, data path width

conversion, ROM, etc. — are readily available using the

CORE Generator™ system, part of the Xilinx development

software.

3

Write

Read

Write

4

Spartan-3

Dual Port

Block RAM

Arrangement of RAM Blocks on Die

Write

The XC3S50 has one column of block RAM. The Spartan-3

devices ranging from the XC3S200 to XC3S2000 have two

columns of block RAM. The XC3S4000 and XC3S5000

have four columns. The position of the columns on the die is

shown in Figure 1 in Module 1: Introduction and Ordering

Information. For a given device, the total available RAM

blocks are distributed equally among the columns. Table 8

shows the number of RAM blocks, the data storage capac-

ity, and the number of columns for each device.

2

1

Read

DS099-2_12_030703

Figure 7: Block RAM Data Paths

Block RAM Port Signal Definitions

Representations

of

the

dual-port

primitive

RAM16_S[w_A]_S[w_B] and the single-port primitive

RAM16_S[w] with their associated signals are shown in

Figure 8a and Figure 8b, respectively. These signals are

defined in Table 9.

Table 8: Number of RAM Blocks by Device

Total

Number

of

Columns

Total Number

of RAM Blocks

Addressable

Locations (bits)

Device

XC3S50

4

12

16

24

32

40

96

104

73,728

221,184

294,912

442,368

589,824

737,280

1,769,472

1,916,928

1

2

4

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

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Spartan-3 1.2V FPGA Family: Functional Description

RAM16_w_A_w_B

WEA

ENA

SSRA

DOPA[p_A1:0]

DOA[w_A1:0]

CLKA

ADDRA[r_A1:0]

DIA[w_A1:0]

DIPA[3:0]

RAM16_Sw

WEB

ENB

WE

EN

SSRB

SSR

DOPB[p_B1:0]

DOB[w_B1:0]

DOP[p 1:0]

DO[w 1:0]

CLKB

CLK

ADDRB[r_B1:0]

DIB[w_B1:0]

DIPB[3:0]

ADDR[r 1:0]

DI[w 1:0]

DIP[p 1:0]

(a) Dual-Port

(b) Single-Port

DS099-2_13_091302

Notes:

1. w_Aand w_Bare integers representing the total data path width (i.e., data bits plus parity bits) at ports A and B, respectively.

2. p_Aand p_Bare integers that indicate the number of data path lines serving as parity bits.

3. r_Aand r_Bare integers representing the address bus width at ports A and B, respectively.

4. The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.

Figure 8: Block RAM Primitives

Table 9: Block RAM Port Signals

Port A

Signal

Name

Port B

Signal

Name

Signal

Description

Direction

Function

ADDRA

ADDRB

Input

Address Bus

The Address Bus selects a memory location for read or write

operations. The width (w) of the port’s associated data path

determines the number of available address lines (r).

DIA

DIB

Input

Data Input Bus

Data at the DI input bus is written to the addressed memory

location addressed on an enabled active CLK edge.

It is possible to configure a port’s total data path width (w) to be

1, 2, 4, 9, 18, or 36 bits. This selection applies to both the DI and

DO paths of a given port. Each port is independent. For a port

assigned a width (w), the number of addressable locations will

be 16,384/(w-p) where "p" is the number of parity bits. Each

memory location will have a width of "w" (including parity bits).

See the DIP signal description for more information of parity.

DIPA

DIPB

Input

Parity Data

Input(s)

Parity inputs represent additional bits included in the data input

path to support error detection. The number of parity bits "p"

included in the DI (same as for the DO bus) depends on a port’s

total data path width (w). See Table 10.

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Spartan-3 1.2V FPGA Family: Functional Description

Table 9: Block RAM Port Signals (Continued)

Port A

Signal

Name

Port B

Signal

Name

Signal

Description

Direction

Function

DOA

DOB

Output

Data Output

Bus

Basic data access occurs whenever WE is inactive. The DO

outputs mirror the data stored in the addressed memory

location.

Data access with WE asserted is also possible if one of the

following two attributes is chosen: WRITE_FIRST accesses

data before the write takes place. READ_FIRST accesses data

after the write occurs.

A third attribute, NO_CHANGE, latches the DO outputs upon

the assertion of WE.

It is possible to configure a port’s total data path width (w) to be

1, 2, 4, 9, 18, or 36 bits. This selection applies to both the DI and

DO paths. See the DI signal description.

DOPA

WEA

DOPB

WEB

Output

Input

Parity Data

Output(s)

Parity inputs represent additional bits included in the data input

path to support error detection. The number of parity bits "p"

included in the DI (same as for the DO bus) depends on a port’s

total data path width (w). See Table 10.

Write Enable

When asserted together with EN, this input enables the writing

of data to the RAM. In this case, the data access attributes

WRITE_FIRST, READ_FIRST or NO_CHANGE determines if

and how data is updated on the DO outputs. See the DO signal

description.

When WE is inactive with EN asserted, read operations are still

possible. In this case, a transparent latch passes data from the

addressed memory location to the DO outputs.

ENA

ENB

Input

Clock Enable

When asserted, this input enables the CLK signal to

synchronize Block RAM functions as follows: the writing of data

to the DI inputs (when WE is also asserted), the updating of data

at the DO outputs as well as the setting/resetting of the DO

output latches.

When de-asserted, the above functions are disabled.

SSRA

CLKA

SSRB

CLKB

Input

Set/Reset

Clock

When asserted, this pin forces the DO output latch to the value

that the SRVAL attribute is set to. A Set/Reset operation on one

port has no effect on the other ports functioning, nor does it

disturb the memory’s data contents. It is synchronized to the

CLK signal.

This input accepts the clock signal to which read and write

operations are synchronized. All associated port inputs are

required to meet setup times with respect to the clock signal’s

active edge. The data output bus responds after a clock-to-out

delay referenced to the clock signal’s active edge.

Block RAM automatically performs a bus-matching function.

When data are written to a port with a narrow bus, then read

from a port with a wide bus, the latter port will effectively

combine “narrow” words to form “wide” words. Similarly,

when data are written into a port with a wide bus, then read

from a port with a narrow bus, the latter port will divide

Port Aspect Ratios

On a given port, it is possible to select a number of different

possible widths (w – p) for the DI/DO buses as shown in

Table 10. These two buses always have the same width.

This data bus width selection is independent for each port. If

the data bus width of Port A differs from that of Port B, the

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Spartan-3 1.2V FPGA Family: Functional Description

“wide” words to form “narrow” words. When the data bus

width is eight bits or greater, extra parity bits become avail-

able. The width of the total data path (w) is the sum of the

DI/DO bus width and any parity bits (p).

n = 2^r

(2)

The product of w and n yields the total block RAM capacity.

Equations (1) and (2) show that as the data bus width

increases, the number of address lines along with the num-

ber of addressable memory locations decreases. Using the

permissible DI/DO bus widths as inputs to these equations

provides the bus width and memory capacity measures

shown in Table 10.

The width selection made for the DI/DO bus determines the

number of address lines according to the relationship

expressed below:

r = 14 – [log(w–p)/log(2)]

(1)

In turn, the number of address lines delimits the total num-

ber (n) of addressable locations or depth according to the

following equation:

Table 10: Port Aspect Ratios for Port A or B

No. of

Addressable

Locations (n)

Block RAM

Capacity

(bits)

DI/DO Bus Width

(w – p bits)

DIP/DOP

Bus Width (p bits)

Total Data Path

Width (w bits)

ADDR Bus

Width (r bits)

1

2

0

1

2

4

1

2

14

13

12

11

10

9

16,384

8,192

4,096

2,048

1,024

512

16,384

18,432

4

8

9

16

32

18

36

condition, data stored in the memory location addressed by

the ADDR lines passes through a transparent output latch

to the DO outputs. The timing for basic data access is

shown in the portions of Figure 9, Figure 10, and Figure 11

during which WE is Low.

Block RAM Data Operations

Writing data to and accessing data from the block RAM are

synchronous operations that take place independently on

each of the two ports.

The waveforms for the write operation are shown in the top

half of the Figure 9, Figure 10, and Figure 11. When the WE

and EN signals enable the active edge of CLK, data at the

DI input bus is written to the block RAM location addressed

by the ADDR lines.

Data can also be accessed on the DO outputs when assert-

ing the WE input. This is accomplished using two different

attributes:

Choosing the WRITE_FIRST attribute, data is written to the

addressed memory location on an enabled active CLK edge

and is also passed to the DO outputs. WRITE_FIRST timing

is shown in the portion of Figure 9 during which WE is High.

There are a number of different conditions under which data

can be accessed at the DO outputs. Basic data access

always occurs when the WE input is inactive. Under this

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Spartan-3 1.2V FPGA Family: Functional Description

CLK

WE

DI

XXXX

aa

1111

bb

2222

cc

XXXX

ADDR

DO

dd

0000

MEM(aa)

1111

2222

MEM(dd)

EN

DISABLED

READ

WRITE

MEM(bb)=1111

WRITE

MEM(cc)=2222

READ

DS099-2_14_030403

Figure 9: Waveforms of Block RAM Data Operations with WRITE_FIRST Selected

Choosing the READ_FIRST attribute, data already stored in

the addressed location pass to the DO outputs before that

location is over-written with new data from the DI inputs on

an enabled active CLK edge. READ_FIRST timing is shown

in the portion of Figure 10 during which WE is High.

CLK

WE

XXXX

aa

1111

2222

cc

XXXX

DI

ADDR

DO

bb

dd

0000

MEM(aa)

old MEM(bb)

old MEM(cc)

MEM(dd)

EN

DISABLED

READ

WRITE

MEM(bb)=1111

WRITE

MEM(cc)=2222

READ

DS099-2_15_030403

Figure 10: Waveforms of Block RAM Data Operations with READ_FIRST Selected

Choosing a third attribute called NO_CHANGE puts the DO

outputs in a latched state when asserting WE. Under this

condition, the DO outputs will retain the data driven just

before WE was asserted. NO_CHANGE timing is shown in

the portion of Figure 11 during which WE is High.

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Spartan-3 1.2V FPGA Family: Functional Description

CLK

WE

XXXX

1111

bb

2222

cc

XXXX

DI

ADDR

DO

aa

dd

0000

MEM(aa)

MEM(dd)

EN

DISABLED

READ

WRITE

MEM(bb)=1111

WRITE

MEM(cc)=2222

READ

DS099-2_16_030403

Figure 11: Waveforms of Block RAM Data Operations with NO_CHANGE Selected

data handling. Cascading multipliers permits multiplicands

more than three in number as well as wider than 18-bits.

The multiplier is placed in a design using one of two primi-

tives: an asynchronous version called MULT18X18 and a

version with a register at the outputs called MULT18X18S,

as shown in Figure 12a and Figure 12b, respectively. The

signals for these primitives are defined in Table 11.

Dedicated Multipliers

All Spartan-3 devices provide embedded multipliers that

accept two 18-bit words as inputs to produce a 36-bit prod-

uct. This section provides an introduction to multipliers. For

further details, see XAPP467: Using Embedded Multipliers

in Spartan-3 FPGAs.

The input buses to the multiplier accept data in two’s-com-

plement form (either 18-bit signed or 17-bit unsigned). One

such multiplier is matched to each block RAM on the die.

The close physical proximity of the two ensures efficient

The CORE Generator system produces multipliers based

on these primitives that can be configured to suit a wide

range of requirements.

MULT18X18S

A[17:0]

B[17:0]

CLK

P[35:0]

MULT18X18

A[17:0]

B[17:0]

P[35:0]

CE

RST

(a) Asynchronous 18-bit Multiplier

(b) 18-bit Multiplier with Register at Outputs

DS099-2_17_091302

Figure 12: Embedded Multiplier Primitives

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Spartan-3 1.2V FPGA Family: Functional Description

Table 11: Embedded Multiplier Primitives Descriptions

Signal

Name

Direction

Function

A[17:0]

Input

Apply one 18-bit multiplicand to these inputs. The MULT18X18S primitive requires a setup time

before the enabled rising edge of CLK.

B[17:0]

P[35:0]

CLK

Input

Output

Input

Apply the other 18-bit multiplicand to these inputs. The MULT18X18S primitive requires a setup

time before the enabled rising edge of CLK.

The output on the P bus is a 36-bit product of the multiplicands A and B. In the case of the

MULT18X18S primitive, an enabled rising CLK edge updates the P bus.

CLK is only an input to the MULT18X18S primitive. The clock signal applied to this input when

enabled by CE, updates the output register that drives the P bus.

CE

Input

CE is only an input to the MULT18X18S primitive. Enable for the CLK signal. Asserting this input

enables the CLK signal to update the P bus.

RST

Input

RST is only an input to the MULT18X18S primitive. Asserting this input resets the output register

on an enabled, rising CLK edge, forcing the P bus to all zeroes.

Notes:

1. The control signals CLK, CE and RST have the option of inverted polarity.

Digital Clock Manager (DCM)

Spartan-3 devices provide flexible, complete control over

clock frequency, phase shift and skew through the use of

the DCM feature. To accomplish this, the DCM employs a

Delay-Locked Loop (DLL), a fully digital control system that

uses feedback to maintain clock signal characteristics with a

high degree of precision despite normal variations in oper-

ating temperature and voltage. This section provides a fun-

damental description of the DCM. For further information,

see XAPP462: Using Digital Clock Managers (DCMs) in

Spartan-3 FPGAs.

clock signal to arrive at different points on the die at

different times. This clock skew can increase set-up

and hold time requirements as well as clock-to-out

time, which may be undesirable in applications

operating at a high frequency, when timing is critical.

The DCM eliminates clock skew by aligning the output

clock signal it generates with another version of the

clock signal that is fed back. As a result, the two clock

signals establish a zero-phase relationship. This

effectively cancels out clock distribution delays that

may lie in the signal path leading from the clock output

of the DCM to its feedback input.

Frequency Synthesis: Provided with an input clock

signal, the DCM can generate a wide range of different

output clock frequencies. This is accomplished by

either multiplying and/or dividing the frequency of the

input clock signal by any of several different factors.

Each member of the Spartan-3 family has four DCMs,

except the smallest, the XC3S50, which has two DCMs.

The DCMs are located at the ends of the outermost Block

RAM column(s). See Figure 1 in Module 1: Introduction

and Ordering Information. The Digital Clock Manager is

placed in a design as the “DCM” primitive.

•

The DCM supports three major functions:

Phase Shifting: The DCM provides the ability to shift

the phase of all its output clock signals with respect to

its input clock signal.

•

Clock-skew Elimination: Clock skew describes the

extent to which clock signals may, under normal

circumstances, deviate from zero-phase alignment. It

occurs when slight differences in path delays cause the

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Spartan-3 1.2V FPGA Family: Functional Description

DCM

PSINCDEC

Phase

Shifter

PSEN

PSCLK

PSDONE

CLK0

Clock

Distribution

Delay

CLKIN

CLKFB

CLK90

CLK180

CLK270

CLK2X

CLK2X180

CLKDV

CLKFX

DFS

CLKFX180

DLL

LOCKED

Status

Logic

RST

8

STATUS [7:0]

DS099-2_07_040103

Figure 13: DCM Functional Blocks and Associated Signals

The DCM has four functional components: the

Delay-Locked Loop (DLL), the Digital Frequency Synthe-

sizer (DFS), the Phase Shifter (PS), and the Status Logic.

Each component has its associated signals, as shown in

Figure 13.

Delay-Locked Loop (DLL)

The most basic function of the DLL component is to elimi-

nate clock skew. The main signal path of the DLL consists of

an input stage, followed by a series of discrete delay ele-

ments or taps, which in turn leads to an output stage. This

path together with logic for phase detection and control

forms a system complete with feedback as shown in

Figure 14.

CLK0

CLK90

CLK180

CLK270

CLK2X

Delay

1

Delay

2

Delay

n-1

Delay

n

CLKIN

CLK2X180

CLKDV

Control

LOCKED

Phase

Detection

CLKFB

RST

DS099-2_08_041103

Figure 14: Simplified Functional Diagram of DLL

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Spartan-3 1.2V FPGA Family: Functional Description

The DLL component has two clock inputs, CLKIN and

CLKFB, as well as seven clock outputs, CLK0, CLK90,

CLK180, CLK270, CLK2X, CLK2X180, and CLKDV as

described in Table 12. The clock outputs drive simulta-

neously; however, the High Frequency mode only supports

a subset of the outputs available in the Low Frequency

mode. See DLL Frequency Modes, page 23. Signals that

initialize and report the state of the DLL are discussed in

The Status Logic Component, page 28.

Table 12: DLL Signals

Mode Support

Low

High

Signal

CLKIN

Direction

Input

Description

Accepts original clock signal.

Frequency Frequency

Yes

CLKFB

Input

Accepts either CLK0 or CLK2X as feed back signal. (Set

CLK_FEEDBACK attribute accordingly).

CLK0

Output

Generates clock signal with same frequency and phase as CLKIN.

Yes

No

CLK90

Generates clock signal with same frequency as CLKIN, only

phase-shifted 90°.

CLK180

CLK270

CLK2X

Output

Generates clock signal with same frequency as CLKIN, only

phase-shifted 180°.

Yes

No

Yes

Generates clock signal with same frequency as CLKIN, only

phase-shifted 270°.

Generates clock signal with same phase as CLKIN, only twice the

frequency.

CLK2X180

CLKDV

Generates clock signal with twice the frequency of CLKIN,

phase-shifted 180° with respect to CLKIN.

Divides the CLKIN frequency by CLKDV_DIVIDE value to generate

lower frequency clock signal that is phase-aligned to CLKIN.

The clock signal supplied to the CLKIN input serves as a

reference waveform, with which the DLL seeks to align the

feedback signal at the CLKFB input. When eliminating clock

skew, the common approach to using the DLL is as follows:

The CLK0 signal is passed through the clock distribution

network to all the registers it synchronizes. These registers

are either internal or external to the FPGA. After passing

through the clock distribution network, the clock signal

returns to the DLL via a feedback line called CLKFB. The

control block inside the DLL measures the phase error

between CLKFB and CLKIN. This phase error is a measure

of the clock skew that the clock distribution network intro-

duces. The control block activates the appropriate number

of delay elements to cancel out the clock skew. Once the

DLL has brought the CLK0 signal in phase with the CLKIN

signal, it asserts the LOCKED output, indicating a “lock” on

to the CLKIN signal.

DLL Attributes and Related Functions

A number of different functional options can be set for the

DLL component through the use of the attributes described

in Table 13. Each attribute is described in detail in the sec-

tions that follow:

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Spartan-3 1.2V FPGA Family: Functional Description

Table 13: DLL Attributes

Attribute

Description

Values

NONE, 1X, 2X

CLK_FEEDBACK

Chooses either the CLK0 or CLK2X output to drive the

CLKFB input

DLL_FREQUENCY_MODE

CLKIN_DIVIDE_BY_2

CLKDV_DIVIDE

Chooses between High Frequency and Low

Frequency modes

LOW, HIGH

Halves the frequency of the CLKIN signal just as it

enters the DCM

TRUE, FALSE

Selects constant used to divide the CLKIN input

frequency to generate the CLKDV output frequency

1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5,

6.0, 6.5, 7.0, 7.5, 8, 9, 10, 11,

12, 13, 14, 15, and 16.

DUTY_CYCLE_CORRECTION

Enables 50% duty cycle correction for the CLK0,

CLK90, CLK180, and CLK270 outputs

TRUE, FALSE

The feedback loop is essential for DLL operation and is

established by driving the CLKFB input with either the CLK0

or the CLK2X signal so that any undesirable clock distribu-

tion delay is included in the loop. It is possible to use either

of these two signals for synchronizing any of the seven DLL

outputs: CLK0, CLK90, CLK180, CLK270, CLKDV, CLK2X,

or CLK2X180. The value assigned to the CLK_FEEDBACK

attribute must agree with the physical feedback connection:

a value of 1X for the CLK0 case, 2X for the CLK2X case. If

the DCM is used in an application that does not require the

DLL — i.e., only the DFS is used — then there is no feed-

back loop so CLK_FEEDBACK is set to NONE.

DLL Clock Input Connections

An external clock source enters the FPGA using a Global

Clock Input Buffer (IBUFG), which directly accesses the glo-

bal clock network or an Input Buffer (IBUF). Clock signals

within the FPGA drive a global clock net using a Global

Clock Multiplexer Buffer (BUFGMUX). The global clock net

connects directly to the CLKIN input. The internal and exter-

nal connections are shown in Figure 15a and Figure 15c,

respectively. A differential clock (e.g., LVDS) can serve as

an input to CLKIN.

DLL Clock Output and Feedback Connections

As many as four of the nine DCM clock outputs can simulta-

neously drive the four BUFGMUX buffers on the same die

edge (top or bottom). All DCM clock outputs can simulta-

neously drive general routing resources, including intercon-

nect leading to OBUF buffers.

There are two basic cases that determine how to connect

the DLL clock outputs and feedback connections: on-chip

synchronization and off-chip synchronization, which are

illustrated in Figure 15a through Figure 15d.

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Spartan-3 1.2V FPGA Family: Functional Description

FPGA

BUFGMUX

CLK0

CLK90

CLK180

CLK270

CLKDV

CLK90

CLK180

CLK270

CLKDV

CLK2X

CLK2X180

BUFG

CLKIN

Clock

Net Delay

Clock

Net Delay

DCM

CLK2X180

CLK2X

CLKFB

CLK0

BUFGMUX

CLK0

CLK2X

(a) On-Chip with CLK0 Feedback

FPGA

(b) On-Chip with CLK2X Feedback

FPGA

OBUFG

CLK0

CLK90

CLK180

CLK270

CLKDV

CLK90

CLK180

CLK270

CLKDV

CLK2X

CLK2X180

OBUFG

IBUFG

CLKIN

Clock

Net Delay

Clock

Net Delay

DCM

CLK2X180

CLKFB

CLK0

CLKFB

CLK2X

OBUFG

IBUFG

OBUFG

CLK0

CLK2X

(c) Off-Chip with CLK0 Feedback

(d) Off-Chip with CLK2X Feedback

DS099-2_09_071003

Notes:

1. In the Low Frequency mode, all seven DLL outputs are available. In the High Frequency mode, only the CLK0, CLK180,

and CLKDV outputs are available.

Figure 15: Input Clock, Output Clock, and Feedback Connections for the DLL

In the on-chip synchronization case (Figure 15a and

Figure 15b), it is possible to connect any of the DLL’s seven

output clock signals through general routing resources to

the FPGA’s internal registers. Either a Global Clock Buffer

(BUFG) or a BUFGMUX affords access to the global clock

network. As shown in Figure 15a, the feedback loop is cre-

ated by routing CLK0 (or CLK2X, in Figure 15b) to a global

clock net, which in turn drives the CLKFB input.

attribute chooses between the two modes. When the

attribute is set to LOW, the Low Frequency mode permits all

seven DLL clock outputs to operate over a low-to-moderate

frequency range. When the attribute is set to HIGH, the High

Frequency mode allows the CLK0, CLK180 and CLKDV out-

puts to operate at the highest possible frequencies. The

remaining DLL clock outputs are not available for use in High

Frequency mode.

In the off-chip synchronization case (Figure 15c and

Figure 15d), CLK0 (or CLK2X) plus any of the DLL’s other

output clock signals exit the FPGA using output buffers

(OBUF) to drive an external clock network plus registers on

the board. As shown in Figure 15c, the feedback loop is

formed by feeding CLK0 (or CLK2X, in Figure 15d) back

into the FPGA using an IBUFG, which directly accesses the

global clock network, or an IBUF. Then, the global clock net

is connected directly to the CLKFB input.

Accommodating High Input Frequencies

If the frequency of the CLKIN signal is high such that it

exceeds the maximum permitted, divide it down to an

acceptable value using the CLKIN_DIVIDE_BY_2 attribute.

When this attribute is set to TRUE, the CLKIN frequency is

divided by a factor of two just as it enters the DCM.

Coarse Phase Shift Outputs of the DLL Compo-

nent

DLL Frequency Modes

In addition to CLK0 for zero-phase alignment to the CLKIN

signal, the DLL also provides the CLK90, CLK180 and

CLK270 outputs for 90°, 180° and 270° phase-shifted sig-

nals, respectively. These signals are described in Table 12.

The DLL supports two distinct operating modes, High Fre-

quency and Low Frequency, with each specified over a differ-

ent clock frequency range. The DLL_FREQUENCY_MODE

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Spartan-3 1.2V FPGA Family: Functional Description

Their relative timing in the Low Frequency Mode is shown in

Figure 16. The CLK90, CLK180 and CLK270 outputs are

not available when operating in the High Frequency mode.

(See the description of the DLL_FREQUENCY_MODE

attribute in Table 13.) For control in finer increments than

90°, see the Phase Shifter (PS), page 26 section.

0^o90^o180^o270^o0^o90^o180^o270^o0^o

Phase:

Input Signal (30% Duty Cycle)

t

CLKIN

Basic Frequency Synthesis Outputs of the DLL

Component

The DLL component provides basic options for frequency

multiplication and division in addition to the more flexible

synthesis capability of the DFS component, described in a

later section. These operations result in output clock signals

with frequencies that are either a fraction (for division) or a

multiple (for multiplication) of the incoming clock frequency.

The CLK2X output produces an in-phase signal that is twice

the frequency of CLKIN. The CLK2X180 output also dou-

bles the frequency, but is 180° out-of-phase with respect to

CLKIN. The CLKDIV output generates a clock frequency

that is a predetermined fraction of the CLKIN frequency.

The CLKDV_DIVIDE attribute determines the factor used to

divide the CLKIN frequency. The attribute can be set to var-

ious values as described in Table 13. The basic frequency

synthesis outputs are described in Table 12. Their relative

timing in the Low Frequency Mode is shown in Figure 16.

Output Signal - Duty Cycle is Always Corrected

CLK2X

CLK2X180

(1)

CLKDV

Output Signal - Attribute Corrects Duty Cycle

DUTY_CYCLE_CORRECTION = FALSE

CLK0

CLK90

CLK180

CLK270

The CLK2X and CLK2X180 outputs are not available when

operating in the High Frequency mode. (See the description

of the DLL_FREQUENCY_MODE attribute in Table 14.)

Duty Cycle Correction of DLL Clock Outputs

The CLK2X⁽¹⁾, CLK2X180, and CLKDV⁽²⁾output signals

ordinarily exhibit a 50% duty cycle – even if the incoming

CLKIN signal has a different duty cycle. Fifty-percent duty

cycle means that the High and Low times of each clock

cycle are equal. The DUTY_CYCLE_CORRECTION

attribute determines whether or not duty cycle correction is

applied to the CLK0, CLK90, CLK180 and CLK270 outputs.

If DUTY_CYCLE_CORRECTION is set to TRUE, then the

duty cycle of these four outputs is corrected to 50%. If

DUTY_CYCLE_CORRECTION is set to FALSE, then these

outputs exhibit the same duty cycle as the CLKIN signal.

Figure 16 compares the characteristics of the DLL’s output

signals to those of the CLKIN signal.

DUTY_CYCLE_CORRECTION = TRUE

CLK0

CLK90

CLK180

CLK270

DS099-2_10_031303

Notes:

1. The DLL attribute CLKDV_DIVIDE is set to 2.

Figure 16: Characteristics of the DLL Clock Outputs

1. The CLK2X output generates a 25% duty cycle clock at the same frequency as the CLKIN signal until the DLL has achieved lock.

2. The duty cycle of the CLKDV outputs may differ somewhat from 50% (i.e., the signal will be High for less than 50% of the period) when

the CLKDV_DIVIDE attribute is set to a non-integer value and the DLL is operating in the High Frequency mode.

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Spartan-3 1.2V FPGA Family: Functional Description

the two DFS outputs to operate over a low-to-moderate fre-

quency range. When the attribute is set to HIGH, the High

Frequency mode allows both these outputs to operate at the

highest possible frequencies.

Digital Frequency Synthesizer (DFS)

The DFS component generates clock signals the frequency

of which is a product of the clock frequency at the CLKIN

input and a ratio of two user-determined integers. Because

of the wide range of possible output frequencies such a ratio

permits, the DFS feature provides still further flexibility than

the DLL’s basic synthesis options as described in the pre-

ceding section. The DFS component’s two dedicated out-

puts, CLKFX and CLKFX180, are defined in Table 15.

DFS With or Without the DLL

The DFS component can be used with or without the DLL

component:

Without the DLL, the DFS component multiplies or divides

the CLKIN signal frequency according to the respective

CLKFX_MULTIPLY and CLKFX_DIVIDE values, generating

a clock with the new target frequency on the CLKFX and

CLKFX180 outputs. Though classified as belonging to the

DLL component, the CLKIN input is shared with the DFS

component. This case does not employ feedback loop;

therefore, it cannot correct for clock distribution delay.

The signal at the CLKFX180 output is essentially an inver-

sion of the CLKFX signal. These two outputs always exhibit

a 50% duty cycle. This is true even when the CLKIN signal

does not. These DFS clock outputs are driven at the same

time as the DLL’s seven clock outputs.

The numerator of the ratio is the integer value assigned to

the attribute CLKFX_MULTIPLY and the denominator is the

integer value assigned to the attribute CLKFX_DIVIDE.

These attributes are described in Table 14.

With the DLL, the DFS operates as described in the preced-

ing case, only with the additional benefit of eliminating the

clock distribution delay. In this case, a feedback loop from

the CLK0 output to the CLKFB input must be present.

The output frequency (f_CLKFX) can be expressed as a func-

tion of the incoming clock frequency (f_CLKIN) as follows:

The DLL and DFS components work together to achieve

this phase correction as follows: Given values for the

CLKFX_MULTIPLY and CLKFX_DIVIDE attributes, the DLL

selects the delay element for which the output clock edge

coincides with the input clock edge whenever mathemati-

cally possible. For example, when CLKFX_MULTIPLY = 5

and CLKFX_DIVIDE = 3, the input and output clock edges

will coincide every three input periods, which is equivalent in

time to five output periods.

f_CLKFX= f_CLKIN*(CLKFX_MULTIPLY/CLKFX_DIVIDE) (3)

Regarding the two attributes, it is possible to assign any

combination of integer values, provided that two conditions

are met:

1. The two values fall within their corresponding ranges,

as specified in Table 14.

2. The f_CLKFXfrequency calculated from the above

expression accords with the DCM’s operating frequency

specifications.

Smaller CLKFX_MULTIPLY and CLKFX_DIVIDE values

achieve faster lock times. With no factors common to the

two attributes, alignment will occur once with every number

of cycles equal to the CLKFX_DIVIDE value. Therefore, it is

recommended that the user reduce these values by factor-

For example, if CLKFX_MULTIPLY = 5 and CLKFX_DIVIDE

= 3, then the frequency of the output clock signal would be

5/3 that of the input clock signal.

ing

wherever

possible.

For

example,

given

DFS Frequency Modes

CLKFX_MULTIPLY = 9 and CLKFX_DIVIDE = 6, removing

a factor of three yields CLKFX_MULTIPLY = 3 and

CLKFX_DIVIDE = 2. While both value-pairs will result in the

multiplication of clock frequency by 3/2, the latter value-pair

will enable the DLL to lock more quickly.

The DFS supports two operating modes, High Frequency

and Low Frequency, with each specified over a different

clock frequency range. The DFS_FREQUENCY_MODE

attribute chooses between the two modes. When the

attribute is set to LOW, the Low Frequency mode permits

Table 14: DFS Attributes

Attribute

Description

Values

DFS_FREQUENCY_MODE Chooses between High Frequency and Low Frequency modes

Low, High

CLKFX_MULTIPLY

CLKFX_DIVIDE

Frequency multiplier constant

Frequency divisor constant

Integer from 2 to 32

Integer from 1 to 32

Table 15: DFS Signals

Signal

CLKFX

Direction

Description

Multiplies the CLKIN frequency by the attribute-value ratio

Output

(CLKFX_MULTIPLY/CLKFX_DIVIDE) to generate a clock signal with a new target frequency.

CLKFX180

Output

Generates a clock signal with same frequency as CLKFX, only shifted 180° out-of-phase.

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Spartan-3 1.2V FPGA Family: Functional Description

DFS Clock Output Connections

PS Component Enabling and Mode Selection

There are two basic cases that determine how to connect

the DFS clock outputs: on-chip and off-chip, which are illus-

trated in Figure 15a and Figure 15c, respectively. This is

similar to what has already been described for the DLL com-

ponent. See the DLL Clock Output and Feedback Con-

nections, page 22 section.

The CLKOUT_PHASE_SHIFT attribute enables the PS

component for use in addition to selecting between two

operating modes. As described in Table 16, this attribute

has three possible values: NONE, FIXED and VARIABLE.

When CLKOUT_PHASE_SHIFT is set to NONE, the PS

component is disabled and its inputs, PSEN, PSCLK, and

PSINCDEC, must be tied to GND. The set of waveforms in

Figure 17a shows the disabled case, where the DLL main-

tains a zero-phase alignment of signals CLKFB and CLKIN

upon which the PS component has no effect. The PS com-

ponent is enabled by setting the attribute to either the

FIXED or VARIABLE values, which select the Fixed Phase

mode and the Variable Phase mode, respectively. These

two modes are described in the sections that follow

In the on-chip case, it is possible to connect either of the

DFS’s two output clock signals through general routing

resources to the FPGA’s internal registers. Either a Global

Clock Buffer (BUFG) or a BUFGMUX affords access to the

global clock network. The optional feedback loop is formed

in this way, routing CLK0 to a global clock net, which in turn

drives the CLKFB input.

In the off-chip case, the DFS’s two output clock signals, plus

CLK0 for an optional feedback loop, can exit the FPGA

using output buffers (OBUF) to drive a clock network plus

registers on the board. The feedback loop is formed by

feeding the CLK0 signal back into the FPGA using an

IBUFG, which directly accesses the global clock network, or

an IBUF. Then, the global clock net is connected directly to

the CLKFB input.

Determining the Fine Phase Shift

The user controls the phase shift of CLKFB relative to

CLKIN by setting and/or adjusting the value of the

PHASE_SHIFT attribute. This value must be an integer

ranging from –255 to +255. The PS component uses this

value to calculate the desired fine phase shift (T_PS) as a

fraction of the CLKIN period (T_CLKIN). Given values for

PHASE-SHIFT and T_CLKIN, it is possible to calculate T_PSas

follows:

Phase Shifter (PS)

The DCM provides two approaches to controlling the phase

of a DCM clock output signal relative to the CLKIN signal:

First, there are nine clock outputs that employ the DLL to

achieve a desired phase relationship: CLK0, CLK90,

CLK180, CLK270, CLK2X, CLK2X180, CLKDV CLKFX, and

CLKFX180. These outputs afford “coarse” phase control.

T

_PS= (PHASE_SHIFT/256)*T_CLKIN

(4)

Both the Fixed Phase and Variable Phase operating modes

employ this calculation. If the PHASE_SHIFT value is zero,

then CLKFB and CLKIN will be in phase, the same as when

the PS component is disabled. When the PHASE_SHIFT

value is positive, the CLKFB signal will be shifted later in

time with respect to CLKIN. If the attribute value is negative,

the CLKFB signal will be shifted earlier in time with respect

to CLKIN.

The second approach uses the PS component described in

this section to provide a still finer degree of control. The PS

component accomplishes this by introducing a "fine phase

shift" (T_PS) between the CLKFB and CLKIN signals inside

the DLL component. The user can control this fine phase

shift down to a resolution of 1/256 of a CLKIN cycle or one

tap delay (DCM_TAP), whichever is greater. When in use,

the PS component shifts the phase of all nine DCM clock

output signals together. If the PS component is used

together with a DCM clock output such as the CLK90,

CLK180, CLK270, CLK2X180 and CLKFX180, then the fine

phase shift of the former gets added to the coarse phase

shift of the latter.

The Fixed Phase Mode

This mode fixes the desired fine phase shift to a fraction of

the T_CLKIN, as determined by Equation (4) and its

user-selected PHASE_SHIFT value P. The set of wave-

forms in Figure 17b illustrates the relationship between

CLKFB and CLKIN in the Fixed Phase mode. In the Fixed

Phase mode, the PSEN, PSCLK and PSINCDEC inputs are

not used and must be tied to GND.

Table 16: PS Attributes

Attribute

Description

Values

CLKOUT_PHASE_SHIFT

Disables PS component or chooses between Fixed Phase NONE, FIXED, VARIABLE

and Variable Phase modes.

PHASE_SHIFT

Determines size and direction of initial fine phase shift.

Integers from –255 to +255⁽¹⁾

Notes:

1. The practical range of values will be less when T_CLKIN> FINE_SHIFT_RANGE in the Fixed Phase mode, also when T_CLKIN

>

(FINE_SHIFT_RANGE)/2 in the Variable Phase mode. the FINE_SHIFT_RANGE represents the sum total delay of all taps.

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Spartan-3 1.2V FPGA Family: Functional Description

a. CLKOUT_PHASE_SHIFT = NONE

CLKIN

CLKFB

b. CLKOUT_PHASE_SHIFT = FIXED

CLKIN

0

–255

+255

Shift Range over all P Values:

P

256

* T

CLKIN

CLKFB

c. CLKOUT_PHASE_SHIFT = VARIABLE

CLKIN

–255

+255

0

Shift Range over all P Values:

P

256

* T

CLKIN

CLKFB before

Decrement

–255

0

+255

Shift Range over all N Values:

N

256

* T

CLKIN

CLKFB after

Decrement

DS099-2_11_031303

Notes:

1. P represents the integer value ranging from –255 to +255 to which the PHASE_SHIFT attribute is assigned.

2. N is an integer value ranging from –255 to +255 that represents the net phase shift effect from a series of increment and/or

decrement operations.

N = {Total number of increments} – {Total number of decrements}

A positive value for N indicates a net increment; a negative value indicates a net decrement.

Figure 17: Phase Shifter Waveforms

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Spartan-3 1.2V FPGA Family: Functional Description

Table 17: Signals for Variable Phase Mode

Signal

PSEN⁽¹⁾

Direction

Input

Description

Enables PSCLK for variable phase adjustment.

PSCLK⁽¹⁾

Input

Clock to synchronize phase shift adjustment.

PSINCDEC⁽¹⁾

Input

Chooses between increment and decrement for phase adjustment. It is synchronized to the

PSCLK signal.

PSDONE

Output

Goes High to indicate that present phase adjustment is complete and PS component is

ready for next phase adjustment request. It is synchronized to the PSCLK signal.

Notes:

1. It is possible to program this input for either a true or inverted polarity

point the output PSDONE goes High for one PSCLK cycle.

This pulse indicates that the PS component has finished the

present adjustment and is now ready for the next request.

Asserting the Reset (RST) input, returns T_PSto its original

shift time, as determined by the PHASE_SHIFT attribute

value. The set of waveforms in Figure 17c illustrates the

relationship between CLKFB and CLKIN in the Variable

Phase mode.

The Variable Phase Mode

The “Variable Phase” mode dynamically adjusts the fine

phase shift over time using three inputs to the PS compo-

nent, namely PSEN, PSCLK and PSINCDEC, as defined in

Table 17.

Just following device configuration, the PS component ini-

tially determines T_PSby evaluating Equation (4) for the

value assigned to the PHASE_SHIFT attribute. Then to

dynamically adjust that phase shift, use the three PS inputs

to increase or decrease the fine phase shift.

The Status Logic Component

The Status Logic component not only reports on the state of

the DCM but also provides a means of resetting the DCM to

an initial known state. The signals associated with the Sta-

tus Logic component are described in Table 18.

PSINCDEC is synchronized to the PSCLK clock signal,

which is enabled by asserting PSEN. It is possible to drive

the PSCLK input with the CLKIN signal or any other clock

signal. A request for phase adjustment is entered as follows:

For each PSCLK cycle that PSINCDEC is High, the PS

component adds 1/256 of a CLKIN cycle to T_PS. Similarly,

for each enabled PSCLK cycle that PSINCDEC is Low, the

PS component subtracts 1/256 of a CLKIN cycle from T_PS

The phase adjustment may require as many as 100 CLKIN

cycles plus three PSCLK cycles to take effect, at which

As a rule, the Reset (RST) input is asserted only upon con-

figuring the device or changing the CLKIN frequency. A

DCM reset does not affect attribute values (e.g.,

CLKFX_MULTIPLY and CLKFX_DIVIDE). If not used, RST

must be tied to GND.

.

The eight bits of the STATUS bus are defined in Table 19.

Table 18: Status Logic Signals

Signal

RST

Direction

Description

Input

A High resets the entire DCM to its initial power-on state. Initializes the DLL taps for a delay

of zero. Sets the LOCKED output Low. This input is asynchronous.

STATUS[7:0]

LOCKED

Output

The bit values on the STATUS bus provide information regarding the state of DLL and PS

operation

Indicates that the CLKIN and CLKFB signals are in phase by going High. The two signals

are out-of-phase when Low.

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Spartan-3 1.2V FPGA Family: Functional Description

Description

Table 19: DCM STATUS Bus

Bit

Name

0

Phase Shift

Overflow

A value of 1 indicates a phase shift overflow when one of two conditions occur:

•

Incrementing (or decrementing) TPS beyond 255/256 of a CLKIN cycle.

The DLL is producing its maximum possible phase shift (i.e., all delay taps are active).⁽¹⁾

1

CLKIN Activity

A value of 1 indicates that the CLKIN signal is not toggling. A value of 0 indicates toggling. This

bit functions only when the CLKFB input is connected.⁽²⁾

2

Reserved

-

3

4

5

6

7

Notes:

1. The DLL phase shift with all delay taps active is specified as the parameter FINE_SHIFT_RANGE.

2. If only the DFS clock outputs are used, but none of the DLL clock outputs, this bit will not go High when the CLKIN signal stops.

Table 20: Status Attributes

Attribute

Description

Values

STARTUP_WAIT

Delays transition from configuration to user mode until lock condition is achieved. TRUE, FALSE

as DCMs. Four BUFGMUX elements are placed at the cen-

ter of the die’s bottom edge, just above the GCLK0 - GCLK4

inputs. The remaining four BUFGMUX elements are placed

at the center of the die’s top edge, just below the GCLK4 -

GCLK7 inputs.

Stabilizing DCM Clocks Before User Mode

It is possible to delay the completion of device configuration

until after the DLL has achieved a lock condition using the

STARTUP_WAIT attribute described in Table 20. This

option ensures that the FPGA does not enter user mode —

i.e., begin functional operation — until all system clocks

generated by the DCM are stable. In order to achieve the

delay, it is necessary to set the attribute to TRUE as well as

set the BitGen option LCK_cycle to one of the six cycles

making up the Startup phase of configuration. The selected

cycle defines the point at which configuration will halt until

the LOCKED output goes High.

Each BUFGMUX element is a 2-to-1 multiplexer that can

receive signals from any of the four following sources:

1. One of the four Global Clock inputs on the same side of

the die — top or bottom — as the BUFGMUX element in

use.

2. Any of four nearby horizontal Double lines.

3. Any of four outputs from the DCM in the right-hand

quadrant that is on the same side of the die as the

BUFGMUX element in use.

Global Clock Network

Spartan-3 devices have eight Global Clock inputs called

GCLK0 - GCLK7. These inputs provide access to a

low-capacitance, low-skew network that is well-suited to

carrying high-frequency signals. The Spartan-3 clock net-

work is shown in Figure 18. GCLK0 through GCLK3 are

placed at the center of the die’s bottom edge. GCLK4

through GCLK7 are placed at the center of the die’s top

edge. It is possible to route each of the eight Global Clock

inputs to any CLB on the die.

4. Any of four outputs from the DCM in the left-hand

quadrant that is on the same side of the die as the

BUFGMUX element in use.

Sources 3 and 4 are not available on the XC3S50 die that

lacks DCMs.

Each BUFGMUX can switch incoming clock signals to two

possible destinations:

1. The vertical spine belonging to the same side of the die

— top or bottom — as the BUFGMUX element in use.

The two spines — top and bottom — each comprise

four vertical clock lines, each running from one of the

Eight Global Clock Multiplexers (also called BUFGMUX ele-

ments) are provided that accept signals from Global Clock

inputs and route them to the internal clock network as well

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Spartan-3 1.2V FPGA Family: Functional Description

BUFGMUX elements on the same side towards the

center of the die. At the center of the die, clock signals

reach the eight-line horizontal spine, which spans the

width of the die. In turn, the horizontal spine branches

out into a subsidiary clock interconnect that accesses

the CLBs.

A Global clock input is placed in a design using either a

BUFGMUX element or the BUFG (Global Clock Buffer) ele-

ment. For the purpose of minimizing the dynamic power dis-

sipation of the clock network, the Xilinx development

software automatically disables all clock line segments that

a design does not use.

2. The clock input of either DCM on the same side of the

die — top or bottom — as the BUFGMUX element in

use.

GCLK7

GCLK6

GCLK5

GCLK4

4

4 BUFGMUX

4

DCM

4

8

•

Array Dependent

•

8

Horizontal Spine

•

Array Dependent

4

DCM

4 BUFGMUX

GCLK2

GCLK0

GCLK3

GCLK1

DS099-2_18_070203

Figure 18: Spartan-3 Clock Network (Top View)

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Spartan-3 1.2V FPGA Family: Functional Description

ble lines in terms of capability: Hex lines approach the

high-frequency characteristics of Long lines at the same

time, offering greater connectivity.

Interconnect

Interconnect (or routing) passes signals among the various

functional elements of Spartan-3 devices. There are four

kinds of interconnect: Long lines, Hex lines, Double lines,

and Direct lines.

Double lines connect to every other CLB (see Figure 19c).

Compared to the types of lines already discussed, Double

lines provide a higher degree of flexibility when making con-

nections.

Long lines connect to one out of every six CLBs (see

Figure 19a). Because of their low capacitance, these lines

are well-suited for carrying high-frequency signals with min-

imal loading effects (e.g. skew). If all eight Global Clock

Inputs are already committed and there remain additional

clock signals to be assigned, Long lines serve as a good

alternative.

Direct lines afford any CLB direct access to neighboring

CLBs (see Figure 19d). These lines are most often used to

conduct a signal from a "source" CLB to a Double, Hex, or

Long line and then from the longer interconnect back to a

Direct line accessing a "destination" CLB.

Hex lines connect one out of every three CLBs (see

Figure 19b). These lines fall between Long lines and Dou-

CLB

6

DS099-2_19_040103

(a) Long Line

8

CLB

DS099-2_20_040103

(b) Hex Line

CLB

2

CLB

DS099-2_21_040103

CLB

(c) Double Line

DS099-2_22_040103

(d) Direct Lines

Figure 19: Types of Interconnect

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Spartan-3 1.2V FPGA Family: Functional Description

can be re-used as general-purpose User I/Os once configu-

ration is complete.

Configuration

Spartan-3 devices are configured by loading application

specific configuration data into the internal configuration

memory. Configuration is carried out using a subset of the

device pins, some of which are "Dedicated" to one function

only, while others, indicated by the term "Dual-Purpose",

Depending on the system design, several configuration

modes are supported, selectable via mode pins. The mode

pins M0, M1, and M2 are Dedicated pins. The mode pin set-

tings are shown in Table 21.

Table 21: Spartan-3 Configuration Mode Pin Settings

Configuration Mode⁽¹⁾

Master Serial

Slave Serial

Master Parallel

Slave Parallel

JTAG

M0

0

M1

0

M2

0

Synchronizing Clock

CCLK Output

CCLK Input

Data Width

Serial DOUT⁽²⁾

1

8

1

Yes

No

1

0

CCLK Output

CCLK Input

0

1

0

1

TCK Input

Notes:

1. The voltage levels on the M0, M1, and M2 pins select the configuration mode.

2. The daisy chain is possible only in the Serial modes when DOUT is used.

An additional pin, HSWAP_EN, is used in conjunction with

the mode pins to select whether user I/O pins have pull-ups

during configuration. By default, HSWAP_EN is tied High

(internal pull-up) which shuts off the pull-ups on the user I/O

pins during configuration. When HSWAP_EN is tied Low,

user I/Os have pull-ups during configuration. Other Dedi-

cated pins are CCLK (the configuration clock pin), DONE,

PROG_B, and the boundary-scan pins: TDI, TDO, TMS,

and TCK. Depending on the configuration mode chosen,

CCLK can be an output generated by the FPGA, or an input

accepting an externally generated clock.

Table 22: Spartan-3 Configuration Data

Xilinx Platform Flash PROM

Serial Parallel

Configuration Configuration

Device

File Sizes

439,264

XC3S50

XCF01S

XCF02S

XCF04S

XCF08P

XCF16P

XCF08P

XCF16P

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

1,047,616

1,699,136

3,223,488

5,214,784

7,673,024

11,316,864

13,271,936

A persist option is available which can be used to force the

configuration pins to retain their configuration function even

after device configuration is complete. If the persist option is

not selected then the configuration pins with the exception

of CCLK, PROG_B, and DONE can be used as user I/O in

normal operation. The persist option does not apply to the

boundary-scan related pins. The persist feature is valuable

in applications that readback configuration data after enter-

ing the User mode.

The Dual-Purpose configuration pins comprise INIT_B,

DOUT, BUSY, RDWR_B, CS_B, and DIN/D0-D7. Each of

these pins, according to its bank placement, uses the V_CCO

lines for either Bank 4 (VCCO_4) or Bank 5 (VCCO_5). All

the signals used in the serial configuration modes rely on

VCCO_4 power. Signals used in the parallel configuration

modes and Readback require from VCCO_5 as well as from

VCCO_4.

Table 22 lists the total number of bits required to configure

each FPGA as well as the PROMs suitable for storing those

bits. See DS123: Platform Flash In-System Programmable

Configuration PROMs data sheet for more information.

The Standard Configuration Interface

Both the Dedicated and Dual-Purpose signals described

above constitute the configuration interface. In the standard

case, this interface is 2.5V-LVCMOS-compatible. This

means that 2.5V is applied to the V_CCAUX, VCCO_4, and

VCCO_5 lines (this last in the parallel or Readback case

only). One need only apply 2.5 Volts to these V_CCOlines

from power-on to the end of configuration. Upon entering

the User mode, it is possible to switch to supply voltage per-

mitting signal swings other than 2.5V.

Configuration signals belong to one of two different catego-

ries: Dedicated or Dual-Purpose. Which category deter-

mines which of the FPGA’s power rails supplies the signal’s

driver and, thus, helps describe the electrical at the pin.

The Dedicated configuration pins include PROG_B,

HSWAP_EN, TDI, TMS, TCK, TDO, CCLK, DONE, and

M0-M2. These pins use the V_CCAUXlines for power.

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Spartan-3 1.2V FPGA Family: Functional Description

3.3V-Tolerant Configuration Interface

Configuration Modes

It is possible to achieve 3.3V-tolerance at the configuration

interface simply by adding a few external resistors. This

approach may prove useful when it is undesirable to switch

the VCCO_4 and VCCO_5 voltages from 2.5V to 3.3V after

configuration.

Spartan-3 supports the following five configuration modes:

•

Slave Serial mode

Master Serial mode

Slave Parallel mode

Master Parallel mode

Boundary-Scan (JTAG) mode (IEEE 1532/IEEE

1149.1)

The 3.3V-tolerance is implemented as follows (a similar

approach can be used for other supply voltage levels):

First, to power the Dual-Purpose configuration pins, apply

3.3V to the VCCO_4 and (as needed) the VCCO_5 lines.

This scales the output voltages and input thresholds associ-

ated with these pins so that they become 3.3V-compatible.

Slave Serial Mode

In Slave Serial mode, the FPGA receives configuration data

in bit-serial form from a serial PROM or other serial source

of configuration data. The FPGA on the far right of Figure 20

is set for the Slave Serial mode. The CCLK pin on the FPGA

is an input in this mode. The serial bitstream must be setup

at the DIN input pin a short time before each rising edge of

the externally generated CCLK.

Second, to power the Dedicated configuration pins, apply

2.5V to the V_CCAUXlines (the same as for the standard

interface). In order to achieve 3.3V-tolerance, the Dedicated

inputs will require series resistors that limit the incoming

current to 10mA or less. The Dedicated outputs will need

pull-up resistors to ensure adequate noise margin when the

FPGA is driving a High logic level into another device’s 3.3V

receiver. Choose a power regulator or supply that can toler-

ate reverse current on the V_CCAUXlines.

Multiple FPGAs can be daisy-chained for configuration from

a single source. After a particular FPGA has been config-

ured, the data for the next device is routed internally to the

DOUT pin. The data on the DOUT pin changes on the rising

edge of CCLK.

2.5V

3.3V

2.5V

1.2V

V

Bank 4

V

Bank 4

CCO

V

CCO

V

CCINT

CCAUX

CCINT

CCAUX

V

CC

CCJ

D0

DIN

DOUT

DIN

Spartan-3

FPGA

Spartan-3

FPGA

Platform

Flash PROM

2.5V

Master

Slave

M0

M1

M2

M0

M1

M2

XCF0xS

or

All

4.7KΩ

XCFxxP

CE

DONE

OE/RESET

CF

INIT_B

PROG_B

CCLK

INIT_B

PROG_B

CCLK

CLK

GND

DS099_23_041103

Notes:

1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for the

last FPGA to be configured in the chain shown above (or for the single FPGA as may be the case). This enables

the DONE pin to drive High; thus, no pull-up resistor is necessary. DriveDone is set to "No" for the remaining

FPGAs in the chain. Second, DriveDone can be set to "No" for all FPGAs. Then all DONE lines are open-drain

and require the pull-up resistor shown in grey. In most cases, a value between 3.3KΩ to 4.7KΩ is sufficient.

However, when using DONE synchronously with a long chain of FPGAs, cumulative capacitance may

necessitate lower resistor values (e.g. down to 330Ω) in order to ensure a rise time within one clock cycle.

2. For information on how to program the FPGA using 3.3V signals and power, see 3.3V-Tolerant Configuration

Interface.

Figure 20: Connection Diagram for Master and Slave Serial Configuration

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Spartan-3 1.2V FPGA Family: Functional Description

Slave Serial mode is selected by applying <111> to the

mode pins (M0, M1, and M2). A weak pull-up on the mode

pins makes slave serial the default mode if the pins are left

unconnected.

controlling the flow of data. An external source provides

8-bit-wide data, CCLK, an active-Low Chip Select (CS_B)

signal and an active-Low Write signal (RDWR_B). If BUSY

is asserted (High) by the FPGA, the data must be held until

BUSY goes Low. Data can also be read using the Slave

Parallel mode. If RDWR_B is asserted, configuration data is

read out of the FPGA as part of a readback operation.

Master Serial Mode

In Master Serial mode, the CCLK pin is an output pin. The

FPGA just to the right of the PROM in Figure 20 is set for

Master Serial mode. It is the FPGA that drives the configu-

ration clock on the CCLK pin to a Xilinx Serial PROM which

in turn feeds bit-serial data to the DIN input. The FPGA

accepts this data on each rising CCLK edge. After the

FPGA has been loaded, the data for the next device in a

daisy-chain is presented on the DOUT pin after the rising

CCLK edge.

After configuration, it is possible to use any of the Multipur-

pose pins (DIN/D0-D7, DOUT/BUSY, INITB, CS_B, and

RDWR_B) as User I/Os. To do this, simply set the BitGen

option Persist to No and assign the desired signals to multi-

purpose configuration pins using the Xilinx development

software. Alternatively, it is possible to continue using the

configuration port (e.g. all configuration pins taken together)

when operating in the User mode. This is accomplished by

setting the Persist option to Yes.

The interface is identical to slave serial except that an inter-

nal oscillator is used to generate the configuration clock

(CCLK). A wide range of frequencies can be selected for

CCLK which always starts at a default frequency of 6 MHz.

Configuration bits then switch CCLK to a higher frequency

for the remainder of the configuration.

Multiple FPGAs can be configured using the Slave Parallel

mode and can be made to start-up simultaneously.

Figure 21 shows the device connections. To configure mul-

tiple devices in this way, wire the individual CCLK, Data,

RDWR_B, and BUSY pins of all the devices in parallel. The

individual devices are loaded separately by deasserting the

CS_B pin of each device in turn and writing the appropriate

data.

Slave Parallel Mode

The Parallel modes support the fastest configuration.

Byte-wide data is written into the FPGA with a BUSY flag

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Spartan-3 1.2V FPGA Family: Functional Description

D[0:7]

CCLK

RDWR_B

BUSY

2.5V

1.2V

V

Banks 4 & 5

V

Banks 4 & 5

CCO

V

CCINT

CCAUX

CCINT

CCAUX

Spartan-3

Slave

Spartan-3

Slave

D[0:7]

CCLK

RDWR_B

BUSY

RDWR_B

BUSY

2.5V

CS_B

M1

M2

M0

M1

M2

M0

PROG_B

DONE

PROG_B

DONE

2.5V

INIT_B

GND

4.7KΩ

DONE

INIT_B

PROG_B

DS099_24_041103

Notes:

1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for the last FPGA

to be configured in the chain shown above (or for the single FPGA as may be the case). This enables the DONE pin to drive

High; thus, no pull-up resistor is necessary. DriveDone is set to "No" for the remaining FPGAs in the chain. Second,

DriveDone can be set to "No" for all FPGAs. Then all DONE lines are open-drain and require the pull-up resistor shown in

grey. In most cases, a value between 3.3KΩ to 4.7KΩ is sufficient. However, when using DONE synchronously with a long

chain of FPGAs, cumulative capacitance may necessitate lower resistor values (e.g. down to 330Ω) in order to ensure a rise

time within one clock cycle.

2. If the FPGAs use different configuration data files, configure them in sequence by first asserting the CS_B of one FPGA then

asserting the CS_B of the other FPGA.

3. For information on how to program the FPGA using 3.3V signals and power, see 3.3V-Tolerant Configuration Interface.

Figure 21: Connection Diagram for Slave Parallel Configuration

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Spartan-3 1.2V FPGA Family: Functional Description

2.5V

3.3V

2.5V

1.2V

V

Banks 4 & 5

CCO

V

CCINT

CCAUX

V

CCO

Spartan-3

Master

V

CC

V

CCJ

DATA[0:7]

CCLK

D[0:7]

CCLK

2.5V

Platform Flash

PROM

All

4.7KΩ

XCFxxP

CF

PROG_B

DONE

CE

OE/RESET

INIT_B

GND

RDWR_B

CS_B

GND

DS099_25_041103

Notes:

1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes"

only for the last FPGA to be configured in the chain shown above (or for the single FPGA as may be

the case). This enables the DONE pin to drive High; thus, no pull-up resistor is necessary. DriveDone

is set to "No" for the remaining FPGAs in the chain. Second, DriveDone can be set to "No" for all

FPGAs. Then all DONE lines are open-drain and require the pull-up resistor shown in grey. In most

cases, a value between 3.3KΩ to 4.7KΩ is sufficient. However, when using DONE synchronously

with a long chain of FPGAs, cumulative capacitance may necessitate lower resistor values (e.g.

down to 330Ω) in order to ensure a rise time within one clock cycle.

Figure 22: Connection Diagram for Master Parallel Configuration

Master Parallel Mode

Configuration Sequence

In this mode, the device is configured byte-wide on a CCLK

supplied by the FPGA. Timing is similar to the Slave Parallel

mode except that CCLK is supplied by the FPGA. The

device connections are shown in Figure 22.

The configuration of Spartan-3 devices is a three-stage pro-

cess that occurs after Power-On Reset or the assertion of

PROG_B. POR occurs after the V_CCINT, V_CCAUX, and V_CCO

Bank 4 supplies have reached their respective maximum

input threshold levels (see Table 7 in Module 3: DC and

Switching Characteristics). After POR, the three-stage

process begins.

Boundary-Scan (JTAG) Mode

In Boundary-Scan mode, dedicated pins are used for con-

figuring the FPGA. The configuration is done entirely

through the IEEE 1149.1 Test Access Port (TAP). FPGA

configuration using the Boundary-Scan mode is compliant

with the IEEE 1149.1-1993 standard and the new IEEE

1532 standard for In-System Configurable (ISC) devices.

First, the configuration memory is cleared. Next, con-

figuration data is loaded into the memory, and finally, the

logic is activated by a start-up process. A flow diagram for

the configuration sequence of the Serial and Parallel modes

is shown in Figure 23. The flow diagram for the Bound-

ary-Scan configuration sequence appears in Figure 24.

Configuration through the boundary-scan port is always

available, independent of the mode selection. Selecting the

Boundary-Scan mode simply turns off the other modes.

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Spartan-3 1.2V FPGA Family: Functional Description

Set PROG_B Low

after Power-On

Power-On

V_CCINT>1V

and V_CCAUX> 2V

No

and V_CCOBank 4 > 1V

Yes

Clear configuration

memory

PROG_B = Low

No

INIT_ B = High?

Yes

Sample mode pins

Load configuration

data frames

No

INIT_B goes Low.

Abort Start-Up

CRC

correct?

Yes

Start-Up

sequence

User mode

No

Yes

Reconfigure?

DS099_26_041103

Figure 23: Configuration Flow Diagram for the Serial and Parallel Modes

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Spartan-3 1.2V FPGA Family: Functional Description

Set PROG_B Low

after Power-On

Power-On

V_CCINT>1V

and V_CCAUX> 2V

No

and V_CCOBank 4 > 1V

Yes

Clear

configuration

memory

Yes

PROG_B = Low

No

INIT_B = High?

Yes

Sample

mode pins

(JTAG port becomes

available)

Load

JShutdown

instruction

Shutdown

sequence

Load CFG_IN

instruction

Load configuration

data frames

No

CRC

correct?

INIT_B goes Low.

Abort Start-Up

Yes

Synchronous

TAP reset

(Clock five 1's

on TMS)

Load JSTART

instruction

Start-Up

sequence

User mode

Yes

No

Reconfigure?

DS099_27_041103

Figure 24: Boundary-Scan Configuration Flow Diagram

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Spartan-3 1.2V FPGA Family: Functional Description

Configuration is automatically initiated after power-on

unless it is delayed by the user. INIT_B is an open-drain line

that the FPGA holds Low during the clearing of the configu-

ration memory. Extending the time that the pin is Low

causes the configuration sequencer to wait. Thus, configu-

ration is delayed by preventing entry into the phase where

data is loaded.

The default start-up sequence, shown in Figure 25, serves

as a transition to the User mode. The default start-up

sequence is that one CCLK cycle after DONE goes High,

the Global Three-State signal (GTS) is released. This per-

mits device outputs to which signals have been assigned to

become active. One CCLK cycle later, the Global Write

Enable (GWE) signal is released. This permits the internal

storage elements to begin changing state in response to the

design logic and the user clock.

The configuration process can also be initiated by asserting

the PROG_B pin. The end of the memory-clearing phase is

signaled by the INIT_B pin going High. At this point, the con-

figuration data is written to the FPGA. The FPGA holds the

Global Set/Reset (GSR) signal active throughout configura-

tion, keeping all flip-flops on the device in a reset state. The

completion of the entire process is signaled by the DONE

pin going High.

The relative timing of configuration events can be changed

via the BitGen options in the Xilinx development software. In

addition, the GTS and GWE events can be made depen-

dent on the DONE pins of multiple devices all going High,

forcing the devices to start synchronously. The sequence

can also be paused at any stage, until lock has been

achieved on any DCM.

Default Cycles

Readback

Start-Up Clock

Using Slave Parallel mode, configuration data from the

FPGA can be read back. Readback is supported only in the

Slave Parallel and Boundary-Scan modes.

Phase

0

1

2

3

4

5

6 7

Along with the configuration data, it is possible to read back

the contents of all registers, distributed SelectRAM, and

block RAM resources. This capability is used for real-time

debugging.

DONE

GTS

GSR

GWE

Sync-to-DONE

Start-Up Clock

Phase

0

1

2

3

4

5

6 7

DONE High

DONE

GTS

GSR

GWE

DS099_028_040803

Notes:

1. The BitGen option StartupClk in the Xilinx

development software selects the CCLK input,

TCK input, or a user-designated global clock input

(the GCLK0 - GCLK7 pins) for receiving the clock

signal that synchronizes Start-Up.

Figure 25: Default Start-Up Sequence

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Spartan-3 1.2V FPGA Family: Functional Description

Revision History

Date

Version No.

Description

04/11/03

05/19/03

07/11/03

1.0

1.1

1.2

Initial Xilinx release

Added Block RAM column, DCMs, and multipliers to XC3S50 descriptions.

Explained the configuration port Persist option in Slave Parallel Mode section. Updated

Figure 2 and Double-Data-Rate Transmission section to indicate that DDR clocking for the

XCS350 is the same as that for all other Spartan-3 devices. Updated description of I/O voltage

tolerance in ESD Protection section. In Table 6, changed input termination type for DCI

version of the LVCMOS standard to None. Added additional flexibility for making DLL

connections in Figure 15 and accompanying text. In the Configuration section, inserted an

explanation of how to choose power supplies for the configuration interface, including

guidelines for achieving 3.3V-tolerance.

The Spartan-3 Family Data Sheet

DS099-1, Spartan-3 1.2V FPGA Family: Introduction and Ordering Information (Module 1)

DS099-2, Spartan-3 1.2V FPGA Family: Functional Description (Module 2)

DS099-3, Spartan-3 1.2V FPGA Family: DC and Switching Characteristics (Module 3)

DS099-4, Spartan-3 1.2V FPGA Family: Pinout Descriptions (Module 4)

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Spartan-3 FPGA Family:

DCand Switching Characteristics

0

DS099-3 (v1.3) March 4, 2004

Advance Product Specification

DC Electrical Characteristics

In this section, some specifications may be designated as

Advance or Preliminary. These terms are defined as fol-

lows:

All parameter limits are representative of worst-case supply

voltage and junction temperature conditions. The following

applies unless otherwise noted: The parameter values pub-

lished in this module apply to all Spartan-3 devices. AC and

DC characteristics are specified using the same numbers

for both commercial and industrial grades. All parameters

representing voltages are measured with respect to GND.

Advance: Initial estimates based on simulation, early char-

acterization, and/or extrapolation from the characteristics of

other families. Values are subject to change. Use as esti-

mates, not for production.

Some specifications list different values for one or more die

revisions. All presently available Spartan-3 devices are

classified as revision 0. Future updates to this module will

introduce further die revisions as needed.

Preliminary: Based on characterization. Further changes

are not expected.

Table 1: Absolute Maximum Ratings

Symbol

V_CCINT

V_CCAUX

V_CCO

Description

Internal supply voltage

Auxiliary supply voltage

Output driver supply voltage

Input reference voltage

Conditions

Min

–0.5

Max

1.32

Units

V

3.00

3.75

(2)

V_REF

V_CCO+ 0.5

(2)

V_IN

Voltage applied to all User I/O pins Driver in a

and Dual-Purpose pins⁽³⁾

high-impedance state

Voltage applied to all Dedicated

pins⁽⁴⁾

–0.5

V_CCAUX+ 0.5

V

T_J

Junction temperature

V_CCO< 3.0V

_CCO> 3.0V

-

125

105

220

150

°C

V

-

(5)

T_SOL

Soldering temperature

Storage temperature

T_STG

–65

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings will cause permanent damage to the device. These are stress

ratings only; functional operation of the device at these or any other conditions beyond those listed under the Recommended

Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time adversely

affects device reliability.

2. Table 5 specifies the range of values for V_CCOand V_CCAUX, which are used to determine the limits of this parameter.

3. All User I/O and Dual-Purpose pins (DIN/D0, D1–D7, CS_B, RDWR_B, BUSY/DOUT, AND INIT_B) draw power from the V_CCO

power rail of the associated bank.

4. All Dedicated pins (M0–M2, CCLK, PROG_B, DONE, HSWAP_EN, TCK, TDI, TDO, and TMS) draw power from the V_CCAUXrail

(2.5V). For information concerning the use of 3.3V signals, see the 3.3V-Tolerant Configuration Interface section in Module 2:

Functional Description.

5. For soldering guidelines, see the information on "Packaging and Thermal Characteristics" at www.xilinx.com.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS099-3 (v1.3) March 4, 2004

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 2: Supply Voltage Thresholds for Power-On Reset

Symbol

V_CCINTT

V_CCAUXT

V_CCO4T

Description

Threshold for the V_CCINTsupply

Threshold for the V_CCAUXsupply

Threshold for the V_CCOBank 4 supply

Min

0.4

0.8

0.4

Max

1.0

Units

V

2.0

1.0

Notes:

1. V_CCINT, V_CCAUX, and V_CCOsupplies may be applied in any order.

2. To ensure successful power-on, V_CCINT, V_CCOBank 4, and V_CCAUXsupplies must rise through their respective threshold-voltage

ranges with no dips at any point.

Table 3: Other Power-On Requirements

Symbol

Description

Device Revision

Min

Max

Units

T_CCO

V_CCOramp time for all eight banks

0

XC3S200, XC3S400,

and XC3S1500 in the

FT and FG packages⁽¹⁾

600

-

µs

All other devices

2.0

-

ms

Future

To be

improved

Notes:

1. This specification is based on characterization.

2. At present, there are no ramp requirements for the V_CCINTand V_CCAUXsupplies.

Table 4: Power Voltage Levels Necessary for Preserving RAM Contents

Symbol

V_DRINT

V_DRAUX

Description

V_CCINTlevel required to retain RAM data

V_CCAUXlevel required to retain RAM data

Min

Units

1.0

2.0

V

Notes:

1. RAM contents include configuration data.

2. The level of the V_CCOsupply has no effect on data retention.

2

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Table 5: General Recommended Operating Conditions

Symbol

Description

Junction temperature

Min

0

Nom

Max

85

Units

° C

V

T_J

Commercial

Industrial

-

–40

-

100

V_CCINT

Internal supply voltage

Output driver supply voltage

Auxiliary supply voltage

1.140

2.375

1.200

-

1.260

3.450

2.625

(1)

V_CCO

V

V_CCAUX

2.500

V

Notes:

1. The V_CCOrange given here spans the lowest and highest operating voltages of all supported I/O standards. The recommended

V_CCOrange specific to each of the single-ended I/O standards is given in Table 8, and that specific to the differential standards is

given in Table 10.

Table 6: General DC Characteristics of User I/O, Dual-Purpose, and Dedicated Pins

Symbol

Description

Test Conditions

Device Revision

Min

–25

–10

Typ

Max

+25

+10

Units

µA

I_L

Leakage current at User

I/O, Dual-Purpose, and

Dedicated pins

Driver is in a

high-impedance state,

_IN= 0V or V_CCOmax,

sample-tested

0

V

_CCO> 3.0V

_CCO< 3.0V

-

µA

V

(2)

I_RPU

Current through pull-up

resistor at User I/O,

Dual-Purpose, and

Dedicated pins

V

_IN=0, V_CCO= 3.3V

0

–0.84

–0.69

–0.47

–0.21

–0.13

–0.06

0.37

-

–2.35

–1.99

–1.41

–0.69

–0.43

–0.22

1.67

mA

V_IN=0, V_CCO= 3.0V

V

_IN=0, V_CCO= 2.5V

_IN=0, V_CCO= 1.8V

V_IN=0, V_CCO= 1.5V

_IN=0, V_CCO= 1.2V

_IN= V_CCO

V

(2)

I_RPD

Current through

V

pull-down resistor at

User I/O, Dual-Purpose,

and Dedicated pins

I_REF

V_REFcurrent per pin

0

V_CCO> 3.0V

_CCO< 3.0V

All

–25

–10

3

-

+25

+10

10

µA

pF

V

C_IN

Input capacitance

Notes:

1. The numbers in this table are based on the conditions set forth in Table 5.

2. This parameter is based on characterization.

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 7: Quiescent Supply Current Characteristics

Commercial

Typ Max

Industrial

Typ Max

Symbol

Description

Device

XC3S50

Units

mA

I_CCINTQQuiescent V_CCINTsupply

current

10.0

20.0

35.0

65.0

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

I_CCOQ

Quiescent V_CCOsupply current XC3S50

1.5

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

I_CCAUXQQuiescent V_CCAUXsupply

current

XC3S50

7.0

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

15.0

20.0

25.0

Notes:

1. The numbers in this table are based on the conditions set forth in Table 5. Quiescent supply current is measured with all I/O drivers

in a high-impedance state and with all pull-up/pull-down resistors at the I/O pads disabled. For typical values, the ambient

temperature (T_A) is 25 °C with V_CCINT= 1.2V, V_CCO= 2.5V, and V_CCAUX= 2.5V. The FPGA is programmed with a "blank"

configuration data file (i.e., a design with no functional elements instantiated).

2. There are two recommended ways to estimate the total power consumption (quiescent plus dynamic) for a specific design: a) The

Spartan-3 Web Power Tool at http://www.xilinx.com/ise/power_tools provides quick, approximate, typical estimates, and does not

require a netlist of the design. b) XPower, part of the Xilinx development software, takes a netlist as input to provide more accurate

maximum and typical estimates.

4

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 8: Recommended Operating Conditions for User I/Os Using Single-Ended Standards

V_CCO

V_REF

Nom (V)

0.8

V_IL

V_IH

Signal Standard

GTL⁽²⁾

Min (V)

Nom (V)

Max (V)

Min (V)

0.74

Max (V)

0.86

1.12

0.9

Max (V)

Min (V)

-

V_REF- 0.05

V_REF+ 0.05

V_REF+ 0.1

GTL_DCI

1.2

-

0.74

0.8

V_REF- 0.05

GTLP⁽²⁾

-

0.88

1

V_REF- 0.1

GTLP_DCI

-

1.5

-

0.88

1

HSTL_I, HSTL_I_DCI

1.4

1.6

0.68

0.75

V

_REF- 0.1

HSTL_III,

HSTL_III_DCI

1.4

1.7

1.5

1.8

1.6

1.9

0.68

0.9

V

_REF- 0.1

V_REF+ 0.1

HSTL_I_18,

HSTL_I_DCI_18

-

V_REF- 0.1

HSTL_II_18,

HSTL_II_DCI_18

HSTL_III_18,

HSTL_III_DCI_18

LVCMOS12⁽³⁾

1.7

1.8

1.2

1.9

1.3

-

1.1

-

V

_REF- 0.1

V_REF+ 0.1

0.70V_CCO

1.14

0.20V_CCO

LVCMOS15,

LVDCI_15,

LVDCI_DV2_15⁽³⁾

1.4

1.7

2.3

3.0

1.5

1.8

2.5

3.3

1.6

1.9

-

0.70V_CCO

1.7

LVCMOS18,

LVDCI_18,

LVDCI_DV2_18⁽³⁾

LVCMOS25⁽⁴⁾

LVDCI_25,

LVDCI_DV2_25⁽³⁾

0.20V_CCO

0.7

,

2.7

LVCMOS33,

LVDCI_33,

LVDCI_DV2_33⁽³⁾

3.45

0.8

2.0

LVTTL

3.0

-

3.3

3.0

3.45

-

0.8

2.0

PCI33_3

0.30V_CCO

0.50V_CCO

SSTL18_I,

SSTL18_I_DCI

1.65

2.3

1.8

2.5

1.95

2.7

0.825

1.15

0.9

0.975

1.35

V_REF- 0.125

V_REF+ 0.125

V_REF+ 0.15

SSTL2_I,

SSTL2_I_DCI

1.25

V

_REF- 0.15

SSTL2_II,

SSTL2_II_DCI

2.3

2.7

V_REF- 0.15

Notes:

1. Descriptions of the symbols used in this table are as follows:

V_CCO-- the supply voltage for output drivers as well as LVCMOS, LVTTL, and PCI inputs

V_REF-- the reference voltage for setting the input switching threshold

V_IL-- the input voltage that indicates a Low logic level

V_IH-- the input voltage that indicates a High logic level

2. Because the GTL and GTLP standards employ open-drain output buffers, V_CCOlines do not supply current to the I/O circuit, rather

this current is provided using an external pull-up resistor connected from the I/O pin to a termination voltage (V_TT). Nevertheless, the

voltage applied to the associated V_CCOlines must always be at or above V_TTand I/O pad voltages.

3. There is approximately 100 mV of hysteresis on inputs using any LVCMOS standard.

4. All Dedicated pins (M0-M2, CCLK, PROG_B, DONE, HSWAP_EN, TCK, TDI, TDO, and TMS) use the LVCMOS25 standard and draw

power from the V_CCAUXrail (2.5V). The Dual-Purpose configuration pins (DIN/D0, D1-D7, CS_B, RDWR_B, BUSY/DOUT, and

INIT_B) use the LVCMOS25 standard before the User mode. For these pins, apply 2.5V to the V_CCOBank 4 and V_CCOBank 5 rails

at power-on as well as throughout configuration. For information concerning the use of 3.3V signals, see the 3.3V-Tolerant

Configuration Interface section in Module 2: Functional Description.

5. The global clock inputs have the following bank associations: GCLK0 and GCLK1 with Bank 4, GCLK2 and GCLK3 with Bank 5,

GCLK4 and GCLK5 with Bank 1, and GCLK6 and GCLK7 with Bank 0. The signal standards assigned to the Global Clock Lines (and

I/Os) of a given bank determine the V_CCOvoltage for that bank.

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 9: DC Characteristics of User I/Os Using Single-Ended Standards

Test Conditions

Logic Level Characteristics

Signal Standard and

Current Drive Attribute

(mA)

I_OL

(mA)

32

I_OH

(mA)

-

V_OL

Max (V)

0.4

V_OH

Min (V)

-

GTL

GTL_DCI

Note 3

36

Note 3

-

GTLP

0.6

0.4

-

GTLP_DCI

Note 3

8

Note 3

–8

HSTL_I

V

_CCO- 0.4

HSTL_I_DCI

HSTL_III

Note 3

24

Note 3

–8

HSTL_III_DCI

HSTL_I_18

HSTL_I_DCI_18

HSTL_II_18

HSTL_II_DCI_18

HSTL_III_18

HSTL_III_DCI_18

LVCMOS12⁽⁴⁾

Note 3

8

Note 3

–8

Note 3

16

Note 3

–16

Note 3

–8

V_CCO- 0.4

_CCO- 0.4

Note 3

24

V

Note 3

2

Note 3

–2

2

4

V_CCO- 0.4

4

–4

6

–6

LVCMOS15⁽⁴⁾

2

–2

0.4

4

–4

6

–6

8

–8

12

–12

Note 3

LVDCI_15,

LVDCI_DV2_15

Note 3

LVCMOS18⁽⁴⁾

2

4

2

–2

–4

0.4

V_CCO- 0.4

4

6

–6

8

–8

12

16

12

–12

–16

Note 3

16

LVDCI_18,

LVDCI_DV2_18

Note 3

LVCMOS25^(4,5)

2

4

2

4

–2

–4

0.4

V_CCO- 0.4

6

–6

8

–8

12

16

24

12

16

24

Note 3

–12

–16

–24

Note 3

LVDCI_25,

LVDCI_DV2_25

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 9: DC Characteristics of User I/Os Using Single-Ended Standards (Continued)

Test Conditions

Logic Level Characteristics

Signal Standard and

Current Drive Attribute

(mA)

I_OL

(mA)

2

I_OH

(mA)

–2

V_OL

Max (V)

0.4

V_OH

Min (V)

LVCMOS33⁽⁴⁾

2

4

V_CCO- 0.4

4

–4

6

–6

8

–8

12

16

24

12

16

24

–12

–16

–24

Note 3

LVDCI_33,

LVDCI_DV2_33

Note 3

LVTTL⁽⁴⁾

2

4

2

4

–2

–4

0.4

2.4

6

–6

8

–8

12

16

24

12

–12

16

–16

24

–24

PCI33_3

Note 6

6.7

Note 6

–6.7

Note 3

–7.5

Note 3

–15

0.10V_CCO

0.90V_CCO

SSTL18_I

SSTL18_I_DCI

SSTL2_I

V_TT- 0.475

V_TT+ 0.475

Note 3

7.5

V

_TT- 0.61

_TT- 0.80

V_TT+ 0.61

V_TT+ 0.80

SSTL2_I_DCI

SSTL2_II

Note 3

15

V

SSTL2_II_DCI

Notes:

Note 3

1. The numbers in this table are based on the conditions set forth in Table 5 and Table 8.

2. Descriptions of the symbols used in this table are as follows:

I_OL-- the output current condition under which V_OLis tested

I_OH-- the output current condition under which V_OHis tested

V_OL-- the output voltage that indicates a Low logic level

V_OH-- the output voltage that indicates a High logic level

V_IL-- the input voltage that indicates a Low logic level

V_IH-- the input voltage that indicates a High logic level

V_CCO-- the supply voltage for output drivers as well as LVCMOS, LVTTL, and PCI inputs

V_REF-- the reference voltage for setting the input switching threshold

V_TT-- the voltage applied to a resistor termination

3. Tested according to the standard’s relevant specifications.

4. For the LVCMOS and LVTTL standards: the same V_OLand V_OHlimits apply for both the Fast and Slow slew attributes.

5. All Dedicated output pins (CCLK, DONE, and TDO) as well as Dual-Purpose totem-pole output pins (D0-D7 and BUSY/DOUT)

exhibit the characteristics of LVCMOS25 with 12 mA drive and Fast slew rate. For information concerning the use of 3.3V signals,

see the 3.3V-Tolerant Configuration Interface section in Module 2: Functional Description.

6. Tested according to the relevant PCI specifications.

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Spartan-3 FPGA Family: DC and Switching Characteristics

V_INP

V_INN

Differential

I/O Pair Pins

P

N

Internal

Logic

V_INN

V

50%

ID

V_INP

V

ICM

GND level

V_INP+ V_INN

V

_ICM= Input common mode voltage =

2

V

V_INP- V_INN

_ID= Differential input voltage =

DS099-3_01_012304

Figure 1: Differential Input Voltages

Table 10: Recommended Operating Conditions for User I/Os Using Differential Signal Standards

(1)

V_CCO

V_ID

V_ICM

V_IH

V_IL

Min

(V)

Nom

(V)

Max

(V)

Min

(mV)

Nom

(mV)

Max

(mV)

Min

(V)

Nom

(V)

Max

(V)

Min

(V)

Max

(V)

Min

(V)

Max

(V)

Signal Standard

LDT_25

2.375

2.50

2.625

200

100

600

350

1000

600

0.44

0.30

0.60

1.25

0.78

2.20

-

LVDS_25,

LVDS_25_DCI

BLVDS_25

2.375

2.50

2.625

-

350

540

-

1.25

1.20

-

LVDSEXT_25,

100

1000

0.30

2.20

LVDSEXT_25_DCI

ULVDS_25

LVPECL_25

RSDS_25

Notes:

2.375

2.50

2.625

200

100

600

-

1000

0.44

0.60

-

0.78

-

0.8

-

2.0

-

0.5

-

1.7

-

200

1.20

1.

V_CCOonly supplies differential output drivers, not input circuits.

2. V_REFinputs are not used for any of the differential I/O standards.

3. V_IDis a differential measurement.

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Spartan-3 FPGA Family: DC and Switching Characteristics

V_OUTP

Differential

I/O Pair Pins

P

N

Internal

Logic

V_OUTN

V_OH

V_OUTN

V_OD

50%

V_OUTP

V_OL

V_OCM

GND level

V_OUTP+ V_OUTN

V

_OCM= Output common mode voltage =

2

V_OUTP- V_OUTN

= Output voltage indicating a High logic level

= Output voltage indicating a Low logic level

V

_OD= Output differential voltage =

V_OH

V_OL

DS099-3_02_012304

Figure 2: Differential Output Voltages

Table 11: DC Characteristics of User I/Os Using Differential Signal Standards

V

∆V

V

∆V

V

OL

OD

OCM

OH

Device

Revision

Min

(mV)

Typ

Max

Min

Max

Min

(V)

Typ

(V)

Max

(V)

Min

(mV)

Max

(mV)

Min

(V)

Max

(V)

Min

(V)

Max

(V)

Signal Standard

LDT_25

(mV) (mV) (mV) (mV)

(3)

(4)

All

430

600

670

600

400

450

600

700

670

-

–15

15

-

0.495

0.80

1.125

-

0.600 0.715

–15

15

-

(3)

LVDS_25

0

100

250

100

330

430

-

1.6

1.375

-

Future

All

-

1.00

1.475

0.925

1.38

BLVDS_25

350

-

1.20

-

(3)

LVDSEXT_25

0

-

0.80

1.125

0.495

-

1.6

-

0.705

-

Future

-

1.375

-

1.700

(3)

ULVDS_25

All

600

-

0.600 0.715

-

(7)

LVPECL_25

All

-

1.35

1.745

0.565 1.005

(3)

RSDS_25

0

100

600

400

-

0.80

1.1

1.6

1.4

-

Future

-

Notes:

1. The numbers in this table are based on the conditions set forth in Table 5 and Table 10.

2. , ∆V , and ∆V are differential measurements.

V

OD

OCM

3. For this standard, to ensure that the FPGA’s output pair meets specifications, it is necessary to set the LVDSBIAS option in the BitGen utility, part of

the Xilinx development software. See XAPP751. The option settings for LVDS_25, LVDSEXT_25, and RSDS_25 are different from those for LDT_25

and ULVDS_25.

4. This value must be compatible with the receiver to which the FPGA’s output pair is connected.

5. Output voltage measurements for all differential standards are made with a termination resistor (R ) of 100Ω across the N and P pins of the differential

T

signal pair.

6. At any given time, only one differential standard may be assigned to each bank.

7. Each LVPECL output-pair requires three external resistors: a 70Ω resistor in series with each output followed by a 240Ω shunt resistor. These are in

addition to the external 100Ω termination resistor at the receiver side. See Figure 3.

70Ω

240Ω

100Ω

70Ω

ds099-3_08_020304

Figure 3: External Terminations for LVPECL

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Spartan-3 FPGA Family: DC and Switching Characteristics

Switching Characteristics

All Spartan-3 devices are available in two speed grades: –4

and the higher performance –5. Switching characteristics in

this document may be designated as Advance, Preliminary,

or Production. Each category is defined as follows:

between speed files and devices over numerous production

lots. There is no under-reporting of delays, and customers

receive formal notification of any subsequent changes. Typ-

ically, the slowest speed grades transition to Production

before faster speed grades.

Advance: These specifications are based on simulations

only and are typically available soon after establishing

FPGA specifications. Although speed grades with this des-

ignation are considered relatively stable and conservative,

some under-reporting might still occur. All –5 grade num-

bers are engineering targets: characterization is still in

progress.

All specified limits are representative of worst-case supply

voltage and junction temperature conditions. Unless other-

wise noted, the following applies: Parameter values apply to

all Spartan-3 devices. All parameters representing voltages

are measured with respect to GND.

Timing parameters and their representative values are

selected for inclusion below either because they are impor-

tant as general design requirements or they indicate funda-

mental device performance characteristics. The Spartan-3

speed files (V1.29), part of the Xilinx Development Soft-

ware, are the original source for many but not all of the val-

ues. For more complete, more precise, and worst-case

data, use the values reported by the Xilinx static timing ana-

lyzer (TRACE in the Xilinx development software) and

back-annotated to the simulation netlist.

Preliminary: These specifications are based on complete

early silicon characterization. Devices and speed grades

with this designation are intended to give a better indication

of the expected performance of production silicon. The

probability of under-reporting preliminary delays is greatly

reduced compared to Advance data.

Production: These specifications are approved once

enough production silicon of a particular device family mem-

ber has been characterized to provide full correlation

10

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Spartan-3 FPGA Family: DC and Switching Characteristics

I/O Timing

Table 12: Pin-to-Pin Clock-to-Output Times for the IOB Output Path

Speed Grade

-5

-4

Symbol

Description

Conditions

Device

XC3S50

Max

Units

Clock-to-Output Times

T_ICKOFDCM

When reading from the

Output Flip-Flop (OFF), the

time from the active

transition on the Global

Clock pin to data appearing

at the Output pin. The DCM

is in use.

LVCMOS25⁽²⁾, 12mA

output drive, Fast slew

rate, with DCM⁽³⁾

2.59

2.60

5.37

5.39

5.42

5.51

5.65

5.83

5.95

6.19

ns

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

XC3S50

T_ICKOF

When reading from OFF, the LVCMOS25⁽²⁾, 12mA

time from the active

transition on the Global

Clock pin to data appearing

at the Output pin. The DCM

is not in use.

output drive, Fast slew

rate, without DCM

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

Notes:

1. The numbers in this table are tested using the methodology presented in Table 20 and are based on the operating conditions set

forth in Table 5 and Table 8.

2. This clock-to-output time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock

Input or a standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the data Output. If the former is true,

add the appropriate Input adjustment from Table 16. If the latter is true, add the appropriate Output adjustment from Table 19.

3. DCM output jitter is included in all measurements.

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 13: Pin-to-Pin Setup and Hold Times for the IOB Input Path

Speed Grade

-5

-4

Symbol

Setup Times

T_PSDCM

Description

Conditions

Device

XC3S50

Min

Units

When writing to the Input LVCMOS25⁽²⁾

,

2.72

2.74

2.76

2.86

2.98

3.06

3.23

2.43

3.53

3.52

3.77

4.15

4.34

4.53

4.90

ns

Flip-Flop (IFF), the time IOBDELAY = NONE⁽⁴⁾

from the setup of data at with DCM⁽⁵⁾

the Input pin to the active

,

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

XC3S50

transition at a Global

Clock pin. The DCM is in

use.

T_PSFD

When writing to IFF, the LVCMOS25⁽²⁾

,

time from the setup of

data at the Input pin to

an active transition at the

Global Clock pin. The

DCM is not in use.

IOBDELAY = NONE⁽⁴⁾

without DCM

,

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

Hold Times

XC3S50

T_PHDCM

When writing to IFF, the LVCMOS25⁽³⁾

,

–1.81

–1.80

–1.03

–1.89

–1.87

–2.01

–2.20

–2.24

–2.32

ns

time from the active

transition at the Global

Clock pin to the point

when data must be held

at the Input pin. The

DCM is in use.

IOBDELAY= NONE⁽⁴⁾

with DCM⁽⁵⁾

,

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

XC3S50

T_PHFD

When writing to IFF, the LVCMOS25⁽³⁾

,

time from the active

transition at the Global

Clock pin to the point

when data must be held

at the Input pin. The

DCM is not in use.

IOBDELAY = NONE⁽⁴⁾

without DCM

,

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

Notes:

1. The numbers in this table are tested using the methodology presented in Table 20 and are based on the operating conditions set

forth in Table 5 and Table 8.

2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the

data Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 16. If this is true of the data Input,

add the appropriate input adjustment from the same table.

3. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the

data Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 16. If this is true of the data Input,

subtract the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data

before the clock’s active edge.

4. All numbers measured with no programmed input delay.

5. DCM output jitter is included in all measurements.

12

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Speed Grade

Table 14: Setup and Hold Times for the IOB Input Path

-5

-4

Symbol

Setup Times

T_IOPICK

Description

Conditions

Device

Min

Units

Time from the setup of data LVCMOS25⁽²⁾

,

1.15

1.32

ns

All

at the Input pin to the active IOBDELAY = NONE

transition at the ICLK input

of the Input Flip-Flop (IFF).

No input delay is

programmed.

XC3S50

T_IOPICKD

Time from the setup of data LVCMOS25⁽²⁾

at the Input pin to the active IOBDELAY = IFD

transition at the IFF’s ICLK

input. The input delay is

,

3.26

3.89

4.15

4.32

4.50

4.67

5.02

3.75

4.47

4.77

4.97

5.17

5.37

5.77

ns

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

programmed.

Hold Times

LVCMOS25⁽³⁾

,

–0.66

ns

All

T_IOICKP

Time from the active

transition at the IFF’s ICLK IOBDELAY = NONE

input to the point where

data must be held at the

Input pin. No input delay is

programmed.

LVCMOS25⁽³⁾

,

–2.36

–2.87

–3.08

–3.22

–3.36

–3.50

–3.78

ns

XC3S50

T_IOICKPD

Time from the active

transition at the IFF’s ICLK IOBDELAY = IFD

input to the point where

data must be held at the

Input pin. The input delay is

programmed.

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

Notes:

1. The numbers in this table are tested using the methodology presented in Table 20 and are based on the operating conditions set

forth in Table 5 and Table 8.

2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true,

add the appropriate Input adjustment from Table 16.

3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true,

subtract the appropriate Input adjustment from Table 16. When the hold time is negative, it is possible to change the data before the

clock’s active edge.

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 15: Propagation Times for the IOB Input Path

Speed Grade

-5

-4

Symbol

Description

Conditions

Device

Max

Units

Propagation Times

The time it takes for data LVCMOS25⁽²⁾

,

1.05

1.20

ns

All

T_IOPI

to travel from the Input

pin to the IOB’s I output

with no input delay

programmed

IOBDELAY = NONE

XC3S50

T_IOPID

The time it takes for data LVCMOS25⁽²⁾

,

3.16

3.79

4.05

4.22

4.40

4.57

4.92

1.55

3.63

4.35

4.65

4.85

5.05

5.25

5.65

1.78

ns

to travel from the Input

pin to the I output with the

Input delay programmed

IOBDELAY = IFD

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

All

T_IOPLI

The time it takes for data LVCMOS25⁽²⁾

,

to travel from the Input

pin through the IFF latch

to the I output with no

input delay programmed

IOBDELAY = NONE

XC3S50

T_IOPLID

The time it takes for data LVCMOS25⁽²⁾

,

3.66

4.29

4.55

4.73

4.90

5.07

5.42

4.21

4.93

5.23

5.43

5.63

5.83

6.23

ns

to travel from the Input

pin through the IFF latch

to the I output with the

input delay programmed

IOBDELAY = IFD

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

Notes:

1. The numbers in this table are tested using the methodology presented in Table 20 and are based on the operating conditions set forth

in Table 5 and Table 8.

2. This propagation time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. When

this is true, add the appropriate Input adjustment from Table 16.

14

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 16: Input Timing Adjustments for IOB (Continued)

Table 16: Input Timing Adjustments for IOB

Add the

Adjustment Below

Add the

Adjustment Below

Convert Input Time from

Speed Grade

LVCMOS25 to the

Following Signal Standard

-5

-4

Units

ns

Following Signal Standard

Single-Ended Standards

GTL, GTL_DCI

-5

-4

Units

PCI33_3

0.32

SSTL18_I, SSTL18_I_DCI

SSTL2_I, SSTL2_I_DCI

SSTL2_II, SSTL2_II_DCI

Differential Standards

LDT_25

–0.17

–0.19

–0.21

–0.17

–0.19

–0.21

ns

–0.37

–0.18

–0.19

–0.26

–0.37

–0.18

–0.19

–0.26

ns

GTLP, GTLP_DCI

ns

HSTL_I, HSTL_I_DCI

HSTL_III, HSTL_III_DCI

0.04

0.06

0.04

0.06

ns

HSTL_I_18,

HSTL_I_DCI_18

LVDS_25, LVDS_25_DCI

BLVDS_25

HSTL_II_18,

HSTL_II_DCI_18

–0.26

–0.20

–0.26

–0.20

ns

LVDSEXT_25,

LVDSEXT_25_DCI

HSTL_III_18,

HSTL_III_DCI_18

ULVDS_25

LVPECL_25

RSDS_25

Notes:

–0.05

ns

LVCMOS12

0.40

0.47

0.40

0.47

ns

LVCMOS15, LVDCI_15,

LVDCI_DV2_15

LVCMOS18, LVDCI_18,

LVDCI_DV2_18

0.30

0

0.30

0

ns

1. The numbers in this table are tested using the methodology

presented in Table 20 and are based on the operating

conditions set forth in Table 5, Table 8, and Table 10.

2. These adjustments are used to convert input path times

originally specified for the LVCMOS25 standard to times that

correspond to other signal standards.

LVCMOS25, LVDCI_25,

LVDCI_DV2_25

LVCMOS33, LVDCI_33,

LVDCI_DV2_33

0.09

–0.31

0.09

–0.31

LVTTL

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 17: Timing for the IOB Output Path

Speed Grade

-5

-4

Symbol

Description

Conditions

Max

Units

Clock-to-Output Times

T_IOCKP

When reading from the

Output Flip-Flop (OFF), the

LVCMOS25⁽²⁾, 12mA

output drive, Fast slew

3.64

4.18

ns

time from the active transition rate

at the OTCLK input to data

appearing at the Output pin

Propagation Times

T_IOOP

The time it takes for data to

travel from the IOB’s O input output drive, Fast slew

to the Output pin

LVCMOS25⁽²⁾, 12mA

2.97

3.41

3.42

3.92

ns

rate

T_IOOLP

The time it takes for data to

travel from the O input

through the OFF latch to the

Output pin

Set/Reset Times

T_IOSRP

Time from asserting the

OFF’s SR input to

setting/resetting data at the

Output pin

LVCMOS25⁽²⁾, 12mA

output drive, Fast slew

rate

4.44

8.07

5.10

9.28

ns

T_IOGSRQ

Time from asserting the

Global Set Reset (GSR) net

to setting/resetting data at

the Output pin

Notes:

1. The numbers in this table are tested using the methodology presented in Table 20 and are based on the operating conditions set

forth in Table 5 and Table 8.

2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned

to the data Output. When this is true, add the appropriate Output adjustment from Table 19.

16

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Speed Grade

Table 18: Timing for the IOB Three-State Path

-5

-4

Symbol

Synchronous Output Enable/Disable Times

T_IOCKHZTime from the active transition at LVCMOS25, 12mA

Description

Conditions

Max

Units

2.32

2.66

ns

the OTCLK input of the

output drive, Fast

slew rate

Three-state Flip-Flop (TFF) to

when the Output pin enters the

high-impedance state

(2)

T_IOCKON

Time from the active transition at

TFF’s OTCLK input to when the

Output pin drives valid data

3.78

7.03

4.34

8.08

ns

Asynchronous Output Enable/Disable Times

T_GTS

Time from asserting the Global

Three State net (GTS) net to

when the Output pin enters the

high-impedance state

LVCMOS25, 12mA

output drive, Fast

slew rate

Set/Reset Times

T_IOSRHZ

Time from asserting TFF’s SR

input to when the Output pin

enters a high-impedance state

LVCMOS25, 12mA

output drive, Fast

slew rate

3.28

4.75

3.77

5.45

ns

(2)

T_IOSRON

Time from asserting TFF’s SR

input at TFF to when the Output

pin drives valid data

Notes:

1. The numbers in this table are tested using the methodology presented in Table 20 and are based on the operating conditions set

forth in Table 5 and Table 8.

2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned

to the data Output. When this is true, add the appropriate Output adjustment from Table 19.

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 19: Output Timing Adjustments for IOB (Continued)

Table 19: Output Timing Adjustments for IOB

Add the

Adjustment

Add the

Adjustment

Below

Convert Output Time from

LVCMOS25 with 12mA Drive and

Fast Slew Rate to the Following

Signal Standard

Below

Convert Output Time from

LVCMOS25 with 12mA Drive and

Fast Slew Rate to the Following

Signal Standard

Speed Grade

-5

-4

Units

ns

-5

-4

Units

LVCMOS18

Slow

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

4.31

2.69

2.23

1.83

1.97

1.62

2.07

0.90

0.77

0.61

0.56

0.50

0.72

0.58

5.11

3.17

2.53

2.21

1.79

1.77

1.53

2.30

0.87

0.30

0.21

0

4.31

2.69

2.23

1.83

1.97

1.62

2.07

0.90

0.77

0.61

0.56

0.50

0.72

0.58

5.11

3.17

2.53

2.21

1.79

1.77

1.53

2.30

0.87

0.30

0.21

0

Single-Ended Standards

GTL

–0.18

–0.15

–0.13

0.08

0.07

–0.05

0.14

0

–0.18

–0.15

–0.13

0.08

0.07

–0.05

0.14

0

ns

GTL_DCI

GTLP

GTLP_DCI

HSTL_I

Fast

HSTL_I_DCI

HSTL_III

HSTL_III_DCI

HSTL_I_18

HSTL_I_DCI_18

HSTL_II_18

HSTL_II_DCI_18

HSTL_III_18

HSTL_III_DCI_18

–0.13

0.31

–0.02

–0.03

6.47

6.70

5.60

3.04

2.25

2.10

3.95

3.49

2.85

3.44

2.82

2.29

1.37

1.15

1.13

1.00

1.34

1.14

–0.13

0.31

–0.02

–0.03

6.47

6.70

5.60

3.04

2.25

2.10

3.95

3.49

2.85

3.44

2.82

2.29

1.37

1.15

1.13

1.00

1.34

1.14

LVDCI_18

LVDCI_DV2_18

LVCMOS25

Slow

2 mA

4 mA

LVCMOS12

Slow

Fast

Slow

2 mA

4 mA

6 mA

2 mA

4 mA

6 mA

2 mA

4 mA

6 mA

8 mA

12 mA

2 mA

4 mA

6 mA

8 mA

12 mA

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

Fast

LVCMOS15

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

0.11

0.04

0.19

0.10

0.11

0.04

0.19

0.10

Fast

LVDCI_25

LVDCI_DV2_25

LVDCI_15

LVDCI_DV2_15

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 19: Output Timing Adjustments for IOB (Continued)

Add the

Adjustment

Below

Convert Output Time from

LVCMOS25 with 12mA Drive and

Fast Slew Rate to the Following

Signal Standard

Convert Output Time from

LVCMOS25 with 12mA Drive and

Fast Slew Rate to the Following

Signal Standard

Speed Grade

-5

6.22

3.80

3.02

3.04

2.18

2.05

1.82

3.15

1.30

0.53

0.54

0.14

0.08

–0.03

0

-4

6.22

3.80

3.02

3.04

2.18

2.05

1.82

3.15

1.30

0.53

0.54

0.14

0.08

–0.03

0

Units

ns

-5

-4

Units

ns

LVCMOS33

Slow

2 mA

4 mA

PCI33_3

–0.26

–0.05

–0.01

0.08

–0.26

–0.05

–0.01

0.08

SSTL18_I

ns

6 mA

SSTL18_I_DCI

SSTL2_I

ns

8 mA

ns

12 mA

16 mA

24 mA

2 mA

SSTL2_I_DCI

SSTL2_II

0.01

ns

–0.04

–0.14

–0.04

–0.14

ns

SSTL2_II_DCI

Differential Standards

LDT_25

ns

Fast

4 mA

–0.52

–0.50

–0.52

–0.50

ns

6 mA

LVDS_25

8 mA

LVDS_25_DCI

BLVDS_25

12 mA

16 mA

24 mA

–0.01

–0.50

–0.01

–0.50

LVDSEXT_25

LVDSEXT_25_DCI

ULVDS_25

LVDCI_33

LVDCI_DV2_33

LVTTL

–0.48

0

LVPECL_25

RSDS_25

Slow

2 mA

4 mA

6.24

3.81

3.03

3.02

2.17

2.05

1.88

3.14

1.31

0.50

0.51

0.12

0.06

0

6.24

3.81

3.03

3.02

2.17

2.05

1.88

3.14

1.31

0.50

0.51

0.12

0.06

0

Notes:

1. The numbers in this table are tested using the methodology

presented in Table 20 and are based on the operating

conditions set forth in Table 5, Table 8, and Table 10.

2. These adjustments are used to convert output- and

three-state-path times originally specified for the LVCMOS25

standard with 12 mA drive and Fast slew rate to times that

correspond to other signal standards. Do not adjust times

that measure when outputs go into a high-impedance state.

6 mA

8 mA

12 mA

16 mA

24 mA

2 mA

Fast

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

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Spartan-3 FPGA Family: DC and Switching Characteristics

LVTTL), then R_Tis set to 1MΩ to indicate an open connec-

tion, and V_Tis set to zero. The same measurement point

(V_M) that was used at the Input is also used at the Output.

Timing Measurement Methodology

When measuring timing parameters at the programmable

I/Os, different signal standards call for different test condi-

tions. Table 20 presents the conditions to use for each stan-

dard.

V (V

)

T

REF

The method for measuring Input timing is as follows: A sig-

nal that swings between a Low logic level of V_Land a High

logic level of V_His applied to the Input under test. Some

standards also require the application of a bias voltage to

the V_REFpins of a given bank to properly set the

input-switching threshold. The measurement point of the

Input signal (V_M) is commonly located halfway between V_L

and V_H.

FPGA Output

R (R

T

)

REF

V

(V

)

M

MEAS

C (C

)

L

REF

ds099-3_07_012004

Notes:

The Output test setup is shown in Figure 4. A termination

voltage V_Tis applied to the termination resistor R_T, the other

end of which is connected to the Output. For each standard,

R_Tand V_Tgenerally take on the standard values recom-

mended for minimizing signal reflections. If the standard

does not ordinarily use terminations (e.g., LVCMOS,

1. The names shown in parentheses are

used in the IBIS file.

Figure 4: Output Test Setup

Table 20: Test Methods for Timing Measurement at I/Os

Inputs and

Inputs

Outputs

V_REF

(V)

V_L

V_H

(V)

R_T

V_T

V_M

Signal Standard

Single-Ended

GTL

(V)

(Ω)

(V)

0.8

1.0

V_REF- 0.2

V_REF+ 0.2

V_REF+ 0.5

25

50

25

50

25

50

1M

1.2

1.5

0.75

1.5

0.9

1.8

0

V_REF

GTL_DCI

GTLP

V_REF- 0.2

GTLP_DCI

HSTL_I

0.75

0.90

1.1

V_REF- 0.5

HSTL_I_DCI

HSTL_III

V

_REF- 0.5

HSTL_III_DCI

HSTL_I_18

HSTL_I_DCI_18

HSTL_II_18

HSTL_II_DCI_18

HSTL_III_18

HSTL_III_DCI_18

LVCMOS12

LVCMOS15

LVDCI_15

V_REF- 0.5

V

_REF- 0.5

-

0

1.2

1.5

0

0.75

0

LVDCI_DV2_15

0

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 20: Test Methods for Timing Measurement at I/Os (Continued)

Inputs and

Outputs

Inputs

Outputs

V_REF

(V)

-

V_L

(V)

0

V_H

(V)

1.8

R_T

(Ω)

1M

25

V_T

(V)

0

V_M

(V)

0.9

Signal Standard

LVCMOS18

LVDCI_18

0

LVDCI_DV2_18

LVCMOS25

LVDCI_25

0

-

0

2.5

3.3

0

1.25

1.65

0

LVDCI_DV2_25

LVCMOS33

LVDCI_33

0

LVDCI_DV2_33

LVTTL

0

-

0

3.3

0

1.4

0.94

2.03

V_REF

PCI33_3

Rising

Falling

Note 2

0

25

3.3

0.9

1.25

SSTL18_I

0.9

V

_REF- 0.5

V_REF+ 0.5

V_REF+ 0.75

50

SSTL18_I_DCI

SSTL2_I

50

1.25

V

_REF- 0.75

50

V_REF

SSTL2_I_DCI

SSTL2_II

50

25

V_REF

SSTL2_II_DCI

Differential

LDT_25

50

-

0.6 - 0.125

1.2 - 0.125

0.6 + 0.125

1.2 + 0.125

60

50

1M

50

-

0.6

1.2

0

0.6

1.2

LVDS_25

LVDS_25_DCI

BLVDS_25

LVDSEXT_25

LVDSEXT_25_DCI

ULVDS_25

LVPECL_25

RSDS_25

-

1.2 - 0.125

1.2 + 0.125

0

1.2

-

0.6 - 0.125

1.6 - 0.3

0.6 + 0.125

1.6 + 0.3

1.3 + 0.1

60

1M

50

0.6

0

0.6

1.6

1.2

1.3 - 0.1

1.2

Notes:

1. Descriptions of the relevant symbols are as follows:

V_REF-- The reference voltage for setting the input switching threshold

_M-- Voltage of measurement point on signal transition

V

V_L-- Low-level test voltage at Input pin

V_H-- High-level test voltage at Input pin

R_T-- Effective termination resistance, which takes on a value of 1MΩ when no parallel termination is required

V_T-- Termination voltage

C_L-- Load capacitance at Output pin, which is 0 pF for all standards

2. According to the PCI specification.

DS099-3 (v1.3) March 4, 2004

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Spartan-3 FPGA Family: DC and Switching Characteristics

The capacitive load (C_L) is connected between the output

and GND. The Output timing for all standards, as published

in the speed files and the data sheet, is always based on a

C_Lvalue of zero unless otherwise specified. High-imped-

ance probes (less than 1 pF) are used for all measure-

ments. Any delay that the test fixture might contribute to test

measurements is subtracted from those measurements to

produce the final timing numbers as published in the speed

files and data sheet.

IBIS models are found at the following link:

http://www.xilinx.com/support/sw_ibis.htm

Simulate delays for a given application according to its spe-

cific load conditions as follows:

1. Simulate the desired signal standard with the output

driver connected to the test setup shown in Figure 4.

Use parameter values V_T, R_T, C_L, and V_Mfrom

Table 20.

2. Record the time to V_M.

Using IBIS Models to Simulate Load

Conditions in Application

3. Simulate the same signal standard with the output

driver connected to the PCB trace with load. Use the

IBIS Models permit the most accurate prediction of timing

delays for a given application. The parameters found in the

IBIS model (V_REF, R_REF, C_REF, and V_MEAS) correspond

directly with the parameters used in Table 20, V_T, R_T, C_L,

and V_M. Do not confuse V_REF(the termination voltage) from

the IBIS model with V_REF(the input-switching threshold)

from the table! The four parameters describe all relevant

output test conditions.

appropriate IBIS model (including V_REF, R_REF, C_REF

and V_MEASvalues) or capacitive value to represent the

load.

,

4. Record the time to V_MEAS

.

5. Compare the results of steps 2 and 4. The increase (or

decrease) in delay should be added to (or subtracted

from) the appropriate Output standard adjustment

(Table 19) to yield the worst-case delay of the PCB

trace.

Simultaneously Switching Output Guidelines

Table 21: Equivalent V_CCO/GND Pairs per Bank

Device

XC3S50

VQ100

TQ144

PQ208

FT256

FG320

FG456

FG676

FG900

FG1156

1

-

1

-

2

-

3

-

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

3

-

5

-

5

6

-

9

10

-

12

-

22

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 22: Maximum Number of Simultaneously

Switching Outputs per V_CCO-GND Pair (Continued)

Table 22: Maximum Number of Simultaneously

Switching Outputs per V_CCO-GND Pair

Package

FT256,

FG320,

FG456,

FG676,

FG900,

FG1156

FT256,

FG320,

FG456,

FG676,

FG900,

FG1156

VQ100,

TQ144,

PQ208

VQ100,

TQ144,

PQ208

Signal Standard

Single-Ended Standards

GTL

LVCMOS18

Slow

2

4

64

34

22

18

13

10

36

21

13

10

9

4

3

6

GTLP_DCI

8

GTLP

4

12

16

2

GTLP_DCI

3

HSTL_I

17

7

Fast

HSTL_I_DCI

HSTL_III

4

6

HSTL_III_DCI

HSTL_I_18

7

8

17

12

16

HSTL_I_DCI_18

HSTL_II_18

HSTL_II_DCI_18

HSTL_III_18

HSTL_III_DCI_18

6

9

8

LVDCI_18

11

6

LVDCI_DV2_18

LVCMOS25

Slow

2

4

76

46

33

24

18

11

7

LVCMOS12

Slow

Fast

Slow

2

4

55

32

18

31

13

9

6

8

6

12

16

24

2

4

6

Fast

42

20

15

13

11

8

LVCMOS15

2

55

31

18

15

10

25

16

13

11

7

4

6

8

12

16

24

12

2

Fast

5

4

LVDCI_25

13

7

6

LVDCI_DV2_25

8

12

LVDCI_15

10

5

LVDCI_DV2_15

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 22: Maximum Number of Simultaneously

Switching Outputs per V_CCO-GND Pair (Continued)

Table 22: Maximum Number of Simultaneously

Switching Outputs per V_CCO-GND Pair (Continued)

Package

FT256,

FG320,

FG456,

FT256,

FG320,

FG456,

VQ100,

TQ144,

PQ208

FG676,

FG900,

FG1156

VQ100,

TQ144,

PQ208

FG676,

FG900,

FG1156

Signal Standard

LVCMOS33⁽¹⁾Slow

Signal Standard

PCI33_3⁽¹⁾

2

4

76

46

27

20

13

10

9

SSTL18_I

17

6

SSTL18_I_DCI

SSTL2_I

8

13

15

9

12

16

24

2

SSTL2_I_DCI

SSTL2_II

SSTL2_II_DCI

Differential Standards

LDT_25

5

Fast

44

26

16

12

10

7

4

LVDS_25

6

LVDS_25_DCI

BLVDS_25

8

12

16

24

LVDSEXT_25

LVDSEXT_25_DCI

ULVDS_25

3

LVDCI_33⁽¹⁾

LVDCI_DV2_33⁽¹⁾

13

7

LVPECL_25

RSDS_25

LVTTL⁽¹⁾

Slow

2

4

60

41

29

22

13

11

9

Notes:

1. The numbers in this table are recommendations that assume

sound board layout practice. For cases that exceed these

maximum numbers, perform IBIS simulations to confirm

signal integrity.

6

8

12

16

24

2

Fast

34

20

15

12

10

9

4

6

8

12

16

24

5

24

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Spartan-3 FPGA Family: DC and Switching Characteristics

Core Logic Timing

Table 23: CLB Timing

Speed Grade

-5

-4

Symbol

Description

Min

Max

Min

Max

Units

Clock-to-Output Times

T_CKO

When reading from the FFX (FFY) Flip-Flop,

the time from the active transition at the CLK

input to data appearing at the XQ (YQ) output

-

0.67

-

0.77

ns

Setup Times

T_DYCK

Time from the setup of data at the D input to

the active transition at the CLK input of FFX

0.08

-

0.09

-

ns

T_DXCK

Time from the setup of data at the D input to

the active transition at the CLK input of FFY

Hold Times

T_CKDY

Time from the active transition at FFY’s CLK

input to the point where data is last held at the

D input

0.01

-

0.01

-

ns

T_CKDX

Time from the active transition at FFX’s CLK

input to the point where data is last held at the

D input

Clock Timing

T_CH

The High pulse width of the CLB’s CLK signal

The Low pulse width of the CLK signal

0.76

-

0.87

-

ns

T_CL

F_TOG

Maximum toggle frequency (for export control)

500

MHz

Propagation Times

T_ILO

The time it takes for data to travel from the

CLB’s F (G) input to input to the X (Y) output

-

0.65

-

0.75

ns

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 5.

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 24: Synchronous 18 x 18 Multiplier Timing

Speed Grade

-5

-4

Symbol

Description

P Outputs

Min

Max

Min

Max

Units

Clock-to-Output Times

T_MULTCK

When reading from the

Multiplier, the time from the

active transition at the C

clock input to data

P[0]

-

0.76

0.97

1.17

1.37

1.78

2.59

3.00

-

0.88

1.11

1.34

1.58

2.04

2.97

3.44

ns

P[15]

P[17]

P[19]

P[23]

P[31]

P[35]

appearing at the P outputs

Setup Times

T_MULIDCK

Time from the setup of data

at the A and B inputs to the

active transition at the C

input of the Multiplier

-

2.18

-

2.50

-

ns

Hold Times

T_MULCKID

Time from the active

transition at the Multiplier’s

C input to the point where

data is last held at the A

and B inputs

-

0

-

0

-

ns

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 5.

Table 25: Asynchronous 18 x 18 Multiplier Timing

Speed Grade

-5 -4

Symbol

Description

P Outputs

Max

Units

Propagation Times

T_MULT

The time it takes for data to travel

from the A and B inputs to the P

outputs

P[0]

1.25

2.88

3.10

3.32

3.75

4.62

5.06

1.44

3.31

3.56

3.81

4.31

5.31

5.81

ns

P[15]

P[17]

P[19]

P[23]

P[31]

P[35]

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 5.

26

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Spartan-3 FPGA Family: DC and Switching Characteristics

Speed Grade

Table 26: Block RAM Timing

-5

-4

Symbol

Description

Min

Max

Min

Max

Units

Clock-to-Output Times

T_BCKO

When reading from the Block

-

2.10

-

2.41

ns

RAM, the time from the active

transition at the CLK input to

data appearing at the DOUT

output

Setup Times

T_BDCK

Time from the setup of data at

the DIN inputs to the active

transition at the CLK input of the

Block RAM

0.43

-

0.49

-

ns

Hold Times

T_BCKD

Time from the active transition

at the Block RAM’s CLK input to

the point where data is last held

at the DIN inputs

0

Clock Timing

T_BPWH

The High pulse width of the

Block RAM’s CLK signal

1.26

-

1.44

-

ns

T_BPWL

The Low pulse width of the CLK

signal

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 5.

DS099-3 (v1.3) March 4, 2004

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Spartan-3 FPGA Family: DC and Switching Characteristics

Digital Clock Manager (DCM) Timing

For specification purposes, the DCM consists of three key

components: the Delay-Locked Loop (DLL), the Digital Fre-

quency Synthesizer (DFS), and the Phase Shifter (PS).

only employs the DLL component. When the DFS and/or

the PS components are used together with the DLL, then

the specifications listed in the DFS and PS tables (Table 29

through Table 32) supersede any corresponding ones in the

DLL tables. DLL specifications that do not change with the

addition of DFS or PS functions are presented in Table 27

and Table 28.

Aspects of DLL operation play a role in all DCM applica-

tions. All such applications inevitably use the CLKIN and the

CLKFB inputs connected to either the CLK0 or the CLK2X

feedback, respectively. Thus, specifications in the DLL

tables (Table 27 and Table 28) apply to any application that

Table 27: Recommended Operating Conditions for the DLL

Speed Grade

Frequency

Mode/

-5

-4

Device

Symbol

Input Frequency Ranges

F_CLKIN

Description

F_CLKINRange

Revision

Min

Max

Min

Max Units

(2)

24

Frequency for the

CLKIN input

Low

All

0

165⁽³⁾

280⁽³⁾

326

24

48

165⁽³⁾MHz

280⁽³⁾MHz

CLKIN_FREQ_DLL_LF

High

48

CLKIN_FREQ_DLL_HF

Future

TBD

MHz

Input Pulse Requirements

CLKIN_PULSE

CLKIN pulse width as

a percentage of the

CLKIN period

All

0

45%

40%

45%

55%

60%

55%

45%

40%

45%

55%

60%

55%

-

F_CLKIN< 200 MHz

Future

F

_CLKIN> 200 MHz

Input Clock Jitter and Delay Path Variation

Cycle-to-cycle jitter at

the CLKIN input

Low

High

Low

High

All

-300

-150

-1

+300

+150

+1

-300

-150

-1

+300

+150

+1

ps

ns

CLKIN_CYC_JITT_DLL_LF

CLKIN_CYC_JITT_DLL_HF

CLKIN_CYC_PER_DLL_LF

CLKIN_CYC_PER_DLL_HF

CLKFB_DELAY_VAR_EXT

Period jitter at the

CLKIN input

-1

+1

-1

+1

Allowable variation of

off-chipfeedbackdelay

from the DCM output

to the CLKFB input

-1

+1

-1

+1

Notes:

1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.

2. Use of the DFS permits lower F_CLKINfrequencies. See Table 29.

3. To double the maximum effective F_CLKINlimit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE.

28

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Spartan-3 FPGA Family: DC and Switching Characteristics

Speed Grade

Table 28: Switching Characteristics for the DLL

-5

-4

Frequency Mode /

F_CLKINRange

Device

Revision

Symbol

Description

Min Max Min Max Units

Output Frequency Ranges

CLKOUT_FREQ_1X_LF

Frequency for the

CLK0, CLK90,

CLK180, and

Low

All

24

165

24

165 MHz

CLK270 outputs

CLKOUT_FREQ_1X_HF

Frequency for the

CLK0 and CLK180

outputs

High

0

Nophase 48

shifting

280

200

48

280 MHz

200 MHz

Phase

48

shifting

Future

48

326

330

48

TBD MHz

330 MHz

CLKOUT_FREQ_2X_LF

Frequency for the

CLK2X and

Low

0⁽³⁾

Future

CLK2X180 outputs

CLKOUT_FREQ_DV_LF

CLKOUT_FREQ_DV_HF

Output Clock Jitter

Frequency for the

CLKDV output

Low

All

1.5

3

100

215

1.5

3

100 MHz

215 MHz

High

CLKOUT_PER_JITT_0

Period jitter at the

CLK0 output

All

-100 +100 -100 +100

-150 +150 -150 +150

-200 +200 -200 +200

ps

CLKOUT_PER_JITT_90

CLKOUT_PER_JITT_180

CLKOUT_PER_JITT_270

CLKOUT_PER_JITT_2X

Period jitter at the

CLK90 output

Period jitter at the

CLK180 output

Period jitter at the

CLK270 output

Period jitter at the

CLK2X and

CLK2X180 outputs

CLKOUT_PER_JITT_DV1

CLKOUT_PER_JITT_DV2

Period jitter at the

CLKDV output

when performing

integer division

-150 +150 -150 +150

-300 +300 -300 +300

ps

Period jitter at the

CLKDV output

when performing

non-integer

division

Duty Cycle

CLKOUT_DUTY_CYCLE_DLL⁽⁴⁾Duty cycle

variation for the

All

-150 +150 -150 +150

ps

CLK0, CLK90,

CLK180, CLK270,

CLK2X,

CLK2X180, and

CLKDV outputs

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 28: Switching Characteristics for the DLL (Continued)

Speed Grade

-5 -4

Min Max Min Max Units

Frequency Mode /

F_CLKINRange

Device

Revision

Symbol

Phase Alignment

Description

CLKIN_CLKFB_PHASE

Phase offset

between the

CLKIN and CLKFB

inputs

All

-50

+50 -50

+50

ps

CLKOUT_PHASE

Phase offset

All

-140 +140 -140 +140

between any DLL

output and any

other DCM outputs

Lock Time

LOCK_DLL_24_30

LOCK_DLL_30_40

LOCK_DLL_40_50

LOCK_DLL_50_60

LOCK_DLL_60

Delay Lines

Time required to

achieve lock

24 MHz < F_CLKIN< 30 MHz

30 MHz < F_CLKIN< 40 MHz

40 MHz < F_CLKIN< 50 MHz

50 MHz < F_CLKIN< 60 MHz

All

-

960

720

400

200

160

-

960

720

400

200

160

µs

F

_CLKIN> 60 MHz

DCM_TAP

Delay tap

resolution

All

30.0 60.0 30.0 60.0

ps

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 5 and Table 27.

2. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.

3. For Rev. 0 devices only, use feedback from the CLK0 output (instead of the CLK2X output) and set the CLK_FEEDBACK attribute to

1X.

4. This specification only applies if the attribute DUTY_CYCLE_CORRECTION = TRUE.

30

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 29: Recommended Operating Conditions for the DFS

Speed Grade

-5

-4

Frequency

Symbol

Description

Mode

Min

Max

Min

Max

Units

Input Frequency Ranges⁽²⁾

F_CLKIN

CLK_FREQ_FX

Frequency for the

CLKIN input

Low

1

210

280

1

210

280

MHz

CLK_FREQ_FX_HF

High

48

Input Clock Jitter

CLKIN_CYC_JITT_FX_LF

CLKIN_CYC_JITT_FX_HF

CLKIN_CYC_PER_FX_LF

CLKIN_CYC_PER_FX_HF

Notes:

Cycle-to-cycle jitter at

the CLKIN input

Low

High

Low

High

-300

-150

-1

+300

+150

+1

-300

-150

-1

+300

+150

+1

ps

ns

Period jitter at the

CLKIN input

-1

+1

-1

+1

1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are in use.

2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 27.

Table 30: Switching Characteristics for the DFS

Speed Grade

-5

-4

Frequency

Mode

Device

Revision

Symbol

Description

Min

Max

Min

Max

Units

Output Frequency Ranges

CLKOUT_FREQ_FX_LF

CLKOUT_FREQ_FX_HF

Frequency for the CLKFX

and CLKFX180 outputs

Low

All

0

24

210

280

326

24

210

280

TBD

MHz

High

210

Future

Output Clock Jitter

CLKOUT_PER_JITT_FX

Period jitter at the CLKFX

and CLKFX180 outputs

All

ps

Duty Cycle⁽³⁾

CLKOUT_DUTY_CYCLE_FX Duty cycle precision for

the CLKFX and

-100

-140

-

+100

+140

10.0

-100

-140

-

+100

+140

10.0

CLKFX180 outputs

Phase Alignment

CLKOUT_PHASE

Phase offset between

either DFS output and

any other DCM output

All

ps

Lock Time

LOCK_FX

Once the CLKIN and

CLKFB signals become

in-phase, the time it takes

for the DCM’s LOCKED

output to go High.

ms

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 5 and Table 29.

2. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) is in use.

3. The CLKFX and CLKFX180 outputs always approximate 50% duty cycles.

DS099-3 (v1.3) March 4, 2004

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Spartan-3 FPGA Family: DC and Switching Characteristics

possible. In order to use the Variable Phase mode, it is nec-

essary to set the BitGen option Centered_x#y# option to 0.

BitGen is part of the Xilinx development software. The lines

to be typed in the command prompt are shown in Table 33,

page 33.

Phase Shifter (PS)

Phase Shifter operation is only supported in the Low fre-

quency mode. For Rev. 0 devices, the Variable Phase mode

only permits positive shifts. For any desired negative phase

shift (–S), an equivalent positive phase shift (360° – S) is

Table 31: Recommended Operating Conditions for the PS in Variable Phase Mode

Speed Grade

-5

-4

Frequency Mode/

F_PSCLKRange

Device

Revision

Symbol

Operating Frequency Ranges

PSCLK_FREQ Frequency for the

Description

Min

Max

Min

Max

Units

Low

All

1

165

1

165

MHz

(F_PSCLKPSCLK input

)

Input Pulse and Requirements

PSCLK_PULSE PSCLK pulse width

as a percentage of

Low

0

45%

40%

45%

55%

60%

55%

45%

40%

45%

55%

60%

55%

-

Low

F_PSCLK< 200 MHz

F_PSCLK> 200 MHz

Future

the PSCLK period

Notes:

1. The PS specifications in this table apply when the PS attribute CLKOUT_PHASE_SHIFT= VARIABLE.

Table 32: Switching Characteristics for the PS in Variable Phase Mode

Speed Grade

-5

-4

Frequency

Symbol

Description

Mode

Min

Max

Min

Max

Units

Phase Shifting Range

FINE_SHIFT_RANGE

Low

Range for variable

phase shifting

-

10.0

-

10.0

ns

Lock Time

LOCK_DLL_FINE_SHIFT⁽³⁾In the Variable

Phase mode, the

-

ms

Low

additional time it

takes for the DCM’s

LOCKED output to

go High

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 5 and Table 31.

2. The PS specifications in this table apply when the PS attribute CLKOUT_PHASE_SHIFT= VARIABLE.

3. When in the Variable Phase mode, add the values for this parameter to the appropriate LOCK_DLL parameter from Table 28 for the

total lock time.

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Table 33: BitGen Commands for Variable Phase Mode

Device

XC3S50

DCM Location (Device Top View)

BitGen Command Line

bitgen -g centered_x0y1:0 design_name.ncd

bitgen -g centered_x0y0:0 design_name.ncd

bitgen -g centered_x0y1:0 design_name.ncd

bitgen -g centered_x1y1:0 design_name.ncd

bitgen -g centered_x0y0:0 design_name.ncd

bitgen -g centered_x1y0:0 design_name.ncd

Upper

Lower

All others

Upper left

Upper right

Lower left

Lower right

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Spartan-3 FPGA Family: DC and Switching Characteristics

Configuration and JTAG Timing

1.2V

2.5V

V

CCINT

(Supply)

V

CCAUX

(Supply)

V

CCO

Bank 4

(Supply)

T_POR

PROG_B

(Input)

T_PL

T_PROG

INIT_B

(Open-Drain)

T_ICCK

CCLK

(Output)

DS099-3_03_022904

Notes:

1. The V_CCINT, V_CCAUX, and V_CCOsupplies may be applied in any order.

2. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.

3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).

Figure 5: Waveforms for Power-On and the Beginning of Configuration

Table 34: Power-On Timing and the Beginning of Configuration

All Speed Grades

Symbol

Description

Device

Min

Max

5

Units

ms

µs

ms

µs

(2)

T_POR

The time from the application of V_CCINT, V_CCAUX, and XC3S50

_CCOBank 4 supply voltages (whichever occurs last)

to the rising transition of the INIT_B pin

-

V

XC3S200

XC3S400

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

-

5

-

5

-

5

-

7

-

7

-

7

-

7

T_PROG

The width of the low-going pulse on the PROG_B pin All

0.3

-

(2)

T_PL

The time from the rising edge of the PROG_B pin to XC3S50

the rising transition on the INIT_B pin

-

2

XC3S200

-

2

XC3S400

-

2

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

-

2

-

3

-

3

-

3

(3)

T_ICCK

The time from the rising edge of the INIT_B pin to the All

generation of the configuration clock signal at the

CCLK output pin

0.5

4.0

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 5.

2. Power-on reset and the clearing of configuration memory occurs during this period.

3. This specification applies only for the Master Serial and Master Parallel modes.

34

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PROG_B

(Input)

INIT_B

(Open-Drain)

T_CCH

T_CCL

CCLK

(Input/Output)

T_DCC

1/F_CCSER

T_CCD

DIN

(Input)

Bit n+1

T_CCO

Bit n

Bit 0

Bit 1

DOUT

(Output)

Bit n-63

Bit n-64

DS099-3_04_041103

Notes:

1. The CS_B, WRITE_B, and BUSY signals are not used in the serial modes. Keep the CS_B and WRITE_B inputs inactive (i.e., both

pins High).

Figure 6: Waveforms for Master and Slave Serial Configuration

Table 35: Timing for the Master and Slave Serial Configuration Modes

All Speed Grades

Symbol

Description

Slave/Master

Min

Max

Units

Clock-to-Output Times

T_CCO

The time from the rising transition on the

Both

-

12.0

ns

CCLK pin to data appearing at the DOUT pin

Setup Times

T_DCC

The time from the setup of data at the DIN pin

to the rising transition at the CCLK pin

Both

-

10.0

0

ns

Hold Times

T_CCD

The time from the rising transition at the

CCLK pin to the point when data is last held

at the DIN pin

Clock Timing

T_CCH

The High pulse width at the CCLK input pin

The Low pulse width at the CCLK input pin

Slave

5.0

-

ns

T_CCL

F_CCSER

Frequency of the clock signal at the CCLK

input pin

66

MHz

∆F_CCSER

Variation from the generated CCLK frequency

set using the ConfigRate BitGen option

Master

–50%

+50%

-

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 5.

DS099-3 (v1.3) March 4, 2004

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Spartan-3 FPGA Family: DC and Switching Characteristics

PROG_B

(Input)

INIT_B

(Open-Drain)

T_SMCSCC

T_SMCCCS

CS_B

(Input)

T_SMCCW

T_SMWCC

RDWR_B

(Input)

T_CCH

T_CCL

CCLK

(Input/Output)

1/F_CCPAR

Byte n

T_SMDCC

T_SMCCD

D0 - D7

(Inputs)

Byte 0

Byte 1

Byte n+1

T_SMCKBY

High-Z

BUSY

(Output)

BUSY

DS099-3_05_041103

Notes:

1. Switching RDWR_B High or Low while holding CS_B Low asynchronously aborts configuration.

Figure 7: Waveforms for Master and Slave Parallel Configuration

Table 36: Timing for the Master and Slave Parallel Configuration Modes

All Speed Grades

Symbol

Description

Slave/Master

Min

Max

Units

Clock-to-Output Times

T_SMCKBY

The time from the rising transition on the CCLK pin to a

signal transition at the BUSY pin

Slave

-

12.0

ns

Setup Times

T_SMDCC

The time from the setup of data at the D0-D7 pins to the

rising transition at the CCLK pin

Both

10.0

-

ns

T_SMCSCC

The time from the setup of a logic level at the CS_B pin to

the rising transition at the CCLK pin

(2)

T_SMCCW

The time from the setup of a logic level at the RDWR_B pin

to the rising transition at the CCLK pin

36

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Spartan-3 FPGA Family: DC and Switching Characteristics

Table 36: Timing for the Master and Slave Parallel Configuration Modes (Continued)

All Speed Grades

Symbol

Hold Times

T_SMCCD

Description

Slave/Master

Min

Max

Units

The time from the rising transition at the CCLK pin to the

point when data is last held at the D0-D7 pins

Both

0

-

ns

T_SMCCCS

The time from the rising transition at the CCLK pin to the

point when a logic level is last held at the CS_B pin

(2)

T_SMWCC

The time from the rising transition at the CCLK pin to the

point when a logic level is last held at the RDWR_B pin

Clock Timing

T_CCH

The High pulse width at the CCLK input pin

Slave

5

-

ns

T_CCL

The Low pulse width at the CCLK input pin

5

F_CCPAR

Frequency of the clock signal Not using the BUSY pin⁽³⁾

-

66

MHz

-

at the CCLK input pin

Using the BUSY pin

100

+50%

∆F_CCPAR

Variation from the generated CCLK frequency set using

the BitGen option ConfigRate

Master

–50%

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 5.

2. RDWR_B is synchronized to CCLK for the purpose of performing the Abort operation. The same pin asynchronously controls the

driver impedance of the D0 - D7 pins. To avoid contention when writing configuration data to the D0 - D7 bus, do not bring RDWR_B

High when CS_B is Low.

3. In the Slave Parallel mode, it is necessary to use the BUSY pin when the CCLK frequency exceeds this maximum specification.

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Spartan-3 FPGA Family: DC and Switching Characteristics

T_CCH

T_CCL

TCK

(Input)

1/F_TCK

T_TCKTMS

T_TMSTCK

TMS

(Input)

T_TDITCK

T_TCKTDI

TDI

(Input)

T_TCKTDO

TDO

(Output)

DS099_06_040703

Figure 8: JTAG Waveforms

Table 37: Timing for the JTAG Test Access Port

All Speed Grades

Min Max

Symbol

Description

Units

Clock-to-Output Times

T_TCKTDO

The time from the falling transition on the TCK pin

to data appearing at the TDO pin

-

11.0

ns

Setup Times

T_TDITCK

The time from the setup of data at the TDI pin to

the rising transition at the TCK pin

5.0

-

ns

T_TMSTCK

The time from the setup of a logic level at the TMS

pin to the rising transition at the TCK pin

Hold Times

T_TCKTDI

The time from the rising transition at the TCK pin

to the point when data is last held at the TDI pin

0

-

ns

T_TCKTMS

The time from the rising transition at the TCK pin

to the point when a logic level is last held at the

TMS pin

Clock Timing

T_CCH

The High pulse width at the TCK pin

The Low pulse width at the TCK pin

Frequency of the TCK signal

5

-

ns

T_CCL

F_TCK

33

MHz

Notes:

1. The numbers in this table are based on the operating conditions set forth in Table 5.

38

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Spartan-3 FPGA Family: DC and Switching Characteristics

Revision History

Date

Version No.

Description

04/11/03

07/11/03

1.0

1.1

Initial Xilinx release.

Extended Absolute Maximum Rating for junction temperature in Table 1. Added numbers for

typical quiescent supply current (Table 7) and DLL timing.

02/06/04

03/04/04

1.2

1.3

Revised V_INmaximum rating (Table 1). Added power-on requirements (Table 3), leakage

current number (Table 6), and differential output voltage levels (Table 11) for Rev. 0. Published

new quiescent current numbers (Table 7). Updated pull-up and pull-down resistor strengths

(Table 6). Added LVDCI_DV2 and LVPECL standards (Table 10 and Table 11). Changed

CCLK setup time (Table 35 and Table 36).

Added timing numbers from v1.29 speed files as well as DCM timing (Table 27 through

Table 32).

The Spartan-3 Family Data Sheet

DS099-1, Spartan-3 FPGA Family: Introduction and Ordering Information (Module 1)

DS099-2, Spartan-3 FPGA Family: Functional Description (Module 2)

DS099-3, Spartan-3 FPGA Family: DC and Switching Characteristics (Module 3)

DS099-4, Spartan-3 FPGA Family: Pinout Descriptions (Module 4)

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Spartan-3 FPGA Family: DC and Switching Characteristics

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Spartan-3 FPGA Family:

Pinout Descriptions

0

DS099-4 (v1.5) July 13, 2004

Product Specification

Introduction

This data sheet module describes the various pins on a

Spartan™-3 FPGA and how they connect to the supported

component packages.

•

The Package Overview section describes the various

packaging options available for Spartan-3 FPGAs.

Detailed pin list tables and footprint diagrams are

provided for each package solution.

•

The Pin Types section categorizes all of the FPGA

pins by their function type.

Pin Descriptions

The Pin Definitions section provides a top-level

description for each pin on the device.

The Detailed, Functional Pin Descriptions section

offers significantly more detail about each pin,

especially for the dual- or special-function pins used

during device configuration.

Pin Types

A majority of the pins on a Spartan-3 FPGA are gen-

eral-purpose, user-defined I/O pins. There are, however, up

to 12 different functional types of pins on Spartan-3 pack-

ages, as outlined in Table 1. In the package footprint draw-

ings that follow, the individual pins are color-coded

according to pin type as in the table.

•

Some pins have associated optional behavior,

controlled by settings in the configuration bitstream.

These options are described in the Bitstream Options

section.

Table 1: Types of Pins on Spartan-3 FPGAs

Type/

Color

Code

Description

Unrestricted, general-purpose user-I/O pin. Most pins can be

paired together to form differential I/Os.

Pin Name(s) in Type

I/O

IO,

IO_Lxxy_#

DUAL

Dual-purpose pin used in some configuration modes during the IO_Lxxy_#/DIN/D0, IO_Lxxy_#/D1,

configuration process and then usually available as a user I/O IO_Lxxy_#/D2, IO_Lxxy_#/D3,

after configuration. If the pin is not used during configuration, this IO_Lxxy_#/D4, IO_Lxxy_#/D5,

pin behaves as an I/O-type pin. There are 12 dual-purpose

configuration pins on every package.

IO_Lxxy_#/D6, IO_Lxxy_#/D7,

IO_Lxxy_#/CS_B, IO_Lxxy_#/RDWR_B,

IO_Lxxy_#/BUSY/DOUT,

IO_Lxxy_#/INIT_B

CONFIG Dedicated configuration pin. Not available as a user-I/O pin.

Every package has seven dedicated configuration pins. These

pins are powered by VCCAUX.

CCLK, DONE, M2, M1, M0, PROG_B,

HSWAP_EN

JTAG

Dedicated JTAG pin. Not available as a user-I/O pin. Every

package has four dedicated JTAG pins. These pins are powered

by VCCAUX.

TDI, TMS, TCK, TDO

DCI

Dual-purpose pin that is either a user-I/O pin or used to calibrate IO/VRN_#

output buffer impedance for a specific bank using Digital

Controlled Impedance (DCI). There are two DCI pins per I/O

bank.

IO_Lxxy_#/VRN_#

IO/VRP_#

IO_Lxxy_#/VRP_#

VREF

Dual-purpose pin that is either a user-I/O pin or, along with all

IO/VREF_#

other VREF pins in the same bank, provides a reference voltage IO_Lxxy_#/VREF_#

input for certain I/O standards. If used for a reference voltage

within a bank, all VREF pins within the bank must be connected.

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

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Spartan-3 FPGA Family: Pinout Descriptions

Table 1: Types of Pins on Spartan-3 FPGAs (Continued)

Type/

Color

Code

Description

Pin Name(s) in Type

GND

Dedicated ground pin. The number of GND pins depends on the GND

package used. All must be connected.

VCCAUX Dedicated auxiliary power supply pin. The number of VCCAUX VCCAUX

pins depends on the package used. All must be connected to

+2.5V.

VCCINT Dedicated internal core logic power supply pin. The number of

VCCINT pins depends on the package used. All must be

connected to +1.2V.

VCCINT

VCCO_#

VCCO

GCLK

N.C.

Dedicated I/O bank, output buffer power supply pin. Along with

other VCCO pins in the same bank, this pin supplies power to the TQ144 Package Only:

output buffers within the I/O bank and sets the input threshold

voltage for some I/O standards.

VCCO_LEFT, VCCO_TOP,

VCCO_RIGHT, VCCO_BOTTOM

Dual-purpose pin that is either a user-I/O pin or an input to a

specific global buffer input. Every package has eight dedicated

GCLK pins.

IO_Lxxy_#/GCLK0, IO_Lxxy_#/GCLK1,

IO_Lxxy_#/GCLK2, IO_Lxxy_#/GCLK3,

IO_Lxxy_#/GCLK4, IO_Lxxy_#/GCLK5,

IO_Lxxy_#/GCLK6, IO_Lxxy_#/GCLK7

This package pin is not connected in this specific

device/package combination but may be connected in larger

devices in the same package.

N.C.

Notes:

1. # = I/O bank number, an integer between 0 and 7.

I/Os with Lxxy_# are part of a differential output pair. ‘L’ indi-

cates differential output capability. The “xx” field is a

two-digit integer, unique to each bank that identifies a differ-

ential pin-pair. The ‘y’ field is either ‘P’ for the true signal or

‘N’ for the inverted signal in the differential pair. The ‘#’ field

is the I/O bank number.

Pin Definitions

Table 2 provides a brief description of each pin listed in the

Spartan-3 pinout tables and package footprint diagrams.

Pins are categorized by their pin type, as listed in Table 1.

See Detailed, Functional Pin Descriptions for more infor-

mation.

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Spartan-3 FPGA Family: Pinout Descriptions

Description

Table 2: Spartan-3 Pin Definitions

Pin Name

Direction

I/O: General-purpose I/O pins

User I/O:

I/O

User-defined as input,

output, bidirectional,

three-state output,

open-drain output,

open-source output

Unrestricted single-ended user-I/O pin. Supports all I/O standards

except the differential standards.

User I/O, Half of Differential Pair:

I/O_Lxxy_#

User-defined as input,

output, bidirectional,

three-state output,

open-drain output,

open-source output

Unrestricted single-ended user-I/O pin or half of a differential pair.

Supports all I/O standards including the differential standards.

DUAL: Dual-purpose configuration pins

Configuration Data Port:

IO_Lxxy_#/DIN/D0,

IO_Lxxy_#/D1,

IO_Lxxy_#/D2,

IO_Lxxy_#/D3,

IO_Lxxy_#/D4,

IO_Lxxy_#/D5,

IO_Lxxy_#/D6,

IO_Lxxy_#/D7

Input during configuration

In Parallel (SelectMAP) modes, D0-D7 are byte-wide configuration

data pins. These pins become user I/Os after configuration unless

the SelectMAP port is retained via the Persist bitstream option.

Possible bidirectional I/O

after configuration if

SelectMap port is retained.

In Serial modes, DIN (D0) serves as the single configuration data

input. This pin becomes a user I/O after configuration unless

retained by the Persist bitstream option.

Otherwise, user I/O after

configuration

Chip Select for Parallel Mode Configuration:

IO_Lxxy_#/CS_B

Input during Parallel mode

configuration

In Parallel (SelectMAP) modes, this is the active-Low Chip Select

signal. This pin becomes a user I/O after configuration unless the

SelectMAP port is retained via the Persist bitstream option.

Possible input after

configuration if SelectMap

port is retained.

Otherwise, user I/O after

configuration

Read/Write Control for Parallel Mode Configuration:

IO_Lxxy_#/RDWR_B Input during Parallel mode

configuration

In Parallel (SelectMAP) modes, this is the active-Low Write

Enable, active-High Read Enable signal. This pin becomes a user

I/O after configuration unless the SelectMAP port is retained via

the Persist bitstream option.

Possible input after

configuration if SelectMap

port is retained.

Otherwise, user I/O after

configuration

Configuration Data Rate Control for Parallel Mode, Serial Data

Output for Serial Mode:

IO_Lxxy_#/

BUSY/DOUT

Output during configuration

Possible output after

configuration if SelectMap

port is retained.

In Parallel (SelectMAP) modes, BUSY throttles the rate at which

configuration data is loaded. This pin becomes a user I/O after

configuration unless the SelectMAP port is retained via the Persist

bitstream option.

Otherwise, user I/O after

configuration

In Serial modes, DOUT provides preamble and configuration data

to downstream devices in a multi-FPGA daisy-chain. This pin

becomes a user I/O after configuration.

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Spartan-3 FPGA Family: Pinout Descriptions

Table 2: Spartan-3 Pin Definitions (Continued)

Pin Name

Direction

Description

Initializing Configuration Memory/Detected Configuration Error:

IO_Lxxy_#/INIT_B

Bidirectional (open-drain)

during configuration

When Low, this pin indicates that configuration memory is being

cleared. When held Low, this pin delays the start of configuration.

After this pin is released or configuration memory is cleared, the

pin goes High. During configuration, a Low on this output indicates

that a configuration data error occurred. This pin becomes a user

I/O after configuration.

User I/O after configuration

DCI: Digitally Controlled Impedance reference resistor input pins

DCI Reference Resistor for NMOS I/O Transistor (per bank):

IO_Lxxy_#/VRN_#or Input when using DCI

IO/VRN_#

If using DCI, a 1% precision impedance-matching resistor is

connected between this pin and the VCCO supply for this bank.

Otherwise, this pin is a user I/O.

Otherwise, same as I/O

DCI Reference Resistor for PMOS I/O Transistor (per bank):

IO_Lxxy_#/VRP_# or Input when using DCI

IO/VRP_#

If using DCI, a 1% precision impedance-matching resistor is

connected between this pin and the ground supply. Otherwise, this

pin is a user I/O.

Otherwise, same as I/O

GCLK: Global clock buffer inputs

Global Buffer Input:

IO_Lxxy_#/GCLK0,

IO_Lxxy_#/GCLK1,

IO_Lxxy_#/GCLK2,

IO_Lxxy_#/GCLK3,

IO_Lxxy_#/GCLK4,

IO_Lxxy_#/GCLK5,

IO_Lxxy_#/GCLK6,

IO_Lxxy_#/GCLK7

Input if connected to global

clock buffers

Direct input to a low-skew global clock buffer. If not connected to a

global clock buffer, this pin is a user I/O.

Otherwise, same as I/O

VREF: I/O bank input reference voltage pins

Input Buffer Reference Voltage for Special I/O Standards (per

bank):

IO_Lxxy_#/VREF_#

or

IO/VREF_#

Voltage supply input when

VREF pins are used within a

bank.

If required to support special I/O standards, all the VREF pins

within a bank connect to a input threshold voltage source.

Otherwise, same as I/O

If not used as input reference voltage pins, these pins are available

as individual user-I/O pins.

CONFIG: Dedicated configuration pins

Configuration Clock:

CCLK

Input in Slave configuration

modes

The configuration clock signal synchronizes configuration data.

Output in Master

configuration modes

Program/Configure Device:

PROG_B

Input

Active Low asynchronous reset to configuration logic. Asserting

PROG_B Low for an extended period delays the configuration

process. This pin has an internal weak pull-up resistor during

configuration.

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Spartan-3 FPGA Family: Pinout Descriptions

Description

Table 2: Spartan-3 Pin Definitions (Continued)

Pin Name

DONE

Direction

Configuration Done, Delay Start-up Sequence:

Bidirectional with open-drain

or totem-pole Output

A Low-to-High output transition on this bidirectional pin signals the

end of the configuration process.

The FPGA produces a Low-to-High transition on this pin to

indicate that the configuration process is complete. The DriveDone

bitstream generation option defines whether this pin functions as

a totem-pole output that actively drives High or as an open-drain

output. An open-drain output requires a pull-up resistor to produce

a High logic level. The open-drain option permits the DONE lines

of multiple FPGAs to be tied together, so that the common node

transitions High only after all of the FPGAs have completed

configuration. Externally holding the open-drain output Low delays

the start-up sequence, which marks the transition to user mode.

Configuration Mode Selection:

M0, M1, M2

HSWAP_EN

Input

These inputs select the configuration mode. The logic levels

applied to the mode pins are sampled on the rising edge of INIT_B.

See Table 7.

Disable Weak Pull-up Resistors During Configuration:

A Low on this pin enables weak pull-up resistors on all pins that are

not actively involved in the configuration process. A High value

disables all pull-ups, allowing the non-configuration pins to float.

JTAG: JTAG interface pins

JTAG Test Clock:

TCK

Input

The TCK clock signal synchronizes all JTAG port operations.

JTAG Test Data Input:

TDI

Input

TDI is the serial data input for all JTAG instruction and data

registers.

JTAG Test Mode Select:

TMS

TDO

Input

The serial TMS input controls the operation of the JTAG port.

JTAG Test Data Output:

Output

TDO is the serial data output for all JTAG instruction and data

registers.

VCCO: I/O bank output voltage supply pins

VCCO_# Supply

Power Supply for Output Buffer Drivers (per bank):

These pins power the output drivers within a specific I/O bank.

VCCAUX: Auxiliary voltage supply pins

VCCAUX Supply

Power Supply for Auxiliary Circuits:

+2.5V power pins for auxiliary circuits, including the Digital Clock

Managers (DCMs), the dedicated configuration pins (CONFIG),

and the dedicated JTAG pins. All VCCAUX pins must be

connected.

VCCINT: Internal core voltage supply pins

VCCINT Supply

Power Supply for Internal Core Logic:

+1.2V power pins for the internal logic. All pins must be connected.

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Spartan-3 FPGA Family: Pinout Descriptions

Table 2: Spartan-3 Pin Definitions (Continued)

Pin Name

Direction

Description

GND: Ground supply pins

Ground:

GND

Supply

Ground pins, which are connected to the power supply’s return

path. All pins must be connected.

N.C.: Unconnected package pins

Unconnected Package Pin:

N.C.

These package pins are unconnected.

Notes:

1. All unused inputs and bidirectional pins must be tied either High or Low. For unused enable inputs, apply the level that disables the

associated function. One common approach is to activate internal pull-up or pull-down resistors. An alternative approach is to

externally connect the pin to either VCCO or GND.

2. All outputs are of the totem-pole type — i.e., they can drive High as well as Low logic levels — except for the cases where “Open

Drain” is indicated. The latter can only drive a Low logic level and require a pull-up resistor to produce a High logic level.

•

‘L’ indicates differential capability.

Detailed, Functional Pin Descriptions

"xx" is a two-digit integer, unique for each bank, that

identifies a differential pin-pair.

‘y’ is replaced by ‘P’ for the true signal or ‘N’ for the

inverted. These two pins form one differential pin-pair.

‘#’ is an integer, 0 through 7, indicating the associated

I/O bank.

I/O Type: Unrestricted, General-purpose I/O

Pins

After configuration, I/O-type pins are inputs, outputs, bidi-

rectional I/O, three-state outputs, open-drain outputs, or

open-source outputs, as defined in the application

•

If unused, these pins are in a high impedance state. The Bit-

stream generator option UnusedPin enables a weak pull-up

or pull-down resistor on all unused I/O pins.

Pins labeled "IO" support all SelectIO™ signal standards

except differential standards. A given device at most only

has a few of these pins.

A majority of the general-purpose I/O pins are labeled in the

format “IO_Lxxy_#”. These pins support all SelectIO signal

standards, including the differential standards such as

LVDS, ULVDS, BLVDS, RSDS, or LDT.

Behavior from Power-On through End of Configu-

ration

During the configuration process, all pins that are not

actively involved in the configuration process are in a

high-impedance state. The HSWAP_EN input determines

whether or not weak pull-up resistors are enabled during

configuration. HSWAP_EN = 0 enables the weak pull-up

resistors. HSWAP_EN = 1 disables the pull-up resistors

allowing the pins to float, which is the desired state for

hot-swap applications.

For additional information, see the “IOB” section under

Functional Description (Module 2 of the Spartan-3 data sheet)

.

Differential Pair Labeling

A pin supports differential standards if the pin is labeled in

the format “Lxxy_#”. The pin name suffix has the following

significance. Figure 1 provides a specific example showing

a differential input to and a differential output from Bank 2.

Pair Number

Bank 0

Bank 1

Bank Number

IO_L38P_2

IO_L38N_2

Positive Polarity,

True Driver

IO_L39P_2

IO_L39N_2

Negative Polarity,

Inverted Driver

Bank 5

Bank 4

DS099-4_01_042303

Figure 1: Differential Pair Labelling

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Spartan-3 FPGA Family: Pinout Descriptions

Serial Configuration Modes

DUAL Type: Dual-Purpose Configuration and

I/O Pins

This section describes the dual-purpose pins used during

either Master or Slave Serial mode. See Table 7 for Mode

Select pin settings required for Serial modes. All such pins

are in Bank 4 and powered by VCCO_4.

These pins serve dual purposes. The user-I/O pins are tem-

porarily borrowed during the configuration process to load

configuration data into the FPGA. After configuration, these

pins are then usually available as a user I/O in the applica-

tion. If a pin is not applicable to the specific configuration

mode—controlled by the mode select pins M2, M1, and

M0—then the pin behaves as an I/O-type pin.

In both the Master and Slave Serial modes, DIN is the serial

configuration data input. The D1-D7 inputs are unused in

serial mode and behave like general-purpose I/O pins.

In all the cases, the configuration data is synchronized to

the rising edge of the CCLK clock signal.

There are 12 dual-purpose configuration pins on every

package, six of which are part of I/O Bank 4, the other six

part of I/O Bank 5. Only a few of the pins in Bank 4 are used

in the Serial configuration modes.

The DIN, DOUT, and INIT_B pins can be retained in the

application to support reconfiguration by setting the Persist

bitstream generation option. However, the serial modes do

not support device readback.

See “Configuration” under Functional Description (Module 2

of the Spartan-3 data sheet).

See “Pin Behavior During Configuration, page 15”.

Table 3: Dual-Purpose Pins Used in Master or Slave Serial Mode

Pin Name

DIN

Direction

Description

Serial Data Input:

Input

During the Master or Slave Serial configuration modes, DIN is the serial configuration data

input, and all data is synchronized to the rising CCLK edge. After configuration, this pin is

available as a user I/O.

This signal is located in Bank 4 and its output voltage determined by VCCO_4.

The BitGen option Persist permits this pin to retain its configuration function in the User

mode.

Serial Data Output:

DOUT

Output

In a multi-FPGA design where all the FPGAs use serial mode, connect the DOUT output of

one FPGA—in either Master or Slave Serial mode—to the DIN input of the next FPGA—in

Slave Serial mode—so that configuration data passes from one to the next, in daisy-chain

fashion. This “daisy chain” permits sequential configuration of multiple FPGAs.

This signal is located in Bank 4 and its output voltage determined by VCCO_4.

The BitGen option Persist permits this pin to retain its configuration function in the User

mode.

Initializing Configuration Memory/Configuration Error:

INIT_B

Bidirectional

(open-drain)

Just after power is applied, the FPGA produces a Low-to-High transition on this pin

indicating that initialization (i.e., clearing) of the configuration memory has finished. Before

entering the User mode, this pin functions as an open-drain output, which requires a pull-up

resistor in order to produce a High logic level. In a multi-FPGA design, tie (wire AND) the

INIT_B pins from all FPGAs together so that the common node transitions High only after

all of the FPGAs have been successfully initialized.

Externally holding this pin Low beyond the initialization phase delays the start of

configuration. This action stalls the FPGA at the configuration step just before the mode

select pins are sampled.

During configuration, the FPGA indicates the occurrence of a data (i.e., CRC) error by

asserting INIT_B Low.

This signal is located in Bank 4 and its output voltage determined by VCCO_4.

The BitGen option Persist permits this pin to retain its configuration function in the User

mode.

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Spartan-3 FPGA Family: Pinout Descriptions

I/O Bank 4 (VCCO_4)

High Nibble

I/O Bank 5 (VCCO_5)

Low Nibble

Configuration Data Byte

D0

D1

D2

D3

D4

D5

D6

D7

0xA5 =

1

0

1

0

1

0

1

Figure 2: Configuration Data Byte Mapping to D0-D7 Bits

CS_B and RDWR_B does not matter, although RDWR_B

must be asserted throughout the configuration process. If

RDWR_B is de-asserted during configuration, the FPGA

aborts the configuration operation.

Parallel Configuration Modes (SelectMAP)

This section describes the dual-purpose configuration pins

used during the Master and Slave Parallel configuration

modes, sometimes also called the SelectMAP modes. In

both Master and Slave Parallel configuration modes, D0-D7

form the byte-wide configuration data input. See Table 7 for

Mode Select pin settings required for Parallel modes.

After configuration, these pins are available as general-pur-

pose user I/O. However, the SelectMAP configuration inter-

face is optionally available for debugging and dynamic

reconfiguration. To use these SelectMAP pins after configu-

ration, set the Persist bitstream generation option.

As shown in Figure 2, D0 is the most-significant bit while D7

is the least-significant bit. Bits D0-D3 form the high nibble of

the byte and bits D4-D7 form the low nibble.

The Readback debugging option, for example, requires the

Persist bitstream generation option. During Readback

mode, assert CS_B Low, along with RDWR_B High, to read

a configuration data byte from the FPGA to the D0-D7 bus

on a rising CCLK edge. During Readback mode, D0-D7 are

output pins.

In the Parallel configuration modes, both the VCCO_4 and

VCCO_5 voltage supplies are required and must both equal

the voltage of the attached configuration device, typically

either 2.5V or 3.3V.

Assert Low both the chip-select pin, CS_B, and the

read/write control pin, RDWR_B, to write the configuration

data byte presented on the D0-D7 pins to the FPGA on a

rising-edge of the configuration clock, CCLK. The order of

In all the cases, the configuration data and control signals

are synchronized to the rising edge of the CCLK clock sig-

nal.

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Spartan-3 FPGA Family: Pinout Descriptions

Table 4: Dual-Purpose Configuration Pins for Parallel (SelectMAP) Configuration Modes

Name

Direction

Description

Configuration Data Port (high nibble):

D0,

Input during

configuration

D1,

D2,

D3

Collectively, the D0-D7 pins are the byte-wide configuration data port for the Parallel

(SelectMAP) configuration modes. Configuration data is synchronized to the rising edge of

CCLK clock signal.

Outputduring

readback

The D0-D3 pins are the high nibble of the configuration data byte and located in Bank 4 and

powered by VCCO_4.

The BitGen option Persist permits this pin to retain its configuration function in the User mode.

Configuration Data Port (low nibble):

D4,

D5,

D6,

D7

Input during

configuration

The D4-D7 pins are the low nibble of the configuration data byte. However, these signals are

located in Bank 5 and powered by VCCO_5.

The BitGen option Persist permits this pin to retain its configuration function in the User mode.

Outputduring

readback

Chip Select for Parallel Mode Configuration:

CS_B

Input

Assert this pin Low, together with RDWR_B to write a configuration data byte from the D0-D7

bus to the FPGA on a rising CCLK edge.

During Readback, assert this pin Low, along with RDWR_B High, to read a configuration data

byte from the FPGA to the D0-D7 bus on a rising CCLK edge.

This signal is located in Bank 5 and powered by VCCO_5.

The BitGen option Persist permits this pin to retain its configuration function in the User mode.

CS_B

Function

0

1

FPGA selected. SelectMAP inputs are valid on the next rising edge of CCLK.

FPGA deselected. All SelectMAP inputs are ignored.

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Spartan-3 FPGA Family: Pinout Descriptions

Table 4: Dual-Purpose Configuration Pins for Parallel (SelectMAP) Configuration Modes (Continued)

Name

Direction

Description

Read/Write Control for Parallel Mode Configuration:

RDWR_B

Input

In Master and Slave Parallel modes, assert this pin Low together with CS_B to write a

configuration data byte from the D0-D7 bus to the FPGA on a rising CCLK edge. Once

asserted during configuration, RDWR_B must remain asserted until configuration is

complete.

During Readback, assert this pin High with CS_B Low to read a configuration data byte from

the FPGA to the D0-D7 bus on a rising CCLK edge.

This signal is located in Bank 5 and powered by VCCO_5.

The BitGen option Persist permits this pin to retain its configuration function in the User mode.

RDWR_B

Function

0

1

If CS_B is Low, then load (write) configuration data to the FPGA.

This option is valid only if the Persist bitstream option is set to Yes. If CS_B is

Low, then read configuration data from the FPGA.

Configuration Data Rate Control for Parallel Mode:

BUSY

Output

In the Slave and Master Parallel modes, BUSY throttles the rate at which configuration data

is loaded. BUSY is only necessary if CCLK operates at greater than 50 MHz. Ignore BUSY

for frequencies of 50 MHz and below.

When BUSY is Low, the FPGA accepts the next configuration data byte on the next rising

CCLK edge for which CS_B and RDWR_B are Low. When BUSY is High, the FPGA ignores

the next configuration data byte. The next configuration data value must be held or reloaded

until the next rising CCLK edge when BUSY is Low. When CS_B is High, BUSY is in a high

impedance state.

BUSY

Function

0

1

The FPGA is ready to accept the next configuration data byte.

The FPGA is busy processing the current configuration data byte and is not

ready to accept the next byte.

Hi-Z

If CS_B is High, then BUSY is high impedance.

This signal is located in Bank 4 and its output voltage is determined by VCCO_4. The BitGen

option Persist permits this pin to retain its configuration function in the User mode.

Initializing Configuration Memory/Configuration Error (active-Low):

INIT_B

Bidirectional

(open-drain)

See description under Serial Configuration Modes, page 7.

LVCMOS25 I/O standard. If connected to +3.3V, then the

pins drive LVCMOS output levels and accept either LVTTL

or LVCMOS input levels.

JTAG Configuration Mode

In the JTAG configuration mode all dual-purpose configura-

tion pins are unused and behave exactly like user-I/O pins,

as shown in Table 10. See Table 7 for Mode Select pin set-

tings required for JTAG mode.

Dual-Purpose Pin Behavior After Configuration

After the configuration process completes, these pins, if

they were borrowed during configuration, become user-I/O

pins available to the application. If a dual-purpose configu-

ration pin is not used during the configuration process—i.e.,

the parallel configuration pins when using serial

mode—then the pin behaves exactly like a general-purpose

I/O. See I/O Type: Unrestricted, General-purpose I/O

Pins section above.

Dual-Purpose Pin I/O Standard During Configura-

tion

During configuration, the dual-purpose pins default to

CMOS input and output levels for the associated VCCO

voltage supply pins. For example, in the Parallel configura-

tion modes, both VCCO_4 and VCCO_5 are required. If

connected to +2.5V, then the associated pins conform to the

10

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Spartan-3 FPGA Family: Pinout Descriptions

LVDSEXT_25_DCI receivers—then both the VRP_# and

VRN_# pins connect to separate 1% precision imped-

ance-matching resistors, as shown in Figure 3c. Neither pin

is available for user I/O.

DCI: User I/O or Digitally Controlled

Impedance Resistor Reference Input

These pins are individual user-I/O pins unless one of the I/O

standards used in the bank requires the Digitally Controlled

Impedance (DCI) feature. If DCI is used, then 1% precision

resistors connected to the VRP_# and VRN_# pins match

the impedance on the input or output buffers of the I/O stan-

dards that use DCI within the bank.

GCLK: Global Clock Buffer Inputs or

General-Purpose I/O Pins

These pins are user-I/O pins unless they specifically con-

nect to one of the eight low-skew global clock buffers on the

device, specified using the IBUFG primitive.

The ‘#’ character in the pin name indicates the associated

I/O bank and is an integer, 0 through 7.

There are eight GCLK pins per device and two each appear

in the top-edge banks, Bank 0 and 1, and the bottom-edge

banks, Banks 4 and 5. See Figure 1 for a picture of bank

labeling.

There are two DCI pins per I/O bank, except in the TQ144

package, which does not have any DCI inputs for Bank 5.

VRP and VRN Impedance Resistor Reference

Inputs

During configuration, these pins behave exactly like

user-I/O pins.

The 1% precision impedance-matching resistor attached to

the VRP_# pin controls the pull-up impedance of PMOS

transistor in the input or output buffer. Consequently, the

VRP_# pin must connect to ground. The ‘P’ character in

“VRP” indicates that this pin controls the I/O buffer’s PMOS

transistor impedance. The VRP_# pin is used for both single

and split termination.

CONFIG: Dedicated Configuration Pins

The dedicated configuration pins control the configuration

process and are not available as user-I/O pins. Every pack-

age has seven dedicated configuration pins. All CON-

FIG-type pins are powered by the +2.5V VCCAUX supply.

The 1% precision impedance-matching resistor attached to

the VRN_# pin controls the pull-down impedance of NMOS

transistor in the input or output buffer. Consequently, the

VRN_# pin must connect to VCCO. The ‘N’ character in

“VRN” indicates that this pin controls the I/O buffer’s NMOS

transistor impedance. The VRN_# pin is only used for split

termination.

See “Configuration” under Functional Description (Module 2

of the Spartan-3 data sheet).

CCLK: Configuration Clock

The configuration clock signal on this pin synchronizes the

reading or writing of configuration data. This pin is an input

for the Slave configuration modes, both parallel and serial.

Each VRN or VRP reference input requires its own resistor.

A single resistor cannot be shared between VRN or VRP

pins associated with different banks.

After configuration, the CCLK pin is in a high-impedance,

floating state. By default, CCLK optionally is pulled High to

VCCAUX as defined by the CclkPin bitstream selection. Any

clocks applied to CCLK after configuration are ignored

unless the bitstream option Persist is set to Yes, which

retains the configuration interface. Persist is set to No by

default. However, if Persist is set to Yes, then all clock edges

are potentially active events, depending on the other config-

uration control signals.

During configuration, these pins behave exactly like

user-I/O pins. The associated DCI behavior is not active or

valid until after configuration completes.

See “Digitally Controlled Impedance (DCI)” under Functional

Description (Module 2 of the Spartan-3 data sheet).

DCI Termination Types

The bitstream generator option ConfigRate determines the

frequency of the internally-generated CCLK oscillator

required for the Master configuration modes. The actual fre-

quency is approximate due to the characteristics of the sili-

con oscillator and varies by up to 30% over the temperature

and voltage range. By default, CCLK operates at approxi-

mately 6 MHz. Via the ConfigRate option, the oscillator fre-

quency is set at approximately 3, 6, 12, 25, or 50 MHz. At

power-on, CCLK always starts operation at its lowest fre-

quency. The device does not start operating at the higher

frequency until the ConfigRate control bits are loaded dur-

ing the configuration process.

If the I/O in an I/O bank do not use the DCI feature, then no

external resistors are required and both the VRP_# and

VRN_# pins are available for user I/O, as shown in

Figure 3a.

If the I/O standards within the associated I/O bank require

single termination—such as GTL_DCI, GTLP_DCI, or

HSTL_III_DCI—then only the VRP_# signal connects to a

1% precision impedance-matching resistor, as shown in

Figure 3b. A resistor is not required for the VRN_# pin.

Finally, if the I/O standards with the associated I/O bank

require

split

termination—such

as

HSTL_I_DCI,

SSTL2_I_DCI, SSTL2_II_DCI, or LVDS_25_DCI and

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Spartan-3 FPGA Family: Pinout Descriptions

One of eight

I/O Banks

One of eight

I/O Banks

One of eight

I/O Banks

V

CCO

R

(1%)

REF

User I/O

VRN

VRP

VRN

User I/O

VRP

R

(1%)

R

REF

DS099-4_03_071304

(a) No termination

(b) Single termination

Figure 3: DCI Termination Types

(c) Split termination

PROG_B: Program/Configure Device

DONE: Configuration Done, Delay Start-Up

Sequence

This asynchronous pin initiates the configuration or re-con-

figuration processes. A Low-going pulse resets the configu-

ration logic, initializing the configuration memory. This

initialization process cannot finish until PROG_B returns

High. Asserting PROG_B Low for an extended period

delays the configuration process. At power-up, there is

always a weak pull-up resistor to VCCAUX on this pin. After

configuration, the bitstream generator option ProgPin deter-

mines whether or not the weak pull-up resistor is present.

By default, the ProgPin option retains the weak pull-up

resistor.

The FPGA produces a Low-to-High transition on this pin

indicating that the configuration process is complete. The

bitstream generator option DriveDone determines whether

this pin functions as a totem-pole output that can drive High

or as an open-drain output. If configured as an open-drain

output—which is the default behavior—then a pull-up resis-

tor is required to produce a High logic level. There is a bit-

stream option that provides an internal weak pull-up

resistor, otherwise an external pull-up resistor is required.

The open-drain option permits the DONE lines of multiple

FPGAs to be tied together, so that the common node transi-

tions High only after all of the FPGAs have completed con-

figuration. Externally holding the open-drain DONE pin Low

delays the start-up sequence, which marks the transition to

user mode.

After configuration, hold the PROG_B input High. Any

Low-going pulse on PROG_B restarts the configuration pro-

cess.

Table 5: PROG_B Operation

PROG_B Input

Power-up

Response

Once the FPGA enters User mode after completing config-

uration, the DONE pin no longer drives the DONE pin Low.

The bitstream generator option DonePin determines

whether or not a weak pull-up resistor is present on the

DONE pin to pull the pin to VCCAUX. If the weak pull-up

resistor is eliminated, then the DONE pin must be pulled

High using an external pull-up resistor or one of the FPGAs

in the design must actively drive the DONE pin High via the

DriveDone bitstream generator option.

Automatically initiates configuration

process.

Low-going pulse

Extended Low

Initiate (re-)configuration process and

continue to completion.

Initiate (re-)configuration process and

stall process at step where

configuration memory is cleared.

Process is stalled until PROG_B

returns High.

The bitstream generator option DriveDone causes the

FPGA to actively drive the DONE output High after configu-

ration. This option should only be used in single-FPGA

designs or on the last FPGA in a multi-FPGA daisy-chain.

1

If the configuration process is started,

continue to completion. If

configuration process is complete,

stay in User mode.

By default, the bitstream generator software retains the

weak pull-up resistor and does not actively drive the DONE

pin as highlighted in Table 6. Table 6 shows the interaction

of these bitstream options in single- and multi-FPGA

designs.

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Spartan-3 FPGA Family: Pinout Descriptions

Table 6: DonePin and DriveDone Bitstream Option Interaction

Single- or Multi-

DonePin DriveDone

FPGA Design

Comments

Pullnone

No

Single

External pull-up resistor, with value between 330Ω to 3.3kΩ, required on

DONE.

Pullnone

No

Multi

External pull-up resistor, with value between 330Ω to 3.3kΩ, required on

common node connecting to all DONE pins.

Pullnone

Pullup

Yes

No

Single

Multi

OK, no external requirements.

DriveDone on last device in daisy-chain only. No external requirements.

Single

OK, but weak pull-up on DONE pin has slow rise time. May require 330 Ω

pull-up resistor for high CCLK frequencies.

Pullup

No

Multi

External pull-up resistor, with value between 330Ω to 3.3kΩ, required on

common node connecting to all DONE pins.

Pullup

Yes

Single

Multi

OK, no external requirements.

DriveDone on last device in daisy-chain only. No external requirements.

completes. A High disables the weak pull-up resistors (dur-

ing configuration, which is the desired state for some appli-

cations.

M2, M1, M0: Configuration Mode Selection

These inputs select the mode to configure the FPGA. The

logic levels applied to the mode pins are sampled on the ris-

ing edge of INIT_B.

Table 8: HSWAP_EN Encoding

Table 7: Spartan-3 Configuration Mode Select Settings

HSWAP_EN

Function

Configuration Mode

Master Serial

Slave Serial

Master Parallel

Slave Parallel

JTAG

M2

0

M1

0

M0

0

During Configuration

0

Enable weak pull-up resistors on all pins

not actively involved in the configuration

process. Pull-ups are only active until

configuration completes. See Table 10.

1

0

1

0

1

No pull-up resistors during configuration.

1

0

1

After Configuration, User Mode

This pin has no function except during

device configuration.

Reserved

0

1

X

Reserved

0

1

0

Notes:

Reserved

1

0

1. X = don’t care, either 0 or 1.

After Configuration

X

After configuration, HSWAP_EN essentially becomes a

"don’t care" input and any pull-up resistors previously

enabled by HSWAP_EN are disabled. If a user I/O in the

application requires a weak pull-up resistor after configura-

tion, place a PULLUP primitive on the associated I/O pin.

Notes:

1. X = don’t care, either 0 or 1.

In user mode, after configuration successfully completes,

any levels applied to these input are ignored. Each of the

bitstream generator options M0Pin, M1Pin, and M2Pin

determines whether a weak pull-up resistor, weak pull-down

resistor, or no resistor is present on its respective mode pin,

M0, M1, or M2.

The Bitstream generator option HswapenPin determines

whether a weak pull-up resistor to VCCAUX, a weak

pull-down resistor, or no resistor is present on HSWAP_EN

after configuration.

HSWAP_EN: Disable Weak Pull-up Resistors Dur-

ing Configuration

JTAG: Dedicated JTAG Port Pins

These pins are dedicated connections to the four-wire IEEE

1532/IEEE 1149.1 JTAG port, shown in Figure 4 and

A Low on this asynchronous pin enables weak pull-up resis-

tors on all user I/Os, although only until device configuration

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Spartan-3 FPGA Family: Pinout Descriptions

described in Table 9. The JTAG port is used for bound-

ary-scan testing, device configuration, application debug-

ging, and possibly an additional serial port for the

application. These pins are dedicated and are not available

as user-I/O pins. Every package has four dedicated JTAG

pins and these pins are powered by the +2.5V VCCAUX

supply.

resistor. Similarly, the TDO pin is a CMOS output powered

from +2.5V. The TDO output can directly drive a 3.3V input

but with reduced noise immunity. See the "3.3V-Tolerant

Configuration Interface" section in Module 2 for additional

details.

The following interface precautions are recommended when

connecting the JTAG port to a 3.3V interface.

1. Set any inactive JTAG signals, including TCK, Low

when not actively used.

JTAG Port

2. Limit the drive current into a JTAG input to no more than

10 mA.

TDI

Data In

TDO

Data Out

TMS

TCK

Mode Select

VREF: User I/O or Input Buffer Reference

Voltage for Special Interface Standards

These pins are individual user-I/O pins unless collectively

they supply an input reference voltage, VREF_#, for any

SSTL, HSTL, GTL, or GTLP I/Os implemented in the asso-

ciated I/O bank.

Clock

DS099-4_04_042103

Figure 4: JTAG Port

Using JTAG Port After Configuration

The ‘#’ character in the pin name represents an integer, 0

through 7, that indicates the associated I/O bank.

The JTAG port is always active and available before, during,

and after FPGA configuration. Add the BSCAN_SPARTAN3

primitive to the design to create user-defined JTAG instruc-

tions and JTAG chains to communicate with internal logic.

The VREF function becomes active for this pin whenever a

signal standard requiring a reference voltage is used in the

associated bank.

Furthermore, the contents of the User ID register within the

JTAG port can be specified as a Bitstream Generation

option. By default, the 32-bit User ID register contains

0xFFFFFFFF.

If used as a user I/O, then each pin behaves as an indepen-

dent I/O described in the I/O type section. If used for a ref-

erence voltage within a bank, then all VREF pins within the

bank must be connected to the same reference voltage.

Precautions When Using the JTAG Port in 3.3V

Environments

Spartan-3 devices are designed and characterized to sup-

port certain I/O standards when VREF is connected to

+1.25V, +1.10V, +1.00V, +0.90V, +0.80V, and +0.75V.

The JTAG port is powered by the +2.5V VCCAUX power

supply. When connecting to a 3.3V interface, the JTAG input

pins must be current-limited to 10 mA or less using a series

During configuration, these pins behave exactly like

user-I/O pins.

Table 9: JTAG Pin Descriptions

Pin Name Direction

Description

Bitstream Generation Option

TCK

Input

Output

Test Clock: The TCK clock signal synchronizes all

boundary scan operations on its rising edge.

The BitGen option TckPin

determines whether a weak pull-up

resistor, weak pull-down resistor or

no resistor is present.

TDI

Test Data Input: TDI is the serial data input for all JTAG The BitGen option TdiPin

instruction and data registers. This input is sampled on determines whether a weak pull-up

the rising edge of TCK.

resistor, weak pull-down resistor or

no resistor is present.

TMS

TDO

Test Mode Select: The TMS input controls the

sequence of states through which the JTAG TAP state determines whether a weak pull-up

machine passes. This input is sampled on the rising

edge of TCK.

The BitGen option TmsPin

resistor, weak pull-down resistor or

no resistor is present.

Test Data Output: The TDO pin is the data output for The BitGen option TdoPin

all JTAG instruction and data registers. This output is determines whether a weak pull-up

sampled on the rising edge of TCK. The TDO output is resistor, weak pull-down resistor or

an active totem-pole driver and is not like the

no resistor is present.

open-collector TDO output on Virtex-II Pro™ FPGAs.

14

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Spartan-3 FPGA Family: Pinout Descriptions

If designing for footprint compatibility across the range of

devices in a specific package, and if the VREF_# pins within

a bank connect to an input reference voltage, then also con-

nect any N.C. (not connected) pins on the smaller devices in

that package to the input reference voltage. More details are

provided later for each package type.

from the VCCINT voltage supply inputs. VCCINT must be

+1.2V.

All VCCINT inputs must be connected together and to the

+1.2V voltage supply. Furthermore, there must be sufficient

supply decoupling to guarantee problem-free operation, as

described in XAPP623: Power Distribution System (PDS)

Design: Using Bypass/Decoupling Capacitors.

N.C. Type: Unconnected Package Pins

VCCAUX Type: Voltage Supply for Auxiliary

Logic

The VCCAUX pins supply power to various auxiliary cir-

cuits, such as to the Digital Clock Managers (DCMs), the

JTAG pins, and to the dedicated configuration pins (CON-

FIG type). VCCAUX must be +2.5V.

Pins marked as “N.C.” are unconnected for the specific

device/package combination. For other devices in this same

package, this pin may be used as an I/O or VREF connec-

tion. In both the pinout tables and the footprint diagrams,

unconnected pins are noted with either a black diamond

symbol () or a black square symbol ().

If designing for footprint compatibility across multiple device

densities, check the pin types of the other Spartan-3

devices available in the same footprint. If the N.C. pin

matches to VREF pins in other devices, and the VREF pins

are used in the associated I/O bank, then connect the N.C.

to the VREF voltage source.

All VCCAUX inputs must be connected together and to the

+2.5V voltage supply. Furthermore, there must be sufficient

supply decoupling to guarantee problem-free operation, as

described in XAPP623: Power Distribution System (PDS)

Design: Using Bypass/Decoupling Capacitors.

Because VCCAUX connects to the DCMs and the DCMs

are sensitive to voltage changes, be sure that the VCCAUX

supply and the ground return paths are designed for low

noise and low voltage drop, especially that caused by a

large number of simultaneous switching I/Os.

VCCO Type: Output Voltage Supply for I/O

Bank

Each I/O bank has its own set of voltage supply pins that

determines the output voltage for the output buffers in the

I/O bank. Furthermore, for some I/O standards such as

LVCMOS, LVCMOS25, LVTTL, etc., VCCO sets the input

threshold voltage on the associated input buffers.

GND Type: Ground

All GND pins must be connected and have a low resistance

path back to the various VCCO, VCCINT, and VCCAUX

supplies.

Spartan-3 devices are designed and characterized to sup-

port various I/O standards for VCCO values of +1.2V, +1.5V,

+1.8V, +2.5V, and +3.3V.

Pin Behavior During Configuration

Most VCCO pins are labeled as VCCO_# where the ‘#’

symbol represents the associated I/O bank number, an inte-

ger ranging from 0 to 7. In the 144-pin TQFP package

(TQ144) however, the VCCO pins along an edge of the

device are combined into a single VCCO input. For exam-

ple, the VCCO inputs for Bank 0 and Bank 1 along the top

edge of the package are combined and relabeled

VCCO_TOP. The bottom, left, and right edges are similarly

combined.

Table 10 shows how various pins behave during the FPGA

configuration process. The actual behavior depends on the

values applied to the M2, M1, and M0 mode select pins and

the HSWAP_EN pin. The mode select pins determine which

of the DUAL type pins are active during configuration. In

JTAG configuration mode, none of the DUAL-type pins are

used for configuration and all behave as user-I/O pins.

All DUAL-type pins not actively used during configuration

and all I/O-type, DCI-type, VREF-type, GCLK-type pins are

high impedance (floating, three-stated, Hi-Z) during the

configuration process. These pins are indicated in Table 10

as shaded table entries or cells. These pins have a weak

pull-up resistor to their associated VCCO if the HSWAP_EN

pin is Low.

In Serial configuration mode, VCCO_4 must be at a level

compatible with the attached configuration memory or data

source. In Parallel configuration mode, both VCCO_4 and

VCCO_5 must be at the same compatible voltage level.

All VCCO inputs to a bank must be connected together and

to the voltage supply. Furthermore, there must be sufficient

supply decoupling to guarantee problem-free operation, as

described in XAPP623: Power Distribution System (PDS)

Design: Using Bypass/Decoupling Capacitors.

After configuration completes, some pins have optional

behavior controlled by the configuration bitstream loaded

into the part. For example, via the bitstream, all unused I/O

pins can collectively be configured to have a weak pull-up

resistor, a weak pull-down resistor, or be left in a

high-impedance state.

VCCINT Type: Voltage Supply for Internal

Core Logic

Internal core logic circuits such as the configurable logic

blocks (CLBs) and programmable interconnect operate

DS099-4 (v1.5) July 13, 2004

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Spartan-3 FPGA Family: Pinout Descriptions

Table 10: Pin Behavior After Power-Up, During Configuration

Configuration Mode Settings <M2:M1:M0>

Serial Modes SelectMap Parallel Modes

Bitstream

Configuration

Option

Master

<0:0:0>

Slave

<1:1:1>

Master

<0:1:1>

Slave

<1:1:0>

JTAG Mode

<1:0:1>

Pin Name

I/O: General-purpose I/O pins

IO

UnusedPin

IO_Lxxy_#

DUAL: Dual-purpose configuration pins

IO_Lxxy_#/

DIN/D0

DIN (I)

D0 (I/O)

D1 (I/O)

D0 (I/O)

D1 (I/O)

Persist

UnusedPin

IO_Lxxy_#/

D1

Persist

UnusedPin

IO_Lxxy_#/

D2

D2 (I/O)

Persist

UnusedPin

IO_Lxxy_#/

D3

D3 (I/O)

Persist

UnusedPin

IO_Lxxy_#/

D4

D4 (I/O)

Persist

UnusedPin

IO_Lxxy_#/

D5

D5 (I/O)

Persist

UnusedPin

IO_Lxxy_#/

D6

D6 (I/O)

Persist

UnusedPin

IO_Lxxy_#/

D7

D7 (I/O)

Persist

UnusedPin

IO_Lxxy_#/

CS_B

CS_B (I)

RDWR_B (I)

BUSY (O)

CS_B (I)

RDWR_B (I)

BUSY (O)

Persist

UnusedPin

IO_Lxxy_#/

RDWR_B

Persist

UnusedPin

IO_Lxxy_#/

DOUT (O)

Persist

BUSY/DOUT

UnusedPin

IO_Lxxy_#/

INIT_B

INIT_B (I/OD) INIT_B (I/OD) INIT_B (I/OD) INIT_B (I/OD)

UnusedPin

DCI: Digitally Controlled Impedance reference resistor input pins

IO_Lxxy_#/

VRN_#

UnusedPin

IO/VRN_#

UnusedPin

IO_Lxxy_#/

VRP_#

IO/VRP_#

UnusedPin

16

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Spartan-3 FPGA Family: Pinout Descriptions

Table 10: Pin Behavior After Power-Up, During Configuration (Continued)

Configuration Mode Settings <M2:M1:M0>

Serial Modes

SelectMap Parallel Modes

Bitstream

Configuration

Option

Master

<0:0:0>

Slave

<1:1:1>

Master

<0:1:1>

Slave

<1:1:0>

JTAG Mode

<1:0:1>

Pin Name

GCLK: Global clock buffer inputs

IO_Lxxy_#/

GCLK0through

GCLK7

UnusedPin

VREF: I/O bank input reference voltage pins

IO_Lxxy_#/

VREF_#

UnusedPin

IO/VREF_#

CONFIG: Dedicated configuration pins

CCLK

CCLK (O)

CCLK (I)

CCLK (O)

CCLK (I)

CclkPin

ConfigRate

PROG_B

PROG_B (I)

(pull-up)

PROG_B (I)

(pull-up)

PROG_B (I)

(pull-up)

PROG_B (I)

(pull-up)

PROG_B (I),

Via JPROG_B

instruction

ProgPin

DONE

DONE (I/OD)

DriveDone

DonePin

DonePipe

M2

M2=0 (I)

M1=0 (I)

M0=0 (I)

M2=1 (I)

M1=1 (I)

M0=1 (I)

M2=0 (I)

M1=1 (I)

M0=1 (I)

M2=1 (I)

M1=1 (I)

M0=0 (I)

M2=1 (I)

M1=0 (I)

M0=1 (I)

M2Pin

M1Pin

M1

M0

M0Pin

HSWAP_EN

(I)

HSWAP_EN

(I)

HSWAP_EN

(I)

HSWAP_EN

(I)

HSWAP_EN

(I)

HswapenPin

JTAG: JTAG interface pins

TDI

TDI (I)

TMS (I)

TCK (I)

TDO (O)

TDI (I)

TMS (I)

TCK (I)

TDO (O)

TDI (I)

TMS (I)

TCK (I)

TDO (O)

TDI (I)

TMS (I)

TCK (I)

TDO (O)

TdiPin

TmsPin

TckPin

TdoPin

TMS

TCK

TDO

TMS (I)

TCK (I)

TDO (O)

VCCO: I/O bank output voltage supply pins

VCCO_4

(for DUAL pins)

Same voltage Same voltage Same voltage Same voltage

VCCO_4

VCCO_5

as external

interface

as external

interface

as external

interface

as external

interface

VCCO_5

(for DUAL pins)

VCCO_5

VCCO_#

Same voltage Same voltage

as external

interface

as external

interface

VCCO_#

+2.5V

VCCAUX: Auxiliary voltage supply pins

VCCAUX +2.5V

+2.5V

DS099-4 (v1.5) July 13, 2004

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Spartan-3 FPGA Family: Pinout Descriptions

Table 10: Pin Behavior After Power-Up, During Configuration (Continued)

Configuration Mode Settings <M2:M1:M0>

Serial Modes

SelectMap Parallel Modes

Bitstream

Configuration

Option

Master

<0:0:0>

Slave

<1:1:1>

Master

<0:1:1>

Slave

<1:1:0>

JTAG Mode

<1:0:1>

Pin Name

VCCINT: Internal core voltage supply pins

VCCINT

+1.2V

GND

+1.2V

GND

+1.2V

GND

+1.2V

GND

GND: Ground supply pins

GND

Notes:

1. #= I/O bank number, an integer from 0 to 7.

2. (I) = input, (O) = output, (OD) = open-drain output, (I/O) = bidirectional, (I/OD) = bidirectional with open-drain output. Open-drain

output requires pull-up to create logic High level.

3.

Shaded cell indicates that the pin is high-impedance during configuration. To enable a soft pull-up resistor during configuration,

drive or tie HSWAP_EN Low.

the name of the bitstream generator option variable, and the

legal values for each variable. The default option setting for

each variable is indicated with bold, underlined text.

Bitstream Options

Table 11 lists the various bitstream options that affect pins

on a Spartan-3 FPGA. The table shows the names of the

affected pins, describes the function of the bitstream option,

Table 11: Bitstream Options Affecting Spartan-3 Pins

Option

Variable

Name

Values

(default

value)

Affected Pin

Name(s)

Bitstream Generation Function

•

Pulldown

Pullup

Pullnone

All unused I/O pins of For all I/O pins that are unused after configuration, this option

UnusedPin

type I/O, DUAL,

defines whether the I/Os are individually tied to VCCO via a weak

pull-up resistor, tied ground via a weak pull-down resistor, or left

floating. If left floating, the unused pins should be connected to a

defined logic level, either from a source internal to the FPGA or

external.

GCLK, DCI, VREF

•

No

Yes

IO_Lxxy_#/DIN,

IO_Lxxy_#/DOUT,

IO_Lxxy_#/INIT_B

Serial configuration mode: If set to Yes, then these pins retain their

functionality after configuration completes, allowing for device

(re-)configuration. Readback is not supported in with serial mode.

Persist

•

No

Yes

IO_Lxxy_#/D0,

IO_Lxxy_#/D1,

IO_Lxxy_#/D2,

IO_Lxxy_#/D3,

IO_Lxxy_#/D4,

IO_Lxxy_#/D5,

IO_Lxxy_#/D6,

IO_Lxxy_#/D7,

IO_Lxxy_#/CS_B,

IO_Lxxy_#/RDWR_B,

IO_Lxxy_#/BUSY,

IO_Lxxy_#/INIT_B

Parallel configuration mode (also called SelectMAP): If set to Yes,

then these pins retain their SelectMAP functionality after

configuration completes, allowing for device readback and for

partial or complete (re-)configuration.

•

Pullup

Pullnone

CCLK

After configuration, this bitstream option either pulls CCLK to

VCCAUX via a weak pull-up resistor, or allows CCLK to float.

CclkPin

CCLK

For Master configuration modes, this option sets the approximate

frequency, in MHz, for the internal silicon oscillator.

ConfigRate 3, 6, 12, 25,

50

18

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Spartan-3 FPGA Family: Pinout Descriptions

Table 11: Bitstream Options Affecting Spartan-3 Pins (Continued)

Option

Variable

Name

Values

(default

value)

Affected Pin

Name(s)

Bitstream Generation Function

•

Pullup

Pullnone

PROG_B

A weak pull-up resistor to VCCAUX exists on PROG_B during

configuration. After configuration, this bitstream option either

pulls DONE to VCCAUX via a weak pull-up resistor, or allows

DONE to float.

ProgPin

•

Pullup

Pullnone

DONE

After configuration, this bitstream option either pulls DONE to

VCCAUX via a weak pull-up resistor, or allows DONE to float. See

also DriveDone option.

DonePin

•

No

Yes

If set to Yes, this option allows the FPGA’s DONE pin to drive High

when configuration completes. By default, the DONE is an

open-drain output and can only drive Low. Only single FPGAs and

the last FPGA in a multi-FPGA daisy-chain should use this option.

DriveDone

•

Pullup

M2

After configuration, this bitstream option either pulls M2 to

VCCAUX via a weak pull-up resistor, to ground via a weak

pull-down resistor, or allows M2 to float.

M2Pin

M1Pin

M0Pin

Pulldown

Pullnone

Pullup

Pulldown

Pullnone

Pullup

Pulldown

Pullnone

Pullup

Pulldown

Pullnone

Pullup

Pulldown

Pullnone

Pullup

Pulldown

Pullnone

Pullup

Pulldown

Pullnone

Pullup

Pulldown

Pullnone

M1

After configuration, this bitstream option either pulls M1 to

VCCAUX via a weak pull-up resistor, to ground via a weak

pull-down resistor, or allows M1 to float.

M0

After configuration, this bitstream option either pulls M0 to

VCCAUX via a weak pull-up resistor, to ground via a weak

pull-down resistor, or allows M0 to float.

HSWAP_EN

TDI

After configuration, this bitstream option either pulls HSWAP_EN HswapenPin

to VCCAUX via a weak pull-up resistor, to ground via a weak

pull-down resistor, or allows HSWAP_EN to float.

After configuration, this bitstream option either pulls TDI to

VCCAUX via a weak pull-up resistor, to ground via a weak

pull-down resistor, or allows TDI to float.

TdiPin

TmsPin

TckPin

TdoPin

TMS

TCK

TDO

After configuration, this bitstream option either pulls TMS to

VCCAUX via a weak pull-up resistor, to ground via a weak

pull-down resistor, or allows TMS to float.

After configuration, this bitstream option either pulls TCK to

VCCAUX via a weak pull-up resistor, to ground via a weak

pull-down resistor, or allows TCK to float.

After configuration, this bitstream option either pulls TDO to

VCCAUX via a weak pull-up resistor, to ground via a weak

pull-down resistor, or allows TDO to float.

where <variable_name> is one of the entries from

Table 11 and <value> is one of the possible values for the

specified variable. Multiple bitstream options may be

entered in this manner.

Setting Options via BitGen Command-Line

Program

To set one or more bitstream generator options using the

BitGen command-line program, enter

For a complete listing of all BitGen options, their possible

settings, and their default settings, enter the following com-

mand.

bitgen –g <variable_name>:<value>

[<variable_name>:<value> …]

bitgen -help spartan3

DS099-4 (v1.5) July 13, 2004

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Spartan-3 FPGA Family: Pinout Descriptions

Click the Configuration options tab and modify the avail-

able options as required by the application, as shown in

Figure 6.

Setting Options in Project Navigator

To set the bitstream generation options in Xilinx ISE Project

Navigator, right-click on the Generate Programming File

step in the Process View and click Properties, as shown in

Figure 5.

DS099-4_05_030103

Figure 5: Setting Properties for Generate Programming File Step

DS099-4_06_030103

Figure 6: Configuration Option Settings

20

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Spartan-3 FPGA Family: Pinout Descriptions

DS099-4_07_030103

Figure 7: Setting to Drive DONE Pin High after Configuration

To have the DONE pin drive High after successful configu-

ration, click the Startup options tab and check the Drive

Done Pin High box, as shown in Figure 7.

is available as a standard and an environmentally-friendly

lead-free (Pb-free) option. The Pb-free packages include an

extra ’G’ in the package style name. For example, the stan-

dard "VQ100" package becomes "VQG100" when ordered

as the Pb-free option. The mechanical dimensions of the

standard and Pb-free packages are similar, as shown in the

mechanical drawings provided in Table 13.

Click OK when finished.

Again, right-click on the Generate Programming File step

in the Process View. This time, choose Run or Rerun to

execute the changes.

Not all Spartan-3 densities are available in all packages.

However, for a specific package there is a common footprint

for that supports the various devices available in that pack-

age. See the footprint diagrams that follow.

Package Overview

Table 12 shows the nine low-cost, space-saving production

package styles for the Spartan-3 family. Each package style

Table 12: Spartan-3 Family Package Options

Maximum

I/O

Pitch

(mm)

Area

(mm)

Height

(mm)

Package

Leads

100

Type

VQ100 / VQG100

TQ144 / TQG144

PQ208 / PQG208

FT256 / FTG256

FG320 / FGG320

FG456 / FGG456

FG676 / FGG676

FG900 / FGG900

FG1156 / FGG1156

Very-thin Quad Flat Pack

Thin Quad Flat Pack

63

0.5

1.0

16 x 16

22 x 22

30.6 x 30.6

17 x 17

19 x 19

23 x 23

27 x 27

31 x 31

35 x 35

1.20

1.60

4.10

1.55

2.00

2.60

144

97

208

Quad Flat Pack

141

173

221

333

489

633

784

256

Fine-pitch, Thin Ball Grid Array

Fine-pitch Ball Grid Array

320

456

676

900

1156

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Spartan-3 FPGA Family: Pinout Descriptions

Detailed mechanical drawings for each package type are

available from the Xilinx website at the specified location in

Table 13.

Table 13: Xilinx Package Mechanical Drawings

Package

Web Link (URL)

http://www.xilinx.com/bvdocs/packages/vq100.pdf

http://www.xilinx.com/bvdocs/packages/tq144.pdf

http://www.xilinx.com/bvdocs/packages/pq208.pdf

http://www.xilinx.com/bvdocs/packages/ft256.pdf

http://www.xilinx.com/bvdocs/packages/fg320.pdf

http://www.xilinx.com/bvdocs/packages/fg456.pdf

http://www.xilinx.com/bvdocs/packages/fg676.pdf

http://www.xilinx.com/bvdocs/packages/fg900.pdf

http://www.xilinx.com/bvdocs/packages/fg1156.pdf

VQ100 / VQG100

TQ144 / TQG144

PQ208 / PQG208

FT256 / FTG256

FG320 / FGG320

FG456 / FGG456

FG676 / FGG676

FG900 /FGG900

FG1156 / FGG1156

Each package has three separate voltage supply

inputs—VCCINT, VCCAUX, and VCCO—and a common

ground return, GND. The numbers of pins dedicated to

these functions varies by package, as shown in Table 14.

A majority of package pins are user-defined I/O pins. How-

ever, the numbers and characteristics of these I/O depends

on the device type and the package in which it is available,

as shown in Table 15. The table shows the maximum num-

ber of single-ended I/O pins available, assuming that all

I/O-, DUAL-, DCI-, VREF-, and GCLK-type pins are used as

general-purpose I/O. Likewise, the table shows the maxi-

mum number of differential pin-pairs available on the pack-

age. Finally, the table shows how the total maximum user

I/Os are distributed by pin type, including the number of

unconnected—i.e., N.C.—pins on the device.

Table 14: Power and Ground Supply Pins by Package

Package

VQ100

TQ144

PQ208

FT256

VCCINT

VCCAUX

VCCO

8

GND

10

4

12

16

4

8

12

28

8

24

32

FG320

FG456

FG676

FG900

FG1156

12

20

32

40

8

28

40

8

40

52

16

24

32

64

76

80

120

184

104

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Spartan-3 FPGA Family: Pinout Descriptions

All Possible I/O Pins by Type

Table 15: Maximum User I/Os by Package

Maximum

Differential

Pairs

Maximum

Device

Package

VQ100

TQ144

PQ208

FT256

FG320

FG456

FG676

FG900

FG1156

User I/Os

I/O

22

DUAL

12

DCI

14

16

VREF

7

GCLK

N.C.

0

XC3S50

63

29

8

XC3S200

XC3S50

63

22

7

0

97

46

51

12

16

22

24

29

32

36

40

48

55

56

0

XC3S200

XC3S400

XC3S50

97

46

51

0

97

46

51

0

124

141

173

221

264

333

391

487

489

565

633

712

784

56

72

17

0

XC3S200

XC3S400

XC3S200

XC3S400

XC3S1000

XC3S400

XC3S1000

XC3S1500

XC3S400

XC3S1000

XC3S1500

XC3S1000

XC3S1500

XC3S2000

XC3S4000

XC3S5000

XC3S4000

XC3S5000

62

83

62

83

0

76

113

156

196

261

315

403

405

481

549

621

692

0

76

0

76

0

100

116

149

175

221

270

300

312

344

0

69

0

98

2

0

68

0

73

1

Electronic versions of the package pinout tables and foot-

prints are available for download from the Xilinx website.

Using a spreadsheet program, the data can be sorted and

reformatted according to any specific needs. Similarly, the

ASCII-text file is easily parsed by most scripting programs.

Download the files from the following location:

http://www.xilinx.com/bvdocs/publications/s3_pin.zip

DS099-4 (v1.5) July 13, 2004

Product Specification

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1-800-255-7778

23

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 16: VQ100 Package Pinout

VQ100: 100-lead Very-thin Quad Flat

Package

The XC3S50 and the XC3S200 devices are available in the

100-lead very-thin quad flat package, VQ100. Both devices

share a common footprint for this package as shown in

Table 16 and Figure 8.

XC3S50

XC3S200

VQ100 Pin

Number

Bank

3

4

5

6

7

Pin Name

Type

I/O

IO_L24P_3

P60

P63

P62

P57

P50

P49

P48

P47

P44

P43

P42

P40

P39

P38

P46

P28

P27

P32

P30

P35

P34

P37

P36

P31

P17

P21

P23

P22

P16

P15

P14

P13

P19

P2

IO_L40N_3/VREF_3

IO_L40P_3

VREF

I/O

All the package pins appear in Table 16 and are sorted by

bank number, then by pin name. Pairs of pins that form a dif-

ferential I/O pair appear together in the table. The table also

shows the pin number for each pin and the pin type, as

defined earlier.

VCCO_3

VCCO

DCI

IO_L01N_4/VRP_4

IO_L01P_4/VRN_4

IO_L27N_4/DIN/D0

IO_L27P_4/D1

IO_L30N_4/D2

IO_L30P_4/D3

IO_L31N_4/INIT_B

IO_L31P_4/DOUT/BUSY

IO_L32N_4/GCLK1

IO_L32P_4/GCLK0

VCCO_4

DCI

DUAL

GCLK

VCCO

DUAL

GCLK

VCCO

I/O

Pinout Table

Table 16: VQ100 Package Pinout

XC3S50

XC3S200

Pin Name

VQ100 Pin

Number

Bank

0

Type

DCI

IO_L01N_0/VRP_0

IO_L01P_0/VRN_0

IO_L31N_0

P97

P96

P92

P91

P90

P89

P94

P81

P80

P79

P86

P85

P88

P87

P83

P75

P74

P72

P71

P68

P67

P65

P64

P70

P55

P59

P54

P53

P61

0

DCI

0

I/O

0

IO_L31P_0/VREF_0

IO_L32N_0/GCLK7

IO_L32P_0/GCLK6

VCCO_0

VREF

GCLK

VCCO

I/O

IO_L01N_5/RDWR_B

IO_L01P_5/CS_B

IO_L28N_5/D6

IO_L28P_5/D7

IO_L31N_5/D4

IO_L31P_5/D5

IO_L32N_5/GCLK3

IO_L32P_5/GCLK2

VCCO_5

0

1

IO

1

IO_L01N_1/VRP_1

IO_L01P_1/VRN_1

IO_L31N_1/VREF_1

IO_L31P_1

DCI

1

DCI

1

VREF

I/O

1

IO_L32N_1/GCLK5

IO_L32P_1/GCLK4

VCCO_1

GCLK

VCCO

DCI

IO

1

IO

I/O

1

IO_L01N_6/VRP_6

IO_L01P_6/VRN_6

IO_L24N_6/VREF_6

IO_L24P_6

DCI

2

IO_L01N_2/VRP_2

IO_L01P_2/VRN_2

IO_L21N_2

DCI

2

DCI

VREF

I/O

2

I/O

2

IO_L21P_2

I/O

IO_L40N_6

I/O

2

IO_L24N_2

I/O

IO_L40P_6/VREF_6

VCCO_6

VREF

VCCO

DCI

2

IO_L24P_2

I/O

2

IO_L40N_2

I/O

IO_L01N_7/VRP_7

IO_L01P_7/VRN_7

IO_L21N_7

2

IO_L40P_2/VREF_2

VCCO_2

VREF

VCCO

I/O

P1

DCI

2

P5

I/O

3

IO

IO_L21P_7

P4

I/O

3

IO

I/O

IO_L23N_7

P9

I/O

3

IO_L01N_3/VRP_3

IO_L01P_3/VRN_3

IO_L24N_3

DCI

IO_L23P_7

P8

I/O

3

DCI

IO_L40N_7/VREF_7

IO_L40P_7

P12

P11

VREF

I/O

3

I/O

24

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 16: VQ100 Package Pinout

XC3S50

XC3S200

Pin Name

XC3S50

XC3S200

Pin Name

VQ100 Pin

Number

VQ100 Pin

Number

Bank

7

Type

VCCO

GND

Bank

Type

VCCINT

CONFIG

JTAG

VCCO_7

P6

N/A

VCCINT

P93

P52

P51

P98

P25

P24

P26

P99

P77

P100

P76

P78

N/A

GND

P3

VCCAUX CCLK

VCCAUX DONE

GND

P10

P20

P29

P41

P56

P66

P73

P82

P95

P7

GND

VCCAUX HSWAP_EN

VCCAUX M0

GND

VCCAUX M1

GND

VCCAUX M2

GND

VCCAUX PROG_B

VCCAUX TCK

VCCAUX TDI

GND

JTAG

GND

VCCAUX TDO

VCCAUX TMS

JTAG

VCCAUX

VCCINT

VCCAUX

VCCINT

JTAG

P33

P58

P84

P18

P45

P69

User I/Os by Bank

Table 17 indicates how the available user-I/O pins are dis-

tributed between the eight I/O banks on the VQ100 pack-

age.

Table 17: User I/Os Per Bank in VQ100 Package

All Possible I/O Pins by Type

Maximum

Package Edge

I/O Bank

I/O

1

DUAL

DCI

2

VREF

GCLK

0

1

2

3

4

5

6

7

6

0

6

0

1

0

2

1

2

0

2

0

Top

7

2

8

5

2

Right

Bottom

Left

8

5

2

10

8

0

2

0

8

4

2

8

5

2

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

25

R

Spartan-3 FPGA Family: Pinout Descriptions

VQ100 Footprint

IO_L01P_7/VRN_7

1

2

75 IO_L01N_2/VRP_2

74 IO_L01P_2/VRN_2

73 GND

Bank 0

Bank 1

IO_L01N_7/VRP_7

GND

3

IO_L21P_7

IO_L21N_7

4

72 IO_L21N_2

71 IO_L21P_2

70 VCCO_2

5

6

VCCO_7

VCCAUX

7

69 VCCINT

IO_L23P_7

IO_L23N_7

8

68 IO_L24N_2

67 IO_L24P_2

66 GND

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

GND

IO_L40P_7

65 IO_L40N_2

64 IO_L40P_2/VREF_2

63 IO_L40N_3/VREF_3

62 IO_L40P_3

61 IO_L24N_3

60 IO_L24P_3

59 IO

IO_L40N_7/VREF_7

IO_L40P_6/VREF_6

IO_L40N_6

IO_L24P_6

IO_L24N_6/VREF_6

IO

VCCINT

58 VCCAUX

57 VCCO_3

VCCO_6

56 GND

GND

55 IO

IO

IO_L01P_6/VRN_6

54 IO_L01N_3/VRP_3

53 IO_L01P_3/VRN_3

52 CCLK

IO_L01N_6/VRP_6

M1

M0

Bank 5

Bank 4

no VREF, no DCI)

(no VREF)

(

51 DONE

DS099-4_15_042303

Figure 8: VQ100 Package Footprint (top view). Note pin 1 indicator in top-left corner and logo orientation.

I/O: Unrestricted, general-purpose user I/O

DUAL: Configuration pin, then possible

user I/O

VREF: User I/O or input voltage reference for

bank

22

12

7

DCI: User I/O or reference resistor input for

bank

GCLK: User I/O or global clock buffer

input

VCCO: Output voltage supply for bank

14

7

8

4

8

4

CONFIG: Dedicated configuration pins

JTAG: Dedicated JTAG port pins

VCCINT: Internal core voltage supply (+1.2V)

VCCAUX: Auxiliary voltage supply (+2.5V)

N.C.: No unconnected pins in this package

GND: Ground

0

10

26

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 18: TQ144 Package Pinout (Continued)

TQ144: 144-lead Thin Quad Flat

Package

The XC3S50, the XC3S200, and the XC3S400 are avail-

able in the 144-lead thin quad flat package, TQ144. Conse-

quently, there is only one footprint for this package as shown

in Table 18 and Figure 9.

XC3S50

XC3S200

XC3S400

Pin Name

TQ144Pin

Number

Bank

2

3

4

5

Type

I/O

IO_L20P_2

P104

P103

P102

P100

P99

P98

P97

P96

P95

P93

P92

P76

P74

P73

P78

P77

P80

P79

P83

P82

P85

P84

P87

P86

P90

P89

P70

P69

P68

P65

P63

P60

P59

P58

P57

P56

P55

P44

P41

P40

P47

IO_L21N_2

I/O

The TQ144 package only has four separate VCCO inputs,

unlike the other packages, which have eight separate

VCCO inputs. The TQ144 package has a separate VCCO

input for the top, bottom, left, and right. However, there are

still eight separate I/O banks, as shown in Table 18 and

Figure 9. Banks 0 and 1 share the VCCO_TOP input, Banks

2 and 3 share the VCCO_RIGHT input, Banks 4 and 5

share the VCCO_BOTTOM input, and Banks 6 and 7 share

the VCCO_LEFT input.

IO_L21P_2

I/O

IO_L22N_2

I/O

IO_L22P_2

I/O

IO_L23N_2/VREF_2

IO_L23P_2

VREF

I/O

IO_L24N_2

I/O

IO_L24P_2

I/O

All the package pins appear in Table 18 and are sorted by

bank number, then by pin name. Pairs of pins that form a dif-

ferential I/O pair appear together in the table. The table also

shows the pin number for each pin and the pin type, as

defined earlier.

IO_L40N_2

I/O

IO_L40P_2/VREF_2

IO

VREF

I/O

IO_L01N_3/VRP_3

IO_L01P_3/VRN_3

IO_L20N_3

DCI

Pinout Table

I/O

IO_L20P_3

I/O

Table 18: TQ144 Package Pinout

IO_L21N_3

I/O

XC3S50

XC3S200

IO_L21P_3

I/O

XC3S400

Pin Name

TQ144Pin

Number

IO_L22N_3

I/O

Bank

0

Type

DCI

I/O

IO_L22P_3

I/O

IO_L01N_0/VRP_0

IO_L01P_0/VRN_0

IO_L27N_0

P141

P140

P137

P135

P132

P131

P130

P129

P128

P127

P116

P113

P112

P119

P118

P123

P122

P125

P124

P108

P107

P105

IO_L23N_3

I/O

0

IO_L23P_3/VREF_3

IO_L24N_3

VREF

I/O

0

IO_L27P_0

I/O

IO_L24P_3

I/O

0

IO_L30N_0

I/O

IO_L40N_3/VREF_3

IO_L40P_3

VREF

I/O

0

IO_L30P_0

I/O

0

IO_L31N_0

I/O

IO/VREF_4

VREF

DCI

0

IO_L31P_0/VREF_0

IO_L32N_0/GCLK7

IO_L32P_0/GCLK6

IO

VREF

GCLK

I/O

IO_L01N_4/VRP_4

IO_L01P_4/VRN_4

IO_L27N_4/DIN/D0

IO_L27P_4/D1

IO_L30N_4/D2

IO_L30P_4/D3

IO_L31N_4/INIT_B

IO_L31P_4/DOUT/BUSY

IO_L32N_4/GCLK1

IO_L32P_4/GCLK0

IO/VREF_5

0

DCI

0

DUAL

GCLK

VREF

DUAL

1

IO_L01N_1/VRP_1

IO_L01P_1/VRN_1

IO_L28N_1

DCI

I/O

1

IO_L28P_1

I/O

1

IO_L31N_1/VREF_1

IO_L31P_1

VREF

I/O

1

IO_L32N_1/GCLK5

IO_L32P_1/GCLK4

IO_L01N_2/VRP_2

IO_L01P_2/VRN_2

IO_L20N_2

GCLK

DCI

I/O

1

IO_L01N_5/RDWR_B

IO_L01P_5/CS_B

IO_L28N_5/D6

2

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

27

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 18: TQ144 Package Pinout (Continued)

XC3S50

XC3S200

XC3S400

Pin Name

TQ144Pin

Number

XC3S400

Pin Name

TQ144Pin

Number

Bank

5

Type

DUAL

GCLK

DCI

Bank

4,5

Type

VCCO

GND

IO_L28P_5/D7

P46

P51

P50

P53

P52

P36

P35

P33

P32

P31

P30

P28

P27

P26

P25

P24

P23

P21

P20

P4

VCCO_BOTTOM

VCCO_LEFT

GND

P43

P66

5

IO_L31N_5/D4

IO_L31P_5/D5

IO_L32N_5/GCLK3

IO_L32P_5/GCLK2

IO_L01N_6/VRP_6

IO_L01P_6/VRN_6

IO_L20N_6

4,5

5

6,7

P19

5

6,7

P34

5

6,7

P3

6

N/A

P136

P139

P114

P117

P94

6

DCI

GND

6

I/O

GND

6

IO_L20P_6

I/O

GND

6

IO_L21N_6

I/O

GND

6

IO_L21P_6

I/O

GND

P101

P81

GND

6

IO_L22N_6

I/O

GND

6

IO_L22P_6

I/O

GND

P88

GND

6

IO_L23N_6

I/O

GND

P64

GND

6

IO_L23P_6

I/O

GND

P67

GND

6

IO_L24N_6/VREF_6

IO_L24P_6

VREF

I/O

GND

P42

GND

6

GND

P45

GND

6

IO_L40N_6

I/O

GND

P22

GND

6

IO_L40P_6/VREF_6

IO/VREF_7

VREF

DCI

GND

P29

GND

7

GND

P9

GND

7

IO_L01N_7/VRP_7

IO_L01P_7/VRN_7

IO_L20N_7

P2

GND

P16

GND

7

P1

DCI

VCCAUX

VCCINT

P134

P120

P62

VCCAUX

VCCINT

CONFIG

JTAG

7

P6

I/O

7

IO_L20P_7

P5

I/O

7

IO_L21N_7

P8

I/O

P48

7

IO_L21P_7

P7

I/O

P133

P121

P61

7

IO_L22N_7

P11

P10

P13

P12

P15

P14

P18

P17

P126

P138

P115

P106

P75

P91

P54

I/O

7

IO_L22P_7

I/O

7

IO_L23N_7

I/O

P49

7

IO_L23P_7

I/O

VCCAUX CCLK

VCCAUX DONE

VCCAUX HSWAP_EN

VCCAUX M0

P72

7

IO_L24N_7

I/O

P71

7

IO_L24P_7

I/O

P142

P38

7

IO_L40N_7/VREF_7

IO_L40P_7

VREF

I/O

7

VCCAUX M1

P37

0,1

2,3

4,5

VCCO_TOP

VCCO

VCCAUX M2

P39

VCCO_TOP

VCCAUX PROG_B

VCCAUX TCK

VCCAUX TDI

P143

P110

P144

P109

P111

VCCO_TOP

VCCO_RIGHT

VCCO_BOTTOM

JTAG

VCCAUX TDO

VCCAUX TMS

JTAG

28

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

User I/Os by Bank

Table 19 indicates how the available user-I/O pins are dis-

tributed between the eight I/O banks on the TQ144 pack-

age.

Table 19: User I/Os Per Bank in TQ144 Package

All Possible I/O Pins by Type

Maximum

Package Edge

I/O Bank

I/O

10

9

I/O

5

DUAL

DCI

2

VREF

GCLK

0

1

2

3

4

5

6

7

0

6

0

1

2

1

2

0

2

0

Top

4

2

14

15

11

9

10

11

0

2

Right

Bottom

Left

2

0

14

15

10

11

2

DS099-4 (v1.5) July 13, 2004

Product Specification

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1-800-255-7778

29

R

Spartan-3 FPGA Family: Pinout Descriptions

TQ144 Footprint

IO_L01P_7/VRN_7

IO_L01N_7/VRP_7

VCCO_LEFT

IO/VREF_7

IO_L20P_7

1

2

3

4

5

6

7

8

9

108 IO_L01N_2/VRP_2

107 IO_L01P_2/VRN_2

106 VCCO_RIGHT

105 IO_L20N_2

104 IO_L20P_2

103 IO_L21N_2

102 IO_L21P_2

101 GND

Bank 0

Bank 1

VCCO for Top Edge

X

IO_L20N_7

IO_L21P_7

IO_L21N_7

GND

100 IO_L22N_2

99 IO_L22P_2

98 IO_L23N_2/VREF_2

97 IO_L23P_2

96 IO_L24N_2

95 IO_L24P_2

94 GND

IO_L22P_7 10

IO_L22N_7 11

IO_L23P_7 12

IO_L23N_7 13

IO_L24P_7 14

IO_L24N_7 15

GND 16

93 IO_L40N_2

92 IO_L40P_2/VREF_2

91 VCCO_RIGHT

90 IO_L40N_3/VREF_3

89 IO_L40P_3

88 GND

IO_L40P_7 17

IO_L40N_7/VREF_7 18

VCCO_LEFT 19

IO_L40P_6/VREF_6 20

IO_L40N_6 21

GND 22

87 IO_L24N_3

86 IO_L24P_3

85 IO_L23N_3

84 IO_L23P_3/VREF_3

83 IO_L22N_3

82 IO_L22P_3

81 GND

IO_L24P_6 23

IO_L24N_6/VREF_6 24

IO_L23P_6 25

IO_L23N_6 26

IO_L22P_6 27

IO_L22N_6 28

GND 29

80 IO_L21N_3

79 IO_L21P_3

78 IO_L20N_3

77 IO_L20P_3

76 IO

IO_L21P_6 30

IO_L21N_6 31

IO_L20P_6 32

IO_L20N_6 33

VCCO_LEFT 34

IO_L01P_6/VRN_6 35

IO_L01N_6/VRP_6 36

VCCO for Bottom Edge

75 VCCO_RIGHT

74

73

IO_L01N_3/VRP_3

IO_L01P_3/VRN_3

Bank 5

Bank 4

(no DCI)

DS099-4_08_121103

Figure 9: TQ144 Package Footprint (top view). Note pin 1 indicator in top-left corner and logo orientation.

I/O: Unrestricted, general-purpose user I/O

DUAL: Configuration pin, then possible

user I/O

VREF: User I/O or input voltage reference for

bank

51

12

DCI: User I/O or reference resistor input for

bank

GCLK: User I/O or global clock buffer

input

VCCO: Output voltage supply for bank

14

7

12

4

8

4

CONFIG: Dedicated configuration pins

JTAG: Dedicated JTAG port pins

VCCINT: Internal core voltage supply (+1.2V)

VCCAUX: Auxiliary voltage supply (+2.5V)

N.C.: No unconnected pins in this package

GND: Ground

0

16

4

30

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Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 20: PQ208 Package Pinout (Continued)

PQ208: 208-lead Plastic Quad Flat Pack

XC3S200

XC3S400

Pin Name

PQ208

Number

The 208-lead plastic quad flat package, PQ208, supports

three different Spartan-3 devices, including the XC3S50,

the XC3S200, and the XC3S400. The footprints for the

XC3S200 and XC3S400 are identical, as shown in Table 20

and Figure 10. The XC3S50, however, has fewer I/O pins

resulting in 17 unconnected pins on the PQ208 package,

labeled as “N.C.” In Table 20 and Figure 10, these uncon-

nected pins are indicated with a black diamond symbol ().

XC3S50

Pin Name

Bank

Type

0

IO_L32N_0/ IO_L32N_0/

P184

GCLK

GCLK7

0

IO_L32P_0/

GCLK6

IO_L32P_0/

GCLK6

P183

GCLK

0

1

VCCO_0

IO

VCCO_0

IO

P188

P201

P167

P175

P182

P162

VCCO

I/O

All the package pins appear in Table 20 and are sorted by

bank number, then by pin name. Pairs of pins that form a dif-

ferential I/O pair appear together in the table. The table also

shows the pin number for each pin and the pin type, as

defined earlier.

IO

I/O

IO

I/O

IO_L01N_1/ IO_L01N_1/

DCI

If there is a difference between the XC3S50 pinout and the

pinout for the XC3S200 and XC3S400, then that difference

is highlighted in Table 20. If the table entry is shaded grey,

then there is an unconnected pin on the XC3S50 that maps

to a user-I/O pin on the XC3S200 and XC3S400. If the table

entry is shaded tan, then the unconnected pin on the

XC3S50 maps to a VREF-type pin on the XC3S200 and

XC3S400. If the other VREF pins in the bank all connect to

a voltage reference to support a special I/O standard, then

also connect the N.C. pin on the XC3S50 to the same VREF

voltage. This provides maximum flexibility as you could

potentially migrate a design from the XC3S50 device to an

XC3S200 or XC3S400 FPGA without changing the printed

circuit board.

VRP_1

1

IO_L01P_1/

VRN_1

IO_L01P_1/

VRN_1

P161

P166

DCI

IO_L10N_1/ IO_L10N_1/

VREF

VREF_1

1

IO_L10P_1

IO_L27N_1

IO_L27P_1

IO_L28N_1

IO_L28P_1

IO_L10P_1

IO_L27N_1

IO_L27P_1

IO_L28N_1

IO_L28P_1

P165

P169

P168

P172

P171

P178

I/O

IO_L31N_1/ IO_L31N_1/

VREF

VREF_1

1

IO_L31P_1

P176

P181

I/O

Pinout Table

IO_L32N_1/ IO_L32N_1/

GCLK5

GCLK

Table 20: PQ208 Package Pinout

GCLK5

XC3S200

XC3S400

Pin Name

PQ208

Number

1

IO_L32P_1/

GCLK4

IO_L32P_1/

GCLK4

P180

GCLK

XC3S50

Pin Name

Bank

Type

I/O

1

2

VCCO_1

N.C. ()

VCCO_1

IO/VREF_2

P164

P177

P154

P156

VCCO

VREF

DCI

0

IO

P189

P197

P200

P205

P204

IO

I/O

N.C. ()

IO/VREF_0

VREF

DCI

IO_L01N_2/ IO_L01N_2/

VRP_2

IO_L01N_0/ IO_L01N_0/

2

IO_L01P_2/

VRN_2

IO_L01P_2/

VRN_2

P155

DCI

VRP_0

0

IO_L01P_0/

VRN_0

IO_L01P_0/

VRN_0

P203

DCI

2

IO_L19N_2

IO_L19P_2

IO_L20N_2

IO_L20P_2

IO_L21N_2

IO_L21P_2

IO_L22N_2

IO_L22P_2

IO_L19N_2

IO_L19P_2

IO_L20N_2

IO_L20P_2

IO_L21N_2

IO_L21P_2

IO_L22N_2

IO_L22P_2

P152

P150

P149

P148

P147

P146

P144

P143

P141

I/O

0

IO_L25N_0

IO_L25P_0

IO_L27N_0

IO_L27P_0

IO_L30N_0

IO_L30P_0

IO_L31N_0

IO_L25N_0

IO_L25P_0

IO_L27N_0

IO_L27P_0

IO_L30N_0

IO_L30P_0

IO_L31N_0

P199

P198

P196

P194

P191

P190

P187

P185

I/O

IO_L23N_2/ IO_L23N_2/

VREF_2

VREF

IO_L31P_0/

VREF_0

IO_L31P_0/

VREF_0

VREF

VREF_2

2

IO_L23P_2

P140

I/O

DS099-4 (v1.5) July 13, 2004

Product Specification

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31

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 20: PQ208 Package Pinout (Continued)

XC3S200

XC3S400

Pin Name

PQ208

Number

XC3S200

XC3S400

Pin Name

PQ208

Number

XC3S50

Pin Name

XC3S50

Pin Name

Bank

Type

I/O

Bank

Type

2

IO_L24N_2

IO_L24P_2

N.C. ()

IO_L24N_2

IO_L24P_2

IO_L39N_2

IO_L39P_2

IO_L40N_2

P139

P138

P137

P135

P133

P132

4

IO_L01P_4/

VRN_4

IO_L01P_4/

VRN_4

P100

DCI

I/O

4

IO_L25N_4

IO_L25P_4

IO_L25N_4

IO_L25P_4

P95

P94

P92

I/O

N.C. ()

I/O

IO_L27N_4/ IO_L27N_4/

DUAL

IO_L40N_2

I/O

DIN/D0

IO_L40P_2/

VREF_2

IO_L40P_2/

VREF_2

VREF

4

IO_L27P_4/

D1

IO_L27P_4/

D1

P90

P87

P86

P83

P81

P80

P79

DUAL

GCLK

2

3

VCCO_2

P136

P153

P107

VCCO

DCI

IO_L30N_4/ IO_L30N_4/

D2

IO_L01N_3/ IO_L01N_3/

IO_L30P_4/

D3

IO_L30P_4/

D3

VRP_3

3

IO_L01P_3/

VRN_3

IO_L01P_3/

VRN_3

P106

DCI

IO_L31N_4/ IO_L31N_4/

INIT_B

3

N.C. ()

IO_L17N_3

P109

P108

I/O

IO_L31P_4/

DOUT/BUSY DOUT/BUSY

IO_L17P_3/

VREF_3

VREF

IO_L32N_4/ IO_L32N_4/

GCLK1

3

IO_L19N_3

IO_L19P_3

IO_L20N_3

IO_L20P_3

IO_L21N_3

IO_L21P_3

IO_L22N_3

IO_L22P_3

IO_L23N_3

IO_L19N_3

IO_L19P_3

IO_L20N_3

IO_L20P_3

IO_L21N_3

IO_L21P_3

IO_L22N_3

IO_L22P_3

IO_L23N_3

P113

P111

P115

P114

P117

P116

P120

P119

P123

P122

I/O

IO_L32P_4/

GCLK0

IO_L32P_4/

GCLK0

I/O

4

5

VCCO_4

IO

VCCO_4

IO

P84

P98

P63

P71

P78

P58

VCCO

I/O

IO

I/O

IO/VREF_5

VREF

DUAL

I/O

IO_L01N_5/ IO_L01N_5/

I/O

RDWR_B

IO_L23P_3/

VREF_3

IO_L23P_3/

VREF_3

VREF

5

IO_L01P_5/

CS_B

IO_L01P_5/

CS_B

P57

P62

P61

P65

DUAL

DCI

3

IO_L24N_3

IO_L24P_3

N.C. ()

IO_L24N_3

IO_L24P_3

IO_L39N_3

IO_L39P_3

P125

P124

P128

P126

P131

I/O

IO_L10N_5/ IO_L10N_5/

VRP_5

I/O

IO_L10P_5/

VRN_5

IO_L10P_5/

VRN_5

DCI

N.C. ()

I/O

IO_L27N_5/ IO_L27N_5/

VREF

IO_L40N_3/ IO_L40N_3/

VREF

VREF_5

VREF_3

IO_L40P_3

VCCO_3

IO

VREF_3

IO_L40P_3

VCCO_3

IO

5

IO_L27P_5

P64

P68

I/O

3

4

P130

P110

P127

P93

I/O

VCCO

I/O

IO_L28N_5/ IO_L28N_5/

DUAL

D6

5

IO_L28P_5/

D7

IO_L28P_5/

D7

P67

P74

P72

P77

DUAL

GCLK

N.C. ()

IO/VREF_4

N.C. ()

IO/VREF_4

IO

P97

I/O

IO_L31N_5/ IO_L31N_5/

IO/VREF_4

P85

VREF

DCI

D4

P96

IO_L31P_5/

D5

IO_L31P_5/

D5

P102

P101

IO_L32N_5/ IO_L32N_5/

GCLK3 GCLK3

IO_L01N_4/ IO_L01N_4/

VRP_4 VRP_4

32

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DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 20: PQ208 Package Pinout (Continued)

XC3S200

XC3S400

Pin Name

PQ208

Number

XC3S200

XC3S400

Pin Name

PQ208

Number

XC3S50

Pin Name

XC3S50

Pin Name

Bank

Type

Bank

Type

I/O

5

IO_L32P_5/

GCLK2

IO_L32P_5/

GCLK2

P76

GCLK

7

IO_L22P_7

IO_L23N_7

IO_L23P_7

IO_L24N_7

IO_L24P_7

N.C. ()

IO_L22P_7

IO_L23N_7

IO_L23P_7

IO_L24N_7

IO_L24P_7

IO_L39N_7

IO_L39P_7

P15

P19

P18

P21

P20

P24

P22

P27

I/O

5

6

VCCO_5

N.C. ()

VCCO_5

IO/VREF_6

P60

P73

P50

P52

VCCO

VREF

DCI

I/O

IO_L01N_6/ IO_L01N_6/

I/O

VRP_6

N.C. ()

I/O

6

IO_L01P_6/

VRN_6

IO_L01P_6/

VRN_6

P51

DCI

IO_L40N_7/ IO_L40N_7/

VREF

VREF_7

IO_L40P_7

VCCO_7

GND

VREF_7

IO_L40P_7

VCCO_7

GND

6

IO_L19N_6

IO_L19P_6

IO_L20N_6

IO_L20P_6

IO_L21N_6

IO_L21P_6

IO_L22N_6

IO_L22P_6

IO_L23N_6

IO_L23P_6

IO_L19N_6

IO_L19P_6

IO_L20N_6

IO_L20P_6

IO_L21N_6

IO_L21P_6

IO_L22N_6

IO_L22P_6

IO_L23N_6

IO_L23P_6

P48

P46

P45

P44

P43

P42

P40

P39

P37

P36

P35

I/O

7

P26

P6

I/O

VCCO

GND

VCCAUX

7

I/O

7

P23

I/O

N/A

P1

I/O

GND

P186

P195

P202

P163

P170

P179

P134

P145

P151

P157

P112

P118

P129

P82

I/O

GND

I/O

GND

I/O

GND

I/O

GND

I/O

GND

IO_L24N_6/ IO_L24N_6/

VREF_6

VREF

GND

VREF_6

GND

6

IO_L24P_6

N.C. ()

IO_L24P_6

IO_L39N_6

IO_L39P_6

IO_L40N_6

P34

P33

P31

P29

P28

I/O

GND

N.C. ()

I/O

GND

IO_L40N_6

I/O

GND

IO_L40P_6/

VREF_6

IO_L40P_6/

VREF_6

VREF

GND

6

7

VCCO_6

P32

P49

P3

VCCO

DCI

GND

P91

IO_L01N_7/ IO_L01N_7/

VRP_7

GND

P99

VRP_7

GND

P105

P53

7

IO_L01P_7/

VRN_7

IO_L01P_7/

VRN_7

P2

DCI

GND

P59

7

N.C. ()

IO_L16N_7

P5

P4

I/O

GND

P66

IO_L16P_7/

VREF_7

VREF

GND

P75

GND

P30

7

IO_L19N_7/ IO_L19N_7/

VREF_7

P9

VREF

VREF_7

GND

P41

7

IO_L19P_7

IO_L20N_7

IO_L20P_7

IO_L21N_7

IO_L21P_7

IO_L22N_7

IO_L19P_7

IO_L20N_7

IO_L20P_7

IO_L21N_7

IO_L21P_7

IO_L22N_7

P7

I/O

GND

P47

P11

P10

P13

P12

P16

GND

P8

GND

P14

GND

P25

VCCAUX

P193

P173

DS099-4 (v1.5) July 13, 2004

Product Specification

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33

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 20: PQ208 Package Pinout (Continued)

XC3S200

XC3S400

Pin Name

PQ208

Number

XC3S200

XC3S400

Pin Name

PQ208

Number

XC3S50

Pin Name

XC3S50

Pin Name

Bank

N/A

Type

Bank

Type

CONFIG

JTAG

VCCAUX

VCCINT

VCCAUX

VCCINT

CCLK

P142

P121

P89

VCCAUX

VCCINT

CONFIG

VCCAUX M1

M1

P54

P56

VCCAUX M2

M2

VCCAUX PROG_B

VCCAUX TCK

VCCAUX TDI

VCCAUX TDO

VCCAUX TMS

PROG_B

TCK

P207

P159

P208

P158

P160

P69

P38

TDI

JTAG

P17

TDO

TMS

JTAG

P192

P174

P88

JTAG

User I/Os by Bank

Table 21 indicates how the available user-I/O pins are dis-

tributed between the eight I/O banks for the XC3S50 in the

PQ208 package. Similarly, Table 22 shows how the avail-

able user-I/O pins are distributed between the eight I/O

banks for the XC3S200 and XC3S400 in the PQ208 pack-

age.

P70

VCCAUX CCLK

VCCAUX DONE

P104

P103

P206

P55

DONE

VCCAUX HSWAP_EN HSWAP_EN

VCCAUX M0 M0

Table 21: User I/Os Per Bank for XC3S50 in PQ208 Package

All Possible I/O Pins by Type

Maximum

Package Edge

I/O Bank

I/O

15

16

15

16

I/O

9

DUAL

DCI

2

VREF

GCLK

0

1

2

3

4

5

6

7

0

6

0

2

0

2

0

Top

9

2

13

12

3

2

Right

Bottom

Left

2

3

2

12

2

34

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DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 22: User I/Os Per Bank for XC3S200 and XC3S400 in PQ208 Package

All Possible I/O Pins by Type

Maximum

I/O

Package Edge

I/O Bank

I/O

9

DUAL

DCI

2

VREF

GCLK

0

1

2

3

4

5

6

7

16

15

19

20

17

15

19

20

0

6

0

3

2

3

2

3

2

0

2

0

Top

9

2

14

15

4

2

Right

Bottom

Left

2

3

2

14

15

2

DS099-4 (v1.5) July 13, 2004

Product Specification

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35

R

Spartan-3 FPGA Family: Pinout Descriptions

PQ208 Footprint

Left Half of Package

(top view)

XC3S50

(124 max. user I/O)

I/O: Unrestricted,

general-purpose user I/O

72

1

GND

IO_L01P_7/VRN_7

IO_L01N_7/VRP_7

() IO_L16P_7/VREF_7

() IO_L16N_7

VCCO_7

Bank 0

2

3

4

5

6

7

8

9

VREF: User I/O or input

voltage reference for bank

16

17

N.C.: Unconnected pins for

XC3S50 ()

IO_L19P_7

GND

IO_L19N_7/VREF_7

IO_L20P_7 10

IO_L20N_7 11

IO_L21P_7 12

IO_L21N_7 13

GND 14

XC3S200, XC3S400

(141 max user I/O)

I/O: Unrestricted,

83

general-purpose user I/O

IO_L22P_7 15

IO_L22N_7 16

VCCAUX 17

VREF: User I/O or input

voltage reference for bank

22

0

IO_L23P_7 18

IO_L23N_7 19

IO_L24P_7 20

IO_L24N_7 21

() IO_L39P_7 22

VCCO_7 23

N.C.: No unconnected pins

in this package

All devices

DUAL: Configuration pin,

then possible user I/O

() IO_L39N_7 24

GND 25

12

IO_L40P_7 26

IO_L40N_7/VREF_7 27

IO_L40P_6/VREF_6 28

IO_L40N_6 29

GND 30

GCLK: User I/O or global

clock buffer input

8

DCI: User I/O or reference

resistor input for bank

() IO_L39P_6 31

VCCO_6 32

16

7

() IO_L39N_6 33

IO_L24P_6 34

IO_L24N_6/VREF_6 35

IO_L23P_6 36

IO_L23N_6 37

VCCAUX 38

CONFIG: Dedicated

configuration pins

JTAG: Dedicated JTAG

port pins

4

IO_L22P_6 39

IO_L22N_6 40

GND 41

IO_L21P_6 42

IO_L21N_6 43

IO_L20P_6 44

IO_L20N_6 45

IO_L19P_6 46

GND 47

VCCINT: Internal core

voltage supply (+1.2V)

4

VCCO: Output voltage

supply for bank

12

8

IO_L19N_6 48

VCCO_6 49

VCCAUX: Auxiliary voltage

supply (+2.5V)

() IO/VREF_6 50

IO_L01P_6/VRN_6 51

IO_L01N_6/VRP_6 52

Bank 5

GND: Ground

28

DS099-4_09a_121103

Figure 10: PQ208 Package Footprint (top view). Note pin 1 indicator in top-left corner and logo orientation.

36

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DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Right Half of Package

(top view)

156 IO_L01N_2/VRP_2

155 IO_L01P_2/VRN_2

154 IO/VREF_2 ()

153 VCCO_2

Bank 1

152 IO_L19N_2

151 GND

150 IO_L19P_2

149 IO_L20N_2

148 IO_L20P_2

147 IO_L21N_2

146 IO_L21P_2

145 GND

144 IO_L22N_2

143 IO_L22P_2

142 VCCAUX

141 IO_L23N_2/VREF_2

140 IO_L23P_2

139 IO_L24N_2

138 IO_L24P_2

137 IO_L39N_2 ()

136 VCCO_2

135 IO_L39P_2 ()

134 GND

133 IO_L40N_2

132 IO_L40P_2/VREF_2

131 IO_L40N_3/VREF_3

130 IO_L40P_3

129 GND

128 IO_L39N_3 ()

127 VCCO_3

126 IO_L39P_3 ()

125 IO_L24N_3

124 IO_L24P_3

123 IO_L23N_3

122 IO_L23P_3/VREF_3

121 VCCAUX

120 IO_L22N_3

119 IO_L22P_3

118 GND

117 IO_L21N_3

116 IO_L21P_3

115 IO_L20N_3

114 IO_L20P_3

113 IO_L19N_3

112 GND

111 IO_L19P_3

110 VCCO_3

109 IO_L17N_3 ()

108 IO_L17P_3/VREF_3 ()

107 IO_L01N_3/VRP_3

106 IO_L01P_3/VRN_3

105 GND

Bank 4

DS099-4_9b_121103

DS099-4 (v1.5) July 13, 2004

Product Specification

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R

Spartan-3 FPGA Family: Pinout Descriptions

Table 23: FT256 Package Pinout (Continued)

FT256: 256-lead Fine-pitch Thin Ball

Grid Array

The 256-lead fine-pitch thin ball grid array package, FT256,

supports three different Spartan-3 devices, including the

XC3S200, the XC3S400, and the XC3S1000. The footprints

for all three devices are identical, as shown in Table 23 and

Figure 11.

XC3S200

XC3S400

XC3S1000

Pin Name

FT256

Number

Bank

1

2

Type

DCI

VREF

I/O

IO_L01P_1/VRN_1

IO_L10N_1/VREF_1

IO_L10P_1

B14

A13

B13

B12

C12

D11

E11

B11

C11

D10

E10

A10

B10

C9

All the package pins appear in Table 23 and are sorted by

bank number, then by pin name. Pairs of pins that form a dif-

ferential I/O pair appear together in the table. The table also

shows the pin number for each pin and the pin type, as

defined earlier.

IO_L27N_1

I/O

IO_L27P_1

I/O

IO_L28N_1

I/O

IO_L28P_1

I/O

Pinout Table

IO_L29N_1

I/O

Table 23: FT256 Package Pinout

IO_L29P_1

I/O

IO_L30N_1

I/O

XC3S200

XC3S400

XC3S1000

Pin Name

FT256

Number

IO_L30P_1

I/O

IO_L31N_1/VREF_1

IO_L31P_1

VREF

I/O

Bank

0

Type

I/O

IO

A5

A7

A3

D5

B4

A4

C5

B5

E6

D6

C6

B6

E7

D7

C7

B7

D8

C8

B8

A8

E8

F7

IO_L32N_1/GCLK5

IO_L32P_1/GCLK4

VCCO_1

GCLK

VCCO

I/O

0

I/O

D9

0

IO/VREF_0

IO_L01N_0/VRP_0

IO_L01P_0/VRN_0

IO_L25N_0

IO_L25P_0

IO_L27N_0

IO_L27P_0

IO_L28N_0

IO_L28P_0

IO_L29N_0

IO_L29P_0

IO_L30N_0

IO_L30P_0

IO_L31N_0

IO_L31P_0/VREF_0

IO_L32N_0/GCLK7

IO_L32P_0/GCLK6

VCCO_0

VREF

DCI

I/O

E9

0

VCCO_1

F9

0

VCCO_1

F10

G16

B16

C16

C15

D14

D15

D16

E13

E14

E15

E16

F12

F13

F14

F15

G12

G13

G14

G15

H13

H14

H15

0

IO

0

IO_L01N_2/VRP_2

IO_L01P_2/VRN_2

IO_L16N_2

DCI

I/O

0

I/O

0

I/O

0

I/O

IO_L16P_2

I/O

0

I/O

IO_L17N_2

I/O

0

I/O

IO_L17P_2/VREF_2

IO_L19N_2

VREF

I/O

0

I/O

0

I/O

IO_L19P_2

I/O

0

I/O

IO_L20N_2

I/O

0

I/O

IO_L20P_2

I/O

0

I/O

IO_L21N_2

I/O

0

VREF

GCLK

VCCO

I/O

IO_L21P_2

I/O

0

IO_L22N_2

I/O

0

IO_L22P_2

I/O

0

IO_L23N_2/VREF_2

IO_L23P_2

VREF

I/O

0

VCCO_0

0

VCCO_0

F8

IO_L24N_2

I/O

1

IO

A9

A12

C10

D12

A14

IO_L24P_2

I/O

1

IO

I/O

IO_L39N_2

I/O

1

IO

I/O

IO_L39P_2

I/O

1

IO/VREF_1

IO_L01N_1/VRP_1

VREF

DCI

IO_L40N_2

I/O

1

38

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DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 23: FT256 Package Pinout (Continued)

XC3S200

XC3S400

XC3S1000

Pin Name

FT256

Number

XC3S400

XC3S1000

Pin Name

FT256

Number

Bank

2

3

4

Type

VREF

VCCO

I/O

Bank

4

5

6

Type

DUAL

I/O

IO_L40P_2/VREF_2

VCCO_2

H16

G11

H11

H12

K15

P16

R16

P15

P14

N16

N15

M14

N14

M16

M15

L13

M13

L15

L14

K12

L12

K14

K13

J14

IO_L27P_4/D1

N11

P11

R11

M10

N10

P10

R10

N9

P9

IO_L28N_4

VCCO_2

IO_L28P_4

I/O

VCCO_2

IO_L29N_4

I/O

IO

IO_L29P_4

I/O

IO_L01N_3/VRP_3

IO_L01P_3/VRN_3

IO_L16N_3

IO_L16P_3

IO_L17N_3

IO_L17P_3/VREF_3

IO_L19N_3

IO_L19P_3

IO_L20N_3

IO_L20P_3

IO_L21N_3

IO_L21P_3

IO_L22N_3

IO_L22P_3

IO_L23N_3

IO_L23P_3/VREF_3

IO_L24N_3

IO_L24P_3

IO_L39N_3

IO_L39P_3

IO_L40N_3/VREF_3

IO_L40P_3

VCCO_3

DCI

I/O

IO_L30N_4/D2

IO_L30P_4/D3

IO_L31N_4/INIT_B

IO_L31P_4/DOUT/BUSY

IO_L32N_4/GCLK1

IO_L32P_4/GCLK0

VCCO_4

DUAL

GCLK

VCCO

I/O

R9

T9

VREF

I/O

L9

I/O

VCCO_4

L10

M9

N5

P7

I/O

VCCO_4

I/O

IO

I/O

IO

I/O

IO

T5

I/O

IO/VREF_5

T8

VREF

DUAL

DCI

I/O

IO_L01N_5/RDWR_B

IO_L01P_5/CS_B

IO_L10N_5/VRP_5

IO_L10P_5/VRN_5

IO_L27N_5/VREF_5

IO_L27P_5

T3

I/O

R3

T4

VREF

I/O

R4

R5

P5

DCI

I/O

VREF

I/O

J13

I/O

IO_L28N_5/D6

IO_L28P_5/D7

IO_L29N_5

N6

M6

R6

P6

DUAL

I/O

J16

VREF

I/O

K16

J11

VCCO

I/O

IO_L29P_5/VREF_5

IO_L30N_5

VREF

I/O

VCCO_3

J12

N7

M7

T7

VCCO_3

K11

T12

T14

N12

P13

T10

R13

T13

P12

R12

M11

IO_L30P_5

I/O

IO

IO_L31N_5/D4

IO_L31P_5/D5

IO_L32N_5/GCLK3

IO_L32P_5/GCLK2

VCCO_5

DUAL

GCLK

VCCO

I/O

IO

I/O

R7

P8

IO/VREF_4

IO_L01N_4/VRP_4

IO_L01P_4/VRN_4

IO_L25N_4

IO_L25P_4

IO_L27N_4/DIN/D0

VREF

DCI

I/O

N8

L7

VCCO_5

L8

VCCO_5

M8

K1

IO

I/O

IO_L01N_6/VRP_6

IO_L01P_6/VRN_6

R1

P1

DCI

DUAL

DCI

DS099-4 (v1.5) July 13, 2004

Product Specification

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1-800-255-7778

39

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 23: FT256 Package Pinout (Continued)

XC3S200

XC3S400

XC3S1000

Pin Name

FT256

Number

XC3S400

XC3S1000

Pin Name

FT256

Number

Bank

6

7

Type

I/O

Bank

7

Type

I/O

IO_L16N_6

P2

N3

N2

N1

M4

M3

M2

M1

L5

L4

L3

L2

K5

K4

K3

K2

J4

IO_L24N_7

G3

G4

H3

H4

H1

G1

G6

H5

H6

A1

IO_L16P_6

I/O

7

IO_L24P_7

IO_L39N_7

IO_L39P_7

IO_L40N_7/VREF_7

IO_L40P_7

VCCO_7

GND

I/O

IO_L17N_6

IO_L17P_6/VREF_6

IO_L19N_6

IO_L19P_6

I/O

7

I/O

VREF

I/O

7

I/O

7

VREF

I/O

7

IO_L20N_6

IO_L20P_6

I/O

7

VCCO

GND

I/O

7

IO_L21N_6

IO_L21P_6

I/O

7

I/O

N/A

IO_L22N_6

IO_L22P_6

I/O

GND

A16

B2

I/O

GND

IO_L23N_6

IO_L23P_6

I/O

GND

B9

I/O

GND

B15

F6

IO_L24N_6/VREF_6

IO_L24P_6

VREF

I/O

GND

F11

G7

G8

G9

G10

H2

H7

H8

H9

H10

J7

IO_L39N_6

IO_L39P_6

I/O

GND

J3

I/O

GND

IO_L40N_6

IO_L40P_6/VREF_6

VCCO_6

J2

I/O

GND

J1

VREF

VCCO

I/O

GND

J5

GND

VCCO_6

J6

GND

VCCO_6

K6

G2

C1

B1

C2

C3

D1

D2

E3

D3

E1

E2

F4

E4

F2

F3

G5

F5

GND

IO

GND

IO_L01N_7/VRP_7

IO_L01P_7/VRN_7

IO_L16N_7

IO_L16P_7/VREF_7

IO_L17N_7

IO_L17P_7

DCI

I/O

GND

J8

VREF

I/O

GND

J9

GND

J10

J15

K7

I/O

GND

IO_L19N_7/VREF_7

IO_L19P_7

VREF

I/O

GND

K8

IO_L20N_7

IO_L20P_7

I/O

GND

K9

I/O

GND

K10

L6

IO_L21N_7

IO_L21P_7

I/O

GND

I/O

GND

L11

R2

R8

R15

T1

IO_L22N_7

IO_L22P_7

I/O

GND

I/O

GND

IO_L23N_7

IO_L23P_7

I/O

GND

I/O

GND

40

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 23: FT256 Package Pinout (Continued)

XC3S200

XC3S400

XC3S1000

Pin Name

FT256

Number

XC3S400

XC3S1000

Pin Name

FT256

Number

Bank

N/A

Type

Bank

Type

VCCINT

CONFIG

JTAG

GND

T16

A6

GND

N/A

VCCINT

N13

T15

R14

C4

VCCAUX

VCCINT

VCCAUX

VCCINT

VCCAUX CCLK

VCCAUX DONE

A11

F1

VCCAUX HSWAP_EN

VCCAUX M0

F16

L1

P3

VCCAUX M1

T2

L16

T6

VCCAUX M2

P4

VCCAUX PROG_B

VCCAUX TCK

VCCAUX TDI

B3

T11

D4

C14

A2

JTAG

D13

E5

VCCAUX TDO

VCCAUX TMS

A15

C13

JTAG

E12

M5

M12

N4

User I/Os by Bank

Table 24 indicates how the available user-I/O pins are dis-

tributed between the eight I/O banks on the FT256 package.

Table 24: User I/Os Per Bank in FT256 Package

All Possible I/O Pins by Type

Maximum

Package Edge

I/O Bank

I/O

20

23

21

20

23

I/O

13

18

8

DUAL

DCI

2

VREF

GCLK

0

1

2

3

4

5

6

7

0

6

0

3

2

0

2

0

Top

2

Right

Bottom

Left

2

7

2

18

2

DS099-4 (v1.5) July 13, 2004

Product Specification

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1-800-255-7778

41

R

Spartan-3 FPGA Family: Pinout Descriptions

FT256 Footprint

Bank 0

Bank 1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

I/O

L01P_0

VRN_0

I/O

L32P_0

GCLK6

I/O

L31N_1

VREF_1

I/O

IO

VREF_0

VCCAUX

TDI

I/O

TDO

GND

A

B

C

D

E

F

GND

L10N_1 L01N_1

VREF_1 VRP_1

I/O

L01P_7

VRN_7

I/O

L01N_0

VRP_0

I/O

L32N_0

GCLK7

I/O

L01N_2

VRP_22

I/O

PROG_B

GND

I/O

GND

L01P_1

L25P_0 L28P_0 L30P_0

L31P_1 L29N_1 L27N_1 L10P_1

VRN_1

I/O

L01N_7

VRP_7

I/O

L16P_7

VREF_7

I/O

L01P_2

VRN_22

I/O

L16N_7

I/O

L16N_2

HSWAP_

EN

I/O

TMS

TCK

L31P_0 L32N_1

VREF_0 GCLK5

L25N_0 L28N_0 L30N_0

L29P_1 L27P_1

I/O

L27P_0 L29P_0 L31N_0

I/O

L17P_2

VREF_2

IO

VREF_0

IO

VREF_1

I/O

VCCINT

I/O

L32P_1

GCLK4

L17N_7 L17P_7 L19P_7

L30N_1 L28N_1

L16P_2 L17N_2

I/O

L19N_7

VREF_7

I/O

L21P_7

I/O

I/O I/O

I/O

VCCO_0 VCCO_1

VCCINT

I/O

VCCINT

I/O

L20N_7 L20P_7

L27N_0 L29N_0

L30P_1 L28P_1

L19N_2 L19P_2 L20N_2 L20P_2

I/O

VCCAUX

VCCO_0 VCCO_0 VCCO_1 VCCO_1

VCCAUX

I/O

GND

VCCO_7

L22N_7 L22P_7 L21N_7 L23P_7

L21N_2 L21P_2 L22N_2 L22P_2

I/O

L23N_2

VREF_2

I/O

L40P_7

I/O

VCCO_2

I/O

G

H

J

GND

L24N_7 L24P_7 L23N_7

L23P_2 L24N_2 L24P_2

I/O

L40N_7

VREF_7

I/O

L40P_2

VREF_2

I/O

VCCO_7 VCCO_7

VCCO_2 VCCO_2

GND

I/O

L39N_7 L39P_7

L39N_2 L39P_2 L40N_2

I/O

L40P_6

VREF_6

I/O

L40N_3

VREF_3

I/O

VCCO_6 VCCO_6

I/O

VCCO_3 VCCO_3

I/O

GND

L40N_6 L39P_6 L39N_6

L39P_3 L39N_3

I/O

L24N_6

VREF_6

I/O

L24P_6

I/O

L40P_3

VCCO_6 GND

GND VCCO_3

I/O

K

L

L23P_6 L23N_6

L23N_3 L24P_3 L24N_3

I/O

L23P_3

VREF_3

I/O

VCCAUX

I/O

VCCO_5 VCCO_5 VCCO_4 VCCO_4

VCCAUX

GND

L22P_6 L22N_6 L21P_6 L21N_6

L21N_3 L22P_3 L22N_3

I/O

L27N_4

DIN

I/O

L28P_5

D7

I/O

L30P_5

I/O

L29N_4

I/O I/O I/O

I/O

VCCO_5 VCCO_4

VCCINT

I/O

VCCINT

M

N

P

R

T

L20P_6 L20N_6 L19P_6 L19N_6

L21P_3 L19N_3 L20P_3 L20N_3

I/O

D0

I/O

L17P_6

VREF_6

I/O

L28N_5

D6

I/O

L27P_4

D1

IO

VREF_4

I/O

L30N_5

I/O

L29P_4

I/O

L19P_3

I/O

L17N_3

VCCINT

L32P_5 L31N_4

GCLK2 INIT_B

L17P_3

VREF_3

L17N_6 L16P_6

I/O

L01P_6

VRN_6

I/O

L29P_5

VREF_5

I/O

L30N_4

D2

I/O

L01N_3

VRP_33

IO

VREF_4

I/O

M0

I/O

L27P_5

I/O

L31P_4

L32N_5

DOUT

M2

I/O

L16N_6

L28N_4 L25N_4

L16P_3 L16N_3

GCLK3

BUSY

I/O

L01N_6

VRP_6

I/O

L31P_5

D5

I/O

L01N_4

VRP_4

I/O

L01P_3

VRN_33

I/O

L29N_5

I/O

GND

DONE

I/O

GND

L01P_5 L10P_5 L27N_5

CS_B VRN_5 VREF_5

L32N_4 L30P_4

L28P_4 L25P_4

GCLK1

D3

I/O

L31N_5

D4

I/O

L32P_4

GCLK0

I/O

L01P_4

VRN_4

IO

VREF_5

IO

VREF_4

VCCAUX

M1

I/O

CCLK

GND

L01N_5 L10N_5

RDWR_B VRP_5

GND

Bank 5

Bank 4

DS099-4_10_030503

Figure 11: FT256 Package Footprint (top view)

I/O: Unrestricted, general-purpose user I/O

DUAL: Configuration pin, then possible

user I/O

VREF: User I/O or input voltage reference for

bank

12

8

24

8

113

16

7

DCI: User I/O or reference resistor input for

bank

GCLK: User I/O or global clock buffer input

JTAG: Dedicated JTAG port pins

GND: Ground

VCCO: Output voltage supply for bank

CONFIG: Dedicated configuration pins

VCCINT: Internal core voltage supply

(+1.2V)

4

N.C.: No unconnected pins in this package

VCCAUX: Auxiliary voltage supply

(+2.5V)

0

32

8

42

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 25: FG320 Package Pinout (Continued)

FG320: 320-lead Fine-pitch Ball Grid

Array

The 320-lead fine-pitch ball grid array package, FG320,

supports three different Spartan-3 devices, including the

XC3S400, the XC3S1000, and the XC3S1500. The footprint

for all three devices is identical, as shown in Table 25 and

Figure 12.

XC3S400

XC3S1000

XC3S1500

Pin Name

FG320

Number

Bank

Type

0

1

2

VCCO_0

C6

VCCO

I/O

VCCO_0

G8

The FG320 package is an 18 x 18 array of solder balls

minus the four center balls.

VCCO_0

G9

IO

A11

B13

D10

A12

A16

A17

A15

B15

C14

C15

A14

B14

D14

D13

E13

E12

C12

D12

F11

E11

C11

D11

A10

B10

E10

F10

B11

C13

G10

G11

J13

All the package pins appear in Table 25 and are sorted by

bank number, then by pin name. Pairs of pins that form a dif-

ferential I/O pair appear together in the table. The table also

shows the pin number for each pin and the pin type, as

defined earlier.

IO

I/O

IO

I/O

IO/VREF_1

IO_L01N_1/VRP_1

IO_L01P_1/VRN_1

IO_L10N_1/VREF_1

IO_L10P_1

IO_L15N_1

IO_L15P_1

IO_L16N_1

IO_L16P_1

IO_L24N_1

IO_L24P_1

IO_L27N_1

IO_L27P_1

IO_L28N_1

IO_L28P_1

IO_L29N_1

IO_L29P_1

IO_L30N_1

IO_L30P_1

IO_L31N_1/VREF_1

IO_L31P_1

IO_L32N_1/GCLK5

IO_L32P_1/GCLK4

VCCO_1

VREF

DCI

VREF

I/O

Pinout Table

Table 25: FG320 Package Pinout

I/O

XC3S400

I/O

XC3S1000

XC3S1500

Pin Name

FG320

Number

I/O

Bank

Type

I/O

0

IO

D9

E7

B3

D6

A2

A3

B4

C4

C5

D5

A4

A5

B5

B6

C7

D7

C8

D8

E8

F8

A7

A8

B9

A9

E9

F9

B8

I/O

IO/VREF_0

VREF

DCI

I/O

IO/VREF_0

I/O

IO_L01N_0/VRP_0

IO_L01P_0/VRN_0

IO_L09N_0

I/O

IO_L09P_0

I/O

IO_L10N_0

I/O

IO_L10P_0

I/O

IO_L15N_0

I/O

VREF

I/O

IO_L15P_0

I/O

IO_L25N_0

I/O

GCLK

VCCO

I/O

IO_L25P_0

I/O

IO_L27N_0

I/O

IO_L27P_0

I/O

VCCO_1

IO_L28N_0

I/O

VCCO_1

IO_L28P_0

I/O

VCCO_1

IO_L29N_0

I/O

IO

IO_L29P_0

I/O

IO_L01N_2/VRP_2

IO_L01P_2/VRN_2

IO_L16N_2

IO_L16P_2

IO_L17N_2

IO_L17P_2/VREF_2

IO_L19N_2

IO_L19P_2

C16

C17

B18

C18

D17

D18

D16

E16

DCI

I/O

IO_L30N_0

I/O

IO_L30P_0

I/O

IO_L31N_0

I/O

IO_L31P_0/VREF_0

IO_L32N_0/GCLK7

IO_L32P_0/GCLK6

VCCO_0

VREF

GCLK

VCCO

I/O

VREF

I/O

DS099-4 (v1.5) July 13, 2004

Product Specification

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1-800-255-7778

43

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 25: FG320 Package Pinout (Continued)

XC3S400

XC3S1000

XC3S1500

Pin Name

FG320

Number

XC3S1000

XC3S1500

Pin Name

FG320

Number

Bank

Type

Bank

Type

2

3

IO_L20N_2

E17

E18

F15

E15

F14

G14

G18

F17

G15

G16

H13

H14

H16

H15

H17

H18

J18

I/O

3

4

IO_L27N_3

L14

L13

L15

L16

L18

L17

K13

K14

K17

K18

K12

L12

N16

P12

V14

R10

U13

V17

U16

V16

P14

R14

U15

V15

T14

U14

R13

P13

T12

R12

V12

V11

R11

T11

N11

P11

U10

V10

I/O

IO_L20P_2

IO_L27P_3

IO_L21N_2

IO_L21P_2

I/O

IO_L34N_3

I/O

IO_L34P_3/VREF_3

IO_L35N_3

VREF

I/O

IO_L22N_2

IO_L22P_2

I/O

IO_L35P_3

I/O

IO_L23N_2/VREF_2

IO_L23P_2

VREF

I/O

IO_L39N_3

I/O

IO_L39P_3

I/O

IO_L24N_2

IO_L24P_2

I/O

IO_L40N_3/VREF_3

IO_L40P_3

VREF

I/O

IO_L27N_2

IO_L27P_2

I/O

VCCO_3

VCCO

I/O

VCCO_3

IO_L34N_2/VREF_2

IO_L34P_2

VREF

I/O

VCCO_3

IO

IO_L35N_2

IO_L35P_2

I/O

IO

I/O

IO/VREF_4

VREF

DCI

IO_L39N_2

IO_L39P_2

I/O

IO/VREF_4

J17

I/O

IO/VREF_4

IO_L40N_2

IO_L40P_2/VREF_2

VCCO_2

J15

I/O

IO_L01N_4/VRP_4

IO_L01P_4/VRN_4

IO_L06N_4/VREF_4

IO_L06P_4

J14

VREF

VCCO

I/O

DCI

F16

H12

J12

VREF

I/O

VCCO_2

IO_L09N_4

I/O

IO

K15

T17

T16

T18

U18

P16

R16

R17

R18

P18

P17

P15

N15

M14

N14

M15

M16

M18

N17

IO_L09P_4

I/O

IO_L01N_3/VRP_3

IO_L01P_3/VRN_3

IO_L16N_3

IO_L16P_3

DCI

I/O

IO_L10N_4

I/O

IO_L10P_4

I/O

IO_L25N_4

I/O

IO_L25P_4

I/O

IO_L17N_3

IO_L17P_3/VREF_3

IO_L19N_3

IO_L19P_3

I/O

IO_L27N_4/DIN/D0

IO_L27P_4/D1

IO_L28N_4

DUAL

I/O

VREF

I/O

IO_L28P_4

I/O

IO_L20N_3

IO_L20P_3

I/O

IO_L29N_4

I/O

IO_L29P_4

I/O

IO_L21N_3

IO_L21P_3

I/O

IO_L30N_4/D2

IO_L30P_4/D3

IO_L31N_4/INIT_B

DUAL

I/O

IO_L22N_3

IO_L22P_3

I/O

IO_L31P_4/

DOUT/BUSY

IO_L23N_3

IO_L23P_3/VREF_3

IO_L24N_3

IO_L24P_3

I/O

4

IO_L32N_4/GCLK1

IO_L32P_4/GCLK0

VCCO_4

N10

P10

M10

GCLK

VCCO

VREF

I/O

44

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DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 25: FG320 Package Pinout (Continued)

XC3S400

XC3S1000

XC3S1500

Pin Name

FG320

Number

XC3S1000

XC3S1500

Pin Name

FG320

Number

Bank

Type

Bank

Type

4

5

6

VCCO_4

M11

T13

U11

N8

P8

U6

R9

V3

V2

T5

VCCO

I/O

6

7

IO_L20N_6

P2

P1

N4

P4

N5

M5

M3

M4

N2

M1

L6

I/O

VCCO_4

IO_L20P_6

VCCO_4

IO_L21N_6

IO_L21P_6

I/O

IO

I/O

IO

I/O

IO_L22N_6

IO_L22P_6

I/O

IO

I/O

IO/VREF_5

VREF

DUAL

I/O

IO_L23N_6

IO_L23P_6

I/O

IO_L01N_5/RDWR_B

IO_L01P_5/CS_B

IO_L06N_5

I/O

IO_L24N_6/VREF_6

IO_L24P_6

VREF

I/O

IO_L06P_5

T4

I/O

IO_L27N_6

IO_L27P_6

I/O

IO_L10N_5/VRP_5

IO_L10P_5/VRN_5

IO_L15N_5

V4

U4

R6

R5

V5

U5

P6

P7

R7

T7

DCI

L5

I/O

DCI

IO_L34N_6/VREF_6

IO_L34P_6

L3

VREF

I/O

L4

IO_L15P_5

I/O

IO_L35N_6

IO_L35P_6

L2

I/O

IO_L16N_5

I/O

L1

I/O

IO_L16P_5

I/O

IO_L39N_6

IO_L39P_6

K5

K4

K1

K2

K7

L7

I/O

IO_L27N_5/VREF_5

IO_L27P_5

VREF

I/O

IO_L40N_6

IO_L40P_6/VREF_6

VCCO_6

I/O

IO_L28N_5/D6

IO_L28P_5/D7

IO_L29N_5

DUAL

I/O

VREF

VCCO

I/O

V8

V7

R8

T8

VCCO_6

IO_L29P_5/VREF_5

IO_L30N_5

VREF

I/O

VCCO_6

N3

J6

IO

IO_L30P_5

I/O

IO_L01N_7/VRP_7

IO_L01P_7/VRN_7

IO_L16N_7

IO_L16P_7/VREF_7

IO_L17N_7

IO_L17P_7

C3

C2

C1

B1

D1

D2

E3

D3

E2

E1

E4

F4

G5

F5

G1

F2

G4

G3

DCI

I/O

IO_L31N_5/D4

IO_L31P_5/D5

IO_L32N_5/GCLK3

IO_L32P_5/GCLK2

VCCO_5

U9

V9

N9

P9

M8

M9

T6

DUAL

GCLK

VCCO

I/O

VREF

I/O

VCCO_5

IO_L19N_7/VREF_7

IO_L19P_7

VREF

I/O

VCCO_5

U8

K6

T3

IO_L20N_7

IO_L20P_7

I/O

IO

I/O

IO_L01N_6/VRP_6

IO_L01P_6/VRN_6

IO_L16N_6

DCI

IO_L21N_7

IO_L21P_7

I/O

T2

DCI

I/O

U1

T1

I/O

IO_L22N_7

IO_L22P_7

I/O

IO_L16P_6

I/O

IO_L17N_6

R2

R1

R3

P3

I/O

IO_L23N_7

IO_L23P_7

I/O

IO_L17P_6/VREF_6

IO_L19N_6

VREF

I/O

IO_L24N_7

IO_L24P_7

I/O

IO_L19P_6

I/O

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

45

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 25: FG320 Package Pinout (Continued)

XC3S400

XC3S1000

XC3S1500

Pin Name

FG320

Number

XC3S1000

XC3S1500

Pin Name

FG320

Number

Bank

Type

Bank

Type

7

IO_L27N_7

H5

H6

I/O

VREF

I/O

N/A

GND

M7

N1

GND

7

IO_L27P_7/VREF_7

IO_L34N_7

IO_L34P_7

IO_L35N_7

IO_L35P_7

IO_L39N_7

IO_L39P_7

IO_L40N_7/VREF_7

IO_L40P_7

VCCO_7

GND

7

H4

N18

T10

T9

GND

7

H3

I/O

GND

7

H1

I/O

GND

7

H2

I/O

U17

U2

GND

7

J1

I/O

GND

7

J2

I/O

V1

GND

7

J5

VREF

I/O

V13

V18

V6

GND

7

J4

GND

7

F3

VCCO

GND

7

H7

VCCAUX

VCCINT

B12

B7

VCCAUX

VCCINT

CONFIG

JTAG

7

J7

N/A

A1

G17

G2

GND

A13

A18

A6

GND

M17

M2

GND

B17

B2

U12

U7

GND

C10

C9

F12

F13

F6

GND

F1

GND

F18

G12

G7

H10

H11

H8

F7

GND

G13

G6

GND

M13

M6

GND

N12

N13

N6

GND

H9

GND

J11

J16

J3

GND

N7

GND

VCCAUX CCLK

VCCAUX DONE

VCCAUX HSWAP_EN

VCCAUX M0

T15

R15

E6

GND

J8

GND

K11

K16

K3

GND

P5

GND

VCCAUX M1

U3

GND

K8

VCCAUX M2

R4

GND

L10

L11

L8

VCCAUX PROG_B

VCCAUX TCK

VCCAUX TDI

E5

GND

E14

D4

GND

JTAG

GND

L9

VCCAUX TDO

VCCAUX TMS

D15

B16

JTAG

GND

M12

JTAG

46

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

User I/Os by Bank

Table 26 indicates how the available user-I/O pins are dis-

tributed between the eight I/O banks on the FG320 pack-

age.

Table 26: User I/Os Per Bank in FG320 Package

Maximum

All Possible I/O Pins by Type

Maximum

I/O

LVDS

Pairs

Package Edge I/O Bank

I/O

19

23

13

23

DUAL

DCI

2

VREF

GCLK

0

26

29

27

26

29

11

14

11

14

0

6

0

3

4

3

4

2

0

2

0

Top

1

2

Right

3

2

4

2

Bottom

5

2

6

2

Left

7

2

DS099-4 (v1.5) July 13, 2004

Product Specification

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1-800-255-7778

47

R

Spartan-3 FPGA Family: Pinout Descriptions

FG320 Footprint

Bank 0

Bank 1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

I/O

GND

L01N_0

L01P_0

GND

L31P_0

L31N_1

L10N_1

L01N_1

L01P_1

A

B

C

D

E

F

VREF_1

L15N_0

L15P_0

L30N_0

L30P_0

L16N_1

VRP_0

VRN_0

VREF_0 VREF_1

VRP_1

VRN_1

VREF_1

I/O

L16P_7

VREF_7

I/O

L16P_1

I/O

L10P_1

I/O

L16N_2

I/O

VREF_0

I/O

L31N_0

I/O

L31P_1

I/O

L25P_0

I/O

L09N_0

I/O

L25N_0

VCCAUX

GND

VCCO_0

VCCO_1

VCCAUX

I/O

TMS

I/O

L01P_7

VRN_7

I/O

L01N_7

VRP_7

I/O

L01N_2

VRP_2

I/O

L01P_2

VRN_2

I/O

L30N_1

I/O

L28N_1

I/O

L15N_1

I/O

L15P_1

I/O

L16P_2

I/O

L16N_7

I/O

L09P_0

I/O

L10N_0

I/O

L27N_0

I/O

L28N_0

VCCO_0

VCCO_1

GND

I/O

L17P_2

VREF_2

I/O

L17N_7

I/O

L17P_7

I/O

L19P_7

I/O

L10P_0

I/O

VREF_0

I/O

L27P_0

I/O

L28P_0

I/O

L30P_1

I/O

L28P_1

I/O

L24P_1

I/O

L24N_1

I/O

L19N_2

I/O

L17N_2

TDI

I/O

TDO

I/O

L19N_7

VREF_7

I/O

L32N_0

GCLK7

I/O

L32N_1

GCLK5

I/O

L29N_0

I/O

L29P_1

I/O

L27P_1

I/O

L27N_1

I/O

L21P_2

I/O

L19P_2

I/O

L20N_2

I/O

L20P_2

I/O

L20P_7

I/O

L20N_7

I/O

L21N_7

HSWAP_

EN

PROG_B

I/O

TCK

I/O

L32P_0

GCLK6

I/O

L32P_1

GCLK4

I/O

L23P_7

I/O

L21P_7

I/O

L22P_7

I/O

L29P_0

I/O

L29N_1

I/O

L22N_2

I/O

L21N_2

I/O

L23P_2

VCCO_2

VCCO_7

VCCINT VCCINT

GND

I/O

VCCAUX

VCCO_1 VCCO_1

VCCINT

GND

VCCINT

GND

VCCO_0 VCCO_0

L23N_2

G

H

J

VCCAUX

L23N_7

L24P_7

L24N_7

L22N_7

L22P_2

L24N_2

L24P_2

VREF_2

I/O

L27P_7

I/O

L34N_2

VREF_2

I/O

L35N_7

I/O

L35P_7

I/O

L34P_7

I/O

L34N_7

I/O

L27N_7

I/O

L27N_2

I/O

L27P_2

I/O

L34P_2

I/O

L35N_2

I/O

L35P_2

VCCO_2

VCCO_3

GND

VCCO_7

VCCO_6

VREF_7

I/O

L40N_7

VREF_7

I/O

L40P_2

VREF_2

I/O

L39N_7

I/O

L39P_7

I/O

L40P_7

I/O

L40N_2

I/O

L39P_2

I/O

L39N_2

GND

I/O

L40P_6

VREF_6

I/O

L40N_3

VREF_3

I/O

L40N_6

I/O

L39P_6

I/O

L39N_6

I/O

L39N_3

I/O

L39P_3

I/O

L40P_3

I/O

K

L

I/O

L34N_6

VREF_6

I/O

L34P_3

VREF_3

I/O

L35P_6

I/O

L35N_6

I/O

L34P_6

I/O

L27P_6

I/O

L27N_6

I/O

L27P_3

I/O

L27N_3

I/O

L34N_3

I/O

L35P_3

I/O

L35N_3

GND

I/O

VCCO_5 VCCO_5 VCCO_4 VCCO_4

VCCINT

VCCAUX

GND

L23P_3

M

N

P

R

T

VCCINT

L24P_6

L23N_6

L23P_6

L22P_6

L22N_3

L23N_3

L24N_3

VREF_3

I/O

L24N_6

VREF_6

I/O

L21N_6

I/O

L22N_6

I/O

L22P_3

I/O

L21P_3

I/O

L24P_3

I/O

GND

VCCINT VCCINT

L32N_5

L32N_4

L30N_4 VCCINT VCCINT

VCCO_3

VCCO_6

D2

GCLK3

GCLK1

I/O

L32P_5

GCLK2

I/O

L32P_4

GCLK0

I/O

L30P_4

D3

I/O

L06N_4

VREF_4

I/O

L20P_6

I/O

L20N_6

I/O

L19P_6

I/O

L21P_6

I/O

L25P_4

I/O

L21N_3

I/O

L17N_3

I/O

L20P_3

I/O

L20N_3

M0

I/O

L27N_5

L27P_5

VREF_5

I/O

L17P_6

VREF_6

I/O

L27P_4

D1

I/O

L17P_3

VREF_3

I/O

L17N_6

I/O

L19N_6

I/O

L15P_5

I/O

L30N_5

I/O

L29N_4

I/O

L25N_4

I/O

L06P_4

I/O

L19N_3

I/O

L19P_3

M2

DONE

CCLK

L28N_5

L15N_5

D6

VREF_5 VREF_4

I/O

L27N_4

DIN

I/O

L01P_6

VRN_6

I/O

L01N_6

VRP_6

I/O

L28P_5

D7

I/O

L01P_3

VRN_3

I/O

L01N_3

VRP_3

I/O

L16P_6

I/O

L06P_5

I/O

L06N_5

I/O

L30P_5

I/O

L29P_4

I/O

L10N_4

I/O

L16N_3

VCCO_5

I/O

GND

VCCO_4

D0

I/O

L10P_5

VRN_5

I/O

L31N_5

D4

I/O

L01N_4

VRP_4

I/O

L16N_6

I/O

L16P_5

I/O

VREF_4

I/O

L10P_4

I/O

L09N_4

I/O

L16P_3

VCCAUX

VCCO_5

VCCO_4

GND

M1

GND

L31N_4

U

V

INIT_B

I/O

L01P_5

CS_B

I/O

L01N_5

RDWR_B VRP_5

I/O

L10N_5

I/O

L29P_5

VREF_5

I/O

L31P_5

D5

I/O

L01P_4

VRN_4

I/O

L16N_5

I/O

L29N_5

I/O

L28P_4

I/O

L28N_4

I/O

L09P_4

I/O

VREF_4

L31P_4

DOUT

GND

I/O

GND

BUSY

Bank 5

Bank 4

ds099-3_16_121103

Figure 12: FG320 Package Footprint (top view)

I/O: Unrestricted, general-purpose user I/O

DUAL: Configuration pin, then possible

user I/O

VREF: User I/O or input voltage reference for

bank

12

8

29

28

12

8

156

DCI: User I/O or reference resistor input for

bank

GCLK: User I/O or global clock buffer input

JTAG: Dedicated JTAG port pins

GND: Ground

VCCO: Output voltage supply for bank

16

7

CONFIG: Dedicated configuration pins

VCCINT: Internal core voltage supply

(+1.2V)

4

N.C.: No unconnected pins in this package

VCCAUX: Auxiliary voltage supply

(+2.5V)

0

40

48

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 27: FG456 Package Pinout (Continued)

FG456: 456-lead Fine-pitch Ball Grid

Array

3S1000

3S1500

FG456

3S400

The 456-lead fine-pitch ball grid array package, FG456,

supports three different Spartan-3 devices, including the

XC3S400, the XC3S1000, and the XC3S1500. The foot-

prints for the XC3S1000 and XC3S1500 are identical, as

shown in Table 27 and Figure 13. The XC3S400, however,

has fewer I/O pins which consequently results in 69 uncon-

nected pins on the FG456 package, labeled as “N.C.” In

Table 27 and Figure 13, these unconnected pins are indi-

cated with a black diamond symbol ().

Bank

0

Pin Name

Number

Type

I/O

VREF

IO_L10N_0

IO_L10P_0

IO_L15N_0

IO_L15P_0

IO_L16N_0

IO_L16P_0

N.C. ()

IO_L10N_0

IO_L10P_0

IO_L15N_0

IO_L15P_0

IO_L16N_0

IO_L16P_0

IO_L19N_0

IO_L19P_0

IO_L22N_0

IO_L22P_0

IO_L24N_0

IO_L24P_0

IO_L25N_0

IO_L25P_0

IO_L27N_0

IO_L27P_0

IO_L28N_0

IO_L28P_0

IO_L29N_0

IO_L29P_0

IO_L30N_0

IO_L30P_0

IO_L31N_0

E6

D6

0

C6

0

B6

0

E7

0

D7

0

B7

All the package pins appear in Table 27 and are sorted by

bank number, then by pin name. Pairs of pins that form a dif-

ferential I/O pair appear together in the table. The table also

shows the pin number for each pin and the pin type, as

defined earlier.

0

N.C. ()

A7

0

N.C. ()

E8

0

N.C. ()

D8

0

IO_L24N_0

IO_L24P_0

IO_L25N_0

IO_L25P_0

IO_L27N_0

IO_L27P_0

IO_L28N_0

IO_L28P_0

IO_L29N_0

IO_L29P_0

IO_L30N_0

IO_L30P_0

IO_L31N_0

B8

0

A8

If there is a difference between the XC3S400 pinout and the

pinout for the XC3S1000 and XC3S1500, then that differ-

ence is highlighted in Table 27. If the table entry is shaded

grey, then there is an unconnected pin on the XC3S400 that

maps to a user-I/O pin on the XC3S1000 and XC3S1500. If

the table entry is shaded tan, then the unconnected pin on

the XC3S400 maps to a VREF-type pin on the XC3S1000

and XC3S1500. If the other VREF pins in the bank all con-

nect to a voltage reference to support a special I/O stan-

dard, then also connect the N.C. pin on the XC3S400 to the

same VREF voltage. This provides maximum flexibility as

you could potentially migrate a design from the XC3S400

device to an XC3S1000 or XC3S1500 FPGA without chang-

ing the printed circuit board.

0

F9

0

E9

0

B9

0

A9

0

F10

E10

C10

B10

F11

E11

D11

C11

0

IO_L31P_0/

VREF_0

IO_L31P_0/

VREF_0

Pinout Table

0

IO_L32N_0/

GCLK7

IO_L32N_0/

GCLK7

B11

A11

GCLK

Table 27: FG456 Package Pinout

3S1000

3S1500

FG456

IO_L32P_0/

GCLK6

IO_L32P_0/

GCLK6

3S400

Bank

Pin Name

Number

Type

I/O

0

1

VCCO_0

IO

VCCO_0

IO

C8

F8

VCCO

I/O

0

IO

A10

D9

D10

F6

IO

I/O

G9

IO

I/O

G10

G11

A12

E16

F12

F13

F16

F17

E13

F14

C19

IO

I/O

IO/VREF_0

N.C. ()

IO/VREF_0

A3

VREF

DCI

C7

E5

IO

I/O

IO

I/O

F7

IO

I/O

IO_L01N_0/

VRP_0

IO_L01N_0/

VRP_0

B4

IO

I/O

IO

I/O

0

IO_L01P_0/

VRN_0

IO_L01P_0/

VRN_0

A4

DCI

IO/VREF_1

N.C. ()

IO/VREF_1

VREF

DCI

0

IO_L06N_0

IO_L06P_0

IO_L09N_0

IO_L09P_0

IO_L06N_0

IO_L06P_0

IO_L09N_0

IO_L09P_0

D5

C5

B5

A5

I/O

IO_L01N_1/

VRP_1

IO_L01N_1/

VRP_1

1

IO_L01P_1/

VRN_1

IO_L01P_1/

VRN_1

B20

DCI

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

49

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 27: FG456 Package Pinout (Continued)

3S1000

3S1500

FG456

3S1000

3S1500

FG456

3S400

Bank

Pin Name

Number

Type

Bank

Pin Name

Number

Type

I/O

1

IO_L06N_1/

VREF_1

IO_L06N_1/

VREF_1

A19

VREF

2

IO_L16P_2

IO_L17N_2

IO_L17P_2

/VREF_2

IO_L16P_2

IO_L17N_2

D19

D21

D22

I/O

1

IO_L06P_1

IO_L09N_1

IO_L09P_1

IO_L06P_1

IO_L09N_1

IO_L09P_1

B19

C18

D18

A18

I/O

IO_L17P_2/

VREF_2

VREF

I/O

2

IO_L19N_2

IO_L19P_2

IO_L20N_2

IO_L20P_2

IO_L21N_2

IO_L21P_2

IO_L22N_2

IO_L22P_2

IO_L23N_2

/VREF_2

IO_L19N_2

IO_L19P_2

IO_L20N_2

IO_L20P_2

IO_L21N_2

IO_L21P_2

IO_L22N_2

IO_L22P_2

E18

F18

E19

E20

E21

E22

G17

G18

F19

I/O

IO_L10N_1/

VREF_1

IO_L10N_1/

VREF_1

VREF

I/O

1

IO_L10P_1

IO_L15N_1

IO_L15P_1

IO_L16N_1

IO_L16P_1

N.C. ()

IO_L10P_1

IO_L15N_1

IO_L15P_1

IO_L16N_1

IO_L16P_1

IO_L19N_1

IO_L19P_1

IO_L22N_1

IO_L22P_1

IO_L24N_1

IO_L24P_1

IO_L25N_1

IO_L25P_1

IO_L27N_1

IO_L27P_1

IO_L28N_1

IO_L28P_1

IO_L29N_1

IO_L29P_1

IO_L30N_1

IO_L30P_1

B18

D17

E17

B17

C17

C16

D16

A16

B16

D15

E15

B15

A15

D14

E14

A14

B14

C13

D13

A13

B13

D12

I/O

VREF

I/O

IO_L23N_2/

VREF_2

VREF

N.C. ()

2

IO_L23P_2

IO_L24N_2

IO_L24P_2

N.C. ()

IO_L23P_2

IO_L24N_2

IO_L24P_2

IO_L26N_2

IO_L26P_2

IO_L27N_2

IO_L27P_2

IO_L28N_2

IO_L28P_2

IO_L29N_2

IO_L29P_2

IO_L31N_2

IO_L31P_2

IO_L32N_2

IO_L32P_2

IO_L33N_2

IO_L33P_2

G19

F20

F21

G20

H19

G21

G22

H18

J17

H21

H22

J18

J19

J21

J22

K17

K18

K19

I/O

VREF

N.C. ()

IO_L24N_1

IO_L24P_1

IO_L25N_1

IO_L25P_1

IO_L27N_1

IO_L27P_1

IO_L28N_1

IO_L28P_1

IO_L29N_1

IO_L29P_1

IO_L30N_1

IO_L30P_1

N.C. ()

IO_L27N_2

IO_L27P_2

N.C. ()

IO_L31N_1/

VREF_1

IO_L31N_1/

VREF_1

N.C. ()

1

IO_L31P_1

E12

B12

I/O

N.C. ()

IO_L32N_1/

GCLK5

IO_L32N_1/

GCLK5

GCLK

IO_L34N_2/

VREF_2

IO_L34N_2/

VREF_2

1

IO_L32P_1/

GCLK4

IO_L32P_1/

GCLK4

C12

GCLK

2

IO_L34P_2

IO_L35N_2

IO_L35P_2

IO_L38N_2

IO_L38P_2

IO_L39N_2

IO_L39P_2

IO_L40N_2

IO_L34P_2

IO_L35N_2

IO_L35P_2

IO_L38N_2

IO_L38P_2

IO_L39N_2

IO_L39P_2

IO_L40N_2

K20

K21

K22

L17

L18

L19

L20

L21

L22

I/O

1

2

VCCO_1

IO

VCCO_1

IO

C15

F15

G12

G13

G14

C22

C20

VCCO

I/O

IO_L01N_2/

VRP_2

IO_L01N_2/

VRP_2

DCI

IO_L40P_2/

VREF_2

IO_L40P_2/

VREF_2

VREF

2

IO_L01P_2/

VRN_2

IO_L01P_2/

VRN_2

C21

D20

DCI

I/O

2

VCCO_2

H17

H20

VCCO

IO_L16N_2

50

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 27: FG456 Package Pinout (Continued)

3S1000

3S1500

FG456

3S1000

3S1500

FG456

3S400

Bank

Pin Name

Number

Type

VCCO

I/O

Bank

Pin Name

Number

Type

I/O

2

3

VCCO_2

IO

VCCO_2

IO

J16

K16

L16

Y21

Y20

3

IO_L38P_3

IO_L39N_3

IO_L39P_3

IO_L38P_3

IO_L39N_3

IO_L39P_3

M17

M20

M19

M22

I/O

IO_L40N_3/

VREF_3

IO_L40N_3/

VREF_3

VREF

IO_L01N_3/

VRP_3

IO_L01N_3/

VRP_3

DCI

3

4

IO_L40P_3

VCCO_3

IO

IO_L40P_3

VCCO_3

IO

M21

M16

N16

P16

I/O

VCCO

I/O

3

IO_L01P_3/

VRN_3

IO_L01P_3/

VRN_3

Y19

DCI

3

IO_L16N_3

IO_L16P_3

IO_L17N_3

IO_L16N_3

IO_L16P_3

IO_L17N_3

W22

Y22

V19

W19

I/O

R17

R20

U16

U17

W13

W14

AB13

V18

I/O

IO_L17P_3/

VREF_3

IO_L17P_3/

VREF_3

VREF

IO

I/O

3

IO_L19N_3

IO_L19P_3

IO_L20N_3

IO_L20P_3

IO_L21N_3

IO_L21P_3

IO_L22N_3

IO_L22P_3

IO_L23N_3

IO_L19N_3

IO_L19P_3

IO_L20N_3

IO_L20P_3

IO_L21N_3

IO_L21P_3

IO_L22N_3

IO_L22P_3

IO_L23N_3

W21

W20

U19

V20

V22

V21

T17

U18

U21

U20

I/O

IO

I/O

IO

I/O

IO/VREF_4

VREF

DCI

I/O

Y16

I/O

IO_L01N_4/

VRP_4

IO_L01N_4/

VRP_4

AA20

I/O

4

IO_L01P_4/

VRN_4

IO_L01P_4/

VRN_4

AB20

DCI

I/O

IO_L23P_3/

VREF_3

IO_L23P_3/

VREF_3

VREF

4

N.C. ()

IO_L05N_4

IO_L05P_4

AA19

AB19

W18

I/O

3

IO_L24N_3

IO_L24P_3

N.C. ()

IO_L27N_3

IO_L27P_3

N.C. ()

IO_L34N_3

IO_L24N_3

IO_L24P_3

IO_L26N_3

IO_L26P_3

IO_L27N_3

IO_L27P_3

IO_L28N_3

IO_L28P_3

IO_L29N_3

IO_L29P_3

IO_L31N_3

IO_L31P_3

IO_L32N_3

IO_L32P_3

IO_L33N_3

IO_L33P_3

IO_L34N_3

R18

T18

T20

T19

T22

T21

R22

R21

P19

R19

P18

P17

P22

P21

N18

N17

N20

N19

I/O

VREF

IO_L06N_4/

VREF_4

IO_L06N_4/

VREF_4

VREF

4

IO_L06P_4

IO_L09N_4

IO_L09P_4

IO_L10N_4

IO_L10P_4

IO_L15N_4

IO_L15P_4

IO_L16N_4

IO_L16P_4

N.C. ()

IO_L06P_4

IO_L09N_4

IO_L09P_4

IO_L10N_4

IO_L10P_4

IO_L15N_4

IO_L15P_4

IO_L16N_4

IO_L16P_4

IO_L19N_4

IO_L19P_4

Y18

AA18

AB18

V17

I/O

W17

Y17

I/O

AA17

V16

I/O

W16

AA16

AB16

V15

I/O

N.C. ()

I/O

N.C. ()

IO_L22N_4/

VREF_4

VREF

4

N.C. ()

IO_L22P_4

IO_L24N_4

IO_L24P_4

IO_L25N_4

IO_L25P_4

W15

AA15

AB15

U14

I/O

IO_L24N_4

IO_L24P_4

IO_L25N_4

IO_L25P_4

I/O

IO_L34P_3/

VREF_3

IO_L34P_3/

VREF_3

I/O

3

IO_L35N_3

IO_L35P_3

IO_L38N_3

IO_L35N_3

IO_L35P_3

IO_L38N_3

N22

N21

M18

I/O

V14

I/O

IO_L27N_4/

DIN/D0

IO_L27N_4/

DIN/D0

AA14

DUAL

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

51

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 27: FG456 Package Pinout (Continued)

3S1000

3S1500

FG456

3S1000

3S1500

FG456

3S400

Bank

Pin Name

Number

Type

Bank

Pin Name

Number

Type

I/O

4

IO_L27P_4/

D1

IO_L27P_4/

D1

AB14

DUAL

5

N.C. ()

IO_L19N_5

Y7

IO_L19P_5/

VREF_5

W7

VREF

4

IO_L28N_4

IO_L28P_4

IO_L29N_4

IO_L29P_4

IO_L28N_4

IO_L28P_4

IO_L29N_4

IO_L29P_4

U13

V13

I/O

5

N.C. ()

IO_L22N_5

IO_L22P_5

IO_L24N_5

IO_L24P_5

IO_L25N_5

IO_L25P_5

AB7

AA7

W8

I/O

Y13

I/O

N.C. ()

AA13

U12

I/O

IO_L24N_5

IO_L24P_5

IO_L25N_5

IO_L25P_5

I/O

IO_L30N_4/

D2

IO_L30N_4/

D2

DUAL

V8

I/O

AB8

AA8

W9

I/O

4

IO_L30P_4/

D3

IO_L30P_4/

D3

V12

W12

Y12

DUAL

GCLK

I/O

IO_L27N_5/

VREF_5

IO_L27N_5/

VREF_5

VREF

IO_L31N_4/

INIT_B

IO_L31N_4/

INIT_B

5

IO_L27P_5

V9

I/O

IO_L31P_4/

DOUT/BUSY DOUT/BUSY

IO_L31P_4/

IO_L28N_5/

D6

IO_L28N_5/

D6

AB9

DUAL

IO_L32N_4/

GCLK1

IO_L32N_4/

GCLK1

AA12

AB12

5

IO_L28P_5/

D7

IO_L28P_5/

D7

AA9

DUAL

IO_L32P_4/

GCLK0

IO_L32P_4/

GCLK0

5

IO_L29N_5

Y10

I/O

IO_L29P_5/

VREF_5

IO_L29P_5/

VREF_5

W10

VREF

4

5

VCCO_4

IO

VCCO_4

IO

T12

T13

T14

U15

Y15

U7

VCCO

I/O

5

IO_L30N_5

IO_L30P_5

IO_L30N_5

IO_L30P_5

AB10

AA10

W11

I/O

IO_L31N_5/

D4

IO_L31N_5/

D4

DUAL

5

IO_L31P_5/

D5

IO_L31P_5/

D5

V11

AA11

Y11

DUAL

GCLK

N.C. ()

IO

U9

I/O

IO

U10

U11

V7

I/O

IO_L32N_5/

GCLK3

IO_L32N_5/

GCLK3

IO

I/O

IO_L32P_5/

GCLK2

IO_L32P_5/

GCLK2

IO

I/O

IO

V10

AB11

U6

I/O

5

6

VCCO_5

IO

VCCO_5

IO

T9

T10

T11

U8

VCCO

I/O

IO/VREF_5

VREF

DUAL

IO_L01N_5/

RDWR_B

IO_L01N_5/

RDWR_B

Y4

Y8

5

IO_L01P_5/

CS_B

IO_L01P_5/

CS_B

AA3

DUAL

Y1

5

IO_L06N_5

IO_L06P_5

IO_L09N_5

IO_L09P_5

IO_L06N_5

IO_L06P_5

IO_L09N_5

IO_L09P_5

AB4

AA4

Y5

I/O

DCI

IO_L01N_6/

VRP_6

IO_L01N_6/

VRP_6

Y3

DCI

6

IO_L01P_6/

VRN_6

IO_L01P_6/

VRN_6

Y2

DCI

W5

6

IO_L16N_6

IO_L16P_6

IO_L17N_6

IO_L16N_6

IO_L16P_6

IO_L17N_6

W4

W3

W2

W1

I/O

IO_L10N_5/

VRP_5

IO_L10N_5/

VRP_5

AB5

I/O

5

IO_L10P_5/

VRN_5

IO_L10P_5/

VRN_5

AA5

DCI

IO_L17P_6/

VREF_6

IO_L17P_6/

VREF_6

VREF

5

IO_L15N_5

IO_L15P_5

IO_L16N_5

IO_L16P_5

IO_L15N_5

IO_L15P_5

IO_L16N_5

IO_L16P_5

W6

V6

I/O

6

IO_L19N_6

IO_L19P_6

IO_L20N_6

IO_L19N_6

IO_L19P_6

IO_L20N_6

V5

U5

V4

I/O

AA6

Y6

52

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 27: FG456 Package Pinout (Continued)

3S1000

3S1500

FG456

3S1000

3S1500

FG456

3S400

Bank

Pin Name

Number

Type

I/O

Bank

Pin Name

Number

Type

I/O

6

IO_L20P_6

IO_L21N_6

IO_L21P_6

IO_L22N_6

IO_L22P_6

IO_L23N_6

IO_L23P_6

IO_L20P_6

IO_L21N_6

IO_L21P_6

IO_L22N_6

IO_L22P_6

IO_L23N_6

IO_L23P_6

V3

V2

V1

T6

T5

U4

T4

U3

7

IO_L16N_7

D1

C1

I/O

IO_L16P_7/

VREF_7

IO_L16P_7/

VREF_7

VREF

I/O

7

IO_L17N_7

IO_L17P_7

IO_L17N_7

IO_L17P_7

E4

D4

D3

I/O

IO_L19N_7/

VREF_7

IO_L19N_7/

VREF_7

VREF

I/O

7

IO_L19P_7

IO_L20N_7

IO_L20P_7

IO_L21N_7

IO_L21P_7

IO_L22N_7

IO_L22P_7

IO_L23N_7

IO_L23P_7

IO_L24N_7

IO_L24P_7

N.C. ()

IO_L19P_7

IO_L20N_7

IO_L20P_7

IO_L21N_7

IO_L21P_7

IO_L22N_7

IO_L22P_7

IO_L23N_7

IO_L23P_7

IO_L24N_7

IO_L24P_7

IO_L26N_7

IO_L26P_7

IO_L27N_7

D2

F4

E3

E1

E2

G6

F5

F2

F3

H5

G5

G3

G4

G1

G2

I/O

IO_L24N_6/

VREF_6

IO_L24N_6/

VREF_6

VREF

I/O

6

IO_L24P_6

N.C. ()

IO_L27N_6

IO_L27P_6

N.C. ()

IO_L24P_6

IO_L26N_6

IO_L26P_6

IO_L27N_6

IO_L27P_6

IO_L28N_6

IO_L28P_6

IO_L29N_6

IO_L29P_6

IO_L31N_6

IO_L31P_6

IO_L32N_6

IO_L32P_6

IO_L33N_6

IO_L33P_6

U2

T3

R4

T2

T1

R5

P6

R2

R1

P5

P4

P2

P1

N6

N5

N4

I/O

VREF

I/O

N.C. ()

I/O

IO_L27N_7

I/O

IO_L27P_7/

VREF_7

IO_L27P_7/

VREF_7

VREF

7

N.C. ()

IO_L28N_7

IO_L28P_7

IO_L29N_7

IO_L29P_7

IO_L31N_7

IO_L31P_7

IO_L32N_7

IO_L32P_7

IO_L33N_7

IO_L33P_7

IO_L34N_7

IO_L34P_7

IO_L35N_7

IO_L35P_7

IO_L38N_7

IO_L38P_7

IO_L39N_7

IO_L39P_7

H1

H2

J4

H4

J5

J6

J1

J2

K5

K6

K3

K4

K1

K2

L5

L6

L3

L4

L1

I/O

VREF

N.C. ()

IO_L34N_6/

VREF_6

IO_L34N_6/

VREF_6

N.C. ()

6

IO_L34P_6

IO_L35N_6

IO_L35P_6

IO_L38N_6

IO_L38P_6

IO_L39N_6

IO_L39P_6

IO_L40N_6

IO_L34P_6

IO_L35N_6

IO_L35P_6

IO_L38N_6

IO_L38P_6

IO_L39N_6

IO_L39P_6

IO_L40N_6

N3

N2

N1

M6

M5

M4

M3

M2

M1

I/O

N.C. ()

I/O

N.C. ()

I/O

N.C. ()

I/O

N.C. ()

I/O

N.C. ()

I/O

IO_L34N_7

IO_L34P_7

IO_L35N_7

IO_L35P_7

IO_L38N_7

IO_L38P_7

IO_L39N_7

IO_L39P_7

I/O

IO_L40P_6/

VREF_6

IO_L40P_6/

VREF_6

VREF

6

7

VCCO_6

IO

VCCO_6

IO

M7

N7

P7

R3

R6

C2

C3

VCCO

I/O

IO_L40N_7/

VREF_7

IO_L40N_7/

VREF_7

IO_L01N_7/

VRP_7

IO_L01N_7/

VRP_7

DCI

7

IO_L40P_7

VCCO_7

IO_L40P_7

VCCO_7

L2

H3

H6

I/O

7

IO_L01P_7/

VRN_7

IO_L01P_7/

VRN_7

C4

DCI

VCCO

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

53

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 27: FG456 Package Pinout (Continued)

3S1000

3S1500

FG456

3S1000

3S1500

FG456

3S400

Bank

7

Pin Name

Number

Type

VCCO

GND

Bank

N/A

Pin Name

Number

Type

GND

VCCO_7

GND

VCCO_7

GND

J7

K7

GND

P3

P9

7

GND

7

L7

GND

P10

P11

P12

P13

P14

P20

Y9

GND

N/A

A1

GND

A22

AA2

AA21

AB1

AB22

B2

GND

Y14

A6

GND

B21

C9

VCCAUX

VCCINT

VCCAUX

VCCINT

CCLK

VCCAUX

VCCINT

CONFIG

JTAG

A17

AB6

AB17

F1

C14

J3

J9

J10

J11

J12

J13

J14

J20

K9

F22

U1

U22

G7

G8

G15

G16

H7

K10

K11

K12

K13

K14

L9

H16

R7

R16

T7

T8

L10

L11

L12

L13

L14

M9

T15

T16

AA22

AB21

B3

VCCAUX CCLK

VCCAUX DONE

DONE

VCCAUX HSWAP_EN HSWAP_EN

VCCAUX M0

VCCAUX M1

VCCAUX M2

VCCAUX PROG_B

VCCAUX TCK

VCCAUX TDI

VCCAUX TDO

VCCAUX TMS

M0

AB2

AA1

AB3

A2

M10

M11

M12

M13

M14

N9

M1

M2

PROG_B

TCK

TDI

A21

B1

JTAG

TDO

TMS

B22

A20

JTAG

N10

N11

N12

N13

N14

JTAG

54

www.xilinx.com

1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

able user-I/O pins are distributed between the eight I/O

banks for the XC3S1000 and XC3S1500 in the FG456

package.

User I/Os by Bank

Table 28 indicates how the available user-I/O pins are dis-

tributed between the eight I/O banks for the XC3S400 in the

FG456 package. Similarly, Table 29 shows how the avail-

Table 28: User I/Os Per Bank for XC3S400 in FG456 Package

All Possible I/O Pins by Type

I/O

Bank

Maximum

I/O

Edge

I/O

27

25

21

25

DUAL

DCI

2

VREF

GCLK

0

1

2

3

4

5

6

7

35

31

35

31

0

6

0

4

2

0

2

0

Top

2

Right

Bottom

Left

2

Table 29: User I/Os Per Bank for XC3S1000 and XC3S1500 in FG456 Package

All Possible I/O Pins by Type

Maximum

I/O

Edge

I/O Bank

I/O

31

37

26

25

37

DUAL

DCI

2

VREF

GCLK

0

1

2

3

4

5

6

7

40

43

41

40

43

0

6

0

5

4

5

4

2

0

2

0

Top

2

Right

Bottom

Left

2

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

55

R

Spartan-3 FPGA Family: Pinout Descriptions

FG456 Footprint

Bank 0

7

1

2

3

4

5

6

8

9

10

11

Left Half of Package

(top view)

I/O

L19P_0

I/O

L01P_0

VRN_0

I/O

L32P_0

GCLK6

IO

VREF_0

I/O

L09P_0

I/O

PROG_B

VCCAUX

I/O

A

B

C

D

E

F

GND

L24P_0 L27P_0

XC3S400

(264 max. user I/O)

I/O

L19N_0

I/O

L01N_0

VRP_0

I/O

L32N_0

GCLK7

HSWAP_

EN

I/O

TDI

GND

L09N_0 L15P_0

L24N_0 L27N_0 L29P_0

I/O: Unrestricted,

general-purpose user I/O

196

I/O

L16P_7

VREF_7

I/O

L31P_0

VREF_0

IO

VREF_0

I/O

VCCO_0

I/O

GND

L01N_7 L01P_7

VRP_7 VRN_7

L06P_0 L15N_0

L29N_0

I/O

VREF: User I/O or input

32

I/O

L22P_0

I/O

voltage reference for bank

I/O

L31N_0

I/O

L19N_7

L16N_7 L19P_7

L17P_7 L06N_0 L10P_0 L16P_0

VREF_7

N.C.: Unconnected pins for

XC3S400 ()

IO

VREF_0

I/O

L22N_0

69

I/O

L21N_7 L21P_7 L20P_7 L17N_7

L10N_0 L16N_0

L25P_0 L28P_0 L30P_0

XC3S1000, XC3S1500

(333 max user I/O)

IO

I/O

VCCAUX

VCCO_0

VREF_0

L23N_7 L23P_7 L20N_7 L22P_7

L25N_0 L28N_0 L30N_0

I/O: Unrestricted,

general-purpose user I/O

261

I/O

L27P_7

VREF_7

I/O

VCCO_0 VCCO_0 VCCO_0

VCCINT VCCINT

VCCINT

G

H

J

L26N_7 L26P_7

L27N_7

L24P_7 L22N_7

VREF: User I/O or input

36

I/O

L29P_7

I/O

L24N_7

L28N_7 L28P_7

voltage reference for bank

VCCO_7

I/O

N.C.: No unconnected pins

in this package

0

L32N_7 L32P_7

L29N_7 L31N_7 L31P_7

VCCO_7

GND

I/O

GND

I/O

All devices

I/O

L33N_7 L33P_7

VCCO_7

K

L35N_7 L35P_7 L34N_7 L34P_7

DUAL: Configuration pin,

then possible user I/O

12

I/O

VCCO_7

L L40N_7

L40P_7 L39N_7 L39P_7 L38N_7 L38P_7

VREF_7

GCLK: User I/O or global

clock buffer input

8

I/O

M L40P_6

VREF_6

I/O

VCCO_6

L40N_6 L39P_6 L39N_6 L38P_6 L38N_6

DCI: User I/O or reference

16

I/O

L34N_6

VREF_6

resistor input for bank

I/O

L33P_6 L33N_6

VCCO_6

N

GND

L35P_6 L35N_6 L34P_6

CONFIG: Dedicated

configuration pins

I/O

7

L32P_6 L32N_6

L31P_6 L31N_6 L28P_6

VCCO_6

GND

P

R

T

I/O

JTAG: Dedicated JTAG

port pins

4

L29P_6 L29N_6

L26P_6 L28N_6

VCCO_6

VCCINT

I/O

L26N_6

VCCINT: Internal core

12

I/O

VCCO_5 VCCO_5 VCCO_5

I/O

VCCINT VCCINT

L27P_6 L27N_6

L23P_6 L22P_6 L22N_6

voltage supply (+1.2V)

I/O

L24N_6

VREF_6

IO

VREF_5

I/O

L24P_6

I/O

VCCO: Output voltage

supply for bank

VCCAUX

VCCO_5

I/O

U

V

L23N_6 L19P_6

40

I/O

L31P_5

D5

I/O

VCCAUX:Auxiliaryvoltage

supply (+2.5V)

L21P_6 L21N_6 L20P_6 L20N_6 L19N_6 L15P_5

L24P_5 L27P_5

8

I/O

L19P_5

VREF_5

I/O

L19N_5

I/O

W L17P_6

L27N_5 L29P_5 L31N_5

L17N_6 L16P_6 L16N_6 L09P_5 L15N_5

L24N_5

GND: Ground

VREF_6

VREF_5 VREF_5

D4

52

I/O

L32P_5

GCLK2

I/O

GND

VCCO_5

I/O

M1

Y

L01P_6 L01N_6 L01N_5

VRN_6 VRP_6 RDWR_B

L09N_5 L16P_5

L29N_5

I/O

L22P_5

I/O

L32N_5

GCLK3

A

I/O

L25P_5

GND

M0

L01P_5

CS_B

L10P_5

L16N_5

VRN_5

L28P_5

L30P_5

D7

L06P_5

I/O

L22N_5

I/O

A

B

IO

VREF_5

I/O

L06N_5

I/O

L25N_5

VCCAUX

L10N_5

GND

M2

L28N_5

L30N_5

D6

VRP_5

Bank 5

DS099-4_11a_030203

Figure 13: FG456 Package Footprint (top view)

56

www.xilinx.com

1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Bank 1

12

13

14

15

16

I/O

L22N_1

17

18

19

20

21

22

Right Half of Package

(top view)

I/O

VCCAUX

I/O

TMS

TCK

GND

L10N_1 L06N_1

VREF_1 VREF_1

A

B

C

L30N_1 L28N_1 L25P_1

I/O

L22P_1

I/O

L32N_1

GCLK5

I/O

L01P_1

VRN_1

I/O

GND

I/O

TDO

L30P_1 L28P_1 L25N_1

L16N_1 L10P_1 L06P_1

I/O

L19N_1

I/O

L32P_1

GCLK4

I/O

VCCO_1

I/O

GND

I/O

L01N_1 L01N_2 L01P_2

VRP_1 VRP_2 VRN_2

L29N_1

I/O

L16P_1 L09N_1

I/O

L19P_1

I/O

L31N_1

VREF_1

I/O

L17P_2 D

L29P_1 L27N_1 L24N_1

L15N_1 L09P_1 L16P_2 L16N_2 L17N_2

VREF_2

IO

VREF_1

I/O

L31P_1

I/O

E

L27P_1 L24P_1

L15P_1 L19N_2 L20N_2 L20P_2 L21N_2 L21P_2

IO

I/O

L23N_2

VREF_2

I/O

VREF_1

VCCO_1

VCCAUX

I/O

F

G

H

J

L19P_2

L24N_2 L24P_2

I/O

L26N_2

I/O

VCCO_1 VCCO_1 VCCO_1

VCCINT VCCINT

VCCINT

L22N_2 L22P_2 L23P_2

L27N_2 L27P_2

I/O

L28N_2 L26P_2

L29N_2 L29P_2

VCCO_2

I/O

VCCO_2

I/O

L28P_2 L31N_2 L31P_2

L32N_2 L32P_2

VCCO_2

GND

I/O

L34N_2

VREF_2

I/O

L33N_2 L33P_2

VCCO_2

K

L

L34P_2 L35N_2 L35P_2

I/O

VCCO_2

L40P_2

L38N_2 L38P_2 L39N_2 L39P_2 L40N_2

VREF_2

I/O

VCCO_3

L40N_3 M

L38P_3 L38N_3 L39P_3 L39N_3 L40P_3

VREF_3

I/O

L34P_3

VREF_3

I/O

L33P_3 L33N_3

VCCO_3

N

L34N_3 L35P_3 L35N_3

I/O

L31P_3 L31N_3 L29N_3

L32P_3 L32N_3

VCCO_3

GND

P

R

T

I/O

L29P_3

I/O

L24N_3

L28P_3 L28N_3

VCCO_3

I/O

VCCINT

I/O

L26P_3 L26N_3

VCCO_4 VCCO_4 VCCO_4

I/O

VCCINT VCCINT

L22N_3 L24P_3

L27P_3 L27N_3

I/O

L23P_3

VREF_3

I/O

L23N_3

VCCO_4

VCCAUX

I/O

L30N_4

D2

U

V

W

Y

L28N_4 L25N_4

L22P_3 L20N_3

I/O

L22N_4

VREF_4

I/O

L22P_4

I/O

L30P_4

D3

IO

VREF_4

I/O

L28P_4 L25P_4

L16N_4 L10N_4

L17N_3 L20P_3 L21P_3 L21N_3

I/O

L31N_4

INIT_B

I/O

L31P_4

DOUT L29N_4

BUSY

I/O

L06N_4 L17P_3

VREF_4 VREF_3

L16P_4 L10P_4

L19P_3 L19N_3 L16N_3

I/O

IO

VREF_4

I/O

L16P_3

VCCO_4

GND

I/O

L01P_3 L01N_3

VRN_3 VRP_3

L15N_4 L06P_4

I/O

L27N_4

DIN

I/O

L19N_4

I/O

L05N_4

I/O

L01N_4

VRP_4

A

I/O

L24N_4

I/O

GND

CCLK

L32N_4

L29P_4

GCLK1

L15P_4 L09N_4

D0

I/O

IO

I/O

L27P_4

D1

I/O

L01P_4

VRN_4

A

B

I/O

L24P_4

I/O

L09P_4

L19P_4

L05P_4

VCCAUX

DONE GND

L32P_4

VREF_4

GCLK0

Bank 4

DS099-4_11b_030503

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

57

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 30: FG676 Package Pinout (Continued)

FG676: 676-lead Fine-pitch Ball Grid

Array

FG676

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

The 676-lead fine-pitch ball grid array package, FG676,

supports three different Spartan-3 devices, including the

XC3S1000, the XC3S1500, and the XC3S2000. All three

have nearly identical footprints but are slightly different due

to unconnected pins on the XC3S1000 and XC3S1500. For

example, because the XC3S1000 has fewer I/O pins, this

device has 98 unconnected pins on the FG676 package,

labeled as “N.C.” In Table 30 and Figure 14, these uncon-

nected pins are indicated with a black diamond symbol ().

The XC3S1500, however, has only two unconnected pins,

also labeled “N.C.” in the pinout table but indicated with a

black square symbol ().

Type

0

IO_L01P_0/ IO_L01P_0/ IO_L01P_0/

D5

DCI

VRN_0

0

IO_L05N_0

B4

A4

I/O

IO_L05P_0/ IO_L05P_0/ IO_L05P_0/

VREF

VREF_0

0

IO_L06N_0

IO_L06P_0

IO_L07N_0

IO_L07P_0

IO_L08N_0

IO_L08P_0

IO_L09N_0

IO_L09P_0

IO_L10N_0

IO_L10P_0

N.C. ()

IO_L06N_0

IO_L06P_0

IO_L07N_0

IO_L07P_0

IO_L08N_0

IO_L08P_0

IO_L09N_0

IO_L09P_0

IO_L10N_0

IO_L10P_0

IO_L11N_0

IO_L11P_0

IO_L12N_0

IO_L12P_0

IO_L15N_0

IO_L15P_0

IO_L16N_0

IO_L16P_0

IO_L17N_0

IO_L17P_0

IO_L18N_0

IO_L18P_0

IO_L19N_0

IO_L19P_0

IO_L22N_0

IO_L22P_0

IO_L23N_0

IO_L23P_0

IO_L24N_0

IO_L24P_0

IO_L25N_0

IO_L25P_0

IO_L26N_0

IO_L06N_0

IO_L06P_0

IO_L07N_0

IO_L07P_0

IO_L08N_0

IO_L08P_0

IO_L09N_0

IO_L09P_0

IO_L10N_0

IO_L10P_0

IO_L11N_0

IO_L11P_0

IO_L12N_0

IO_L12P_0

IO_L15N_0

IO_L15P_0

IO_L16N_0

IO_L16P_0

IO_L17N_0

IO_L17P_0

IO_L18N_0

IO_L18P_0

IO_L19N_0

IO_L19P_0

IO_L22N_0

IO_L22P_0

IO_L23N_0

IO_L23P_0

IO_L24N_0

IO_L24P_0

IO_L25N_0

IO_L25P_0

IO_L26N_0

C5

B5

I/O

VREF

E6

D6

C6

B6

All the package pins appear in Table 30 and are sorted by

bank number, then by pin name. Pairs of pins that form a dif-

ferential I/O pair appear together in the table. The table also

shows the pin number for each pin and the pin type, as

defined earlier.

E7

D7

B7

A7

If there is a difference between the XC1000, XC3S1500 and

XC3S2000 pinouts, then that difference is highlighted in

Table 30. If the table entry is shaded grey, then there is an

unconnected pin on either the XC3S1000 or XC3S1500 that

maps to a user-I/O pin on the XC3S2000. If the table entry

is shaded tan, then the unconnected pin on either the

XC3S1000 or XC3S1500 maps to a VREF-type pin on the

XC3S2000. If the other VREF pins in the bank all connect to

a voltage reference to support a special I/O standard, then

also connect the N.C. pin on the XC3S1000 or XC3S1500

to the same VREF voltage. This provides maximum flexibil-

ity as you could potentially migrate a design from the

XC3S1000 through to the XC3S2000 FPGA without chang-

ing the printed circuit board.

G8

F8

N.C. ()

E8

N.C. ()

D8

IO_L15N_0

IO_L15P_0

IO_L16N_0

IO_L16P_0

N.C. ()

B8

A8

G9

F9

E9

N.C. ()

D9

N.C. ()

C9

N.C. ()

B9

IO_L19N_0

IO_L19P_0

IO_L22N_0

IO_L22P_0

N.C. ()

F10

E10

D10

C10

B10

A10

G11

F11

E11

D11

B11

A11

Pinout Table

Table 30: FG676 Package Pinout

FG676

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

Type

I/O

N.C. ()

0

IO

A3

A5

IO_L24N_0

IO_L24P_0

IO_L25N_0

IO_L25P_0

N.C. ()

IO

I/O

IO

A6

I/O

IO

C4

I/O

N.C. ()

IO

C8

I/O

IO

C12

E13

H11

H12

B3

I/O

N.C. ()

IO_L26P_0/ IO_L26P_0/

IO

I/O

VREF_0

IO

I/O

0

IO_L27N_0

IO_L27P_0

IO_L28N_0

IO_L28P_0

IO_L29N_0

IO_L29P_0

IO_L27N_0

IO_L27P_0

IO_L28N_0

IO_L28P_0

IO_L29N_0

IO_L29P_0

IO_L27N_0

IO_L27P_0

IO_L28N_0

IO_L28P_0

IO_L29N_0

IO_L29P_0

G12

H13

F12

E12

B12

A12

I/O

IO

I/O

IO/VREF_0

VREF

DCI

F7

G10

E5

IO_L01N_0/ IO_L01N_0/ IO_L01N_0/

VRP_0 VRP_0 VRP_0

58

www.xilinx.com

1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 30: FG676 Package Pinout (Continued)

FG676

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

Type

I/O

Type

I/O

VREF

0

IO_L30N_0

IO_L30P_0

IO_L31N_0

IO_L30N_0

IO_L30P_0

IO_L31N_0

IO_L30N_0

IO_L30P_0

IO_L31N_0

G13

F13

D13

C13

1

IO_L10P_1

N.C. ()

IO_L10P_1

IO_L11N_1

IO_L11P_1

IO_L12N_1

IO_L12P_1

IO_L15N_1

IO_L15P_1

IO_L16N_1

IO_L16P_1

IO_L18N_1

IO_L18P_1

IO_L19N_1

IO_L19P_1

IO_L22N_1

IO_L22P_1

IO_L23N_1

IO_L23P_1

IO_L24N_1

IO_L24P_1

IO_L25N_1

IO_L25P_1

IO_L26N_1

IO_L26P_1

IO_L27N_1

IO_L27P_1

IO_L28N_1

IO_L28P_1

IO_L29N_1

IO_L29P_1

IO_L30N_1

IO_L30P_1

IO_L10P_1

IO_L11N_1

IO_L11P_1

IO_L12N_1

IO_L12P_1

IO_L15N_1

IO_L15P_1

IO_L16N_1

IO_L16P_1

IO_L18N_1

IO_L18P_1

IO_L19N_1

IO_L19P_1

IO_L22N_1

IO_L22P_1

IO_L23N_1

IO_L23P_1

IO_L24N_1

IO_L24P_1

IO_L25N_1

IO_L25P_1

IO_L26N_1

IO_L26P_1

IO_L27N_1

IO_L27P_1

IO_L28N_1

IO_L28P_1

IO_L29N_1

IO_L29P_1

IO_L30N_1

IO_L30P_1

B20

E19

F19

C19

D19

A19

B19

F18

G18

B18

C18

F17

G17

D17

E17

A17

B17

G16

H16

E16

F16

A16

B16

G15

H15

E15

F15

A15

B15

G14

H14

D14

I/O

N.C. ()

I/O

IO_L31P_0/ IO_L31P_0/ IO_L31P_0/

VREF_0 VREF_0 VREF_0

IO_L32N_0/ IO_L32N_0/ IO_L32N_0/

GCLK7 GCLK7 GCLK7

IO_L32P_0/ IO_L32P_0/ IO_L32P_0/

GCLK6

VCCO_0

IO

N.C. ()

VREF

N.C. ()

0

B13

A13

GCLK

IO_L15N_1

IO_L15P_1

IO_L16N_1

IO_L16P_1

N.C. ()

GCLK6

VCCO_0

IO

GCLK6

VCCO_0

IO

0

1

C7

C11

H9

VCCO

I/O

N.C. ()

H10

J11

J12

J13

K13

A14

A22

A23

D16

E18

F14

F20

G19

C15

C17

D18

D22

IO_L19N_1

IO_L19P_1

IO_L22N_1

IO_L22P_1

N.C. ()

IO

I/O

IO_L24N_1

IO_L24P_1

IO_L25N_1

IO_L25P_1

N.C. ()

IO

I/O

IO

I/O

IO

I/O

IO

I/O

IO

I/O

N.C. ()

IO

I/O

IO_L27N_1

IO_L27P_1

IO_L28N_1

IO_L28P_1

IO_L29N_1

IO_L29P_1

IO_L30N_1

IO_L30P_1

IO/VREF_1

N.C. ()

IO/VREF_1

VREF

DCI

IO_L01N_1/ IO_L01N_1/ IO_L01N_1/

VRP_1 VRP_1 VRP_1

IO_L01P_1/ IO_L01P_1/ IO_L01P_1/

1

E22

DCI

VRN_1

1

IO_L04N_1

IO_L04P_1

IO_L05N_1

IO_L05P_1

IO_L04N_1

IO_L04P_1

IO_L05N_1

IO_L05P_1

IO_L04N_1

IO_L04P_1

IO_L05N_1

IO_L05P_1

B23

C23

E21

F21

B22

I/O

IO_L31N_1/ IO_L31N_1/ IO_L31N_1/

VREF_1

I/O

1

IO_L31P_1

E14

B14

I/O

IO_L32N_1/ IO_L32N_1/ IO_L32N_1/

GCLK5 GCLK5 GCLK5

IO_L32P_1/ IO_L32P_1/ IO_L32P_1/

GCLK

IO_L06N_1/ IO_L06N_1/ IO_L06N_1/

VREF_1

VREF

VREF_1

1

C14

GCLK

1

IO_L06P_1

IO_L07N_1

IO_L07P_1

IO_L08N_1

IO_L08P_1

IO_L09N_1

IO_L09P_1

IO_L06P_1

IO_L07N_1

IO_L07P_1

IO_L08N_1

IO_L08P_1

IO_L09N_1

IO_L09P_1

IO_L06P_1

IO_L07N_1

IO_L07P_1

IO_L08N_1

IO_L08P_1

IO_L09N_1

IO_L09P_1

C22

C21

D21

A21

B21

D20

E20

A20

I/O

GCLK4

1

VCCO_1

C16

C20

H17

H18

J14

J15

J16

VCCO

I/O

IO_L10N_1/ IO_L10N_1/ IO_L10N_1/

VREF_1 VREF_1 VREF_1

VREF

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

59

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 30: FG676 Package Pinout (Continued)

FG676

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

Type

VCCO

I/O

Type

I/O

1

2

VCCO_1

IO

K14

F22

C25

2

IO_L27P_2

IO_L28N_2

IO_L28P_2

IO_L29N_2

IO_L29P_2

IO_L31N_2

IO_L31P_2

IO_L32N_2

IO_L32P_2

IO_L33N_2

IO_L33P_2

IO_L27P_2

IO_L28N_2

IO_L28P_2

IO_L29N_2

IO_L29P_2

IO_L31N_2

IO_L31P_2

IO_L32N_2

IO_L32P_2

IO_L33N_2

IO_L33P_2

IO_L27P_2

IO_L28N_2

IO_L28P_2

IO_L29N_2

IO_L29P_2

IO_L31N_2

IO_L31P_2

IO_L32N_2

IO_L32P_2

IO_L33N_2

IO_L33P_2

L20

L21

L22

L25

L26

M19

M20

M21

M22

L23

M24

M25

N.C. ()

I/O

IO_L01N_2/ IO_L01N_2/ IO_L01N_2/

VRP_2 VRP_2 VRP_2

IO_L01P_2/ IO_L01P_2/ IO_L01P_2/

DCI

I/O

2

C26

DCI

I/O

VRN_2

I/O

2

IO_L02N_2

IO_L02P_2

IO_L02N_2

IO_L02P_2

IO_L02N_2

IO_L02P_2

E23

E24

D25

I/O

IO_L03N_2/ IO_L03N_2/ IO_L03N_2/

VREF

VREF_2

IO_L03P_2

N.C. ()

VREF_2

I/O

2

IO_L03P_2

IO_L05N_2

IO_L05P_2

IO_L06N_2

IO_L06P_2

IO_L07N_2

IO_L07P_2

IO_L08N_2

IO_L08P_2

IO_L03P_2

IO_L05N_2

IO_L05P_2

IO_L06N_2

IO_L06P_2

IO_L07N_2

IO_L07P_2

IO_L08N_2

IO_L08P_2

D26

E25

E26

G20

G21

F23

F24

G22

G23

F25

I/O

IO_L34N_2/ IO_L34N_2/ IO_L34N_2/

VREF_2

VREF

VREF_2

I/O

2

IO_L34P_2

IO_L35N_2

IO_L35P_2

IO_L38N_2

IO_L38P_2

IO_L39N_2

IO_L39P_2

IO_L40N_2

IO_L34P_2

IO_L35N_2

IO_L35P_2

IO_L38N_2

IO_L38P_2

IO_L39N_2

IO_L39P_2

IO_L40N_2

IO_L34P_2

IO_L35N_2

IO_L35P_2

IO_L38N_2

IO_L38P_2

IO_L39N_2

IO_L39P_2

IO_L40N_2

M26

N19

N20

N21

N22

N23

N24

N25

N26

I/O

IO_L09N_2/ IO_L09N_2/

VREF_2

VREF

VREF_2

I/O

2

N.C. ()

IO_L09P_2

IO_L10N_2

IO_L10P_2

IO_L14N_2

IO_L14P_2

IO_L16N_2

IO_L16P_2

IO_L17N_2

IO_L09P_2

IO_L10N_2

IO_L10P_2

IO_L14N_2

IO_L14P_2

IO_L16N_2

IO_L16P_2

IO_L17N_2

F26

G25

G26

H20

H21

H22

J21

I/O

N.C. ()

IO_L40P_2/ IO_L40P_2/ IO_L40P_2/

VREF

VREF_2

VCCO_2

VREF_2

VCCO_2

VREF_2

VCCO_2

N.C. ()

I/O

2

3

G24

J19

VCCO

DCI

IO_L14N_2

IO_L14P_2

IO_L16N_2

IO_L16P_2

IO_L17N_2

I/O

K19

L18

I/O

L24

H23

H24

I/O

M18

N17

N18

AA22

IO_L17P_2/ IO_L17P_2/ IO_L17P_2/

VREF_2

VREF

VREF_2

2

IO_L19N_2

IO_L19P_2

IO_L20N_2

IO_L20P_2

IO_L21N_2

IO_L21P_2

IO_L22N_2

IO_L22P_2

IO_L19N_2

IO_L19P_2

IO_L20N_2

IO_L20P_2

IO_L21N_2

IO_L21P_2

IO_L22N_2

IO_L22P_2

IO_L19N_2

IO_L19P_2

IO_L20N_2

IO_L20P_2

IO_L21N_2

IO_L21P_2

IO_L22N_2

IO_L22P_2

H25

H26

J20

K20

J22

J23

J24

J25

K21

I/O

IO_L01N_3/ IO_L01N_3/ IO_L01N_3/

VRP_3 VRP_3 VRP_3

IO_L01P_3/ IO_L01P_3/ IO_L01P_3/

VRN_3 VRN_3 VRN_3

IO_L02N_3/ IO_L02N_3/ IO_L02N_3/

I/O

3

AA21

AB24

DCI

I/O

VREF

I/O

VREF_3

3

IO_L02P_3

IO_L03N_3

IO_L03P_3

N.C. ()

IO_L02P_3

IO_L03N_3

IO_L03P_3

IO_L05N_3

IO_L05P_3

IO_L06N_3

IO_L06P_3

IO_L07N_3

IO_L07P_3

IO_L08N_3

IO_L02P_3

IO_L03N_3

IO_L03P_3

IO_L05N_3

IO_L05P_3

IO_L06N_3

IO_L06P_3

IO_L07N_3

IO_L07P_3

IO_L08N_3

AB23

AC26

AC25

Y21

I/O

IO_L23N_2/ IO_L23N_2/ IO_L23N_2/

VREF_2

VREF

VREF_2

2

IO_L23P_2

IO_L24N_2

IO_L24P_2

IO_L26N_2

IO_L26P_2

IO_L27N_2

IO_L23P_2

IO_L24N_2

IO_L24P_2

IO_L26N_2

IO_L26P_2

IO_L27N_2

IO_L23P_2

IO_L24N_2

IO_L24P_2

IO_L26N_2

IO_L26P_2

IO_L27N_2

K22

K23

K24

K25

K26

L19

I/O

Y20

AB26

AB25

AA24

AA23

Y23

60

www.xilinx.com

1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 30: FG676 Package Pinout (Continued)

FG676

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

Type

I/O

Type

I/O

3

N.C. ()

IO_L08P_3

IO_L09N_3

IO_L08P_3

IO_L09N_3

Y22

3

IO_L38P_3

IO_L39N_3

IO_L39P_3

IO_L38P_3

IO_L39N_3

IO_L39P_3

IO_L38P_3

IO_L39N_3

IO_L39P_3

P21

P24

P23

P26

AA26

AA25

I/O

IO_L09P_3/ IO_L09P_3/

VREF_3

VREF

I/O

VREF_3

IO_L40N_3/ IO_L40N_3/ IO_L40N_3/

VREF

3

N.C. ()

IO_L10N_3

IO_L10P_3

IO_L14N_3

IO_L14P_3

IO_L16N_3

IO_L16P_3

IO_L17N_3

IO_L10N_3

IO_L10P_3

IO_L14N_3

IO_L14P_3

IO_L16N_3

IO_L16P_3

IO_L17N_3

W21

W20

Y26

Y25

V21

W22

W24

W23

I/O

VREF_3

IO_L40P_3

VCCO_3

IO

VREF_3

IO_L40P_3

VCCO_3

IO

VREF_3

IO_L40P_3

VCCO_3

IO

N.C. ()

3

4

P25

P17

I/O

VCCO

I/O

IO_L14N_3

IO_L14P_3

IO_L16N_3

IO_L16P_3

IO_L17N_3

I/O

P18

I/O

R18

I/O

T18

I/O

T24

I/O

IO_L17P_3/ IO_L17P_3/ IO_L17P_3/

VREF_3

U19

VREF

VREF_3

V19

3

IO_L19N_3

IO_L19P_3

IO_L20N_3

IO_L20P_3

IO_L21N_3

IO_L21P_3

IO_L22N_3

IO_L22P_3

IO_L23N_3

IO_L19N_3

IO_L19P_3

IO_L20N_3

IO_L20P_3

IO_L21N_3

IO_L21P_3

IO_L22N_3

IO_L22P_3

IO_L23N_3

IO_L19N_3

IO_L19P_3

IO_L20N_3

IO_L20P_3

IO_L21N_3

IO_L21P_3

IO_L22N_3

IO_L22P_3

IO_L23N_3

W26

W25

U20

V20

V23

V22

V25

V24

U22

U21

I/O

Y24

AA20

AD15

AD19

AD23

AF21

AF22

W15

W16

AB14

AD25

Y17

I/O

IO

I/O

N.C. ()

IO

I/O

IO

I/O

IO

I/O

IO

I/O

IO

I/O

IO

I/O

IO_L23P_3/ IO_L23P_3/ IO_L23P_3/

VREF_3

VREF

IO/VREF_4

VREF

DCI

VREF_3

3

IO_L24N_3

IO_L24P_3

IO_L26N_3

IO_L26P_3

IO_L27N_3

IO_L27P_3

IO_L28N_3

IO_L28P_3

IO_L29N_3

IO_L29P_3

IO_L31N_3

IO_L31P_3

IO_L32N_3

IO_L32P_3

IO_L33N_3

IO_L33P_3

IO_L34N_3

IO_L24N_3

IO_L24P_3

IO_L26N_3

IO_L26P_3

IO_L27N_3

IO_L27P_3

IO_L28N_3

IO_L28P_3

IO_L29N_3

IO_L29P_3

IO_L31N_3

IO_L31P_3

IO_L32N_3

IO_L32P_3

IO_L33N_3

IO_L33P_3

IO_L34N_3

IO_L24N_3

IO_L24P_3

IO_L26N_3

IO_L26P_3

IO_L27N_3

IO_L27P_3

IO_L28N_3

IO_L28P_3

IO_L29N_3

IO_L29P_3

IO_L31N_3

IO_L31P_3

IO_L32N_3

IO_L32P_3

IO_L33N_3

IO_L33P_3

IO_L34N_3

U24

U23

U26

U25

T20

T19

T22

T21

T26

T25

R20

R19

R22

R21

R24

T23

R26

R25

I/O

VREF

IO_L01N_4/ IO_L01N_4/ IO_L01N_4/

VRP_4 VRP_4 VRP_4

IO_L01P_4/ IO_L01P_4/ IO_L01P_4/

AB22

4

AC22

DCI

VRN_4

4

IO_L04N_4

IO_L04P_4

IO_L05N_4

IO_L05P_4

IO_L04N_4

IO_L04P_4

IO_L05N_4

IO_L05P_4

IO_L04N_4

IO_L04P_4

IO_L05N_4

IO_L05P_4

AE24

AF24

AE23

AF23

AD22

I/O

IO_L06N_4/ IO_L06N_4/ IO_L06N_4/

VREF_4

VREF

VREF_4

4

IO_L06P_4

IO_L07N_4

IO_L07P_4

IO_L08N_4

IO_L08P_4

IO_L09N_4

IO_L09P_4

IO_L10N_4

IO_L10P_4

N.C. ()

IO_L06P_4

IO_L07N_4

IO_L07P_4

IO_L08N_4

IO_L08P_4

IO_L09N_4

IO_L09P_4

IO_L10N_4

IO_L10P_4

IO_L11N_4

IO_L11P_4

IO_L06P_4

IO_L07N_4

IO_L07P_4

IO_L08N_4

IO_L08P_4

IO_L09N_4

IO_L09P_4

IO_L10N_4

IO_L10P_4

IO_L11N_4

IO_L11P_4

AE22

AB21

AC21

AD21

AE21

AB20

AC20

AE20

AF20

Y19

I/O

IO_L34P_3/ IO_L34P_3/ IO_L34P_3/

VREF_3

3

IO_L35N_3

IO_L35P_3

IO_L38N_3

IO_L35N_3

IO_L35P_3

IO_L38N_3

IO_L35N_3

IO_L35P_3

IO_L38N_3

P20

P19

P22

I/O

N.C. ()

AA19

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

61

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 30: FG676 Package Pinout (Continued)

FG676

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

Type

I/O

Type

VCCO

I/O

4

N.C. ()

IO_L12N_4

IO_L12P_4

IO_L15N_4

IO_L15P_4

IO_L16N_4

IO_L16P_4

IO_L17N_4

IO_L17P_4

IO_L18N_4

IO_L18P_4

IO_L19N_4

IO_L19P_4

IO_L12N_4

IO_L12P_4

IO_L15N_4

IO_L15P_4

IO_L16N_4

IO_L16P_4

IO_L17N_4

IO_L17P_4

IO_L18N_4

IO_L18P_4

IO_L19N_4

IO_L19P_4

AB19

AC19

AE19

AF19

Y18

4

5

VCCO_4

IO

VCCO_4

V15

V16

N.C. ()

VCCO_4

I/O

IO_L15N_4

IO_L15P_4

IO_L16N_4

IO_L16P_4

N.C. ()

VCCO_4

W17

W18

AA7

AA13

AB9

AC9

AC11

AD10

AD12

AF4

I/O

VCCO_4

I/O

IO

I/O

AA18

AB18

AC18

AD18

AE18

AC17

AA17

AD17

IO

I/O

IO

I/O

N.C. ()

IO

I/O

N.C. ()

IO

I/O

N.C. ()

IO

I/O

IO_L19N_4

IO_L19P_4

IO

I/O

IO

I/O

IO_L22N_4/ IO_L22N_4/ IO_L22N_4/

VREF_4

IO

Y8

VREF

I/O

VREF_4

IO/VREF_5

AF5

VREF

DUAL

4

IO_L22P_4

N.C. ()

IO_L22P_4

IO_L23N_4

IO_L23P_4

IO_L24N_4

IO_L24P_4

IO_L25N_4

IO_L25P_4

IO_L26N_4

IO_L22P_4

IO_L23N_4

IO_L23P_4

IO_L24N_4

IO_L24P_4

IO_L25N_4

IO_L25P_4

IO_L26N_4

AB17

AE17

AF17

Y16

I/O

AF13

AC5

IO_L01N_5/ IO_L01N_5/ IO_L01N_5/

RDWR_B RDWR_B RDWR_B

IO_L01P_5/ IO_L01P_5/ IO_L01P_5/

N.C. ()

I/O

IO_L24N_4

IO_L24P_4

IO_L25N_4

IO_L25P_4

N.C. ()

5

AB5

I/O

DUAL

CS_B

AA16

AB16

AC16

AE16

AF16

I/O

5

IO_L04N_5

IO_L04P_5

IO_L05N_5

IO_L05P_5

IO_L06N_5

IO_L06P_5

IO_L07N_5

IO_L07P_5

IO_L08N_5

IO_L08P_5

IO_L09N_5

IO_L09P_5

IO_L04N_5

IO_L04P_5

IO_L05N_5

IO_L05P_5

IO_L06N_5

IO_L06P_5

IO_L07N_5

IO_L07P_5

IO_L08N_5

IO_L08P_5

IO_L09N_5

IO_L09P_5

IO_L04N_5

IO_L04P_5

IO_L05N_5

IO_L05P_5

IO_L06N_5

IO_L06P_5

IO_L07N_5

IO_L07P_5

IO_L08N_5

IO_L08P_5

IO_L09N_5

IO_L09P_5

AE4

AD4

AB6

AA6

AE5

AD5

AD6

AC6

AF6

AE6

AC7

AB7

AF7

I/O

DCI

I/O

N.C. ()

IO_L26P_4/ IO_L26P_4/

VREF_4 VREF_4

IO_L27N_4/ IO_L27N_4/ IO_L27N_4/

DIN/D0 DIN/D0 DIN/D0

IO_L27P_4/ IO_L27P_4/ IO_L27P_4/

VREF

4

Y15

DUAL

W14

D1

4

IO_L28N_4

IO_L28P_4

IO_L29N_4

IO_L29P_4

IO_L28N_4

IO_L28P_4

IO_L29N_4

IO_L29P_4

IO_L28N_4

IO_L28P_4

IO_L29N_4

IO_L29P_4

AA15

AB15

AE15

AF15

Y14

I/O

IO_L10N_5/ IO_L10N_5/ IO_L10N_5/

VRP_5 VRP_5 VRP_5

IO_L10P_5/ IO_L10P_5/ IO_L10P_5/

IO_L30N_4/ IO_L30N_4/ IO_L30N_4/

D2 D2 D2

IO_L30P_4/ IO_L30P_4/ IO_L30P_4/

D3 D3 D3

IO_L31N_4/ IO_L31N_4/ IO_L31N_4/

INIT_B INIT_B INIT_B

DUAL

5

AE7

AB8

DCI

4

AA14

AC14

AD14

AE14

AF14

DUAL

GCLK

VRN_5

N.C. ()

IO_L11N_5/ IO_L11N_5/

VREF_5

VREF

VREF_5

5

N.C. ()

IO_L11P_5

IO_L12N_5

IO_L12P_5

IO_L15N_5

IO_L15P_5

IO_L16N_5

IO_L16P_5

IO_L18N_5

IO_L18P_5

IO_L19N_5

IO_L11P_5

IO_L12N_5

IO_L12P_5

IO_L15N_5

IO_L15P_5

IO_L16N_5

IO_L16P_5

IO_L18N_5

IO_L18P_5

IO_L19N_5

AA8

AD8

AC8

AF8

AE8

AA9

Y9

I/O

IO_L31P_4/ IO_L31P_4/ IO_L31P_4/

DOUT/BUSY DOUT/BUSY DOUT/BUSY

N.C. ()

IO_L32N_4/ IO_L32N_4/ IO_L32N_4/

GCLK1

N.C. ()

GCLK1

IO_L15N_5

IO_L15P_5

IO_L16N_5

IO_L16P_5

N.C. ()

IO_L32P_4/ IO_L32P_4/ IO_L32P_4/

GCLK0

4

VCCO_4

AD16

AD20

U14

VCCO

AE9

AD9

AA10

N.C. ()

V14

IO_L19N_5

62

www.xilinx.com

1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 30: FG676 Package Pinout (Continued)

FG676

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

Type

I/O

5

IO_L19P_5/ IO_L19P_5/ IO_L19P_5/

Y10

6

IO_L03P_6

N.C. ()

IO_L03P_6

IO_L05N_6

IO_L05P_6

IO_L06N_6

IO_L06P_6

IO_L07N_6

IO_L07P_6

IO_L08N_6

IO_L08P_6

IO_L03P_6

IO_L05N_6

IO_L05P_6

IO_L06N_6

IO_L06P_6

IO_L07N_6

IO_L07P_6

IO_L08N_6

IO_L08P_6

AC1

AB2

AB1

Y7

VREF

VREF_5

I/O

5

IO_L22N_5

IO_L22P_5

N.C. ()

IO_L22N_5

IO_L22P_5

IO_L23N_5

IO_L23P_5

IO_L24N_5

IO_L24P_5

IO_L25N_5

IO_L25P_5

IO_L26N_5

IO_L26P_5

IO_L22N_5

IO_L22P_5

IO_L23N_5

IO_L23P_5

IO_L24N_5

IO_L24P_5

IO_L25N_5

IO_L25P_5

IO_L26N_5

IO_L26P_5

AC10

AB10

AF10

AE10

Y11

I/O

Y6

I/O

N.C. ()

I/O

AA4

AA3

Y5

I/O

IO_L24N_5

IO_L24P_5

IO_L25N_5

IO_L25P_5

N.C. ()

I/O

W11

I/O

AB11

AA11

AF11

AE11

Y12

I/O

Y4

I/O

IO_L09N_6/ IO_L09N_6/

VREF_6

AA2

VREF

I/O

VREF_6

N.C. ()

6

N.C. ()

IO_L09P_6

IO_L10N_6

IO_L10P_6

IO_L14N_6

IO_L14P_6

IO_L16N_6

IO_L16P_6

IO_L17N_6

IO_L09P_6

IO_L10N_6

IO_L10P_6

IO_L14N_6

IO_L14P_6

IO_L16N_6

IO_L16P_6

IO_L17N_6

AA1

Y2

I/O

IO_L27N_5/ IO_L27N_5/ IO_L27N_5/

N.C. ()

VREF

VREF_5

N.C. ()

Y1

I/O

5

IO_L27P_5

W12

I/O

IO_L14N_6

IO_L14P_6

IO_L16N_6

IO_L16P_6

IO_L17N_6

W7

W6

V6

I/O

IO_L28N_5/ IO_L28N_5/ IO_L28N_5/

D6 D6 D6

IO_L28P_5/ IO_L28P_5/ IO_L28P_5/

AB12

DUAL

I/O

5

AA12

DUAL

D7

W5

W4

W3

I/O

5

IO_L29N_5

AF12

AE12

I/O

IO_L29P_5/ IO_L29P_5/ IO_L29P_5/

VREF

IO_L17P_6/ IO_L17P_6/ IO_L17P_6/

VREF_6

VREF

VREF_5

VREF_6

5

IO_L30N_5

IO_L30P_5

IO_L30N_5

IO_L30P_5

IO_L30N_5

IO_L30P_5

Y13

W13

AC13

I/O

6

IO_L19N_6

IO_L19P_6

IO_L20N_6

IO_L20P_6

IO_L21N_6

IO_L21P_6

IO_L22N_6

IO_L22P_6

IO_L23N_6

IO_L23P_6

IO_L19N_6

IO_L19P_6

IO_L20N_6

IO_L20P_6

IO_L21N_6

IO_L21P_6

IO_L22N_6

IO_L22P_6

IO_L23N_6

IO_L23P_6

IO_L19N_6

IO_L19P_6

IO_L20N_6

IO_L20P_6

IO_L21N_6

IO_L21P_6

IO_L22N_6

IO_L22P_6

IO_L23N_6

IO_L23P_6

W2

W1

V7

U7

V5

V4

V3

V2

U6

U5

U4

I/O

IO_L31N_5/ IO_L31N_5/ IO_L31N_5/

D4 D4 D4

IO_L31P_5/ IO_L31P_5/ IO_L31P_5/

D5 D5 D5

IO_L32N_5/ IO_L32N_5/ IO_L32N_5/

GCLK3 GCLK3 GCLK3

IO_L32P_5/ IO_L32P_5/ IO_L32P_5/

DUAL

I/O

5

AB13

AE13

AD13

DUAL

GCLK

I/O

GCLK2

I/O

5

6

VCCO_5

N.C. ()

VCCO_5

N.C. ()

VCCO_5

IO

AD7

AD11

U13

V11

V12

V13

W9

VCCO

I/O

IO_L24N_6/ IO_L24N_6/ IO_L24N_6/

VREF_6

VREF

VREF_6

6

IO_L24P_6

IO_L26N_6

IO_L26P_6

IO_L27N_6

IO_L27P_6

IO_L28N_6

IO_L28P_6

IO_L29N_6

IO_L29P_6

IO_L31N_6

IO_L31P_6

IO_L32N_6

IO_L32P_6

IO_L24P_6

IO_L26N_6

IO_L26P_6

IO_L27N_6

IO_L27P_6

IO_L28N_6

IO_L28P_6

IO_L29N_6

IO_L29P_6

IO_L31N_6

IO_L31P_6

IO_L32N_6

IO_L32P_6

IO_L24P_6

IO_L26N_6

IO_L26P_6

IO_L27N_6

IO_L27P_6

IO_L28N_6

IO_L28P_6

IO_L29N_6

IO_L29P_6

IO_L31N_6

IO_L31P_6

IO_L32N_6

IO_L32P_6

U3

U2

U1

T8

T7

T6

T5

T2

T1

R8

R7

R6

R5

I/O

W10

AA5

AD2

IO_L01N_6/ IO_L01N_6/ IO_L01N_6/

VRP_6 VRP_6 VRP_6

IO_L01P_6/ IO_L01P_6/ IO_L01P_6/

DCI

6

AD1

DCI

VRN_6

6

IO_L02N_6

IO_L02P_6

IO_L02N_6

IO_L02P_6

IO_L02N_6

IO_L02P_6

AB4

AB3

AC2

I/O

IO_L03N_6/ IO_L03N_6/ IO_L03N_6/

VREF_6 VREF_6 VREF_6

VREF

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

63

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 30: FG676 Package Pinout (Continued)

FG676

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

Type

I/O

Type

6

IO_L33N_6

IO_L33P_6

IO_L33N_6

IO_L33P_6

IO_L33N_6

IO_L33P_6

T4

R3

R2

7

IO_L16P_7/ IO_L16P_7/ IO_L16P_7/

VREF_7

H5

VREF

VREF_7

I/O

7

IO_L17N_7

IO_L17P_7

IO_L17N_7

IO_L17P_7

IO_L17N_7

IO_L17P_7

H3

H4

H1

I/O

IO_L34N_6/ IO_L34N_6/ IO_L34N_6/

VREF_6

VREF

VREF_6

6

IO_L34P_6

IO_L35N_6

IO_L35P_6

IO_L38N_6

IO_L38P_6

IO_L39N_6

IO_L39P_6

IO_L40N_6

IO_L34P_6

IO_L35N_6

IO_L35P_6

IO_L38N_6

IO_L38P_6

IO_L39N_6

IO_L39P_6

IO_L40N_6

IO_L34P_6

IO_L35N_6

IO_L35P_6

IO_L38N_6

IO_L38P_6

IO_L39N_6

IO_L39P_6

IO_L40N_6

R1

P8

P7

P6

P5

P4

P3

P2

P1

IO_L19N_7/ IO_L19N_7/ IO_L19N_7/

VREF_7

I/O

VREF

VREF_7

7

IO_L19P_7

IO_L20N_7

IO_L20P_7

IO_L21N_7

IO_L21P_7

IO_L22N_7

IO_L22P_7

IO_L23N_7

IO_L23P_7

IO_L24N_7

IO_L24P_7

IO_L26N_7

IO_L26P_7

IO_L27N_7

IO_L19P_7

IO_L20N_7

IO_L20P_7

IO_L21N_7

IO_L21P_7

IO_L22N_7

IO_L22P_7

IO_L23N_7

IO_L23P_7

IO_L24N_7

IO_L24P_7

IO_L26N_7

IO_L26P_7

IO_L27N_7

IO_L19P_7

IO_L20N_7

IO_L20P_7

IO_L21N_7

IO_L21P_7

IO_L22N_7

IO_L22P_7

IO_L23N_7

IO_L23P_7

IO_L24N_7

IO_L24P_7

IO_L26N_7

IO_L26P_7

IO_L27N_7

H2

K7

J7

J4

J5

J2

J3

K5

K6

K3

K4

K1

K2

L7

L8

I/O

IO_L40P_6/ IO_L40P_6/ IO_L40P_6/

VREF

I/O

VREF_6

VCCO_6

VREF_6

VCCO_6

VREF_6

VCCO_6

6

7

P9

P10

R9

T3

VCCO

DCI

I/O

T9

I/O

U8

V8

Y3

F5

I/O

IO_L27P_7/ IO_L27P_7/ IO_L27P_7/

VREF_7

VREF

VREF_7

7

IO_L28N_7

IO_L28P_7

IO_L29N_7

IO_L29P_7

IO_L31N_7

IO_L31P_7

IO_L32N_7

IO_L32P_7

IO_L33N_7

IO_L33P_7

IO_L34N_7

IO_L34P_7

IO_L35N_7

IO_L35P_7

IO_L38N_7

IO_L38P_7

IO_L39N_7

IO_L39P_7

IO_L28N_7

IO_L28P_7

IO_L29N_7

IO_L29P_7

IO_L31N_7

IO_L31P_7

IO_L32N_7

IO_L32P_7

IO_L33N_7

IO_L33P_7

IO_L34N_7

IO_L34P_7

IO_L35N_7

IO_L35P_7

IO_L38N_7

IO_L38P_7

IO_L39N_7

IO_L39P_7

IO_L28N_7

IO_L28P_7

IO_L29N_7

IO_L29P_7

IO_L31N_7

IO_L31P_7

IO_L32N_7

IO_L32P_7

IO_L33N_7

IO_L33P_7

IO_L34N_7

IO_L34P_7

IO_L35N_7

IO_L35P_7

IO_L38N_7

IO_L38P_7

IO_L39N_7

IO_L39P_7

L5

L6

I/O

VREF

IO_L01N_7/ IO_L01N_7/ IO_L01N_7/

VRP_7 VRP_7 VRP_7

IO_L01P_7/ IO_L01P_7/ IO_L01P_7/

7

F6

L1

DCI

VRN_7

L2

7

IO_L02N_7

IO_L02P_7

IO_L02N_7

IO_L02P_7

IO_L02N_7

IO_L02P_7

E3

E4

D1

I/O

M7

M8

M6

M5

M3

L4

IO_L03N_7/ IO_L03N_7/ IO_L03N_7/

VREF

VREF_7

IO_L03P_7

N.C. ()

VREF_7

7

IO_L03P_7

IO_L05N_7

IO_L05P_7

IO_L06N_7

IO_L06P_7

IO_L07N_7

IO_L07P_7

IO_L08N_7

IO_L08P_7

IO_L09N_7

IO_L09P_7

IO_L10N_7

IO_L03P_7

IO_L05N_7

IO_L05P_7

IO_L06N_7

IO_L06P_7

IO_L07N_7

IO_L07P_7

IO_L08N_7

IO_L08P_7

IO_L09N_7

IO_L09P_7

IO_L10N_7

D2

G6

G7

E1

E2

F3

F4

G4

G5

F1

F2

H6

H7

I/O

M1

M2

N7

N8

N5

N6

N3

N4

N1

I/O

IO_L40N_7/ IO_L40N_7/ IO_L40N_7/

VREF_7

I/O

VREF_7

IO_L10P_7/ IO_L10P_7/

VREF_7

VREF

7

IO_L40P_7

VCCO_7

IO_L40P_7

VCCO_7

IO_L40P_7

VCCO_7

N2

G3

J8

I/O

VREF_7

VCCO

7

IO_L14N_7

IO_L14P_7

IO_L16N_7

IO_L14N_7

IO_L14P_7

IO_L16N_7

IO_L14N_7

IO_L14P_7

IO_L16N_7

G1

G2

J6

I/O

K8

64

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Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 30: FG676 Package Pinout (Continued)

FG676

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

Type

VCCO

GND

Type

GND

7

VCCO_7

GND

VCCO_7

GND

L3

L9

N/A GND

N/A VCCAUX

GND

M17

M23

N11

N12

N13

N14

N15

N16

P11

P12

P13

P14

P15

P16

R4

GND

M9

GND

N9

GND

N10

A1

GND

N/A GND

GND

A26

AC4

AC12

AC15

AC23

AD3

AD24

AE2

AE25

AF1

AF26

B2

GND

R10

R11

R12

R13

R14

R15

R16

R17

R23

T10

T11

T12

T13

T14

T15

T16

T17

U11

U12

U15

U16

A2

GND

B25

C3

GND

C24

D4

GND

D12

D15

D23

K11

K12

K15

K16

L10

L11

L12

L13

L14

L15

L16

L17

M4

GND

VCCAUX

A9

M10

M11

M12

M13

M14

M15

M16

A18

A25

AE1

AE26

AF2

AF9

AF18

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

65

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 30: FG676 Package Pinout (Continued)

FG676

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

XC3S1000

Bank Pin Name

XC3S1500

Pin Name

XC3S2000

Pin Name Number

Type

N/A VCCAUX

N/A VCCINT

VCCAUX

VCCINT

CCLK

VCCAUX

VCCINT

CCLK

AF25

B1

VCC DONE

AUX

DONE

AC24

C2

VCCAUX

VCCINT

CONFIG

JTAG

VCC HSWAP_EN HSWAP_EN HSWAP_EN

AUX

B26

J1

VCC M0

AUX

M0

AE3

AC3

AF3

D3

J26

V1

VCC M1

AUX

M1

V26

H8

VCC M2

AUX

M2

H19

J9

VCC PROG_B

AUX

PROG_B

TCK

TDI

PROG_B

TCK

TDI

VCC TCK

AUX

B24

C1

J10

J17

J18

K9

VCC TDI

AUX

JTAG

VCC TDO

AUX

TDO

TMS

TDO

TMS

D24

A24

JTAG

K10

K17

K18

U9

VCC TMS

AUX

JTAG

User I/Os by Bank

U10

U17

U18

V9

Table 31 indicates how the available user-I/O pins are dis-

tributed between the eight I/O banks for the XC3S1000 in

the FG676 package. Similarly, Table 32 shows how the

available user-I/O pins are distributed between the eight I/O

banks for the XC3S1500 in the FG676 package. Finally,

Table 33 shows the same information for the XC3S2000 in

the FG676 package.

V10

V17

V18

W8

W19

AD26

VCC CCLK

AUX

Table 31: User I/Os Per Bank for XC3S1000 in FG676 Package

All Possible I/O Pins by Type

I/O

Bank

Maximum

I/O

Edge

I/O

40

41

35

41

DUAL

DCI

2

VREF

GCLK

0

1

2

3

4

5

6

7

49

50

48

50

48

0

6

0

5

2

0

2

0

Top

2

Right

Bottom

Left

2

66

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DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

All Possible I/O Pins by Type

Table 32: User I/Os Per Bank for XC3S1500 in FG676 Package

I/O

Bank

Maximum

I/O

Edge

I/O

52

51

52

47

45

52

DUAL

DCI

2

VREF

GCLK

0

1

2

3

4

5

6

7

62

61

60

63

61

60

0

6

0

6

2

0

2

0

Top

2

Right

Bottom

Left

2

Table 33: User I/Os Per Bank for XC3S2000 in FG676 Package

All Possible I/O Pins by Type

Maximum

Edge

I/O Bank

I/O

62

61

60

63

61

60

I/O

52

51

53

52

47

45

53

52

DUAL

DCI

2

VREF

GCLK

0

1

2

3

4

5

6

7

0

6

0

6

2

0

2

0

Top

2

Right

Bottom

Left

2

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

67

R

Spartan-3 FPGA Family: Pinout Descriptions

FG676 Footprint

Bank 0

8

1

2

3

4

I/O

L05P_0

VREF_0

5

6

7

9

VCCAUX

I/O

10

11

12

13

I/O

L32P_0

GCLK6

I/O

Left Half of Package

(top view)

I/O

L26P_0

VREF_0

I/O

L10P_0

I/O

L15P_0

I/O

L29P_0

L23P_0

VCCAUX

GND

I/O

A

B

C

D

E

F

I/O

L32N_0

GCLK7

I/O

L29N_0

L18P_0 L23N_0 L26N_0

XC3S1000

GND

VCCAUX

TD I

VREF_0 L05N_0 L06P_0 L08P_0 L10N_0 L15N_0

(391 max. user I/O)

I/O: Unrestricted,

I/O

L18N_0

I/O

L31P_0

VREF_0

I/O

HSWAP_

EN

I/O

L22P_0

GND

VCCO_0

I/O

VCCO_0

I/O

315

L06N_0 L08N_0

general-purpose user I/O

I/O

L03N_7

VREF_7

I/O

L03P_7

I/O

L31N_0

L12P_0 L17P_0

VREF: User I/O or input

voltage reference for bank

PROG_B

I/O

GND

I/O

GND

I/O

L01P_0

L07P_0 L09P_0

L22N_0 L25P_0

40

VRN_0

I/O

L01N_0

VRP_0

I/O

L19P_0

I/O

L06N_7 L06P_7

L12N_0 L17N_0

I/O

L02N_7 L02P_7

L07N_0 L09N_0

L25N_0 L28P_0

N.C.: Unconnected pins for

XC3S1000 ()

98

I/O

I/O I/O

I/O

L11P_0

I/O

L09N_7 L09P_7 L07N_7 L07P_7

L01N_7 L01P_7

VRP_7

VREF_0

L16P_0 L19N_0 L24P_0 L28N_0 L30P_0

VRN_7

XC3S1500

I/O

L16N_0

I/O

VREF_0

I/O

(487 max user I/O)

I/O: Unrestricted,

L08N_7 L08P_7 L05N_7 L05P_7 L11N_0

VCCO_7

G

H

J

L14N_7 L14P_7

L24N_0 L27N_0 L30N_0

I/O

L10P_7

VREF_7

403

I/O

L10N_7

general-purpose user I/O

I/O

L16P_7

VREF_7

I/O

L27P_0

VCCO_0 VCCO_0

VCCINT VCCINT

VCCINT

I/O

L19N_7

L19P_7 L17N_7 L17P_7

VREF_7

VREF: User I/O or input

voltage reference for bank

48

I/O

VCCAUX

VCCO_7

VCCO_0 VCCO_0 VCCO_0

L22N_7 L22P_7 L21N_7 L21P_7 L16N_7 L20P_7

N.C.: Unconnected pins for

XC3S1500 ()

I/O

2

VCCO_0

K

L

GND

L26N_7 L26P_7 L24N_7 L24P_7 L23N_7 L23P_7 L20N_7

I/O

L27P_7

VREF_7

I/O

XC3S2000

VCCO_7

GND

L29N_7 L29P_7

L33P_7 L28N_7 L28P_7 L27N_7

(489 max user I/O)

I/O: Unrestricted,

I/O

VCCO_7

GND

I/O

M

N

P

R

T

GND

405

L34N_7 L34P_7 L33N_7

L32P_7 L32N_7 L31N_7 L31P_7

general-purpose user I/O

I/O

L40N_7

VREF_7

I/O

VREF: User I/O or input

voltage reference for bank

VCCO_7 VCCO_7

VCCO_6 VCCO_6

L40P_7 L39N_7 L39P_7 L38N_7 L38P_7 L35N_7 L35P_7

48

I/O

L40P_6

VREF_6

I/O

L35N_6

GND

L40N_6 L39P_6 L39N_6 L38P_6 L38N_6 L35P_6

N.C.: No unconnected pins

0

I/O

L34N_6

VREF_6

I/O

L34P_6

I/O

L33P_6

I/O

L31N_6

VCCO_6

GND

I/O

L32P_6 L32N_6 L31P_6

All devices

DUAL: Configuration pin,

then possible user I/O

I/O

L27N_6

VCCO_6

GND

12

L29P_6 L29N_6

L33N_6 L28P_6 L28N_6 L27P_6

I/O

L24N_6

VREF_6

I/O

VCCO_6

VCCINT

I/O

VCCO_5

VCCINT VCCINT

VCCO_5 VCCO_5

U

V

W

Y

GCLK: User I/O or global

clock buffer input

L26P_6 L26N_6 L24P_6

L23P_6 L23N_6 L20P_6

8

I/O

VCCAUX

VCCO_5 VCCO_5 VCCO_5

L22P_6 L22N_6 L21P_6 L21N_6 L16N_6 L20N_6

DCI: User I/O or reference

resistor input for bank

16

I/O

L17P_6

VREF_6

I/O

L19P_6 L19N_6

L17N_6 L16P_6 L14P_6 L14N_6

L24P_5 L27P_5 L30P_5

CONFIG: Dedicated

configuration pins

I/O

7

I/O

L16P_5

I/O

L27N_5

VREF_5

I/O

L24N_5

I/O

L30N_5

L10P_6 L10N_6

L08P_6 L08N_6 L06P_6 L06N_6

VCCO_6

I/O

L19P_5

VREF_5

I/O

L09N_6

VREF_6

I/O

L09P_6

I/O

L11P_5

JTAG: Dedicated JTAG

port pins

I/O

L28P_5

D7

I/O

A

I/O

L05P_5

I/O

L07P_6 L07N_6

4

I/O

L16N_5 L19N_5 L25P_5

I/O

L01P_5

CS_B

I/O

A

B

L11N_5

VREF_5

I/O

L22P_5

I/O

L25N_5

VCCINT: Internal core

voltage supply (+1.2V)

L05P_6 L05N_6

I/O

L28N_5 L31P_5

D6

L02P_6 L02N_6

L05N_5 L09P_5

20

D5

I/O

L12P_5

I/O

L03N_6

VREF_6

I/O

L01N_5

RDWR_B

I/O

L31N_5

D4

I/O

A

C

I/O

L03P_6

I/O

L22N_5

M1

GND

M0

GND

I/O

GND

VCCO: Output voltage

supply for bank

L07P_5 L09N_5

64

I/O

L32P_5

GCLK2

A

D

I/O

L12N_5 L18P_5

VCCO_5

I/O

L01P_6 L01N_6

VRN_6

L04P_5 L06P_5 L07N_5

VRP_6

VCCAUX: Auxiliary voltage

supply (+2.5V)

16

I/O

L10P_5

VRN_5

I/O

A

E

I/O

L15P_5

L18N_5 L23P_5 L26P_5

VCCAUX

GND

L29P_5 L32N_5

VREF_5 GCLK3

L04N_5 L06N_5 L08P_5

GND: Ground

I/O

76

I/O

L10N_5

VRP_5

A

F

I/O

L15N_5

I/O

L23N_5 L26N_5

VCCAUX

M2

I/O

GND

VCCAUX

VREF_5 L08N_5

L29N_5 VREF_5

Bank 5

DS099-4_12a_030203

Figure 14: FG676 Package Footprint (top view)

68

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DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Bank 1

14

15

16

17

18

VCCAUX

I/O

19

20

I/O

L10N_1

VREF_1

21

22

23

24

25

26

Right Half of Package

(top view)

I/O

L29N_1

I/O

L15N_1

I/O

L08N_1

L26N_1 L23N_1

GND

VCCAUX

I/O

TMS

A

B

C

D

E

F

I/O

L32N_1

GCLK5

I/O

L06N_1

VREF_1

I/O

L29P_1

I/O

L04N_1

L26P_1 L23P_1 L18N_1

VCCAUX

I/O

TCK

GND

I/O

L01N_2 L01P_2

VRP_2

L15P_1 L10P_1 L08P_1

I/O

L32P_1

GCLK4

I/O

VREF_1

I/O

VREF_1

I/O

L07N_1

I/O

L18P_1 L12N_1

VCCO_1

GND

L06P_1 L04P_1

VRN_2

I/O

L31N_1

VREF_1

I/O

L01N_1

VRP_1

I/O

L03N_2

VREF_2

I/O

L22N_1

I/O

L03P_2

VREF_1 L12P_1

GND

I/O

GND

TDO

I/O

L09N_1 L07P_1

I/O

L11N_1

I/O

L22P_1

I/O

L05N_2 L05P_2

I/O

L01P_1

L31P_1 L28N_1 L25N_1

L09P_1 L05N_1

L02N_2 L02P_2

VRN_1

I/O

L11P_1

I/O

L09P_2

I/O

L09N_2

VREF_2

I/O

L07N_2 L07P_2

I/O

L28P_1 L25P_1 L19N_1 L16N_1

L05P_1

I/O

L06N_2 L06P_2 L08N_2 L08P_2

L10N_2 L10P_2

VCCO_2

I/O

G

H

J

L30N_1 L27N_1 L24N_1 L19P_1 L16P_1

I/O

L17P_2

VREF_2

I/O

VCCO_1 VCCO_1

VCCINT VCCINT

VCCINT

VCCO_2

L30P_1 L27P_1 L24P_1

L14N_2 L14P_2 L16N_2 L17N_2

L19N_2 L19P_2

I/O

L22N_2

I/O

L22P_2

VCCO_1 VCCO_1 VCCO_1

VCCAUX

L20N_2 L16P_2 L21N_2 L21P_2

I/O

L23N_2

VREF_2

I/O

L20P_2

I/O

VCCO_1

GND

VCCO_2

I/O

GND

K

L

L23P_2 L24N_2 L24P_2 L26N_2 L26P_2

I/O

GND

VCCO_2

L27N_2 L27P_2 L28N_2

L28P_2 L33N_2

L29N_2 L29P_2

I/O

L32P_2

I/O

L33P_2

I/O

GND

L34N_2

L34P_2

VREF_2

M

N

P

R

T

L31N_2 L31P_2 L32N_2

I/O

GND

VCCO_2 VCCO_2

VCCO_3 VCCO_3

L40P_2

VREF_2

L35N_2 L35P_2 L38N_2

L38P_2 L39N_2 L39P_2 L40N_2

I/O

L40N_3

VREF_3

I/O

L39N_3

I/O

L40P_3

GND

L35P_3 L35N_3 L38P_3 L38N_3 L39P_3

I/O

L34P_3

VREF_3

I/O

L33N_3

I/O

L34N_3

VCCO_3

GND

I/O

L31P_3 L31N_3 L32P_3 L32N_3

I/O

L29P_3

I/O

L29N_3

VCCO_3

GND

VCCO_3

GND

L27P_3 L27N_3 L28P_3 L28N_3 L33P_3

I/O

L23P_3

VREF_3

I/O

L20N_3

I/O

L24N_3

I/O

L26P_3

I/O

L26N_3

VCCO_4

VCCO_3

VCCINT VCCINT

VCCO_4 VCCO_4

U

V

W

Y

L23N_3 L24P_3

I/O

VCCO_4 VCCO_4 VCCO_4

I/O

L27P_4

D1

VCCAUX

L20P_3 L16N_3

L21P_3 L21N_3 L22P_3 L22N_3

I/O

L17P_3

VREF_3

I/O

L16P_3

I/O

L17N_3

I/O

L19P_3

I/O

L19N_3

L10P_3 L10N_3

I/O

VCCINT

I/O

L27N_4

DIN

I/O

L30N_4

D2

I/O

L14P_3

I/O

L14N_3

L11N_4 L05P_3 L05N_3

L08P_3 L08N_3

VCCO_3

I/O

L24N_4 VREF_4 L16N_4

D0

I/O

L11P_4

I/O

L09N_3

I/O

L30P_4

D3

I/O

A

L09P_3

VREF_3

I/O

L07P_3 L07N_3

I/O

L01P_3 L01N_3

VRN_3

L28N_4 L24P_4 L19P_4 L16P_4

VRP_3

I/O

L01N_4

VRP_4

I/O

L02N_3

VREF_3

A

B

IO

VREF_4

I/O

L02P_3

L17N_4 L12N_4

L06P_3 L06N_3

L28P_4 L25N_4 L22P_4

L09N_4 L07N_4

I/O

L31N_4

INIT_B

I/O

L01P_4

VRN_4

A

C

I/O

L03P_3

I/O

L03N_3

L17P_4 L12P_4

GND

I/O

GND

DONE

L25P_4 L19N_4

L09P_4 L07P_4

I/O

L18N_4

I/O

L06N_4

VREF_4

I/O

A

D

I/O

L08N_4

I/O

VREF_4

L31P_4

DOUT

BUSY

VCCO_4

L22N_4

VCCO_4

GND

I/O

CCLK

VREF_4

I/O

L32N_4

GCLK1

A

E

I/O

L29N_4

I/O

L26N_4 L23N_4 L18P_4

VCCAUX

GND

L15N_4 L10N_4 L08P_4 L06P_4 L05N_4 L04N_4

I/O

L23P_4

I/O

L32P_4

GCLK0

A

F

L26P_4

VREF_4

I/O

L29P_4

I/O

L05P_4

I/O

L04P_4

VCCAUX

I/O

GND

L15P_4 L10P_4

Bank 4

DS099-4_12b_121103

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

69

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 34: FG900 Package Pinout (Continued)

FG900: 900-lead Fine-pitch Ball Grid

Array

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S2000

Pin Name

The 900-lead fine-pitch ball grid array package, FG900,

supports three different Spartan-3 devices, including the

XC3S2000, the XC3S4000, and the XC3S5000. The foot-

prints for the XC3S4000 and XC3S5000 are identical, as

shown in Table 34 and Figure 15. The XC3S2000, however,

has fewer I/O pins which consequently results in 68 uncon-

nected pins on the FG900 package, labeled as “N.C.” In

Table 34 and Figure 15, these unconnected pins are indi-

cated with a black diamond symbol ().

Bank

0

Type

I/O

VREF

IO_L07P_0

IO_L08N_0

IO_L08P_0

IO_L09N_0

IO_L09P_0

IO_L10N_0

IO_L10P_0

IO_L11N_0

IO_L11P_0

IO_L12N_0

IO_L12P_0

IO_L13N_0

IO_L13P_0

IO_L14N_0

IO_L14P_0

IO_L15N_0

IO_L15P_0

IO_L16N_0

IO_L16P_0

IO_L17N_0

IO_L17P_0

IO_L18N_0

IO_L18P_0

IO_L19N_0

IO_L19P_0

IO_L20N_0

IO_L20P_0

IO_L21N_0

IO_L21P_0

IO_L22N_0

IO_L22P_0

IO_L23N_0

IO_L23P_0

IO_L24N_0

IO_L24P_0

IO_L25N_0

IO_L25P_0

IO_L26N_0

IO_L07P_0

IO_L08N_0

IO_L08P_0

IO_L09N_0

IO_L09P_0

IO_L10N_0

IO_L10P_0

IO_L11N_0

IO_L11P_0

IO_L12N_0

IO_L12P_0

IO_L13N_0

IO_L13P_0

IO_L14N_0

IO_L14P_0

IO_L15N_0

IO_L15P_0

IO_L16N_0

IO_L16P_0

IO_L17N_0

IO_L17P_0

IO_L18N_0

IO_L18P_0

IO_L19N_0

IO_L19P_0

IO_L20N_0

IO_L20P_0

IO_L21N_0

IO_L21P_0

IO_L22N_0

IO_L22P_0

IO_L23N_0

IO_L23P_0

IO_L24N_0

IO_L24P_0

IO_L25N_0

IO_L25P_0

IO_L26N_0

E8

D8

C8

B8

A8

J9

H9

All the package pins appear in Table 34 and are sorted by

bank number, then by pin name. Pairs of pins that form a dif-

ferential I/O pair appear together in the table. The table also

shows the pin number for each pin and the pin type, as

defined earlier.

G10

F10

C10

B10

J10

K11

H11

G11

F11

E11

D11

C11

B11

A11

K12

J12

H12

G12

F12

E12

D12

C12

B12

A12

J13

H13

F13

E13

B13

A13

K14

J14

If there is a difference between the XC3S2000 pinout and

the pinout for the XC3S4000 and XC3S5000, then that dif-

ference is highlighted in Table 34. If the table entry is

shaded, then there is an unconnected pin on the XC3S2000

that maps to a user-I/O pin on the XC3S4000 and

XC3S5000.

Pinout Table

Table 34: FG900 Package Pinout

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S2000

Pin Name

Bank

Type

I/O

0

IO

E15

K15

D13

K13

G8

IO

I/O

IO

I/O

IO

I/O

IO

I/O

IO/VREF_0

F9

VREF

DCI

C4

IO_L01N_0/

VRP_0

IO_L01N_0/

VRP_0

B4

0

IO_L01P_0/

VRN_0

IO_L01P_0/

VRN_0

A4

DCI

0

IO_L02N_0

IO_L02P_0

IO_L03N_0

IO_L03P_0

IO_L04N_0

IO_L04P_0

IO_L05N_0

IO_L02N_0

IO_L02P_0

IO_L03N_0

IO_L03P_0

IO_L04N_0

IO_L04P_0

IO_L05N_0

B5

A5

D5

E6

C6

B6

F6

F7

I/O

IO_L26P_0/

VREF_0

IO_L26P_0/

VREF_0

I/O

IO_L05P_0/

VREF_0

IO_L05P_0/

VREF_0

VREF

0

IO_L27N_0

IO_L27P_0

IO_L28N_0

IO_L28P_0

IO_L29N_0

IO_L27N_0

IO_L27P_0

IO_L28N_0

IO_L28P_0

IO_L29N_0

G14

F14

C14

B14

J15

I/O

0

IO_L06N_0

IO_L06P_0

IO_L07N_0

IO_L06N_0

IO_L06P_0

IO_L07N_0

D7

C7

F8

I/O

70

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DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 34: FG900 Package Pinout (Continued)

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S2000

Pin Name

XC3S2000

Pin Name

Bank

Type

I/O

Bank

Type

I/O

0

IO_L29P_0

IO_L30N_0

IO_L30P_0

IO_L31N_0

IO_L29P_0

IO_L30N_0

IO_L30P_0

IO_L31N_0

H15

G15

F15

D15

C15

1

IO_L05P_1

F25

C24

I/O

IO_L06N_1/

VREF_1

IO_L06N_1/

VREF_1

VREF

I/O

1

IO_L06P_1

IO_L07N_1

IO_L07P_1

IO_L08N_1

IO_L08P_1

IO_L09N_1

IO_L09P_1

IO_L06P_1

IO_L07N_1

IO_L07P_1

IO_L08N_1

IO_L08P_1

IO_L09N_1

IO_L09P_1

D24

A24

B24

H23

G24

F23

G23

C23

I/O

IO_L31P_0/

VREF_0

IO_L31P_0/

VREF_0

VREF

I/O

0

IO_L32N_0/

GCLK7

IO_L32N_0/

GCLK7

B15

A15

GCLK

I/O

IO_L32P_0/

GCLK6

IO_L32P_0/

GCLK6

I/O

0

1

N.C. ()

VCCO_0

IO

IO_L35N_0

IO_L35P_0

IO_L36N_0

IO_L36P_0

IO_L37N_0

IO_L37P_0

IO_L38N_0

IO_L38P_0

VCCO_0

IO

B7

A7

I/O

IO_L10N_1/

VREF_1

IO_L10N_1/

VREF_1

VREF

G7

I/O

1

IO_L10P_1

IO_L11N_1

IO_L11P_1

IO_L12N_1

IO_L12P_1

IO_L13N_1

IO_L13P_1

IO_L14N_1

IO_L14P_1

IO_L15N_1

IO_L15P_1

IO_L16N_1

IO_L16P_1

IO_L10P_1

IO_L11N_1

IO_L11P_1

IO_L12N_1

IO_L12P_1

IO_L13N_1

IO_L13P_1

IO_L14N_1

IO_L14P_1

IO_L15N_1

IO_L15P_1

IO_L16N_1

IO_L16P_1

D23

A23

B23

H22

J22

I/O

H8

I/O

E9

I/O

D9

I/O

B9

I/O

A9

I/O

F22

E23

D22

E22

A22

B22

F21

G21

B21

I/O

C5

VCCO

I/O

E7

I/O

C9

I/O

G9

I/O

J11

L12

C13

G13

L13

L14

E25

J21

K20

F18

F16

A16

J17

A27

I/O

IO_L17N_1/

VREF_1

IO_L17N_1/

VREF_1

VREF

1

IO_L17P_1

IO_L18N_1

IO_L18P_1

IO_L19N_1

IO_L19P_1

IO_L20N_1

IO_L20P_1

IO_L21N_1

IO_L21P_1

IO_L22N_1

IO_L22P_1

IO_L23N_1

IO_L23P_1

IO_L24N_1

IO_L24P_1

IO_L25N_1

IO_L25P_1

IO_L26N_1

IO_L17P_1

IO_L18N_1

IO_L18P_1

IO_L19N_1

IO_L19P_1

IO_L20N_1

IO_L20P_1

IO_L21N_1

IO_L21P_1

IO_L22N_1

IO_L22P_1

IO_L23N_1

IO_L23P_1

IO_L24N_1

IO_L24P_1

IO_L25N_1

IO_L25P_1

IO_L26N_1

C21

G20

H20

E20

F20

C20

D20

A20

B20

J19

I/O

IO

I/O

IO

I/O

IO

I/O

IO

I/O

IO

I/O

IO/VREF_1

VREF

DCI

IO_L01N_1/

VRP_1

IO_L01N_1/

VRP_1

1

IO_L01P_1/

VRN_1

IO_L01P_1/

VRN_1

B27

DCI

K19

G19

H19

E19

F19

C19

D19

A19

1

IO_L02N_1

IO_L02P_1

IO_L03N_1

IO_L03P_1

IO_L04N_1

IO_L04P_1

IO_L05N_1

IO_L02N_1

IO_L02P_1

IO_L03N_1

IO_L03P_1

IO_L04N_1

IO_L04P_1

IO_L05N_1

D26

C27

A26

B26

B25

C25

F24

I/O

DS099-4 (v1.5) July 13, 2004

Product Specification

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1-800-255-7778

71

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 34: FG900 Package Pinout (Continued)

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S2000

Pin Name

XC3S2000

Pin Name

Bank

Type

I/O

Bank

Type

I/O

1

IO_L26P_1

IO_L27N_1

IO_L27P_1

IO_L28N_1

IO_L28P_1

IO_L29N_1

IO_L29P_1

IO_L30N_1

IO_L30P_1

IO_L26P_1

IO_L27N_1

IO_L27P_1

IO_L28N_1

IO_L28P_1

IO_L29N_1

IO_L29P_1

IO_L30N_1

IO_L30P_1

B19

F17

G17

B17

C17

J16

2

IO_L05N_2

IO_L05P_2

IO_L06N_2

IO_L06P_2

IO_L07N_2

IO_L07P_2

IO_L08N_2

IO_L08P_2

IO_L05N_2

IO_L05P_2

IO_L06N_2

IO_L06P_2

IO_L07N_2

IO_L07P_2

IO_L08N_2

IO_L08P_2

F28

F29

G27

G28

G29

G30

G25

H24

H25

I/O

K16

G16

H16

D16

I/O

IO_L09N_2/

VREF_2

IO_L09N_2/

VREF_2

VREF

IO_L31N_1/

VREF_1

IO_L31N_1/

VREF_1

VREF

2

IO_L09P_2

IO_L10N_2

IO_L10P_2

IO_L12N_2

IO_L12P_2

IO_L13N_2

IO_L09P_2

IO_L10N_2

IO_L10P_2

IO_L12N_2

IO_L12P_2

IO_L13N_2

H26

H27

H28

H29

H30

J26

I/O

1

IO_L31P_1

E16

B16

I/O

IO_L32N_1/

GCLK5

IO_L32N_1/

GCLK5

GCLK

I/O

1

IO_L32P_1/

GCLK4

IO_L32P_1/

GCLK4

C16

GCLK

I/O

1

2

N.C. ()

VCCO_1

IO

IO_L37N_1

IO_L37P_1

IO_L38N_1

IO_L38P_1

IO_L39N_1

IO_L39P_1

IO_L40N_1

IO_L40P_1

VCCO_1

IO

H18

J18

D18

E18

A18

B18

K17

K18

L17

C18

G18

L18

L19

J20

C22

G22

E24

C26

J25

C29

I/O

IO_L13P_2/

VREF_2

IO_L13P_2/

VREF_2

J27

VREF

I/O

2

IO_L14N_2

IO_L14P_2

IO_L15N_2

IO_L15P_2

IO_L16N_2

IO_L16P_2

IO_L19N_2

IO_L19P_2

IO_L20N_2

IO_L20P_2

IO_L21N_2

IO_L21P_2

IO_L22N_2

IO_L22P_2

IO_L14N_2

IO_L14P_2

IO_L15N_2

IO_L15P_2

IO_L16N_2

IO_L16P_2

IO_L19N_2

IO_L19P_2

IO_L20N_2

IO_L20P_2

IO_L21N_2

IO_L21P_2

IO_L22N_2

IO_L22P_2

J29

J30

J23

K22

K24

K25

L25

L26

L27

L28

L29

L30

M22

M23

M24

I/O

VREF

I/O

VCCO

I/O

IO_L23N_2/

VREF_2

IO_L23N_2/

VREF_2

2

IO_L23P_2

IO_L24N_2

IO_L24P_2

IO_L26N_2

IO_L26P_2

IO_L27N_2

IO_L27P_2

IO_L28N_2

IO_L28P_2

IO_L29N_2

IO_L29P_2

IO_L23P_2

IO_L24N_2

IO_L24P_2

IO_L26N_2

IO_L26P_2

IO_L27N_2

IO_L27P_2

IO_L28N_2

IO_L28P_2

IO_L29N_2

IO_L29P_2

M25

M27

M28

M21

N21

N22

N23

M26

N25

N26

N27

I/O

IO_L01N_2/

VRP_2

IO_L01N_2/

VRP_2

DCI

2

IO_L01P_2/

VRN_2

IO_L01P_2/

VRN_2

C30

DCI

2

IO_L02N_2

IO_L02P_2

IO_L02N_2

IO_L02P_2

D27

D28

D29

I/O

IO_L03N_2/

VREF_2

IO_L03N_2/

VREF_2

VREF

2

IO_L03P_2

IO_L04N_2

IO_L04P_2

IO_L03P_2

IO_L04N_2

IO_L04P_2

D30

E29

E30

I/O

72

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DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 34: FG900 Package Pinout (Continued)

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S2000

Pin Name

XC3S2000

Pin Name

Bank

Type

I/O

Bank

Type

2

IO_L31N_2

IO_L31P_2

IO_L32N_2

IO_L32P_2

IO_L33N_2

IO_L33P_2

IO_L31N_2

IO_L31P_2

IO_L32N_2

IO_L32P_2

IO_L33N_2

IO_L33P_2

N29

N30

P21

P22

P24

P25

P28

3

IO_L02N_3/

VREF_3

IO_L02N_3/

VREF_3

AG28

VREF

I/O

3

IO_L02P_3

IO_L03N_3

IO_L03P_3

IO_L04N_3

IO_L04P_3

IO_L05N_3

IO_L05P_3

IO_L06N_3

IO_L06P_3

IO_L07N_3

IO_L07P_3

IO_L08N_3

IO_L08P_3

IO_L09N_3

IO_L02P_3

IO_L03N_3

IO_L03P_3

IO_L04N_3

IO_L04P_3

IO_L05N_3

IO_L05P_3

IO_L06N_3

IO_L06P_3

IO_L07N_3

IO_L07P_3

IO_L08N_3

IO_L08P_3

IO_L09N_3

AG27

AG30

AG29

AF30

AF29

AE26

AF27

AE29

AE28

AD28

AD27

AD30

AD29

AC24

AD25

I/O

VREF

I/O

IO_L34N_2/

VREF_2

IO_L34N_2/

VREF_2

VREF

2

IO_L34P_2

IO_L35N_2

IO_L35P_2

IO_L37N_2

IO_L37P_2

IO_L38N_2

IO_L38P_2

IO_L39N_2

IO_L39P_2

IO_L40N_2

IO_L34P_2

IO_L35N_2

IO_L35P_2

IO_L37N_2

IO_L37P_2

IO_L38N_2

IO_L38P_2

IO_L39N_2

IO_L39P_2

IO_L40N_2

P29

R21

R22

R23

R24

R25

R26

R27

R28

R29

R30

I/O

IO_L09P_3/

VREF_3

IO_L09P_3/

VREF_3

I/O

3

IO_L10N_3

IO_L10P_3

IO_L11N_3

IO_L11P_3

IO_L10N_3

IO_L10P_3

IO_L11N_3

IO_L11P_3

AC26

AC25

AC28

AC27

AC30

I/O

IO_L40P_2/

VREF_2

IO_L40P_2/

VREF_2

VREF

2

3

N.C. ()

VCCO_2

IO

IO_L41N_2

IO_L41P_2

IO_L45N_2

IO_L45P_2

IO_L46N_2

IO_L46P_2

IO_L47N_2

IO_L47P_2

IO_L50N_2

IO_L50P_2

VCCO_2

IO

E27

F26

K28

K29

K21

L21

I/O

IO_L13N_3/

VREF_3

IO_L13N_3/

VREF_3

VREF

I/O

3

IO_L13P_3

IO_L14N_3

IO_L14P_3

IO_L15N_3

IO_L15P_3

IO_L16N_3

IO_L16P_3

IO_L17N_3

IO_L13P_3

IO_L14N_3

IO_L14P_3

IO_L15N_3

IO_L15P_3

IO_L16N_3

IO_L16P_3

IO_L17N_3

AC29

AB27

AB26

AB30

AB29

AA22

AB23

AA25

AA24

I/O

L23

I/O

L24

I/O

M29

M30

M20

N20

P20

L22

I/O

VCCO

I/O

IO_L17P_3/

VREF_3

IO_L17P_3/

VREF_3

VREF

3

IO_L19N_3

IO_L19P_3

IO_L20N_3

IO_L20P_3

IO_L21N_3

IO_L21P_3

IO_L22N_3

IO_L22P_3

IO_L23N_3

IO_L19N_3

IO_L19P_3

IO_L20N_3

IO_L20P_3

IO_L21N_3

IO_L21P_3

IO_L22N_3

IO_L22P_3

IO_L23N_3

AA29

AA28

Y21

I/O

J24

N24

G26

E28

J28

I/O

AA21

Y24

I/O

Y23

I/O

N28

AB25

AH30

Y26

I/O

Y25

I/O

IO_L01N_3/

VRP_3

IO_L01N_3/

VRP_3

DCI

Y28

I/O

IO_L23P_3/

VREF_3

IO_L23P_3/

VREF_3

Y27

VREF

3

IO_L01P_3/

VRN_3

IO_L01P_3/

VRN_3

AH29

DCI

3

IO_L24N_3

Y30

I/O

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

73

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 34: FG900 Package Pinout (Continued)

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S2000

Pin Name

XC3S2000

Pin Name

Bank

Type

I/O

Bank

Type

VCCO

I/O

3

IO_L24P_3

IO_L26N_3

IO_L26P_3

IO_L27N_3

IO_L27P_3

IO_L28N_3

IO_L28P_3

IO_L29N_3

IO_L29P_3

IO_L31N_3

IO_L31P_3

IO_L32N_3

IO_L32P_3

IO_L33N_3

IO_L33P_3

IO_L34N_3

IO_L24P_3

IO_L26N_3

IO_L26P_3

IO_L27N_3

IO_L27P_3

IO_L28N_3

IO_L28P_3

IO_L29N_3

IO_L29P_3

IO_L31N_3

IO_L31P_3

IO_L32N_3

IO_L32P_3

IO_L33N_3

IO_L33P_3

IO_L34N_3

Y29

W30

W29

V21

W21

V23

V22

V25

W26

V30

V29

U22

U21

U25

U24

U29

U28

3

4

VCCO_3

AB28

AF28

AA16

AG18

AA18

AE22

AD23

AH27

AF16

AK28

AJ27

I/O

VCCO_3

I/O

IO

I/O

IO

I/O

IO

I/O

IO

I/O

IO

I/O

IO

I/O

IO/VREF_4

VREF

DCI

I/O

IO_L01N_4/

VRP_4

IO_L01N_4/

VRP_4

I/O

4

IO_L01P_4/

VRN_4

IO_L01P_4/

VRN_4

AK27

DCI

I/O

4

IO_L02N_4

IO_L02P_4

IO_L03N_4

IO_L03P_4

IO_L04N_4

IO_L04P_4

IO_L05N_4

IO_L05P_4

IO_L02N_4

IO_L02P_4

IO_L03N_4

IO_L03P_4

IO_L04N_4

IO_L04P_4

IO_L05N_4

IO_L05P_4

AJ26

AK26

AG26

AF25

AD24

AC23

AE23

AF23

AG23

I/O

IO_L34P_3/

VREF_3

IO_L34P_3/

VREF_3

VREF

I/O

3

IO_L35N_3

IO_L35P_3

IO_L37N_3

IO_L37P_3

IO_L38N_3

IO_L38P_3

IO_L39N_3

IO_L39P_3

IO_L35N_3

IO_L35P_3

IO_L37N_3

IO_L37P_3

IO_L38N_3

IO_L38P_3

IO_L39N_3

IO_L39P_3

T22

T21

T24

T23

T26

T25

T28

T27

T30

I/O

IO_L06N_4/

VREF_4

IO_L06N_4/

VREF_4

VREF

I/O

4

IO_L06P_4

IO_L07N_4

IO_L07P_4

IO_L08N_4

IO_L08P_4

IO_L09N_4

IO_L09P_4

IO_L10N_4

IO_L10P_4

IO_L11N_4

IO_L11P_4

IO_L12N_4

IO_L12P_4

IO_L13N_4

IO_L13P_4

IO_L14N_4

IO_L14P_4

IO_L15N_4

IO_L15P_4

IO_L16N_4

IO_L16P_4

IO_L06P_4

IO_L07N_4

IO_L07P_4

IO_L08N_4

IO_L08P_4

IO_L09N_4

IO_L09P_4

IO_L10N_4

IO_L10P_4

IO_L11N_4

IO_L11P_4

IO_L12N_4

IO_L12P_4

IO_L13N_4

IO_L13P_4

IO_L14N_4

IO_L14P_4

IO_L15N_4

IO_L15P_4

IO_L16N_4

IO_L16P_4

AH23

AJ23

AK23

AB22

AC22

AF22

AG22

AJ22

AK22

AD21

AE21

AH21

AJ21

AB21

AA20

AC20

AD20

AE20

AF20

AG20

AH20

I/O

IO_L40N_3/

VREF_3

IO_L40N_3/

VREF_3

VREF

3

IO_L40P_3

N.C. ()

VCCO_3

IO_L40P_3

IO_L46N_3

IO_L46P_3

IO_L47N_3

IO_L47P_3

IO_L48N_3

IO_L48P_3

IO_L50N_3

IO_L50P_3

VCCO_3

T29

W23

W22

W25

W24

W28

W27

V27

I/O

V26

I/O

U20

V20

VCCO

VCCO_3

W20

Y22

VCCO_3

V24

VCCO_3

AB24

AD26

V28

VCCO_3

74

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 34: FG900 Package Pinout (Continued)

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S2000

Pin Name

XC3S2000

Pin Name

Bank

Type

I/O

Bank

4

Type

I/O

4

IO_L17N_4

IO_L17P_4

IO_L18N_4

IO_L18P_4

IO_L19N_4

IO_L19P_4

IO_L20N_4

IO_L20P_4

IO_L21N_4

IO_L21P_4

IO_L17N_4

IO_L17P_4

IO_L18N_4

IO_L18P_4

IO_L19N_4

IO_L19P_4

IO_L20N_4

IO_L20P_4

IO_L21N_4

IO_L21P_4

AJ20

AK20

AA19

AB19

AC19

AD19

AE19

AF19

AG19

AH19

AJ19

N.C. ()

VCCO_4

IO

IO_L35P_4

IO_L38N_4

IO_L38P_4

VCCO_4

IO

AH24

AJ24

AK24

Y17

I/O

4

I/O

4

I/O

4

VCCO

I/O

4

Y18

I/O

4

AD18

AH18

Y19

I/O

4

I/O

4

I/O

4

AB20

AD22

AH22

AF24

AH26

AE6

I/O

4

IO_L22N_4/

VREF_4

IO_L22N_4/

VREF_4

VREF

4

IO_L22P_4

IO_L23N_4

IO_L23P_4

IO_L24N_4

IO_L24P_4

IO_L25N_4

IO_L25P_4

IO_L26N_4

IO_L22P_4

IO_L23N_4

IO_L23P_4

IO_L24N_4

IO_L24P_4

IO_L25N_4

IO_L25P_4

IO_L26N_4

AK19

AB18

AC18

AE18

AF18

AJ18

AK18

AA17

AB17

I/O

4

5

I/O

5

IO

AB10

AA11

AA15

AE15

AH4

I/O

5

IO

I/O

5

IO

I/O

5

IO

I/O

5

IO/VREF_5

VREF

DUAL

I/O

5

AK15

AK4

IO_L26P_4/

VREF_4

IO_L26P_4/

VREF_4

VREF

5

IO_L01N_5/

RDWR_B

IO_L01N_5/

RDWR_B

4

IO_L27N_4/

DIN/D0

IO_L27N_4/

DIN/D0

AD17

AE17

DUAL

5

IO_L01P_5/

CS_B

IO_L01P_5/

CS_B

AJ4

DUAL

IO_L27P_4/

D1

IO_L27P_4/

D1

5

IO_L02N_5

IO_L02P_5

IO_L03N_5

IO_L03P_5

IO_L04N_5

IO_L04P_5

IO_L05N_5

IO_L05P_5

IO_L06N_5

IO_L06P_5

IO_L07N_5

IO_L07P_5

IO_L08N_5

IO_L08P_5

IO_L09N_5

IO_L09P_5

IO_L02N_5

IO_L02P_5

IO_L03N_5

IO_L03P_5

IO_L04N_5

IO_L04P_5

IO_L05N_5

IO_L05P_5

IO_L06N_5

IO_L06P_5

IO_L07N_5

IO_L07P_5

IO_L08N_5

IO_L08P_5

IO_L09N_5

IO_L09P_5

AK5

AJ5

AF6

AG5

AJ6

AH6

AE7

AD7

AH7

AG7

AK8

AJ8

AC9

AB9

AG9

AF9

AK9

I/O

DCI

4

IO_L28N_4

IO_L28P_4

IO_L29N_4

IO_L29P_4

IO_L28N_4

IO_L28P_4

IO_L29N_4

IO_L29P_4

AH17

AJ17

AB16

AC16

AD16

I/O

IO_L30N_4/

D2

IO_L30N_4/

D2

DUAL

4

IO_L30P_4/

D3

IO_L30P_4/

D3

AE16

AG16

AH16

AJ16

AK16

DUAL

GCLK

IO_L31N_4/

INIT_B

IO_L31N_4/

INIT_B

IO_L31P_4/

DOUT/BUSY DOUT/BUSY

IO_L31P_4/

IO_L32N_4/

GCLK1

IO_L32N_4/

GCLK1

IO_L32P_4/

GCLK0

IO_L32P_4/

GCLK0

IO_L10N_5/

VRP_5

IO_L10N_5/

VRP_5

4

N.C. ()

IO_L33N_4

IO_L33P_4

IO_L34N_4

IO_L34P_4

IO_L35N_4

AH25

AJ25

AE25

AE24

AG24

I/O

5

IO_L10P_5/

VRN_5

IO_L10P_5/

VRN_5

AJ9

DCI

IO_L11N_5/

VREF_5

IO_L11N_5/

VREF_5

AE10

VREF

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

75

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 34: FG900 Package Pinout (Continued)

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S2000

Pin Name

XC3S2000

Pin Name

Bank

Type

I/O

Bank

Type

5

IO_L11P_5

IO_L12N_5

IO_L12P_5

IO_L13N_5

IO_L13P_5

IO_L14N_5

IO_L14P_5

IO_L15N_5

IO_L15P_5

IO_L16N_5

IO_L16P_5

IO_L17N_5

IO_L17P_5

IO_L18N_5

IO_L18P_5

IO_L19N_5

IO_L11P_5

IO_L12N_5

IO_L12P_5

IO_L13N_5

IO_L13P_5

IO_L14N_5

IO_L14P_5

IO_L15N_5

IO_L15P_5

IO_L16N_5

IO_L16P_5

IO_L17N_5

IO_L17P_5

IO_L18N_5

IO_L18P_5

IO_L19N_5

AE9

AJ10

AH10

AD11

AD10

AF11

AE11

AH11

AG11

AK11

AJ11

AB12

AC11

AD12

AC12

AF12

AE12

5

IO_L31P_5/

D5

IO_L31P_5/

D5

AF15

AJ15

AH15

DUAL

I/O

5

IO_L32N_5/

GCLK3

IO_L32N_5/

GCLK3

GCLK

I/O

IO_L32P_5/

GCLK2

IO_L32P_5/

GCLK2

I/O

5

6

N.C. ()

VCCO_5

IO

IO_L35N_5

IO_L35P_5

IO_L36N_5

IO_L36P_5

IO_L37N_5

IO_L37P_5

IO_L38N_5

IO_L38P_5

VCCO_5

IO

AK7

AJ7

I/O

AD8

AC8

AF8

AE8

AH8

AG8

AH5

AF7

AD9

AH9

AB11

Y12

I/O

VCCO

I/O

IO_L19P_5/

VREF_5

IO_L19P_5/

VREF_5

VREF

5

IO_L20N_5

IO_L20P_5

IO_L21N_5

IO_L21P_5

IO_L22N_5

IO_L22P_5

IO_L23N_5

IO_L23P_5

IO_L24N_5

IO_L24P_5

IO_L25N_5

IO_L25P_5

IO_L26N_5

IO_L26P_5

IO_L20N_5

IO_L20P_5

IO_L21N_5

IO_L21P_5

IO_L22N_5

IO_L22P_5

IO_L23N_5

IO_L23P_5

IO_L24N_5

IO_L24P_5

IO_L25N_5

IO_L25P_5

IO_L26N_5

IO_L26P_5

AH12

AG12

AK12

AJ12

AA13

AA12

AC13

AB13

AG13

AF13

AK13

AJ13

AB14

AA14

AE14

I/O

VREF

Y13

AD13

AH13

Y14

AB6

AH2

IO_L01N_6/

VRP_6

IO_L01N_6/

VRP_6

DCI

6

IO_L01P_6/

VRN_6

IO_L01P_6/

VRN_6

AH1

DCI

6

IO_L02N_6

IO_L02P_6

IO_L02N_6

IO_L02P_6

AG4

AG3

AG2

I/O

IO_L03N_6/

VREF_6

IO_L03N_6/

VREF_6

VREF

6

IO_L03P_6

IO_L04N_6

IO_L04P_6

IO_L05N_6

IO_L05P_6

IO_L06N_6

IO_L06P_6

IO_L07N_6

IO_L07P_6

IO_L08N_6

IO_L08P_6

IO_L03P_6

IO_L04N_6

IO_L04P_6

IO_L05N_6

IO_L05P_6

IO_L06N_6

IO_L06P_6

IO_L07N_6

IO_L07P_6

IO_L08N_6

IO_L08P_6

AG1

AF2

AF1

AF4

AE5

AE3

AE2

AD4

AD3

AD2

AD1

AD6

I/O

IO_L27N_5/

VREF_5

IO_L27N_5/

VREF_5

5

IO_L27P_5

AE13

AJ14

I/O

IO_L28N_5/

D6

IO_L28N_5/

D6

DUAL

I/O

5

IO_L28P_5/

D7

IO_L28P_5/

D7

AH14

DUAL

I/O

5

IO_L29N_5

AC15

AB15

I/O

IO_L29P_5/

VREF_5

IO_L29P_5/

VREF_5

VREF

I/O

5

IO_L30N_5

IO_L30P_5

IO_L30N_5

IO_L30P_5

AD15

AD14

AG15

I/O

IO_L09N_6/

VREF_6

IO_L09N_6/

VREF_6

VREF

IO_L31N_5/

D4

IO_L31N_5/

D4

DUAL

76

www.xilinx.com

1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 34: FG900 Package Pinout (Continued)

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S2000

Pin Name

XC3S2000

Pin Name

Bank

Type

I/O

Bank

Type

I/O

6

IO_L09P_6

IO_L10N_6

IO_L10P_6

IO_L11N_6

IO_L11P_6

IO_L13N_6

IO_L09P_6

IO_L10N_6

IO_L10P_6

IO_L11N_6

IO_L11P_6

IO_L13N_6

AC7

AC6

AC5

AC4

AC3

AC2

AC1

6

IO_L33P_6

V1

I/O

IO_L34N_6/

VREF_6

IO_L34N_6/

VREF_6

U10

VREF

I/O

6

IO_L34P_6

IO_L35N_6

IO_L35P_6

N.C. ()

IO_L34P_6

IO_L35N_6

IO_L35P_6

IO_L36N_6

IO_L36P_6

IO_L37N_6

IO_L37P_6

IO_L38N_6

IO_L38P_6

IO_L39N_6

IO_L39P_6

IO_L40N_6

U9

U7

U6

U3

U2

T10

T9

T6

T5

T4

T3

T2

T1

I/O

IO_L13P_6/

VREF_6

IO_L13P_6/

VREF_6

VREF

N.C. ()

I/O

6

IO_L14N_6

IO_L14P_6

IO_L15N_6

IO_L15P_6

IO_L16N_6

IO_L16P_6

IO_L17N_6

IO_L14N_6

IO_L14P_6

IO_L15N_6

IO_L15P_6

IO_L16N_6

IO_L16P_6

IO_L17N_6

AB5

AB4

AB2

AB1

AB8

AA9

AA7

AA6

I/O

IO_L37N_6

IO_L37P_6

IO_L38N_6

IO_L38P_6

IO_L39N_6

IO_L39P_6

IO_L40N_6

I/O

IO_L17P_6/

VREF_6

IO_L17P_6/

VREF_6

VREF

IO_L40P_6/

VREF_6

IO_L40P_6/

VREF_6

VREF

6

IO_L19N_6

IO_L19P_6

IO_L20N_6

IO_L20P_6

IO_L21N_6

IO_L21P_6

IO_L22N_6

IO_L22P_6

IO_L19N_6

IO_L19P_6

IO_L20N_6

IO_L20P_6

IO_L21N_6

IO_L21P_6

IO_L22N_6

IO_L22P_6

AA3

AA2

AA10

Y10

Y8

I/O

6

7

N.C. ()

VCCO_6

IO

IO_L45N_6

IO_L45P_6

IO_L52N_6

IO_L52P_6

VCCO_6

IO

Y4

Y3

I/O

T8

I/O

T7

I/O

V3

VCCO

I/O

Y7

I/O

AB3

AF3

AD5

V7

Y6

I/O

Y5

I/O

IO_L24N_6/

VREF_6

IO_L24N_6/

VREF_6

Y2

VREF

AB7

Y9

6

IO_L24P_6

N.C. ()

IO_L24P_6

IO_L25N_6

IO_L25P_6

IO_L26N_6

IO_L26P_6

IO_L27N_6

IO_L27P_6

IO_L28N_6

IO_L28P_6

IO_L29N_6

IO_L29P_6

IO_L30N_6

IO_L30P_6

IO_L31N_6

IO_L31P_6

IO_L32N_6

IO_L32P_6

IO_L33N_6

Y1

W9

W8

W7

W6

W4

W3

W2

W1

W10

V10

V9

I/O

U11

V11

W11

J6

N.C. ()

IO_L26N_6

IO_L26P_6

IO_L27N_6

IO_L27P_6

IO_L28N_6

IO_L28P_6

IO_L29N_6

IO_L29P_6

N.C. ()

IO_L01N_7/

VRP_7

IO_L01N_7/

VRP_7

C1

DCI

7

IO_L01P_7/

VRN_7

IO_L01P_7/

VRN_7

C2

DCI

7

IO_L02N_7

IO_L02P_7

IO_L02N_7

IO_L02P_7

D3

D4

D1

I/O

IO_L03N_7/

VREF_7

IO_L03N_7/

VREF_7

VREF

N.C. ()

V8

7

IO_L03P_7

IO_L04N_7

IO_L04P_7

IO_L05N_7

IO_L05P_7

IO_L06N_7

IO_L03P_7

IO_L04N_7

IO_L04P_7

IO_L05N_7

IO_L05P_7

IO_L06N_7

D2

E1

E2

F5

E4

F2

I/O

IO_L31N_6

IO_L31P_6

IO_L32N_6

IO_L32P_6

IO_L33N_6

W5

V6

V5

V4

V2

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

77

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 34: FG900 Package Pinout (Continued)

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S2000

Pin Name

XC3S2000

Pin Name

Bank

Type

I/O

Bank

Type

I/O

7

IO_L06P_7

IO_L07N_7

IO_L07P_7

IO_L08N_7

IO_L08P_7

IO_L09N_7

IO_L09P_7

IO_L10N_7

IO_L06P_7

IO_L07N_7

IO_L07P_7

IO_L08N_7

IO_L08P_7

IO_L09N_7

IO_L09P_7

IO_L10N_7

F3

G3

G4

G1

G2

H7

G6

H5

H6

7

IO_L29P_7

IO_L31N_7

IO_L31P_7

IO_L32N_7

IO_L32P_7

IO_L33N_7

IO_L33P_7

IO_L34N_7

IO_L34P_7

IO_L35N_7

IO_L35P_7

IO_L37N_7

IO_L29P_7

IO_L31N_7

IO_L31P_7

IO_L32N_7

IO_L32P_7

IO_L33N_7

IO_L33P_7

IO_L34N_7

IO_L34P_7

IO_L35N_7

IO_L35P_7

IO_L37N_7

N9

N1

N2

P9

I/O

P10

P6

I/O

P7

I/O

P2

I/O

IO_L10P_7/

VREF_7

IO_L10P_7/

VREF_7

VREF

P3

I/O

R9

R10

R7

R8

I/O

7

IO_L11N_7

IO_L11P_7

IO_L13N_7

IO_L13P_7

IO_L14N_7

IO_L14P_7

IO_L15N_7

IO_L15P_7

IO_L16N_7

IO_L11N_7

IO_L11P_7

IO_L13N_7

IO_L13P_7

IO_L14N_7

IO_L14P_7

IO_L15N_7

IO_L15P_7

IO_L16N_7

H3

H4

H1

H2

J4

J5

J1

J2

K9

J8

I/O

IO_L37P_7/

VREF_7

IO_L37P_7/

VREF_7

VREF

I/O

7

IO_L38N_7

IO_L38P_7

IO_L39N_7

IO_L39P_7

IO_L38N_7

IO_L38P_7

IO_L39N_7

IO_L39P_7

R5

R6

R3

R4

R1

I/O

IO_L40N_7/

VREF_7

IO_L40N_7/

VREF_7

VREF

IO_L16P_7/

VREF_7

IO_L16P_7/

VREF_7

VREF

7

IO_L40P_7

N.C. ()

VCCO_7

GND

IO_L40P_7

IO_L46N_7

IO_L46P_7

IO_L49N_7

IO_L49P_7

IO_L50N_7

IO_L50P_7

VCCO_7

GND

R2

M8

M9

N6

M5

N4

N5

E3

I/O

7

IO_L17N_7

IO_L17P_7

IO_L17N_7

IO_L17P_7

K6

K7

K2

I/O

7

I/O

IO_L19N_7/

VREF_7

IO_L19N_7/

VREF_7

VREF

7

I/O

7

I/O

7

IO_L19P_7

IO_L20N_7

IO_L20P_7

IO_L21N_7

IO_L21P_7

IO_L22N_7

IO_L22P_7

IO_L23N_7

IO_L23P_7

IO_L24N_7

IO_L24P_7

N.C. ()

IO_L19P_7

IO_L20N_7

IO_L20P_7

IO_L21N_7

IO_L21P_7

IO_L22N_7

IO_L22P_7

IO_L23N_7

IO_L23P_7

IO_L24N_7

IO_L24P_7

IO_L25N_7

IO_L25P_7

IO_L26N_7

IO_L26P_7

IO_L27N_7

K3

L10

K10

L7

I/O

VREF

7

I/O

7

I/O

7

VCCO

GND

7

J3

L8

7

N3

G5

J7

L5

7

L6

7

L3

7

N7

L9

L4

7

L1

7

M11

N11

P11

A1

L2

7

M6

M7

M3

M4

M1

M2

7

N.C. ()

N/A

IO_L26N_7

IO_L26P_7

IO_L27N_7

GND

B1

GND

F1

GND

K1

IO_L27P_7/

VREF_7

IO_L27P_7/

VREF_7

GND

P1

GND

U1

AA1

AE1

7

IO_L28N_7

IO_L28P_7

IO_L29N_7

IO_L28N_7

IO_L28P_7

IO_L29N_7

N10

M10

N8

I/O

GND

78

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 34: FG900 Package Pinout (Continued)

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S2000

Pin Name

XC3S2000

Pin Name

Bank

N/A

Type

GND

Bank

N/A

Type

GND

AJ1

AK1

A2

GND

P15

R15

T15

GND

B2

U15

V15

W15

M16

N16

P16

R16

T16

AJ2

E5

K5

P5

U5

AA5

AF5

A6

U16

V16

W16

A17

E17

H17

N17

P17

R17

T17

AK6

K8

P8

U8

AA8

A10

E10

H10

AC10

AF10

AK10

R12

T12

N13

P13

R13

T13

U13

V13

A14

E14

H14

N14

P14

R14

T14

U14

V14

AC14

AF14

AK14

M15

N15

U17

V17

AC17

AF17

AK17

N18

P18

R18

T18

U18

V18

R19

T19

A21

E21

H21

AC21

AF21

AK21

K23

P23

U23

AA23

A25

DS099-4 (v1.5) July 13, 2004

Product Specification

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1-800-255-7778

79

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 34: FG900 Package Pinout (Continued)

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S4000

XC3S5000

Pin Name

FG900

Number

XC3S2000

Pin Name

XC3S2000

Pin Name

Bank

N/A

Type

GND

Bank

N/A

Type

GND

AK25

E26

VCCAUX

VCCINT

VCCAUX

VCCINT

CCLK

AE27

L11

VCCAUX

VCCINT

CONFIG

JTAG

GND

K26

GND

R11

T11

Y11

M12

N12

P12

U12

V12

W12

M13

W13

M14

W14

L15

GND

P26

GND

U26

AA26

AF26

A29

GND

B29

GND

AJ29

AK29

A30

GND

B30

GND

F30

GND

K30

GND

P30

GND

U30

AA30

AE30

AJ30

AK30

AK2

F4

GND

Y15

L16

GND

Y16

M17

W17

M18

W18

M19

N19

P19

U19

V19

W19

L20

GND

VCCAUX

K4

P4

U4

AA4

AE4

D6

AG6

D10

AG10

D14

AG14

D17

AG17

D21

AG21

D25

AG25

F27

R20

T20

Y20

AH28

AJ28

A3

VCCAUX CCLK

VCCAUX DONE

VCCAUX HSWAP_EN

VCCAUX M0

DONE

HSWAP_EN

M0

AJ3

AH3

AK3

B3

VCCAUX M1

M1

VCCAUX M2

M2

VCCAUX PROG_B

VCCAUX TCK

VCCAUX TDI

PROG_B

TCK

B28

C3

K27

TDI

JTAG

P27

VCCAUX TDO

VCCAUX TMS

TDO

C28

A28

JTAG

U27

AA27

TMS

JTAG

80

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

available user-I/O pins are distributed between the eight I/O

banks for the XC3S4000 and XC3S5000 in the FG900

package.

User I/Os by Bank

Table 35 indicates how the available user-I/O pins are dis-

tributed between the eight I/O banks for the XC3S2000 in

the FG900 package. Similarly, Table 36 shows how the

Table 35: User I/Os Per Bank for XC3S2000 in FG900 Package

All Possible I/O Pins by Type

I/O

Bank

Maximum

I/O

Edge

I/O

62

61

62

57

55

60

62

DUAL

DCI

2

VREF

GCLK

0

1

2

3

4

5

6

7

71

69

71

72

71

69

71

0

6

0

5

6

7

5

6

7

2

0

2

0

Top

2

Right

Bottom

Left

2

Table 36: User I/Os Per Bank for XC3S4000 and XC3S5000 in FG900 Package

All Possible I/O Pins by Type

I/O

Bank

Maximum

I/O

Edge

I/O

70

71

70

65

63

70

DUAL

DCI

2

VREF

GCLK

0

1

2

3

4

5

6

7

79

80

79

0

6

0

5

6

7

5

6

7

2

0

2

0

Top

2

Right

Bottom

Left

2

DS099-4 (v1.5) July 13, 2004

Product Specification

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1-800-255-7778

81

R

Spartan-3 FPGA Family: Pinout Descriptions

FG900 Footprint

Bank 0

1

2

3

4

5

I/O

6

7

8

I/O

9

10

11

I/O

12

I/O

13

I/O

14

15

I/O

L35P_0

I/O

L38P_0

I/O

Left Half of Package

(top view)

HSWAP_

EN

A

B

C

D

E

F

L01P_0

VRN_0

L32P_0

GCLK6

GND

L02P_0

L09P_0

L17P_0 L22P_0 L25P_0

I/O

L35N_0

I/O

L38N_0

I/O

L01N_0

VRP_0

I/O

L32N_0

GCLK7

I/O

L09N_0

I/O

PROG_B

GND

I/O

L01N_7 L01P_7

VRP_7

GND

I/O

L02N_0 L04P_0

L12P_0 L17N_0 L22N_0 L25N_0 L28P_0

XC3S2000

I/O

L31P_0

VREF_0

(565 max. user I/O)

I/O: Unrestricted,

IO

VREF_0

I/O

L28N_0

V

CCO_0

V

CCO_0

VCCO_0

TDI

I/O

L04N_0 L06P_0 L08P_0

L12N_0 L16P_0 L21P_0

V

RN_

7

481

I/O

L03N_7

VREF_7

general-purpose user I/O

I/O

L31N_0

L37P_0

VCCAUX

I/O

L03P_7 L02N_7 L02P_7 L03N_0

L06N_0 L08N_0

L16N_0 L21N_0

I/O

VREF: User I/O or input

voltage reference for bank

I/O

L05P_7

I/O

L03P_0

I/O

L07P_0

I/O

L37N_0

V

CCO_7

GND

V

CCO_0

GND

I/O

GND

I/O

48

L04N_7 L04P_7

L15P_0 L20P_0 L24P_0

I/O

L05P_0

VREF_0

IO

VREF_0

I/O

L07N_0

I/O I/O I/O

I/O

VCCAUX

GND

L06N_7 L06P_7

L05N_7 L05N_0

L11P_0 L15N_0 L20N_0 L24N_0 L27P_0 L30P_0

N.C.: Unconnected pins for

XC3S2000 ()

68

I/O

L36N_0

I/O

L09P_7

I/O

V

CCO_7

VCCO_0

I/O

G

H

J

L08N_7 L08P_7 L07N_7 L07P_7

L11N_0 L14P_0 L19P_0

L27N_0 L30N_0

I/O

L36P_0

XC3S4000, XC3S5000

(633 max user I/O)

I/O: Unrestricted,

I/O

L10P_7

VREF_7

I/O

L09N_7

I/O

GND

I/O

L13N_7 L13P_7 L11N_7 L11P_7 L10N_7

L10P_0

L14N_0 L19N_0 L23P_0

L29P_0

I/O

L16P_7

VREF_7

I/O

549

V

CCO_7

V

CCO_7

VCCO_0

I/O

L26P_0

L29N_0

VREF_0

L15N_7 L15P_7

L14N_7 L14P_7

L10N_0 L13N_0

L18P_0 L23N_0

general-purpose user I/O

I/O

VCCAUX

I/O

GND

I/O

GND

I/O

K

L

L19N_7

VREF: User I/O or input

voltage reference for bank

L19P_7

L17N_7 L17P_7

L16N_7 L20P_7 L13P_0 L18N_0

I/O

VCCO_0 VCCO_0 VCCO_0

VCCINT VCCINT

L26N_0

VREF_7

48

I/O

I/O I/O

V

CCO_7

L24N_7 L24P_7 L23N_7 L23P_7 L22N_7 L22P_7 L21N_7 L21P_7

L20N_7

N.C.: No unconnected pins

in this package

I/O

L27P_7

VREF_7

I/O

0

L49P_7 L25N_7 L25P_7 L46N_7 L46P_7

V

CCO_7

VCCINT VCCINT VCCINT GND

M

N

P

R

T

L27N_7

L26N_7 L26P_7

L28P_7

I/O

L50N_7 L50P_7 L49N_7

V

CCO_7

V

CCO_7

VCCO_7

VCCINT GND

GND

All devices

L31N_7 L31P_7

L29N_7 L29P_7 L28N_7

DUAL: Configuration pin,

then possible user I/O

12

I/O

VCCAUX

VCCO_7

VCCINT

GND

VCCINT

I/O

L34N_7 L34P_7

L33N_7 L33P_7

L32N_7 L32P_7

I/O

L40N_7

VREF_7

I/O

L37P_7

VREF_7

I/O

VCCINT

GCLK: User I/O or global

clock buffer input

GND

L40P_7 L39N_7 L39P_7 L38N_7 L38P_7 L37N_7

L35N_7 L35P_7

8

I/O

L40P_6

VREF_6

I/O

L52P_6 L52N_6

L40N_6 L39P_6 L39N_6 L38P_6 L38N_6

L37P_6 L37N_6

GND

I/O

DCI: User I/O or reference

resistor input for bank

I/O

16

I/O

L36P_6 L36N_6

VCCO_6

GND

VCCAUX GND

VCCINT

U

V

L34N_6

L34P_6

VREF_6

L35P_6 L35N_6

I/O

CONFIG: Dedicated

configuration pins

L30P_6 L30N_6

V

CCO_6

V

CCO_6

VCCO_6

L33P_6 L33N_6

L32P_6 L32N_6 L31P_6

L29P_6

7

I/O

I/O I/O I/O

L28N_6 L27P_6 L27N_6 L31N_6 L26P_6 L26N_6

I/O

L29N_6

L25P_6 L25N_6

VCCO_6

VCCINT VCCINT VCCINT

W _{L28P_6}

JTAG: Dedicated JTAG port

pins

I/O

4

I/O

L24N_6

VREF_6

I/O

Y

I/O

L20P_6

L45P_6 L45N_6

V

CCO_6

VCCO_5 VCCO_5 VCCO_5

VCCINT

I/O

L24P_6

L22P_6 L22N_6 L21P_6 L21N_6

I/O

A

VCCINT: Internal core

voltage supply (+1.2V)

I/O

GND

A

GND

VCCAUX

L17P_6

VREF_6

L19P_6 L19N_6

L17N_6

L16P_6 L20N_6

L22P_5 L22N_5 L26P_5

32

I/O

L29P_5

VREF_5

A

I/O

V

CCO_6

V

CCO_6

VCCO_5

I/O

L15P_6 L15N_6

L14P_6 L14N_6

L16N_6 L08P_5

L17N_5 L23P_5 L26N_5

B

VCCO: Output voltage

supply for bank

80

I/O

L36P_5

I/O

A _{L13P_6}

C _{VREF_6}

I/O

L08N_5

I/O

GND

I/O

GND

I/O

L13N_6 L11P_6 L11N_6 L10P_6 L10N_6 L09P_6

L17P_5 L18P_5 L23N_5

L29N_5

I/O

L36N_5

I/O

L09N_6

VREF_6

VCCAUX: Auxiliary voltage

supply (+2.5V)

A

I/O

L05P_5

I/O

V

CCO_6

V

CCO_5

VCCO_5

24

L08P_6 L08N_6 L07P_6 L07N_6

L13P_5 L13N_5 L18N_5

L30P_5 L30N_5

D

I/O

L37P_5

I/O

L11N_5

VREF_5

I/O

L19P_5

VREF_5

I/O

L27N_5

VREF_5

A

E

I/O

L05P_6

I/O

L05N_5

I/O

L11P_5

I/O

L27P_5

VCCAUX

GND

I/O

L06P_6 L06N_6

L14P_5

GND: Ground

120

I/O

L31P_5

D5

A

F

I/O

L05N_6

I/O

L03N_5

I/O

L09P_5

I/O

L37N_5

VCCO_5

VCCO_6

GND

L04P_6 L04N_6

L14N_5 L19N_5 L24P_5

I/O

L31N_5

D4

A

G

I/O

L38P_5

V

CCAUX

L03N_6

L03P_6

VREF_6

VCCAUX

I/O

VCCAUX

I/O

L02P_6 L02N_6 L03P_5

L06P_5

L09N_5

L15P_5 L20P_5 L24N_5

I/O

L38N_5

I/O

A

H

IO

VREF_5

I/O

V

CCO_5

V

CCO_5

V

CCO_5

M1

M0

M2

L01P_6 L01N_6

VRN_6 VRP_6

L28P_5 L32P_5

L04P_5 L06N_5

L12P_5 L15N_5 L20N_5

D7

GCLK2

I/O

L35P_5

I/O

L01P_5

CS_B

I/O

L10P_5

VRN_5

I/O

A

J

I/O

L07P_5

I/O

GND

L28N_5 L32N_5

L02P_5 L04N_5

L12N_5 L16P_5 L21P_5 L25P_5

D6

GCLK3

I/O

L35N_5

I/O

L01N_5

RDWR_B

I/O

L10N_5

VRP_5

A

K

IO

VREF_5

I/O

GND

I/O

L07N_5

I/O

GND

L02N_5

L16N_5 L21N_5 L25N_5

Bank 5

DS099-4_13a_121103

Figure 15: FG900 Package Footprint (top view)

82

www.xilinx.com

1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Bank 1

16

17

18

19

I/O

20

I/O

21

22

23

I/O

24

I/O

25

26

I/O

27

28

29

30

I/O

Right Half of Package

L39N_1

I/O

GND

TMS

GND

L01N_1

VRP_1

A

L26N_1 L21N_1

L15N_1 L11N_1 L07N_1

L03N_1

(top view)

I/O

L32N_1

GCLK5

I/O

L17N_1

VREF_1

I/O

L28N_1

I/O

L39P_1

TCK

GND

I/O

GND

I/O

L01P_1

L15P_1 L11P_1 L07P_1 L04N_1 L03P_1

VRN_1

B

L26P_1 L21P_1

I/O

L32P_1

GCLK4

I/O

VCCO_1

TDO

I/O

L10N_1 L06N_1

VREF_1 VREF_1

^{L01N_2 L01P_2}C

VCCO_1

L28P_1

L25N_1 L20N_1 L17P_1

L04P_1

L02P_1

VRP_2 VRN_2

I/O

L38N_1

I/O

L31N_1

VREF_1

I/O

VCCAUX

GND

L03N_2

VREF_2

D

E

F

VCCAUX

L25P_1 L20P_1

L14N_1 L10P_1 L06P_1

L02N_1 L02N_2 L02P_2

L03P_2

I/O

L38P_1

I/O

L41N_2

I/O

L31P_1

I/O

GND

I/O

GND

VCCO_2

I/O

VCCO_1

L24N_1 L19N_1

L14P_1 L13P_1

L04N_2 L04P_2

I/O

L41P_2

I/O

L27N_1

I/O

GND

VCCAUX

L24P_1 L19P_1 L16N_1 L13N_1 L09N_1 L05N_1 L05P_1

L05N_2 L05P_2

I/O

VCCO_1

VCCO_2

VCCO_1

G

H

J

L30N_1 L27P_1

L23N_1 L18N_1 L16P_1

L09P_1 L08P_1 L08N_2

L06N_2 L06P_2 L07N_2 L07P_2

I/O

L37N_1

I/O

L09N_2

VREF_2

I/O

L30P_1

I/O

I/O I/O I/O I/O

L09P_2 L10N_2 L10P_2 L12N_2 L12P_2

GND

I/O

L23P_1 L18P_1

L12N_1 L08N_1 L08P_2

I/O

L37P_1

I/O

L13P_2

VREF_2

IO

VREF_1

I/O

L29N_1

I/O

L13N_2

I/O

VCCO_1

L22N_1

I/O

VCCO_2

I/O

VCCO_2

I/O

L45N_2 L45P_2

L12P_1 L15N_2

L14N_2 L14P_2

I/O

L46N_2

I/O

L29P_1

I/O

L15P_2

I/O

L40N_1 L40P_1

GND

I/O

K

L

VCCAUX

L22P_1

L16N_2 L16P_2

I/O

L46P_2

I/O

L47N_2 L47P_2

I/O

VCCO_2

VCCINT

VCCO_1 VCCO_1 VCCO_1

L19N_2 L19P_2 L20N_2 L20P_2 L21N_2 L21P_2

I/O

L23N_2

VREF_2

I/O

L50N_2 L50P_2

GND VCCINT VCCINT VCCINT

VCCO_2

M

N

P

L26N_2 L22N_2 L22P_2

L23P_2 L28N_2 L24N_2 L24P_2

I/O

GND

GND VCCINT

VCCO_2

L26P_2 L27N_2 L27P_2

L28P_2 L29N_2 L29P_2

L31N_2 L31P_2

I/O

L34N_2

VREF_2

I/O

L34P_2

GND

I/O

GND

VCCAUX

L32N_2 L32P_2

L33N_2 L33P_2

I/O I/O

I/O

GND

GND VCCINT

^L40P_2R

L35N_2 L35P_2 L37N_2 L37P_2 L38N_2 L38P_2 L39N_2 L39P_2 L40N_2

VREF_2

I/O

^L40N_3T

L35P_3 L35N_3 L37P_3 L37N_3 L38P_3 L38N_3 L39P_3 L39N_3 L40P_3

VREF_3

I/O

L34P_3

VREF_3

I/O

L34N_3

GND VCCINT

GND

I/O

GND

I/O

VCCAUX

I/O

GND

U

VCCO_3

L32P_3 L32N_3

L33P_3 L33N_3

I/O

VCCO_3

I/O

L50P_3 L50N_3

GND VCCINT VCCO_3

VCCO_3

I/O

V

L27N_3 L28P_3 L28N_3

L29N_3

L31P_3 L31N_3

I/O

L27P_3

I/O

L29P_3

I/O

L46P_3 L46N_3 L47P_3 L47N_3

L48P_3 L48N_3

VCCO_3

GND VCCINT VCCINT VCCINT

W

Y

L26P_3 L26N_3

I/O

L20N_3

I/O

VCCINT VCCO_4 VCCO_4 VCCO_4 VCCINT

L23P_3

L23N_3 L24P_3 L24N_3

VREF_3

VCCO_3

L21P_3 L21N_3 L22P_3 L22N_3

I/O

A

I/O

VCCAUX

I/O

GND

I/O

L17P_3

VREF_3

L26N_4

L18N_4 L13P_4 L20P_3 L16N_3

L17N_3

L19P_3 L19N_3

I/O

L26P_4

VREF_4

A

B

I/O

L29N_4

I/O

L13N_4

I/O

VCCO_4

I/O

VCCO_3

L23N_4 L18P_4

L08N_4 L16P_3

L14P_3 L14N_3

I/O I/O

L15P_3 L15N_3

I/O

A

C

I/O

L29P_4

I/O I/O

L23P_4 L19N_4 L14N_4

I/O

I/O I/O

I/O

GND

L13N_3

VREF_3

L08P_4 L04P_4 L09N_3 L10P_3 L10N_3 L11P_3 L11N_3 L13P_3

I/O

L27N_4

DIN

I/O

L30N_4

D2

I/O

A

D

I/O

L04N_4

I/O

VCCO_4

I/O

L09P_3 VCCO_3

VREF_3

VCCO_4

L19P_4 L14P_4 L11N_4

L07P_3 L07N_3 L08P_3 L08N_3

D0

I/O

A

E

I/O

I/O I/O I/O

I/O

L34P_4 L34N_4

I/O

VCCAUX

GND

L30P_4 L27P_4

L24N_4 L20N_4 L15N_4 L11P_4

L05N_4

L05N_3

GND

I/O

L06P_3 L06N_3

D3

D1

A

F

I/O

VREF_4

I/O

L03P_4

I/O

L05P_3

I/O

VCCO_3

GND

VCCO_4

L24P_4 L20P_4 L15P_4

L09N_4 L05P_4

L04P_3 L04N_3

I/O

L35N_4

I/O

L31N_4

INIT_B

I/O

L02N_3

VREF_3

A

G

I/O

VCCAUX

I/O

VCCAUX

I/O

VCCAUX

I/O

L06N_4

L09P_4

VREF_4

L21N_4 L16N_4

L03N_4 L02P_3

L03P_3 L03N_3

I/O

A

H

I/O

L31P_4

L35P_4 L33N_4

I/O

CCLK

DONE

L01P_3 L01N_3

VRN_3 VRP_3

VCCO_4

I/O

VCCO_4

L06P_4

VCCO_4

DOUT L28N_4

L21P_4 L16P_4 L12N_4

BUSY

I/O

L22N_4

VREF_4

I/O

A

J

I/O

L38N_4 L33P_4

GND

L32N_4

L01N_4

L02N_4

VRP_4

L28P_4 L25N_4

L17N_4 L12P_4 L10N_4 L07N_4

GCLK1

I/O

L38P_4

I/O

L32P_4

GCLK0

I/O

A

K

IO

VREF_4

I/O

GND

L01P_4

L02P_4

VRN_4

L25P_4 L22P_4 L17P_4

L10P_4 L07P_4

Bank 4

DS099-4_13b_121103

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

83

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 37: FG1156 Package Pinout (Continued)

FG1156: 1156-lead Fine-pitch Ball Grid

Array

FG1156

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

The 1,156-lead fine-pitch ball grid array package, FG1156,

supports two different Spartan-3 devices, namely the

XC3S4000, and the XC3S5000. The XC3S2000, however,

has fewer I/O pins, which consequently results in 73 uncon-

nected pins on the FG1156 package, labeled as “N.C.” In

Table 37 and Figure 16, these unconnected pins are indi-

cated with a black diamond symbol ().

Bank

Type

I/O

0

IO

L16

L17

D5

IO

I/O

IO/VREF_0

VREF

DCI

E10

J14

L15

B3

The XC3S5000 has a single unconnected package pin, ball

AK31, which is also unconnected for the XC3S4000.

IO_L01N_0/

VRP_0

IO_L01N_0/

VRP_0

All the package pins appear in Table 37 and are sorted by

bank number, then by pin name. Pairs of pins that form a dif-

ferential I/O pair appear together in the table. The table also

shows the pin number for each pin and the pin type, as

defined earlier.

0

IO_L01P_0/

VRN_0

IO_L01P_0/

VRN_0

A3

DCI

0

IO_L02N_0

IO_L02P_0

IO_L03N_0

IO_L03P_0

IO_L04N_0

IO_L04P_0

IO_L05N_0

IO_L02N_0

IO_L02P_0

IO_L03N_0

IO_L03P_0

IO_L04N_0

IO_L04P_0

IO_L05N_0

B4

A4

C5

B5

D6

C6

B6

A6

I/O

If there is a difference between the XC3S2000 and

XC3S5000 pinouts, then that difference is highlighted in

Table 37. If the table entry is shaded grey, then there is an

unconnected pin on the XC3S2000 that maps to a user-I/O

pin on the XC3S4000 and XC3S5000. If the table entry is

shaded tan, which only occurs on ball L29 in I/O Bank 2,

then the unconnected pin on XC3S4000 maps to a

VREF-type pin on the XC3S5000. If the other VREF_2 pins

all connect to a voltage reference to support a special I/O

standard, then also connect the N.C. pin on the XC3S4000

to the same VREF_2 voltage. This provides maximum flexi-

bility as you could potentially migrate a design from the

XC3S4000 to the XC3S5000 FPGA without changing the

printed circuit board.

I/O

IO_L05P_0/

VREF_0

IO_L05P_0/

VREF_0

VREF

0

IO_L06N_0

IO_L06P_0

IO_L07N_0

IO_L07P_0

IO_L08N_0

IO_L08P_0

IO_L09N_0

IO_L09P_0

IO_L10N_0

IO_L10P_0

IO_L11N_0

IO_L11P_0

IO_L12N_0

IO_L12P_0

IO_L13N_0

IO_L13P_0

IO_L14N_0

IO_L14P_0

IO_L15N_0

IO_L15P_0

IO_L16N_0

IO_L16P_0

IO_L17N_0

IO_L06N_0

IO_L06P_0

IO_L07N_0

IO_L07P_0

IO_L08N_0

IO_L08P_0

IO_L09N_0

IO_L09P_0

IO_L10N_0

IO_L10P_0

IO_L11N_0

IO_L11P_0

IO_L12N_0

IO_L12P_0

IO_L13N_0

IO_L13P_0

IO_L14N_0

IO_L14P_0

IO_L15N_0

IO_L15P_0

IO_L16N_0

IO_L16P_0

IO_L17N_0

F7

E7

I/O

G9

F9

D9

Pinout Table

C9

Table 37: FG1156 Package Pinout

J10

H10

G10

F10

L12

K12

J12

H12

F12

E12

D12

C12

B12

A12

H13

G13

D13

FG1156

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

Bank

Type

I/O

0

IO

B9

E17

F6

IO

F8

IO

G12

H8

IO

H9

IO

J11

J9

N.C. ()

K11

K13

K16

K17

L13

IO

84

www.xilinx.com

1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 37: FG1156 Package Pinout (Continued)

FG1156

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

Bank

0

Type

I/O

VREF

Bank

0

1

Type

I/O

IO_L17P_0

IO_L18N_0

IO_L18P_0

IO_L19N_0

IO_L19P_0

IO_L20N_0

IO_L20P_0

IO_L21N_0

IO_L21P_0

IO_L22N_0

IO_L22P_0

IO_L23N_0

IO_L23P_0

IO_L24N_0

IO_L24P_0

IO_L25N_0

IO_L25P_0

IO_L26N_0

IO_L17P_0

IO_L18N_0

IO_L18P_0

IO_L19N_0

IO_L19P_0

IO_L20N_0

IO_L20P_0

IO_L21N_0

IO_L21P_0

IO_L22N_0

IO_L22P_0

IO_L23N_0

IO_L23P_0

IO_L24N_0

IO_L24P_0

IO_L25N_0

IO_L25P_0

IO_L26N_0

C13

L14

K14

H14

G14

F14

E14

D14

C14

B14

A14

K15

J15

IO_L36P_0

IO_L37N_0

IO_L37P_0

IO_L38N_0

IO_L38P_0

N.C. ()

VCCO_0

IO

IO_L36P_0

IO_L37N_0

IO_L37P_0

IO_L38N_0

IO_L38P_0

IO_L39N_0

IO_L39P_0

IO_L40N_0

IO_L40P_0

VCCO_0

IO

A8

0

D10

C10

B10

A10

G11

F11

B11

A11

B13

C4

I/O

0

I/O

0

I/O

0

I/O

0

I/O

0

I/O

0

I/O

0

I/O

0

VCCO

I/O

0

C8

0

D11

D16

F13

G8

0

G15

F15

D15

C15

B15

A15

0

H11

H15

M13

M14

M15

M16

B26

A18

C23

E21

E25

F18

F27

F29

H23

H26

J26

K19

L19

L20

L21

L23

L24

D30

K21

0

IO_L26P_0/

VREF_0

IO_L26P_0/

VREF_0

0

IO_L27N_0

IO_L27P_0

IO_L28N_0

IO_L28P_0

IO_L29N_0

IO_L29P_0

IO_L30N_0

IO_L30P_0

IO_L31N_0

IO_L27N_0

IO_L27P_0

IO_L28N_0

IO_L28P_0

IO_L29N_0

IO_L29P_0

IO_L30N_0

IO_L30P_0

IO_L31N_0

G16

F16

C16

B16

J17

I/O

IO

I/O

IO

I/O

H17

G17

F17

D17

C17

I/O

IO

I/O

IO

I/O

IO

I/O

IO

I/O

IO_L31P_0/

VREF_0

IO_L31P_0/

VREF_0

VREF

IO

I/O

IO

I/O

0

IO_L32N_0/

GCLK7

IO_L32N_0/

GCLK7

B17

A17

GCLK

IO

I/O

N.C. ()

IO

I/O

IO_L32P_0/

GCLK6

IO_L32P_0/

GCLK6

IO

I/O

0

N.C. ()

IO_L33N_0

IO_L33P_0

IO_L34N_0

IO_L34P_0

IO_L35N_0

IO_L35P_0

IO_L36N_0

D7

C7

B7

A7

E8

D8

B8

I/O

IO

I/O

N.C. ()

IO

I/O

N.C. ()

IO

I/O

N.C. ()

IO

I/O

IO_L35N_0

IO_L35P_0

IO_L36N_0

IO

I/O

IO/VREF_1

VREF

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

85

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 37: FG1156 Package Pinout (Continued)

FG1156

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

Bank

Type

VREF

DCI

Bank

1

Type

I/O

VREF

1

IO/VREF_1

L18

A32

IO_L19N_1

IO_L19P_1

IO_L20N_1

IO_L20P_1

IO_L21N_1

IO_L21P_1

IO_L22N_1

IO_L22P_1

IO_L23N_1

IO_L23P_1

IO_L24N_1

IO_L24P_1

IO_L25N_1

IO_L25P_1

IO_L26N_1

IO_L26P_1

IO_L27N_1

IO_L27P_1

IO_L28N_1

IO_L28P_1

IO_L29N_1

IO_L29P_1

IO_L30N_1

IO_L30P_1

IO_L19N_1

IO_L19P_1

IO_L20N_1

IO_L20P_1

IO_L21N_1

IO_L21P_1

IO_L22N_1

IO_L22P_1

IO_L23N_1

IO_L23P_1

IO_L24N_1

IO_L24P_1

IO_L25N_1

IO_L25P_1

IO_L26N_1

IO_L26P_1

IO_L27N_1

IO_L27P_1

IO_L28N_1

IO_L28P_1

IO_L29N_1

IO_L29P_1

IO_L30N_1

IO_L30P_1

A23

B23

K22

L22

G22

H22

C22

D22

H21

J21

IO_L01N_1/

VRP_1

IO_L01N_1/

VRP_1

1

IO_L01P_1/

VRN_1

IO_L01P_1/

VRN_1

B32

DCI

1

IO_L02N_1

IO_L02P_1

IO_L03N_1

IO_L03P_1

IO_L04N_1

IO_L04P_1

IO_L05N_1

IO_L05P_1

IO_L02N_1

IO_L02P_1

IO_L03N_1

IO_L03P_1

IO_L04N_1

IO_L04P_1

IO_L05N_1

IO_L05P_1

A31

B31

B30

C30

C29

D29

A29

B29

E28

I/O

1

I/O

1

I/O

1

I/O

1

I/O

1

F21

G21

C21

D21

A21

B21

F19

G19

B19

C19

J18

I/O

1

I/O

1

IO_L06N_1/

VREF_1

IO_L06N_1/

VREF_1

VREF

1

IO_L06P_1

IO_L07N_1

IO_L07P_1

IO_L08N_1

IO_L08P_1

IO_L09N_1

IO_L09P_1

IO_L06P_1

IO_L07N_1

IO_L07P_1

IO_L08N_1

IO_L08P_1

IO_L09N_1

IO_L09P_1

F28

D27

E27

A27

B27

F26

G26

C26

I/O

1

I/O

1

I/O

1

I/O

1

I/O

1

I/O

1

K18

G18

H18

D18

IO_L10N_1/

VREF_1

IO_L10N_1/

VREF_1

VREF

1

IO_L10P_1

IO_L11N_1

IO_L11P_1

IO_L12N_1

IO_L12P_1

IO_L13N_1

IO_L13P_1

IO_L14N_1

IO_L14P_1

IO_L15N_1

IO_L15P_1

IO_L16N_1

IO_L16P_1

IO_L10P_1

IO_L11N_1

IO_L11P_1

IO_L12N_1

IO_L12P_1

IO_L13N_1

IO_L13P_1

IO_L14N_1

IO_L14P_1

IO_L15N_1

IO_L15P_1

IO_L16N_1

IO_L16P_1

D26

H25

J25

F25

G25

C25

D25

A25

B25

A24

B24

J23

K23

F23

I/O

1

IO_L31N_1/

VREF_1

IO_L31N_1/

VREF_1

I/O

1

IO_L31P_1

E18

B18

I/O

IO_L32N_1/

GCLK5

IO_L32N_1/

GCLK5

GCLK

I/O

1

IO_L32P_1/

GCLK4

IO_L32P_1/

GCLK4

C18

GCLK

I/O

1

N.C. ()

IO_L37N_1

IO_L37P_1

IO_L38N_1

IO_L33N_1

IO_L33P_1

IO_L34N_1

IO_L34P_1

IO_L35N_1

IO_L35P_1

IO_L36N_1

IO_L36P_1

IO_L37N_1

IO_L37P_1

IO_L38N_1

C28

D28

A28

B28

J24

K24

F24

G24

J20

K20

F20

I/O

IO_L17N_1/

VREF_1

IO_L17N_1/

VREF_1

VREF

1

IO_L17P_1

IO_L18N_1

IO_L18P_1

IO_L17P_1

IO_L18N_1

IO_L18P_1

G23

D23

E23

I/O

86

www.xilinx.com

1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 37: FG1156 Package Pinout (Continued)

FG1156

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

Bank

1

Type

I/O

Bank

Type

IO_L38P_1

IO_L39N_1

IO_L39P_1

IO_L40N_1

IO_L40P_1

VCCO_1

IO

IO_L38P_1

IO_L39N_1

IO_L39P_1

IO_L40N_1

IO_L40P_1

VCCO_1

IO

G20

C20

D20

A20

B20

B22

C27

C31

D19

D24

F22

G27

H20

H24

M19

M20

M21

M22

G33

G34

U25

U26

C33

2

IO_L09N_2/

VREF_2

IO_L09N_2/

VREF_2

H31

VREF

1

I/O

2

IO_L09P_2

IO_L10N_2

IO_L10P_2

IO_L11N_2

IO_L11P_2

IO_L12N_2

IO_L12P_2

IO_L13N_2

IO_L09P_2

IO_L10N_2

IO_L10P_2

IO_L11N_2

IO_L11P_2

IO_L12N_2

IO_L12P_2

IO_L13N_2

J31

J32

J33

J27

K26

K27

K28

K29

K30

I/O

1

I/O

1

I/O

1

I/O

1

VCCO

I/O

1

I/O

1

I/O

1

I/O

1

IO_L13P_2/

VREF_2

IO_L13P_2/

VREF_2

VREF

1

2

IO_L14N_2

IO_L14P_2

IO_L15N_2

IO_L15P_2

IO_L16N_2

IO_L16P_2

N.C. ()

IO_L14N_2

IO_L14P_2

IO_L15N_2

IO_L15P_2

IO_L16N_2

IO_L16P_2

IO_L17N_2

K31

K32

K33

K34

L25

L26

L28

L29

I/O

1

I/O

1

I/O

1

I/O

1

I/O

1

I/O

2

N.C. ()

IO_L17P_2/

VREF_2

VREF

2

IO

I/O

2

IO

I/O

2

IO_L19N_2

IO_L19P_2

IO_L20N_2

IO_L20P_2

IO_L21N_2

IO_L21P_2

IO_L22N_2

IO_L22P_2

IO_L19N_2

IO_L19P_2

IO_L20N_2

IO_L20P_2

IO_L21N_2

IO_L21P_2

IO_L22N_2

IO_L22P_2

M29

M30

M31

M32

M26

N25

N27

N28

N31

I/O

2

IO

I/O

2

IO_L01N_2/

VRP_2

IO_L01N_2/

VRP_2

DCI

I/O

2

IO_L01P_2/

VRN_2

IO_L01P_2/

VRN_2

C34

DCI

I/O

2

IO_L02N_2

IO_L02P_2

IO_L02N_2

IO_L02P_2

D33

D34

E32

I/O

IO_L03N_2/

VREF_2

IO_L03N_2/

VREF_2

VREF

IO_L23N_2/

VREF_2

IO_L23N_2/

VREF_2

VREF

2

IO_L03P_2

IO_L04N_2

IO_L04P_2

IO_L05N_2

IO_L05P_2

IO_L06N_2

IO_L06P_2

IO_L07N_2

IO_L07P_2

IO_L08N_2

IO_L08P_2

IO_L03P_2

IO_L04N_2

IO_L04P_2

IO_L05N_2

IO_L05P_2

IO_L06N_2

IO_L06P_2

IO_L07N_2

IO_L07P_2

IO_L08N_2

IO_L08P_2

E33

F31

F32

G29

G30

H29

H30

H33

H34

J28

I/O

2

IO_L23P_2

IO_L24N_2

IO_L24P_2

IO_L26N_2

IO_L26P_2

IO_L27N_2

IO_L27P_2

IO_L28N_2

IO_L28P_2

IO_L29N_2

IO_L29P_2

IO_L23P_2

IO_L24N_2

IO_L24P_2

IO_L26N_2

IO_L26P_2

IO_L27N_2

IO_L27P_2

IO_L28N_2

IO_L28P_2

IO_L29N_2

IO_L29P_2

N32

N24

P24

P29

P30

P31

P32

P33

P34

R24

R25

I/O

J29

DS099-4 (v1.5) July 13, 2004

Product Specification

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87

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 37: FG1156 Package Pinout (Continued)

FG1156

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

Bank

Type

I/O

Bank

Type

VCCO

I/O

2

IO_L30N_2

IO_L30P_2

IO_L31N_2

IO_L31P_2

IO_L32N_2

IO_L32P_2

IO_L33N_2

IO_L33P_2

IO_L30N_2

IO_L30P_2

IO_L31N_2

IO_L31P_2

IO_L32N_2

IO_L32P_2

IO_L33N_2

IO_L33P_2

R28

R29

R31

R32

R33

R34

R26

T25

T28

2

3

VCCO_2

IO

VCCO_2

IO

H32

L27

I/O

L31

I/O

N23

N29

N33

P23

R23

R27

T23

I/O

IO_L34N_2/

VREF_2

IO_L34N_2/

VREF_2

VREF

2

IO_L34P_2

IO_L35N_2

IO_L35P_2

IO_L37N_2

IO_L37P_2

IO_L38N_2

IO_L38P_2

IO_L39N_2

IO_L39P_2

IO_L40N_2

IO_L34P_2

IO_L35N_2

IO_L35P_2

IO_L37N_2

IO_L37P_2

IO_L38N_2

IO_L38P_2

IO_L39N_2

IO_L39P_2

IO_L40N_2

T29

T32

T33

U27

U28

U29

U30

U31

U32

U33

U34

I/O

T31

AH33

AH34

V25

V26

AM34

I/O

IO

I/O

IO

I/O

IO

I/O

IO_L01N_3/

VRP_3

IO_L01N_3/

VRP_3

DCI

I/O

3

IO_L01P_3/

VRN_3

IO_L01P_3/

VRN_3

AM33

AL34

DCI

I/O

IO_L02N_3/

VREF_3

IO_L02N_3/

VREF_3

VREF

I/O

IO_L40P_2/

VREF_2

IO_L40P_2/

VREF_2

VREF

3

IO_L02P_3

IO_L03N_3

IO_L03P_3

IO_L04N_3

IO_L04P_3

IO_L05N_3

IO_L05P_3

IO_L06N_3

IO_L06P_3

IO_L07N_3

IO_L07P_3

IO_L08N_3

IO_L08P_3

IO_L09N_3

IO_L02P_3

IO_L03N_3

IO_L03P_3

IO_L04N_3

IO_L04P_3

IO_L05N_3

IO_L05P_3

IO_L06N_3

IO_L06P_3

IO_L07N_3

IO_L07P_3

IO_L08N_3

IO_L08P_3

IO_L09N_3

AL33

AK33

AK32

AJ32

AJ31

AJ34

AJ33

AH30

AH29

AG30

AG29

AG34

AG33

AF29

AF28

I/O

2

IO_L41N_2

IO_L41P_2

N.C. ()

IO_L41N_2

IO_L41P_2

IO_L42N_2

IO_L42P_2

IO_L45N_2

IO_L45P_2

IO_L46N_2

IO_L46P_2

IO_L47N_2

IO_L47P_2

IO_L48N_2

IO_L48P_2

IO_L49N_2

IO_L49P_2

IO_L50N_2

IO_L50P_2

IO_L51N_2

IO_L51P_2

VCCO_2

F33

F34

G31

G32

L33

L34

M24

M25

M27

M28

M33

M34

P25

P26

P27

P28

T24

U24

D32

H28

I/O

N.C. ()

I/O

IO_L45N_2

IO_L45P_2

IO_L46N_2

IO_L46P_2

IO_L47N_2

IO_L47P_2

IO_L48N_2

IO_L48P_2

N.C. ()

I/O

IO_L09P_3/

VREF_3

IO_L09P_3/

VREF_3

VREF

N.C. ()

I/O

IO_L50N_2

IO_L50P_2

N.C. ()

I/O

3

IO_L10N_3

IO_L10P_3

IO_L11N_3

IO_L11P_3

IO_L12N_3

IO_L10N_3

IO_L10P_3

IO_L11N_3

IO_L11P_3

IO_L12N_3

AF31

AG31

AF33

AF32

AE26

I/O

N.C. ()

I/O

VCCO_2

VCCO

VCCO_2

88

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 37: FG1156 Package Pinout (Continued)

FG1156

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

Bank

Type

I/O

Bank

Type

I/O

3

IO_L12P_3

AF27

AE28

3

IO_L34N_3

W29

W28

IO_L13N_3/

VREF_3

IO_L13N_3/

VREF_3

VREF

IO_L34P_3/

VREF_3

IO_L34P_3/

VREF_3

VREF

3

IO_L13P_3

IO_L14N_3

IO_L14P_3

IO_L15N_3

IO_L15P_3

IO_L16N_3

IO_L16P_3

IO_L17N_3

IO_L13P_3

IO_L14N_3

IO_L14P_3

IO_L15N_3

IO_L15P_3

IO_L16N_3

IO_L16P_3

IO_L17N_3

AE27

AE30

AE29

AE32

AE31

AE34

AE33

AD26

AD25

I/O

3

IO_L35N_3

IO_L35P_3

IO_L37N_3

IO_L37P_3

IO_L38N_3

IO_L38P_3

IO_L39N_3

IO_L39P_3

IO_L35N_3

IO_L35P_3

IO_L37N_3

IO_L37P_3

IO_L38N_3

IO_L38P_3

IO_L39N_3

IO_L39P_3

W33

W32

V28

V27

V30

V29

V32

V31

V34

I/O

IO_L17P_3/

VREF_3

IO_L17P_3/

VREF_3

VREF

IO_L40N_3/

VREF_3

IO_L40N_3/

VREF_3

VREF

3

IO_L19N_3

IO_L19P_3

IO_L20N_3

IO_L20P_3

IO_L21N_3

IO_L21P_3

IO_L22N_3

IO_L22P_3

IO_L23N_3

IO_L19N_3

IO_L19P_3

IO_L20N_3

IO_L20P_3

IO_L21N_3

IO_L21P_3

IO_L22N_3

IO_L22P_3

IO_L23N_3

AD34

AD33

AC25

AC24

AC28

AC27

AC30

AC29

AC32

AC31

I/O

3

IO_L40P_3

N.C. ()

IO_L40P_3

IO_L41N_3

IO_L41P_3

IO_L44N_3

IO_L44P_3

IO_L45N_3

IO_L45P_3

IO_L46N_3

IO_L46P_3

IO_L47N_3

IO_L47P_3

IO_L48N_3

IO_L48P_3

IO_L49N_3

IO_L49P_3

IO_L50N_3

IO_L50P_3

IO_L51N_3

IO_L51P_3

VCCO_3

V33

AH32

AH31

AD29

AD28

AC34

AC33

AB28

AB27

AB32

AB31

AA24

AB24

AA26

AA25

Y25

I/O

N.C. ()

I/O

N.C. ()

I/O

N.C. ()

I/O

IO_L45N_3

IO_L45P_3

IO_L46N_3

IO_L46P_3

IO_L47N_3

IO_L47P_3

IO_L48N_3

IO_L48P_3

N.C. ()

I/O

IO_L23P_3/

VREF_3

IO_L23P_3/

VREF_3

VREF

I/O

3

IO_L24N_3

IO_L24P_3

IO_L26N_3

IO_L26P_3

IO_L27N_3

IO_L27P_3

IO_L28N_3

IO_L28P_3

IO_L29N_3

IO_L29P_3

IO_L30N_3

IO_L30P_3

IO_L31N_3

IO_L31P_3

IO_L32N_3

IO_L32P_3

IO_L33N_3

IO_L33P_3

IO_L24N_3

IO_L24P_3

IO_L26N_3

IO_L26P_3

IO_L27N_3

IO_L27P_3

IO_L28N_3

IO_L28P_3

IO_L29N_3

IO_L29P_3

IO_L30N_3

IO_L30P_3

IO_L31N_3

IO_L31P_3

IO_L32N_3

IO_L32P_3

IO_L33N_3

IO_L33P_3

AB25

AC26

AA28

AA27

AA30

AA29

AA32

AA31

AA34

AA33

Y29

I/O

N.C. ()

I/O

IO_L50N_3

IO_L50P_3

N.C. ()

I/O

Y24

I/O

V24

I/O

N.C. ()

W24

I/O

VCCO_3

AA23

AB23

AB29

AB33

AD27

AD31

AG28

AG32

AL32

W23

VCCO

VCCO_3

Y28

VCCO_3

Y32

VCCO_3

Y31

VCCO_3

Y34

VCCO_3

Y33

VCCO_3

W25

Y26

VCCO_3

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

89

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 37: FG1156 Package Pinout (Continued)

FG1156

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

Bank

3

Type

VCCO

I/O

Bank

4

Type

I/O

VREF

VCCO_3

W31

Y23

IO_L09N_4

IO_L09P_4

IO_L10N_4

IO_L10P_4

IO_L11N_4

IO_L11P_4

IO_L12N_4

IO_L12P_4

IO_L13N_4

IO_L13P_4

IO_L14N_4

IO_L14P_4

IO_L15N_4

IO_L15P_4

IO_L16N_4

IO_L16P_4

IO_L17N_4

IO_L17P_4

IO_L18N_4

IO_L18P_4

IO_L19N_4

IO_L19P_4

IO_L20N_4

IO_L20P_4

IO_L21N_4

IO_L21P_4

IO_L09N_4

IO_L09P_4

IO_L10N_4

IO_L10P_4

IO_L11N_4

IO_L11P_4

IO_L12N_4

IO_L12P_4

IO_L13N_4

IO_L13P_4

IO_L14N_4

IO_L14P_4

IO_L15N_4

IO_L15P_4

IO_L16N_4

IO_L16P_4

IO_L17N_4

IO_L17P_4

IO_L18N_4

IO_L18P_4

IO_L19N_4

IO_L19P_4

IO_L20N_4

IO_L20P_4

IO_L21N_4

IO_L21P_4

AL25

AM25

AN25

AP25

AD23

AE23

AF23

AG23

AJ23

AK23

AL23

AM23

AN23

AP23

AG22

AH22

AL22

AM22

AD21

AE21

AG21

AH21

AJ21

AK21

AL21

AM21

AN21

3

VCCO_3

4

3

VCCO_3

Y27

4

IO

AD18

AD19

AD20

AD22

AE18

AE19

AE22

AE24

AF24

AF26

AG26

AG27

AJ27

AJ29

AK25

AN26

AF21

AH23

AK18

AL30

AN32

4

IO

I/O

4

IO

I/O

4

IO

I/O

4

IO

I/O

4

IO

I/O

4

IO

I/O

4

N.C. ()

IO

I/O

4

IO

I/O

4

N.C. ()

IO

I/O

4

IO

I/O

4

IO

I/O

4

IO

I/O

4

IO

I/O

4

IO

I/O

4

IO

I/O

4

IO/VREF_4

VREF

DCI

4

IO_L01N_4/

VRP_4

IO_L01N_4/

VRP_4

4

IO_L01P_4/

VRN_4

IO_L01P_4/

VRN_4

AP32

DCI

4

IO_L22N_4/

VREF_4

IO_L22N_4/

VREF_4

4

IO_L02N_4

IO_L02P_4

IO_L03N_4

IO_L03P_4

IO_L04N_4

IO_L04P_4

IO_L05N_4

IO_L05P_4

IO_L02N_4

IO_L02P_4

IO_L03N_4

IO_L03P_4

IO_L04N_4

IO_L04P_4

IO_L05N_4

IO_L05P_4

AN31

AP31

AM30

AN30

AN27

AP27

AH26

AJ26

AL26

I/O

4

IO_L22P_4

IO_L23N_4

IO_L23P_4

IO_L24N_4

IO_L24P_4

IO_L25N_4

IO_L25P_4

IO_L26N_4

IO_L22P_4

IO_L23N_4

IO_L23P_4

IO_L24N_4

IO_L24P_4

IO_L25N_4

IO_L25P_4

IO_L26N_4

AP21

AE20

AF20

AH20

AJ20

AL20

AM20

AN20

AP20

I/O

IO_L06N_4/

VREF_4

IO_L06N_4/

VREF_4

VREF

I/O

IO_L26P_4/

VREF_4

IO_L26P_4/

VREF_4

VREF

4

IO_L06P_4

IO_L07N_4

IO_L07P_4

IO_L08N_4

IO_L08P_4

IO_L06P_4

IO_L07N_4

IO_L07P_4

IO_L08N_4

IO_L08P_4

AM26

AF25

AG25

AH25

AJ25

I/O

4

IO_L27N_4/

DIN/D0

IO_L27N_4/

DIN/D0

AH19

AJ19

DUAL

IO_L27P_4/

D1

IO_L27P_4/

D1

90

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 37: FG1156 Package Pinout (Continued)

FG1156

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

Bank

Type

I/O

Bank

4

Type

VCCO

I/O

4

IO_L28N_4

IO_L28P_4

IO_L29N_4

IO_L29P_4

IO_L28N_4

IO_L28P_4

IO_L29N_4

IO_L29P_4

AM19

AN19

AF18

AG18

AH18

VCCO_4

AM31

AN22

AD11

AD12

AD14

AD15

AD16

AD17

AE14

AE16

AF9

I/O

4

VCCO_4

I/O

5

IO

I/O

5

N.C. ()

IO

I/O

IO_L30N_4/

D2

IO_L30N_4/

D2

DUAL

5

IO

I/O

5

IO

I/O

4

IO_L30P_4/

D3

IO_L30P_4/

D3

AJ18

AL18

AM18

AN18

AP18

DUAL

GCLK

5

IO

I/O

5

IO

I/O

IO_L31N_4/

INIT_B

IO_L31N_4/

INIT_B

5

IO

I/O

5

IO

I/O

IO_L31P_4/

DOUT/BUSY DOUT/BUSY

IO_L31P_4/

5

N.C. ()

IO

I/O

IO_L32N_4/

GCLK1

IO_L32N_4/

GCLK1

5

IO

AG9

I/O

5

IO

AG12

AJ6

I/O

IO_L32P_4/

GCLK0

IO_L32P_4/

GCLK0

5

IO

I/O

5

IO

AJ17

AK10

AK14

AM12

AN9

I/O

4

IO_L33N_4

IO_L33P_4

IO_L34N_4

IO_L34P_4

IO_L35N_4

IO_L35P_4

N.C. ()

IO_L38N_4

IO_L38P_4

N.C. ()

VCCO_4

IO_L33N_4

IO_L33P_4

IO_L34N_4

IO_L34P_4

IO_L35N_4

IO_L35P_4

IO_L36N_4

IO_L36P_4

IO_L37N_4

IO_L37P_4

IO_L38N_4

IO_L38P_4

IO_L39N_4

IO_L39P_4

IO_L40N_4

IO_L40P_4

VCCO_4

AL29

AM29

AN29

AP29

AJ28

AK28

AL28

AM28

AN28

AP28

AK27

AL27

AH24

AJ24

AN24

AP24

AC19

AC20

AC21

AC22

AG20

AG24

AH27

AJ22

AL19

AL24

AM27

I/O

5

IO

I/O

5

IO

I/O

5

IO

I/O

5

IO

I/O

5

IO/VREF_5

AJ8

VREF

DUAL

I/O

5

AL5

I/O

5

AP17

AP3

I/O

5

IO_L01N_5/

RDWR_B

IO_L01N_5/

RDWR_B

I/O

5

IO_L01P_5/

CS_B

IO_L01P_5/

CS_B

AN3

DUAL

I/O

5

IO_L02N_5

IO_L02P_5

IO_L03N_5

IO_L03P_5

IO_L04N_5

IO_L04P_5

IO_L05N_5

IO_L05P_5

IO_L06N_5

IO_L06P_5

IO_L07N_5

IO_L07P_5

IO_L08N_5

IO_L08P_5

IO_L09N_5

IO_L09P_5

IO_L02N_5

IO_L02P_5

IO_L03N_5

IO_L03P_5

IO_L04N_5

IO_L04P_5

IO_L05N_5

IO_L05P_5

IO_L06N_5

IO_L06P_5

IO_L07N_5

IO_L07P_5

IO_L08N_5

IO_L08P_5

IO_L09N_5

IO_L09P_5

AP4

AN4

AN5

AM5

AM6

AL6

I/O

VCCO

VCCO_4

AP6

VCCO_4

AN6

AK7

VCCO_4

AJ7

VCCO_4

AG10

AF10

AJ10

AH10

AM10

AL10

VCCO_4

DS099-4 (v1.5) July 13, 2004

Product Specification

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91

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 37: FG1156 Package Pinout (Continued)

FG1156

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

Bank

Type

Bank

Type

5

IO_L10N_5/

VRP_5

IO_L10N_5/

VRP_5

AP10

AN10

AP11

DCI

5

IO_L28P_5/

D7

IO_L28P_5/

D7

AM16

DUAL

5

IO_L10P_5/

VRN_5

IO_L10P_5/

VRN_5

DCI

5

IO_L29N_5

AF17

AE17

I/O

IO_L29P_5/

VREF_5

IO_L29P_5/

VREF_5

VREF

IO_L11N_5/

VREF_5

IO_L11N_5/

VREF_5

VREF

5

IO_L30N_5

IO_L30P_5

IO_L30N_5

IO_L30P_5

AH17

AG17

AL17

I/O

5

IO_L11P_5

IO_L12N_5

IO_L12P_5

IO_L13N_5

IO_L13P_5

IO_L14N_5

IO_L14P_5

IO_L15N_5

IO_L15P_5

IO_L16N_5

IO_L16P_5

IO_L17N_5

IO_L17P_5

IO_L18N_5

IO_L18P_5

IO_L19N_5

IO_L11P_5

IO_L12N_5

IO_L12P_5

IO_L13N_5

IO_L13P_5

IO_L14N_5

IO_L14P_5

IO_L15N_5

IO_L15P_5

IO_L16N_5

IO_L16P_5

IO_L17N_5

IO_L17P_5

IO_L18N_5

IO_L18P_5

IO_L19N_5

AN11

AF12

AE12

AJ12

AH12

AL12

AK12

AP12

AN12

AE13

AD13

AH13

AG13

AM13

AL13

AG14

AF14

I/O

VREF

IO_L31N_5/

D4

IO_L31N_5/

D4

DUAL

5

IO_L31P_5/

D5

IO_L31P_5/

D5

AK17

AN17

AM17

DUAL

GCLK

IO_L32N_5/

GCLK3

IO_L32N_5/

GCLK3

IO_L32P_5/

GCLK2

IO_L32P_5/

GCLK2

5

N.C. ()

IO_L35N_5

IO_L35P_5

IO_L36N_5

IO_L36P_5

IO_L37N_5

IO_L37P_5

IO_L38N_5

IO_L38P_5

N.C. ()

VCCO_5

IO_L33N_5

IO_L33P_5

IO_L34N_5

IO_L34P_5

IO_L35N_5

IO_L35P_5

IO_L36N_5

IO_L36P_5

IO_L37N_5

IO_L37P_5

IO_L38N_5

IO_L38P_5

IO_L39N_5

IO_L39P_5

IO_L40N_5

IO_L40P_5

VCCO_5

AM7

AL7

I/O

AP7

I/O

AN7

I/O

AL8

I/O

AK8

I/O

AP8

I/O

AN8

I/O

IO_L19P_5/

VREF_5

IO_L19P_5/

VREF_5

AJ9

I/O

AH9

I/O

5

IO_L20N_5

IO_L20P_5

IO_L21N_5

IO_L21P_5

IO_L22N_5

IO_L22P_5

IO_L23N_5

IO_L23P_5

IO_L24N_5

IO_L24P_5

IO_L25N_5

IO_L25P_5

IO_L26N_5

IO_L26P_5

IO_L20N_5

IO_L20P_5

IO_L21N_5

IO_L21P_5

IO_L22N_5

IO_L22P_5

IO_L23N_5

IO_L23P_5

IO_L24N_5

IO_L24P_5

IO_L25N_5

IO_L25P_5

IO_L26N_5

IO_L26P_5

AJ14

AH14

AM14

AL14

AP14

AN14

AF15

AE15

AJ15

AH15

AM15

AL15

AP15

AN15

AJ16

I/O

VREF

AM9

AL9

I/O

AF11

AE11

AJ11

AH11

AC13

AC14

AC15

AC16

AG11

AG15

AH8

I/O

VCCO

VCCO_5

AJ13

AL11

AL16

AM4

AM8

IO_L27N_5/

VREF_5

IO_L27N_5/

VREF_5

VCCO_5

5

IO_L27P_5

AH16

AN16

I/O

VCCO_5

IO_L28N_5/

D6

IO_L28N_5/

D6

DUAL

VCCO_5

92

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Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 37: FG1156 Package Pinout (Continued)

FG1156

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

Bank

Type

VCCO

I/O

Bank

Type

I/O

5

6

VCCO_5

AN13

AH1

AH2

V9

6

IO_L17N_6

AD10

AD9

IO

IO_L17P_6/

VREF_6

IO_L17P_6/

VREF_6

VREF

I/O

6

IO_L19N_6

IO_L19P_6

IO_L20N_6

IO_L20P_6

IO_L21N_6

IO_L21P_6

IO_L22N_6

IO_L22P_6

IO_L23N_6

IO_L23P_6

IO_L19N_6

IO_L19P_6

IO_L20N_6

IO_L20P_6

IO_L21N_6

IO_L21P_6

IO_L22N_6

IO_L22P_6

IO_L23N_6

IO_L23P_6

AD2

AD1

AC11

AC10

AC8

AC7

AC6

AC5

AC2

AC1

AC9

I/O

V10

AM2

I/O

IO_L01N_6/

VRP_6

IO_L01N_6/

VRP_6

DCI

I/O

6

IO_L01P_6/

VRN_6

IO_L01P_6/

VRN_6

AM1

DCI

I/O

6

IO_L02N_6

IO_L02P_6

IO_L02N_6

IO_L02P_6

AL2

AL1

AK3

I/O

IO_L03N_6/

VREF_6

IO_L03N_6/

VREF_6

VREF

I/O

6

IO_L03P_6

IO_L04N_6

IO_L04P_6

IO_L05N_6

IO_L05P_6

IO_L06N_6

IO_L06P_6

IO_L07N_6

IO_L07P_6

IO_L08N_6

IO_L08P_6

IO_L03P_6

IO_L04N_6

IO_L04P_6

IO_L05N_6

IO_L05P_6

IO_L06N_6

IO_L06P_6

IO_L07N_6

IO_L07P_6

IO_L08N_6

IO_L08P_6

AK2

AJ4

AJ3

AJ2

AJ1

AH6

AH5

AG6

AG5

AG2

AG1

AF7

I/O

IO_L24N_6/

VREF_6

IO_L24N_6/

VREF_6

VREF

I/O

6

IO_L24P_6

IO_L25N_6

IO_L25P_6

IO_L26N_6

IO_L26P_6

IO_L27N_6

IO_L27P_6

IO_L28N_6

IO_L28P_6

IO_L29N_6

IO_L29P_6

IO_L30N_6

IO_L30P_6

IO_L31N_6

IO_L31P_6

IO_L32N_6

IO_L32P_6

IO_L33N_6

IO_L33P_6

IO_L24P_6

IO_L25N_6

IO_L25P_6

IO_L26N_6

IO_L26P_6

IO_L27N_6

IO_L27P_6

IO_L28N_6

IO_L28P_6

IO_L29N_6

IO_L29P_6

IO_L30N_6

IO_L30P_6

IO_L31N_6

IO_L31P_6

IO_L32N_6

IO_L32P_6

IO_L33N_6

IO_L33P_6

AB10

AB8

AB7

AB4

AB3

AB11

AA11

AA8

AA7

AA6

AA5

AA4

AA3

AA2

AA1

Y11

Y10

Y4

I/O

VREF

I/O

IO_L09N_6/

VREF_6

IO_L09N_6/

VREF_6

VREF

6

IO_L09P_6

IO_L10N_6

IO_L10P_6

IO_L11N_6

IO_L11P_6

IO_L12N_6

IO_L12P_6

IO_L13N_6

IO_L09P_6

IO_L10N_6

IO_L10P_6

IO_L11N_6

IO_L11P_6

IO_L12N_6

IO_L12P_6

IO_L13N_6

AF6

AG4

AF4

AF3

AF2

AF8

AE9

AE8

AE7

I/O

Y3

IO_L13P_6/

VREF_6

IO_L13P_6/

VREF_6

VREF

IO_L34N_6/

VREF_6

IO_L34N_6/

VREF_6

Y2

6

IO_L14N_6

IO_L14P_6

IO_L15N_6

IO_L15P_6

IO_L16N_6

IO_L16P_6

IO_L14N_6

IO_L14P_6

IO_L15N_6

IO_L15P_6

IO_L16N_6

IO_L16P_6

AE6

AE5

AE4

AE3

AE2

AE1

I/O

6

IO_L34P_6

IO_L35N_6

IO_L35P_6

IO_L36N_6

IO_L36P_6

IO_L37N_6

IO_L34P_6

IO_L35N_6

IO_L35P_6

IO_L36N_6

IO_L36P_6

IO_L37N_6

Y1

Y9

I/O

W10

W7

W6

W3

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

93

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 37: FG1156 Package Pinout (Continued)

FG1156

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

Bank

Type

I/O

Bank

Type

6

IO_L37P_6

IO_L38N_6

IO_L38P_6

IO_L39N_6

IO_L39P_6

IO_L40N_6

IO_L37P_6

IO_L38N_6

IO_L38P_6

IO_L39N_6

IO_L39P_6

IO_L40N_6

W2

V6

V5

V4

V3

V2

V1

7

IO_L01P_7/

VRN_7

IO_L01P_7/

VRN_7

C2

DCI

I/O

7

IO_L02N_7

IO_L02P_7

IO_L02N_7

IO_L02P_7

D1

D2

E2

I/O

IO_L03N_7/

VREF_7

IO_L03N_7/

VREF_7

VREF

I/O

7

IO_L03P_7

IO_L04N_7

IO_L04P_7

IO_L05N_7

IO_L05P_7

IO_L06N_7

IO_L06P_7

IO_L07N_7

IO_L07P_7

IO_L08N_7

IO_L08P_7

IO_L09N_7

IO_L09P_7

IO_L10N_7

IO_L03P_7

IO_L04N_7

IO_L04P_7

IO_L05N_7

IO_L05P_7

IO_L06N_7

IO_L06P_7

IO_L07N_7

IO_L07P_7

IO_L08N_7

IO_L08P_7

IO_L09N_7

IO_L09P_7

IO_L10N_7

E3

F3

F4

F1

F2

G5

G6

H5

H6

H1

H2

J6

I/O

IO_L40P_6/

VREF_6

IO_L40P_6/

VREF_6

VREF

I/O

6

7

N.C. ()

IO_L45N_6

IO_L45P_6

N.C. ()

IO_L48N_6

IO_L48P_6

N.C. ()

IO_L52N_6

IO_L52P_6

VCCO_6

IO

IO_L41N_6

IO_L41P_6

IO_L44N_6

IO_L44P_6

IO_L45N_6

IO_L45P_6

IO_L46N_6

IO_L46P_6

IO_L48N_6

IO_L48P_6

IO_L49N_6

IO_L49P_6

IO_L52N_6

IO_L52P_6

VCCO_6

IO

AH4

AH3

AD7

AD6

AC4

AC3

AA10

AA9

Y7

I/O

Y6

I/O

J7

I/O

W11

V11

V8

I/O

J4

I/O

IO_L10P_7/

VREF_7

IO_L10P_7/

VREF_7

H4

VREF

I/O

V7

I/O

7

IO_L11N_7

IO_L11P_7

IO_L12N_7

IO_L12P_7

IO_L13N_7

IO_L13P_7

IO_L14N_7

IO_L14P_7

IO_L15N_7

IO_L15P_7

IO_L16N_7

IO_L11N_7

IO_L11P_7

IO_L12N_7

IO_L12P_7

IO_L13N_7

IO_L13P_7

IO_L14N_7

IO_L14P_7

IO_L15N_7

IO_L15P_7

IO_L16N_7

J2

J3

I/O

AA12

AB12

AB2

AB6

AD4

AD8

AG3

AG7

AL3

W12

W4

VCCO

I/O

K9

J8

I/O

K7

K8

K5

K6

K3

K4

K1

K2

I/O

IO_L16P_7/

VREF_7

IO_L16P_7/

VREF_7

VREF

Y12

Y8

7

IO_L17N_7

IO_L17P_7

IO_L17N_7

IO_L17P_7

L9

L10

L1

I/O

G1

IO

G2

I/O

IO_L19N_7/

VREF_7

IO_L19N_7/

VREF_7

VREF

IO

U10

U9

I/O

7

IO_L19P_7

IO_L20N_7

IO_L20P_7

IO_L19P_7

IO_L20N_7

IO_L20P_7

L2

I/O

IO

I/O

M10

M11

IO_L01N_7/

VRP_7

IO_L01N_7/

VRP_7

C1

DCI

94

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DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 37: FG1156 Package Pinout (Continued)

FG1156

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

Bank

Type

I/O

Bank

7

Type

I/O

7

IO_L21N_7

IO_L21P_7

IO_L22N_7

IO_L22P_7

IO_L23N_7

IO_L23P_7

IO_L24N_7

IO_L24P_7

IO_L25N_7

IO_L25P_7

IO_L26N_7

IO_L26P_7

IO_L27N_7

IO_L21N_7

IO_L21P_7

IO_L22N_7

IO_L22P_7

IO_L23N_7

IO_L23P_7

IO_L24N_7

IO_L24P_7

IO_L25N_7

IO_L25P_7

IO_L26N_7

IO_L26P_7

IO_L27N_7

M7

M8

M5

M6

M3

M4

N10

M9

N3

N.C. ()

IO_L45N_7

IO_L45P_7

IO_L46N_7

IO_L46P_7

N.C. ()

IO_L49N_7

IO_L49P_7

IO_L50N_7

IO_L50P_7

N.C. ()

VCCO_7

GND

IO_L41P_7

IO_L44N_7

IO_L44P_7

IO_L45N_7

IO_L45P_7

IO_L46N_7

IO_L46P_7

IO_L47N_7

IO_L47P_7

IO_L49N_7

IO_L49P_7

IO_L50N_7

IO_L50P_7

IO_L51N_7

IO_L51P_7

VCCO_7

GND

G4

L6

I/O

7

I/O

7

L7

I/O

7

M1

M2

N7

I/O

7

I/O

7

I/O

7

N8

I/O

7

P9

I/O

7

P10

P1

I/O

N4

I/O

7

I/O

P11

N11

P7

I/O

7

P2

I/O

7

R10

R11

U11

T11

D3

I/O

7

I/O

IO_L27P_7/

VREF_7

IO_L27P_7/

VREF_7

P8

VREF

7

I/O

7

I/O

7

IO_L28N_7

IO_L28P_7

IO_L29N_7

IO_L29P_7

IO_L30N_7

IO_L30P_7

IO_L31N_7

IO_L31P_7

IO_L32N_7

IO_L32P_7

IO_L33N_7

IO_L33P_7

IO_L34N_7

IO_L34P_7

IO_L35N_7

IO_L35P_7

IO_L37N_7

IO_L28N_7

IO_L28P_7

IO_L29N_7

IO_L29P_7

IO_L30N_7

IO_L30P_7

IO_L31N_7

IO_L31P_7

IO_L32N_7

IO_L32P_7

IO_L33N_7

IO_L33P_7

IO_L34N_7

IO_L34P_7

IO_L35N_7

IO_L35P_7

IO_L37N_7

P5

P6

P3

P4

R6

R7

R3

R4

R1

R2

T10

R9

T6

I/O

VREF

7

VCCO

GND

7

H3

7

H7

7

L4

7

L8

7

N12

N2

7

N6

7

P12

R12

R8

7

T12

T4

7

T7

N/A

A1

T2

GND

A13

A16

A19

A2

T3

GND

U7

U8

GND

IO_L37P_7/

VREF_7

IO_L37P_7/

VREF_7

GND

A22

A26

A30

A33

A34

A5

7

IO_L38N_7

IO_L38P_7

IO_L39N_7

IO_L39P_7

IO_L38N_7

IO_L38P_7

IO_L39N_7

IO_L39P_7

U5

U6

U3

U4

U1

I/O

GND

I/O

GND

I/O

GND

IO_L40N_7/

VREF_7

IO_L40N_7/

VREF_7

VREF

GND

A9

7

IO_L40P_7

IO_L41N_7

U2

G3

I/O

GND

AA14

N.C. ()

DS099-4 (v1.5) July 13, 2004

Product Specification

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1-800-255-7778

95

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 37: FG1156 Package Pinout (Continued)

FG1156

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

Bank

N/A

Type

GND

Bank

N/A

Type

GND

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AB1

GND

AM3

AM32

AN1

AN2

AN33

AN34

AP1

AP13

AP16

AP19

AP2

AP22

AP26

AP30

AP33

AP34

AP5

AP9

B1

GND

AB17

AB18

AB26

AB30

AB34

AB5

AB9

AD3

AD32

AE10

AE25

AF1

B2

AF13

AF16

AF19

AF22

AF30

AF34

AF5

B33

B34

C11

C24

C3

C32

E1

AH28

AH7

E13

E16

E19

E22

E26

E30

E34

E5

AK1

AK13

AK16

AK19

AK22

AK26

AK30

AK34

AK5

E9

G28

G7

AK9

J1

AM11

AM24

J13

J16

96

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 37: FG1156 Package Pinout (Continued)

FG1156

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

Bank

N/A

Type

GND

Bank

N/A

Type

GND

J19

J22

J30

J34

J5

GND

T21

T26

T30

T34

T5

GND

K10

K25

L3

T9

U13

U14

U15

U16

U17

U18

U19

U20

U21

U22

V13

V14

V15

V16

V17

V18

V19

V20

V21

V22

W1

L32

N1

N17

N18

N26

N30

N34

N5

N9

P14

P15

P16

P17

P18

P19

P20

P21

R14

R15

R16

R17

R18

R19

R20

R21

T1

W14

W15

W16

W17

W18

W19

W20

W21

W26

W30

W34

W5

T14

T15

T16

T17

T18

T19

T20

W9

Y14

DS099-4 (v1.5) July 13, 2004

Product Specification

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1-800-255-7778

97

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 37: FG1156 Package Pinout (Continued)

FG1156

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

XC3S4000

Pin Name

XC3S5000

Pin Name

Number

Bank

N/A

Type

Bank

N/A

Type

GND

Y15

Y16

Y17

Y18

Y19

Y20

Y21

AK31

AD30

AD5

AG16

AG19

AJ30

AJ5

AK11

AK15

AK20

AK24

AK29

AK6

E11

E15

E20

E24

E29

E6

GND

VCCINT

CCLK

AA22

AB13

AB14

AB15

AB16

AB19

AB20

AB21

AB22

AC12

AC17

AC18

AC23

M12

M17

M18

M23

N13

VCCINT

CONFIG

GND

N.C. ()

VCCAUX

VCCINT

N.C. ()

VCCAUX

VCCINT

N.C.

VCCAUX

VCCINT

N14

N15

N16

N19

N20

N21

N22

P13

F30

F5

P22

R13

H16

H19

L30

R22

T13

T22

L5

U12

R30

R5

U23

V12

T27

T8

V23

W13

W22

Y13

W27

W8

Y30

Y5

Y22

VCCAUX CCLK

VCCAUX DONE

AL31

AD24

AA13

DONE

98

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DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

Table 37: FG1156 Package Pinout (Continued)

User I/Os by Bank

FG1156

Number

Table 38 indicates how the available user-I/O pins are dis-

tributed between the eight I/O banks for the XC3S4000 in

the FG1156 package. Similarly, Table 39 shows how the

available user-I/O pins are distributed between the eight I/O

banks for the XC3S5000 in the FG1156 package.

XC3S4000

Pin Name

XC3S5000

Pin Name

Bank

Type

CONFIG

JTAG

VCCAUX HSWAP_EN

VCCAUX M0

HSWAP_EN

M0

L11

AL4

AK4

AG8

D4

VCCAUX M1

M1

VCCAUX M2

M2

VCCAUX PROG_B

VCCAUX TCK

VCCAUX TDI

PROG_B

TCK

D31

E4

TDI

JTAG

VCCAUX TDO

VCCAUX TMS

TDO

E31

H27

JTAG

TMS

JTAG

Table 38: User I/Os Per Bank for XC3S4000 in FG1156 Package

All Possible I/O Pins by Type

I/O

Bank

Maximum

I/O

Package Edge

I/O

79

80

79

73

79

DUAL

DCI

2

VREF

GCLK

0

1

2

3

4

5

6

7

90

88

90

88

0

6

0

7

6

7

2

0

2

0

Top

2

Right

Bottom

Left

2

Table 39: User I/Os Per Bank for XC3S5000 in FG1156 Package

All Possible I/O Pins by Type

I/O

Bank

Maximum

I/O

Package Edge

I/O

89

87

83

87

DUAL

DCI

2

VREF

GCLK

0

1

2

3

4

5

6

7

100

96

0

6

0

7

2

0

2

0

Top

2

Right

Bottom

Left

96

2

100

96

2

96

2

DS099-4 (v1.5) July 13, 2004

Product Specification

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1-800-255-7778

99

R

Spartan-3 FPGA Family: Pinout Descriptions

FG1156 Footprint

Top Left Corner of

Package (top view)

XC3S4000

(712 max. user I/O)

I/O: Unrestricted,

general-purpose user I/O

VREF: User I/O or input voltage

reference for bank

N.C.: Unconnected pins for

XC3S4000 ()

621

55

56

73

1

XC3S5000

(784 max. user I/O)

I/O: Unrestricted,

general-purpose user I/O

VREF: User I/O or input voltage

reference for bank

N.C.: Unconnected pins for

XC3S5000 ()

692

Figure 16: FG1156 Package Footprint (top view)

Bank 0

1

2

3

I/O

L01P_0

VRN_0

4

5

6

I/O

L05P_0

VREF_0

7

8

9

10

11

12

13

14

15

I/O

L26P_0

VREF_0

16

17

I/O

L32P_0

GCLK6

I/O

L02P_0

I/O

L36P_0

I/O

L38P_0

I/O

L15P_0

I/O

L22P_0

L34P_0

L40P_0

GND

A

B

C

D

E

F

I/O

L34N_0

I/O

L40N_0

I/O

L01N_0

VRP_0

I/O

L32N_0

GCLK7

I/O

L02N_0

I/O

L03P_0

I/O

L05N_0

I/O

L36N_0

I/O

L38N_0

I/O

L15N_0

I/O

L22N_0

I/O

L26N_0

I/O

L28P_0

GND

VCCO_0

I/O

L33P_0

I/O

L01N_7

VRP_7

I/O

L01P_7

VRN_7

I/O

L31P_0

VREF_0

I/O

L03N_0

I/O

L04P_0

I/O

L08P_0

I/O

L37P_0

I/O

L14P_0

I/O

L17P_0

I/O

L21P_0

I/O

L25P_0

I/O

L28N_0

VCCO_0

GND

I/O

L33N_0

IO

VREF_0

I/O

L02N_7

I/O

L02P_7

I/O

L04N_0

I/O

L35P_0

I/O

L08N_0

I/O

L37N_0

I/O

L14N_0

I/O

L17N_0

I/O

L21N_0

I/O

L25N_0

I/O

L31N_0

VCCO_7 PROG_B

VCCO_0

VCCAUX

VCCO_0

GND

I/O

L03N_7

VREF_7

IO

VREF_0

I/O

TDI

I/O

L06P_0

I/O

L35N_0

I/O

L13P_0

I/O

L20P_0

GND

VCCAUX

I/O

GND

VCCAUX

I/O

GND

L03P_7

I/O

L39P_0

I/O

L05N_7

I/O

L05P_7

I/O

L04N_7

I/O

L04P_7

I/O

L06N_0

I/O

L07P_0

I/O

L10P_0

I/O

L13N_0

I/O

L20N_0

I/O

L24P_0

I/O

L27P_0

I/O

L30P_0

VCCAUX

VCCO_0

I/O

VCCO_0

I/O

L41N_7

I/O

L41P_7

I/O

L39N_0

I/O

L06N_7

I/O

L06P_7

I/O

L07N_0

I/O

L10N_0

I/O

L16P_0

I/O

L19P_0

I/O

L24N_0

I/O

L27N_0

I/O

L30N_0

I/O

GND

I/O

G

H

J

I/O

L10P_7

VREF_7

I/O

L08N_7

I/O

L08P_7

I/O

L07N_7

I/O

L07P_7

I/O

L09P_0

I/O

L12P_0

I/O

L16N_0

I/O

L19N_0

I/O

L29P_0

VCCO_7

VCCO_0

VCCO_0 VCCAUX

I/O

IO

VREF_0

I/O

L11N_7

I/O

L11P_7

I/O

L10N_7

I/O

L09N_7

I/O

L09P_7

I/O

L12P_7

I/O

L09N_0

I/O

L12N_0

I/O

L23P_0

I/O

L29N_0

GND

I/O

GND

I/O

GND

I/O

L16P_7

VREF_7

I/O

L16N_7

I/O

L15N_7

I/O

L15P_7

I/O

L14N_7

I/O

L14P_7

I/O

L13N_7

I/O

L13P_7

I/O

L12N_7

I/O

L11P_0

I/O

L18P_0

I/O

GND

I/O

K

L

L23N_0

I/O

L44N_7

I/O

L44P_7

I/O

L19N_7

VREF_7

HSWAP_

EN

IO

I/O

L19P_7

I/O

L17N_7

I/O

L17P_7

I/O

L11N_0

I/O

L18N_0

GND

VCCO_7 VCCAUX

VCCO_7

I/O

VREF_0

I/O

L45N_7

I/O

L45P_7

I/O

L23N_7

I/O

L23P_7

I/O

L22N_7

I/O

L22P_7

I/O

L21N_7

I/O

L21P_7

I/O

L24P_7

I/O

L20N_7

I/O

L20P_7

VCCO_0 VCCO_0 VCCO_0 VCCO_0

VCCINT VCCINT VCCINT VCCINT

VCCINT

VCCO_7

VCCINT

GND

M

N

P

R

T

I/O

L25N_7

I/O

L25P_7

I/O

L46N_7

I/O

L46P_7

I/O

L24N_7

I/O

L26P_7

VCCO_7

GND

VCCO_7

GND

I/O

L47N_7

I/O

L47P_7

I/O

L27P_7

VREF_7

I/O

L49N_7

I/O

L49P_7

I/O

L29N_7

I/O

L29P_7

I/O

L28N_7

I/O

L28P_7

I/O

L27N_7

I/O

L26N_7

GND

VCCINT

GND

I/O

L32N_7

I/O

L32P_7

I/O

L31N_7

I/O

L31P_7

I/O

L30N_7

I/O

L30P_7

I/O

L33P_7

I/O

L50N_7

I/O

L50P_7

VCCAUX

GND

VCCO_7

VCCAUX

I/O

L51P_7

I/O

L35N_7

I/O

L35P_7

I/O

L34N_7

I/O

L34P_7

I/O

L33N_7

VCCO_7

GND

I/O

GND

I/O

L51N_7

I/O

L40N_7

VREF_7

I/O

L37P_7

VREF_7

I/O

L40P_7

I/O

L39N_7

I/O

L39P_7

I/O

L38N_7

I/O

L38P_7

I/O

L37N_7

U

I/O

DS099-4_14a_072903

100

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

All Devices

Top Right Corner of

Package (top view)

DUAL: Configuration pin, then

possible user I/O

DCI: User I/O or reference

resistor input for bank

GCLK: User I/O or global clock

buffer input

12

7

16

4

8

CONFIG: Dedicated

configuration pins

JTAG: Dedicated JTAG port

pins

VCCO: Output voltage supply

for bank

104

184

VCCINT: Internal core voltage

supply (+1.2V)

VCCAUX: Auxiliary voltage

supply (+2.5V)

GND: Ground

40

32

Bank 1

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

I/O

L01N_1

VRP_1

33

34

I/O

L40N_1

I/O

L26N_1

I/O

L19N_1

I/O

L15N_1

I/O

L14N_1

I/O

L08N_1

I/O

L05N_1

I/O

L02N_1

L34N_1

I/O

GND

A

B

C

D

E

F

GND

I/O

L34P_1

I/O

L32N_1

GCLK5

I/O

L01P_1

VRN_1

I/O

L28N_1

I/O

L40P_1

I/O

L26P_1

I/O

L19P_1

I/O

L15P_1

I/O

L14P_1

I/O

L08P_1

I/O

L05P_1

I/O

L03N_1

I/O

L02P_1

VCCO_1

I/O

GND

I/O

L33N_1

I/O

L32P_1

GCLK4

I/O

L10N_1

VREF_1

I/O

L01N_2

VRP_2

I/O

L01P_2

VRN_2

I/O

L28P_1

I/O

L39N_1

I/O

L25N_1

I/O

L22N_1

I/O

L13N_1

I/O

L04N_1

I/O

L03P_1

GND

VCCO_1

I/O

GND

I/O

L33P_1

I/O

L31N_1

VREF_1

IO

VREF_1

I/O

L39P_1

I/O

L25P_1

I/O

L22P_1

I/O

L18N_1

I/O

L13P_1

I/O

L10P_1

I/O

L07N_1

I/O

L04P_1

I/O

L02N_2

I/O

L02P_2

VCCO_1

GND

VCCO_1

VCCAUX

VCCO_2

TCK

TDO

I/O

L06N_1

VREF_1

I/O

L03N_2

VREF_2

I/O

L31P_1

I/O

L18P_1

I/O

L07P_1

I/O

L03P_2

VCCAUX

I/O

GND

I/O

GND

I/O

L36N_1

I/O

L17N_1

VREF_1

I/O

L27N_1

I/O

L38N_1

I/O

L24N_1

I/O

L12N_1

I/O

L09N_1

I/O

L06P_1

I/O

L04N_2

I/O

L04P_2

I/O

L41N_2

I/O

L41P_2

VCCO_1

VCCAUX

I/O

L36P_1

I/O

L42N_2

I/O

L42P_2

I/O

L30N_1

I/O

L27P_1

I/O

L38P_1

I/O

L24P_1

I/O

L21N_1

I/O

L17P_1

I/O

L12P_1

I/O

L09P_1

I/O

L05N_2

I/O

L05P_2

I/O

VCCO_1

TMS

GND

G

H

J

I/O

L09N_2

VREF_2

I/O

L30P_1

I/O

L23N_1

I/O

L21P_1

I/O

L11N_1

I/O

L06N_2

I/O

L06P_2

I/O

L07N_2

I/O

L07P_2

VCCAUX VCCO_1

VCCO_1

VCCO_2

I/O

L35N_1

I/O

L29N_1

I/O

L37N_1

I/O

L23P_1

I/O

L16N_1

I/O

L11P_1

I/O

L11N_2

I/O

L08N_2

I/O

L08P_2

I/O

L09P_2

I/O

L10N_2

I/O

L10P_2

GND

I/O

L35P_1

I/O

L13P_2

VREF_2

IO

VREF_1

I/O

L29P_1

I/O

L20N_1

I/O

L16P_1

I/O

L11P_2

I/O

L12N_2

I/O

L12P_2

I/O

L13N_2

I/O

L14N_2

I/O

L14P_2

I/O

L15N_2

I/O

L15P_2

GND

K

L

L37P_1

I/O

L17N_2

I/O

L17P_2

VREF_2

IO

VREF_1

I/O

L20P_1

I/O

L16N_2

I/O

L16P_2

I/O

L45N_2

I/O

L45P_2

GND

VCCO_2

VCCAUX VCCO_2

I/O

L46N_2

I/O

L46P_2

I/O

L21N_2

I/O

L47N_2

I/O

L47P_2

I/O

L19N_2

I/O

L19P_2

I/O

L20N_2

I/O

L20P_2

I/O

L48N_2

I/O

L48P_2

VCCO_1 VCCO_1 VCCO_1 VCCO_1

VCCINT VCCINT VCCINT VCCINT

VCCINT

GND

VCCINT

VCCO_2

VCCINT

M

N

P

R

T

I/O

L23N_2

VREF_2

I/O

L24N_2

I/O

L21P_2

I/O

L22N_2

I/O

L22P_2

I/O

L23P_2

GND

VCCO_2

GND

I/O

L49N_2

I/O

L49P_2

I/O

L24P_2

I/O

L50N_2

I/O

L50P_2

I/O

L26N_2

I/O

L26P_2

I/O

L27N_2

I/O

L27P_2

I/O

L28N_2

I/O

L28P_2

GND

I/O

L29N_2

I/O

L29P_2

I/O

L33N_2

I/O

L30N_2

I/O

L30P_2

I/O

L31N_2

I/O

L31P_2

I/O

L32N_2

I/O

L32P_2

VCCO_2

VCCAUX

GND

VCCINT

GND

I/O

L51N_2

I/O

L34N_2

VREF_2

I/O

L33P_2

I/O

L34P_2

I/O

L35N_2

I/O

L35P_2

VCCO_2

GND

I/O

GND

I/O

L51P_2

I/O

L40P_2

VREF_2

I/O

L37N_2

I/O

L37P_2

I/O

L38N_2

I/O

L38P_2

I/O

L39N_2

I/O

L39P_2

I/O

L40N_2

I/O

U

DS099-4_14b_072903

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

101

R

Spartan-3 FPGA Family: Pinout Descriptions

1

I/O

L40P_6

VREF_6

2

3

4

5

6

7

8

9

10

11

I/O

L49P_6

12

13

14

15

16

17

I/O

L40N_6

I/O

L39P_6

I/O

L39N_6

I/O

L38P_6

I/O

L38N_6

I/O

L52P_6

I/O

L52N_6

VCCINT

V

W

Y

I/O

GND

I/O

L49N_6

I/O

L37P_6

I/O

L37N_6

I/O

L36P_6

I/O

L36N_6

I/O

L35P_6

GND

VCCO_6

GND

VCCAUX

VCCO_6

GND

VCCO_6

VCCINT

GND

I/O

L34N_6

VREF_6

I/O

L34P_6

I/O

L33P_6

I/O

L33N_6

I/O

L48P_6

I/O

L48N_6

I/O

L35N_6

I/O

L32P_6

I/O

L32N_6

VCCAUX

GND

I/O

L46P_6

I/O

L46N_6

A

I/O

L31P_6

I/O

L31N_6

I/O

L30P_6

I/O

L30N_6

I/O

L29P_6

I/O

L29N_6

I/O

L28P_6

I/O

L28N_6

I/O

L27P_6

A

B

I/O

L26P_6

I/O

L26N_6

I/O

L25P_6

I/O

L25N_6

I/O

L24P_6

I/O

L27N_6

VCCO_6

GND

VCCINT VCCINT VCCINT VCCINT

I/O

L24N_6

VREF_6

A

C

I/O

L23P_6

I/O

L23N_6

I/O

L45P_6

I/O

L45N_6

I/O

L22P_6

I/O

L22N_6

I/O

L21P_6

I/O

L21N_6

I/O

L20P_6

I/O

L20N_6

VCCO_5 VCCO_5 VCCO_5 VCCO_5

VCCINT

I/O

L44P_6

I/O

L44N_6

I/O

L17P_6

VREF_6

I/O

A

D

I/O

L19P_6

I/O

L19N_6

I/O

L17N_6

I/O

L16P_5

VCCO_6 VCCAUX

VCCO_6

I/O

GND

I/O

L39P_5

I/O

L13P_6

VREF_6

I/O

L29P_5

VREF_5

A

E

I/O

L16P_6

I/O

L16N_6

I/O

L15P_6

I/O

L15N_6

I/O

L14P_6

I/O

L14N_6

I/O

L13N_6

I/O

L12P_6

I/O

L12P_5

I/O

L16N_5

I/O

L23P_5

GND

I/O

L39N_5

I/O

L09N_6

VREF_6

I/O

L19P_5

VREF_5

I/O

A

F

I/O

L11P_6

I/O

L11N_6

I/O

L10P_6

I/O

L09P_6

I/O

L12N_6

I/O

L07P_5

I/O

L12N_5

I/O

L23N_5

I/O

L29N_5

GND

A

G

I/O

L08P_6

I/O

L08N_6

I/O

L10N_6

I/O

L07P_6

I/O

L07N_6

I/O

L07N_5

I/O

L17P_5

I/O

L19N_5

I/O

L30P_5

VCCO_6

GND

VCCO_5

VCCO_5 VCCAUX

M2

I/O

L41P_6

I/O

L41N_6

I/O

L40P_5

A

H

I/O

L06P_6

I/O

L06N_6

I/O

L37P_5

I/O

L08P_5

I/O

L13P_5

I/O

L17N_5

I/O

L20P_5

I/O

L30N_5

I/O

VCCO_5

L24P_5

L27P_5

I/O

L40N_5

I/O

L27N_5

VREF_5

A

J

IO

VREF_5

I/O

L05P_6

I/O

L05N_6

I/O

L04P_6

I/O

L04N_6

I/O

L06P_5

I/O

L37N_5

I/O

L08N_5

I/O

L13N_5

I/O

L20N_5

I/O

L24N_5

VCCAUX

GND

VCCO_5

GND

I/O

L03N_6

VREF_6

I/O

L31P_5

D5

A

K

I/O

L03P_6

I/O

L06N_5

I/O

L35P_5

I/O

L14P_5

VCCAUX

VCCO_5

GND

VCCAUX

M1

M0

I/O

GND

I/O

L33P_5

I/O

L31N_5

D4

A

L

IO

VREF_5

I/O

L02P_6

I/O

L02N_6

I/O

L04P_5

I/O

L35N_5

I/O

L38P_5

I/O

L09P_5

I/O

L14N_5

I/O

L18P_5

I/O

L21P_5

I/O

L25P_5

VCCO_6

GND

VCCO_5

I/O

L33N_5

I/O

L01P_6

VRN_6

I/O

L01N_6

VRP_6

I/O

L28P_5

D7

I/O

L32P_5

GCLK2

A

M

I/O

L03P_5

I/O

L04N_5

I/O

L38N_5

I/O

L09N_5

I/O

L18N_5

I/O

L21N_5

I/O

L25N_5

VCCO_5

I/O

L34P_5

I/O

L01P_5

CS_B

I/O

L10P_5

VRN_5

I/O

L28N_5

D6

I/O

L32N_5

GCLK3

A

N

I/O

L02P_5

I/O

L03N_5

I/O

L05P_5

I/O

L36P_5

I/O

L11P_5

I/O

L15P_5

I/O

L22P_5

I/O

L26P_5

VCCO_5

GND

I/O

GND

I/O

L34N_5

I/O

L01N_5

RDWR_B

I/O

L10N_5

VRP_5

I/O

L11N_5

VREF_5

A

P

IO

VREF_5

I/O

L02N_5

I/O

L05N_5

I/O

L36N_5

I/O

L15N_5

I/O

L22N_5

I/O

L26N_5

GND

Bank 5

DS099-4_14c_072503

Bottom Left Corner of

Package (top view)

102

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

I/O

L40N_3

VREF_3

I/O

L37P_3

I/O

L37N_3

I/O

L38P_3

I/O

L38N_3

I/O

L39P_3

I/O

L39N_3

I/O

L40P_3

L51N_3

I/O

GND

VCCINT

V

W

Y

I/O

L51P_3

I/O

L34P_3

VREF_3

I/O

L33N_3

I/O

L34N_3

I/O

L35P_3

I/O

L35N_3

VCCO_3

VCCINT

VCCAUX

VCCO_3

GND

VCCINT

I/O

GND

VCCINT

GND

I/O

L50P_3

I/O

L50N_3

I/O

L33P_3

I/O

L30P_3

I/O

L30N_3

I/O

L31P_3

I/O

L31N_3

I/O

L32P_3

I/O

L32N_3

VCCAUX

I/O

L49P_3

I/O

L49N_3

A

I/O

L48N_3

I/O

L26P_3

I/O

L26N_3

I/O

L27P_3

I/O

L27N_3

I/O

L28P_3

I/O

L28N_3

I/O

L29P_3

I/O

L29N_3

A

B

I/O

L48P_3

I/O

L24N_3

I/O

L46P_3

I/O

L46N_3

I/O

L47P_3

I/O

L47N_3

VCCO_3

VCCINT VCCINT VCCINT VCCINT

GND

I/O

L23P_3

VREF_3

A

C

I/O

L20P_3

I/O

L20N_3

I/O

L24P_3

I/O

L21P_3

I/O

L21N_3

I/O

L22P_3

I/O

L22N_3

I/O

L23N_3

I/O

L45P_3

I/O

L45N_3

VCCO_4 VCCO_4 VCCO_4 VCCO_4

I/O

L44P_3

I/O

L44N_3

I/O

L17P_3

VREF_3

A

D

I/O

L18N_4

I/O

L11N_4

I/O

L17N_3

I/O

L19P_3

I/O

L19N_3

VCCO_3

VCCAUX VCCO_3

GND

I/O

DONE

I/O

L13N_3

VREF_3

I/O

A

E

I/O

L23N_4

I/O

L18P_4

I/O

L11P_4

I/O

L12N_3

I/O

L13P_3

I/O

L14P_3

I/O

L14N_3

I/O

L15P_3

I/O

L15N_3

I/O

L16P_3

I/O

L16N_3

GND

I/O

L09P_3

VREF_3

I/O

A

F

IO

VREF_4

I/O

L29N_4

I/O

L23P_4

I/O

L12N_4

I/O

L07N_4

I/O

L12P_3

I/O

L09N_3

I/O

L10N_3

I/O

L11P_3

I/O

L11N_3

I/O

GND

A

G

I/O

L29P_4

I/O

L19N_4

I/O

L16N_4

I/O

L12P_4

I/O

L07P_4

I/O

L07P_3

I/O

L07N_3

I/O

L10P_3

I/O

L08P_3

I/O

L08N_3

VCCAUX VCCO_4

I/O

VCCO_4

VCCO_3

GND

VCCO_3

I/O

VCCO_4

I/O

L39N_4

I/O

L41P_3

I/O

L41N_3

I/O

L30N_4

D2

A

H

IO

VREF_4

I/O

L24N_4

I/O

L19P_4

I/O

L16P_4

I/O

L08N_4

I/O

L05N_4

I/O

L06P_3

I/O

L06N_3

L27N_4

DIN

I/O

D0

I/O

L39P_4

I/O

L30P_4

D3

I/O

L27P_4

D1

A

J

I/O

L24P_4

I/O

L20N_4

I/O

L13N_4

I/O

L08P_4

I/O

L05P_4

I/O

L35N_4

I/O

L04P_3

I/O

L04N_3

I/O

L05P_3

I/O

L05N_3

VCCO_4

GND

VCCAUX

GND

I/O

N.C.

A

K

IO

VREF_4

I/O

L20P_4

I/O

L13P_4

I/O

L38N_4

I/O

L35P_4

I/O

L03P_3

I/O

L03N_3

VCCAUX

I/O

GND

I/O

L36N_4

I/O

L31N_4

INIT_B

I/O

L06N_4

VREF_4

I/O

L02N_3

VREF_3

A

L

IO

VREF_4

I/O

L25N_4

I/O

L21N_4

I/O

L17N_4

I/O

L14N_4

I/O

L09N_4

I/O

L38P_4

I/O

L33N_4

I/O

L02P_3

VCCO_4

GND

VCCO_3

GND

CCLK

I/O

L36P_4

I/O

L01P_3

VRN_3

I/O

L01N_3

VRP_3

A

M

I/O

L28N_4

I/O

L25P_4

I/O

L21P_4

I/O

L17P_4

I/O

L14P_4

I/O

L09P_4

I/O

L06P_4

I/O

L33P_4

I/O

L03N_4

L31P_4

DOUT

BUSY

VCCO_4

I/O

L40N_4

I/O

L37N_4

I/O

L32N_4

GCLK1

I/O

L22N_4

VREF_4

I/O

L01N_4

VRP_4

A

N

I/O

L28P_4

I/O

L26N_4

I/O

L15N_4

I/O

L10N_4

I/O

L04N_4

I/O

L34N_4

I/O

L03P_4

I/O

L02N_4

VCCO_4

GND

I/O

L40P_4

I/O

L37P_4

I/O

L32P_4

GCLK0

I/O

L26P_4

VREF_4

I/O

L01P_4

VRN_4

A

P

I/O

L22P_4

I/O

L15P_4

I/O

L10P_4

I/O

L04P_4

I/O

L34P_4

I/O

L02P_4

GND

Bank 4

DS099-4_14d_072903

Bottom Right Corner

of Package (top view)

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

103

R

Spartan-3 FPGA Family: Pinout Descriptions

Revision History

Date

Version No.

Description

04/03/03

04/21/03

1.0

1.1

Initial Xilinx release.

Added information on the VQ100 package footprint, including a complete pinout table

(Table 16) and footprint diagram (Figure 8).

Updated Table 15 with final I/O counts for the VQ100 package. Also added final differential I/O

pair counts for the TQ144 package.

Added clarifying comments to HSWAP_EN pin description on page 13.

Updated the footprint diagram for the FG900 package shown in Figure 15a and Figure 15b.

Some thick lines separating I/O banks were incorrect.

Made cosmetic changes to Figure 1, Figure 3, and Figure 4.

Updated Xilinx hypertext links.

Added XC3S200 and XC3S400 to Pin Name column in Table 18.

AM32 pin was missing GND label in FG1156 package diagram (Figure 16).

05/12/03

07/11/03

1.1.1

1.1.2

Corrected misspellings of GCLK in Table 1 and Table 2. Changed CMOS25 to LVCMOS25 in

Dual-Purpose Pin I/O Standard During Configuration section. Clarified references to

Module 2. For XC3S5000 in FG1156 package, corrected N.C. symbol to a black square in

Table 37, key, and package drawing.

07/29/03

1.2

Corrected pin names on FG1156 package. Some package balls incorrectly included LVDS pair

names. The affected balls on the FG1156 package include G1, G2, G33, G34, U9, U10, U25,

U26, V9, V10, V25, V26, AH1, AH2, AH33, AH34. The number of LVDS pairs is unaffected.

Modified affected balls and re-sorted rows in Table 37. Updated affected balls in Figure 16.

Also updated ASCII and Excel electronic versions of FG1156 pinout.

08/19/03

10/09/03

1.2.1

1.2.2

Removed 100 MHz ConfigRate option in CCLK: Configuration Clock section and in Table 11.

Added note that TDO is a totem-pole output in Table 9.

Some pins had incorrect bank designations and were improperly sorted in Table 20. No pin

names or functions changed. Renamed DCI_IN to DCI and added black diamond to N.C. pins

in Table 20. In Figure 10, removed some extraneous text from pin 106 and corrected spelling

of pins 45, 48, and 81.

12/17/03

1.3

Added FG320 pin tables and pinout diagram (FG320: 320-lead Fine-pitch Ball Grid Array).

Made cosmetic changes to the TQ144 footprint (Figure 9), the PQ208 footprint (Figure 10), the

FG676 footprint (Figure 14), and the FG900 footprint (Figure 15). Clarified wording in

Precautions When Using the JTAG Port in 3.3V Environments section.

02/27/04

07/13/04

1.4

1.5

Clarified wording in Using JTAG Port After Configuration section. In Table 12, reduced

package height for FG320 and increased maximum I/O values for the FG676, FG900, and

FG1156 packages.

Added information on lead-free (Pb-free) package options to the Package Overview section

plus Table 12 and Table 13. Clarified the VRN_# reference resistor requirements for I/O

standards that use single termination as described in the DCI Termination Types section and

in Figure 3b. Graduated from Advance Product Specification to Product Specification.

104

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1-800-255-7778

DS099-4 (v1.5) July 13, 2004

Product Specification

R

Spartan-3 FPGA Family: Pinout Descriptions

The Spartan-3 Family Data Sheet

DS099-1, Spartan-3 FPGA Family: Introduction and Ordering Information (Module 1)

DS099-2, Spartan-3 FPGA Family: Functional Description (Module 2)

DS099-3, Spartan-3 FPGA Family: DC and Switching Characteristics (Module 3)

DS099-4, Spartan-3 FPGA Family: Pinout Descriptions (Module 4)

DS099-4 (v1.5) July 13, 2004

Product Specification

www.xilinx.com

1-800-255-7778

105


型号：	XC3S5000-4FG320I
厂家：	XILINX, INC
描述：	Spartan-3 FPGA Family : Complete Data Sheet Spartan-3系列FPGA系列：完整的数据手册
文件：	总192页 (文件大小：1695K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XC3S5000-4FG320I [XILINX]

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XC3S5000-4FGG676C

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