XC2V10000-5BG728I_技术文档

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Virtex-II 1.5V

Field-Programmable Gate Arrays

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DS031-2 (v1.3) January 25, 2001

Advance Product Specification

Detailed Description

Input/Output Blocks (IOBs)

Virtex-II I/O blocks (IOBs) are provided in groups of two or four on the perimeter of each device.

Each IOB can be used as input and/or output for single-ended I/Os. Two IOBs can be used as a

differential pair. A differential pair is always connected to the same switch matrix, as shown in

Figure 1.

IOB blocks are designed for high performances I/Os, supporting 19 single-ended standards, as well

as differential signaling with LVDS, LDT, Bus LVDS, and LVPECL.

IOB

PAD4

Differential Pair

IOB

PAD3

Switch

Matrix

IOB

PAD2

Differential Pair

IOB

PAD1

DS031_30_101600

Figure 1: Virtex-II Input/Output Tile

Supported I/O Standards

Virtex-II IOB blocks feature SelectI/O inputs and outputs that support a wide variety of I/O signaling

standards. In addition to the internal supply voltage (V_CCINT= 1.5V), output driver supply voltage

(V_CCO) is dependent on the I/O standard (see Table 1). An auxiliary supply voltage

(V_CCAUX= 3.3 V) is required, regardless of the I/O standard used. For exact supply voltage

absolute maximum ratings, DC Input and Output Levels.

Table 1: Supported Single-Ended I/O Standards

Board

Termination

Voltage (V_TT

I/O

Standard

Output

V_CCO

Input

V_CCO

Input

V_REF

)

LVTTL

3.3

2.5

1.8

1.5

3.3

2.5

1.8

1.5

N/A

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

N/A

All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.

DS031-2 (v1.3) January 25, 2001

Advance Product Specification

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Table 1: Supported Single-Ended I/O Standards (Continued)

Board

Termination

Voltage (V_TT

I/O

Standard

Output

V_CCO

Input

V_CCO

Input

V_REF

)

PCI33_3

3.3

N/A

0.8

N/A

PCI66_3

PCI-X

N/A

3.3

N/A

GTL

Note 1

1.5

Note 1

N/A

1.2

GTLP

1.0

1.5

HSTL_I

HSTL_II

HSTL_III

HSTL_IV

SSTL2_I

SSTL2_II

SSTL3_I

SSTL3_II

AGP-2X/AGP

0.75

0.9

0.75

1.5

N/A

1.5

N/A

1.5

N/A

0.9

1.5

2.5

N/A

1.25

1.5

1.25

1.5

2.5

N/A

3.3

N/A

3.3

N/A

1.5

3.3

N/A

1.32

N/A

Notes:

1.

V

_CCOof GTL or GTLP should not be lower than the termination voltage or

the voltage seen at the I/O pad.

Table 2: Supported Differential Signal I/O Standards

I/O

Standard

Output Input Input

V_CCOV_CCOV_REF

Output

V_OD

LVPECL_33

3.3

N/A

V_CCO– 1.025

to

V_CCO– 1.64

LDT_25

2.5

3.3

2.5

3.3

2.5

N/A

0.430 - 0.670

0.250 - 0.400

0.330 - 0.700

0.250 - 0.450

0.430 - 0.670

LVDS_33

LVDS_25

LVDSEXT_33

LVDSEXT_25

BLVDS_25

ULVDS_25

All of the user IOBs have fixed-clamp diodes to V_CCOand to ground. The IOBs are not compatible

or compliant with 5 V I/O standards (not 5 V tolerant).

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Advance Product Specification

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Virtex-II 1.5V Field-Programmable Gate Arrays

Table 3 lists supported I/O standards with Digitally Controlled Impedance. See Digitally

Controlled Impedance (DCI), page 10.

Table 3: Supported DCI I/O Standards

I/O

Standard

Output

V_CCO

Input

V_CCO

Input

V_REF

Termination

Type

LVDCI_33

3.3

2.5

1.8

1.5

1.2

1.5

2.5

3.3

2.5

1.8

1.5

1.2

1.5

2.5

3.3

N/A

0.8

Series

Single

Split

LVDCI_DV2_33

LVDCI_25

LVDCI_DV2_25

LVDCI_18

LVDCI_DV2_18

LVDCI_15

LVDCI_DV2_15

GTL_DCI

GTLP_DCI

1.0

HSTL_I_DCI

HSTL_II_DCI

HSTL_III_DCI

HSTL_IV_DCI

SSTL2_I_DCI²

SSTL2_II_DCI²

SSTL3_I_DCI²

SSTL3_II_DCI²

0.75

0.9

Split

Single

Split

0.9

1.25

1.5

Split

1.5

Split

Notes:

1. LVDCI_XX and LVDCI_DV2_XX are LVCMOS controlled impedance

buffers, matching the reference resistors or half of the reference resistors.

2. These are SSTL compatible.

DS031-2 (v1.3) January 25, 2001

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Virtex-II 1.5V Field-Programmable Gate Arrays

Logic Resources

IOB blocks include six storage elements, as shown in Figure 2.

IOB

Input

DDR mux

Reg

OCK1

Reg

ICK1

Reg

3-State

OCK2

Reg

ICK2

DDR mux

Reg

OCK1

PAD

Reg

Output

OCK2

DS031_29_100900

Figure 2: Virtex-II IOB Block

Each storage element can be configured either as an edge-triggered D-type flip-flop or as a level-

sensitive latch. On the input, output, and 3-state path, one or two DDR registers can be used.

Double data rate is directly accomplished by the two registers on each path, clocked by the rising

edges (or falling edges) from two different clock nets. The two clock signals are generated by the

DCM and must be 180 degrees out of phase, as shown in Figure 3. There are two input, output, and

3-state data signals, each being alternately clocked out.

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Virtex-II 1.5V Field-Programmable Gate Arrays

DCM

180° 0°

FDDR

D1

Q1

CLK1

Q1

CLOCK

CLK1

Q

DDR MUX

D2

Q2

CLK2

Q2

CLK2

(50/50 duty cycle clock)

DS031_26_100900

Figure 3: Double Data Rate Registers

This DDR mechanism can be used to mirror a copy of the clock on the output. This is useful for

propagating a clock along the data that has an identical delay. It is also useful for multiple clock

generation, where there is a unique clock driver for every clock load. Virtex-II devices can produce

many copies of a clock with very little skew.

Each group of two registers has a clock enable signal (ICE for the input registers, OCE for the

output registers, and TCE for the 3-state registers). The clock enable signals are active High by

default. If left unconnected, the clock enable for that storage element defaults to the active state.

Each IOB block has common synchronous or asynchronous set and reset (SR and REV signals).

SR forces the storage element into the state specified by the SRHIGH or SRLOW attribute. SRHIGH

forces a logic “1”. SRLOW forces a logic “0”. When SR is used, a second input (REV) forces the

storage element into the opposite state. The reset condition predominates over the set condition. The

initial state after configuration or global initialization state is defined by a separate INIT0 and INIT1

attribute. By default, the SRLOW attribute forces INIT0, and the SRHIGH attribute forces INIT1.

For each storage element, the SRHIGH, SRLOW, INIT0, and INIT1 attributes are independent.

Synchronous or asynchronous set / reset is consistent in an IOB block.

All the control signals have independent polarity. Any inverter placed on a control input is

automatically absorbed.

Each register or latch (independent of all other registers or latches) (see Figure 4) can be

configured as follows:

•

No set or reset

Synchronous set

Synchronous reset

Synchronous set and reset

Asynchronous set (preset)

Asynchronous reset (clear)

Asynchronous set and reset (preset and clear)

The synchronous reset overrides a set, and an asynchronous clear overrides a preset.

DS031-2 (v1.3) January 25, 2001

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Virtex-II 1.5V Field-Programmable Gate Arrays

(O/T) 1

Attribute

INIT1

INIT0

FF

SRHIGH

SRLOW

LATCH

Q1

D1

(O/T) CE

CE

(O/T) CLK1

CK1

SR REV

SR

Shared

by all

registers

FF1

(OQ or TQ)

DDR MUX

FF2

REV

FF

LATCH

D2

Q2

CE

Attribute

INIT1

INIT0

SRHIGH

SRLOW

(O/T) CLK2

(O/T) 2

CK2

SR REV

Reset Type

SYNC

ASYNC

DS031_25_110300

Figure 4: Register / Latch Configuration in an IOB Block

Input/Output Individual Options

Each device pad has optional pull-up, pull-down, and weak-keeper in LVTTL and LVCMOS

SelectI/O configurations, as illustrated in Figure 5. Values of the optional pull-up and pull-down

resistors are in the range 50 - 100 K , which is the specification for V_CCOwhen operating at 3.3 V

(from 3.0 to 3.6 V only).

V

CCO

Clamp

Diode

OBUF

Weak

Keeper

V

CCO

Program Current

10-60KΩ

PAD

V

CCO

10-60KΩ

V

= 3.3V

= 1.5V

Program

Delay

CCAUX

V

CCINT

IBUF

DS031_23_011601

Figure 5: LVTTL, LVCMOS or PCI SelectI/O Standards

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Advance Product Specification

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Virtex-II 1.5V Field-Programmable Gate Arrays

The optional weak-keeper circuit is connected to each output. When selected, the circuit monitors

the voltage on the pad and weakly drives the pin High or Low. If the pin is connected to a multiple-

source signal, the weak-keeper holds the signal in its last state if all drivers are disabled.

Maintaining a valid logic level in this way eliminates bus chatter; pull-up or pull-down override the

weak-keeper circuit.

LVTTL sinks and sources current up to 24 mA. The current is programmable for LVTTL and

LVCMOS SelectI/O standards (see Table 4). Drive-strength and slew-rate controls for each output

driver, minimize bus transients. For LVDCI and LVDCI_DV2 standards, drive strength and slew-rate

controls are not available.

Table 4: LVTTL and LVCMOS Programmable Currents (Sink and Source)

SelectI/O Programmable Current (Worst-Case Guaranteed Minimum)

LVTTL

2 mA

4 mA

6 mA

8 mA

12 mA

16 mA

24 mA

n/a

LVCMOS33

LVCMOS25

LVCMOS18

LVCMOS15

n/a

Figure 6 shows the SSTL2, SSTL3, and HSTL configurations. HSTL can sink current up to 48 mA.

(HSTL IV)

V

CCO

Clamp

Diode

OBUF

PAD

V

= 3.3V

CCAUX

= 1.5V

CCINT

V

REF

DS031_24_100900

Figure 6: SSTL or HSTL SelectI/O Standards

All pads are protected against damage from electrostatic discharge (ESD) and from over-voltage

transients. Virtex-II uses two memory cells to control the configuration of an I/O as an input. This is

to reduce the probability of an I/O configured as an input from flipping to an output when subjected

to a single event upset (SEU) in space applications.

Prior to configuration, all outputs not involved in configuration are forced into their high-impedance

state. The pull-down resistors and the weak-keeper circuits are inactive. The dedicated pin

HSWAP_EN controls the pull-up resistors prior to configuration. By default, HSWAP_EN is set high,

which disables the pull-up resistors on user I/O pins. When HSWAP_EN is set low, the pull-up

resistors are activated on user I/O pins.

All Virtex-II IOBs support IEEE 1149.1 compatible boundary scan testing.

DS031-2 (v1.3) January 25, 2001

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Virtex-II 1.5V Field-Programmable Gate Arrays

Input Path

The Virtex-II IOB input path routes input signals directly to internal logic and / or through an optional

input flip-flop or latch, or through the DDR input registers. An optional delay element at the D-input

of the storage element eliminates pad-to-pad hold time. The delay is matched to the internal clock-

distribution delay of the Virtex-II device, and when used, assures that the pad-to-pad hold time is

zero.

Each input buffer can be configured to conform to any of the low-voltage signaling standards

supported. In some of these standards the input buffer utilizes a user-supplied threshold voltage,

V_REF. The need to supply V_REFimposes constraints on which standards can be used in the same

bank. See I/O banking description.

Output Path

The output path includes a 3-state output buffer that drives the output signal onto the pad. The

output and / or the 3-state signal can be routed to the buffer directly from the internal logic or

through an output / 3-state flip-flop or latch, or through the DDR output / 3-state registers.

Each output driver can be individually programmed for a wide range of low-voltage signaling

standards. In most signaling standards, the output High voltage depends on an externally supplied

V_CCOvoltage. The need to supply V_CCOimposes constraints on which standards can be used in

the same bank. See I/O banking description.

I/O Banking

Some of the I/O standards described above require V_CCOand V_REFvoltages. These voltages are

externally supplied and connected to device pins that serve groups of IOB blocks, called banks.

Consequently, restrictions exist about which I/O standards can be combined within a given bank.

Eight I/O banks result from dividing each edge of the FPGA into two banks, as shown in Figure 7

and Figure 8. Each bank has multiple V_CCOpins, all of which must be connected to the same

voltage. This voltage is determined by the output standards in use.

Bank 0

Bank 1

Bank 5

Bank 4

ug002_c2_014_112900

Figure 7: Virtex-II I/O Banks: Top View for Wire-Bond Packages (CS, FG, & BG)

Within a bank, output standards can be mixed only if they use the same V_CCO. Compatible

standards are shown in Table 5. GTL and GTLP appear under all voltages because their open-drain

outputs do not depend on V_CCO

.

Some input standards require a user-supplied threshold voltage, V_REF. In this case, certain user-I/O

pins are automatically configured as inputs for the V_REFvoltage. Approximately one in six of the I/O

pins in the bank assume this role.

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Virtex-II 1.5V Field-Programmable Gate Arrays

Bank 1

Bank 0

Bank 4

Bank 5

ds031_66_112900

Figure 8: Virtex-II I/O Banks: Top View for Flip-Chip Packages (FF & BF)

V_REFpins within a bank are interconnected internally, and consequently only one V_REFvoltage can

be used within each bank. However, for correct operation, all V_REFpins in the bank must be

connected to the external reference voltage source.

Table 5: Compatible Output Standards

V_CCO

Compatible Standards

3.3 V PCI, LVTTL, SSTL3 (I & II), AGP-2X, LVDS_33,

LVDSEXT_33, LVCMOS33, LVDCI_33,

LVDCI_DV2_33, SSTL3_DCI (I & II), BLVDS,

LVPECL, GTL, GTLP

2.5 V SSTL2 (I & II), LVCMOS25, GTL, GTLP,

LVDS_25, LVDSEXT_25, LVDCI_25,

LVDCI_DV2_25, SSTL2_DCI (I & II), LDT,

ULVDS, BLVDS

1.8 V LVCMOS18, GTL, GTLP, LVDCI_18,

LVDCI_DV2_18

1.5 V HSTL (I, II, III, & IV), LVCMOS15, GTL, GTLP,

LVDCI_15, LVDCI_DV2_15, GTLP_DCI,

HSTL_DCI (I,II, III & IV)

1.2V GTL_DCI

The V_CCOand the V_REFpins for each bank appear in the device pinout tables. Within a given

package, the number of V_REFand V_CCOpins can vary depending on the size of device. In larger

devices, more I/O pins convert to V_REFpins. Since these are always a superset of the V_REFpins

used for smaller devices, it is possible to design a PCB that permits migration to a larger device if

necessary.

All V_REFpins for the largest device anticipated must be connected to the V_REFvoltage and not used

for I/O. In smaller devices, some V_CCOpins used in larger devices do not connect within the

package. These unconnected pins can be left unconnected externally, or, if necessary, they can be

connected to the V_CCOvoltage to permit migration to a larger device.

DS031-2 (v1.3) January 25, 2001

Advance Product Specification

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Virtex-II 1.5V Field-Programmable Gate Arrays

Digitally Controlled Impedance (DCI)

Today’s chip output signals with fast edge rates require termination to prevent reflections and

maintain signal integrity. High pin count packages (especially ball grid arrays) can not

accommodate external termination resistors.

Virtex-II DCI provides controlled impedance drivers and on-chip termination for single-ended I/Os.

This eliminates the need for external resistors, and improves signal integrity. The DCI feature can

be used on any IOB by selecting one of the DCI I/O standards.

When applied to inputs, DCI provides input parallel termination. When applied to outputs, DCI

provides controlled impedance drivers (series termination) or output parallel termination.

DCI operates independently on each I/O bank. When a DCI I/O standard is used in a particular I/O

bank, external reference resistors must be connected to two dual-function pins on the bank. These

resistors, voltage reference of N transistor (VRN) and the voltage reference of P transistor (VRP)

are shown in Figure 9.

1 Bank

DCI

V

CCO

R

(1%)

REF

VRN

VRP

R

REF

GND

DS031_50_101200

Figure 9: DCI in a Virtex-II Bank

When used with a terminated I/O standard, the value of the resistor is specified by the standard

(typically 50 ). When used with a controlled impedance driver, the resistor sets the output

impedance of the driver within the specified range (25 to 150 . The resistors connected to VRN

and VRP do not need to be the same value. 1% resistors are recommended.

The DCI system adjusts the I/O impedance to match the two external reference resistors, or half of

the reference resistor, and compensates for impedance changes due to voltage and/or temperature

fluctuations. The adjustment is done by turning parallel transistors in the IOB on or off.

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Virtex-II 1.5V Field-Programmable Gate Arrays

Controlled Impedance Drivers (Series Termination)

DCI can be used to provide a buffer with a controlled output impedance. It is desirable for this output

impedance to match the transmission line impedance (Z). Virtex-II input buffers also support LVDCI

and LVDCI_DV2 I/O standards.

IOB

Z

Virtex-II DCI

V

= 3.3 V, 2.5 V, 1.8 V or 1.5 V

CCO

DS031_51_110600

Figure 10: Internal Series Termination

Table 6: SelectI/O Controlled Impedance Buffers

V_CCO

3.3 V

2.5 V

1.8 V

1.5 V

DCI

DCI Half Impedance

LVDCI_DV2_33

LVDCI_DV2_25

LVDCI_DV2_18

LVDCI_DV2_15

LVDCI_33

LVDCI_25

LVDCI_18

LVDCI_15

Controlled Impedance Drivers (Parallel Termination)

DCI also provides on-chip termination for SSTL3, SSTL2, HSTL (Class I, II, III, or IV), and

GTL/GTLP receivers or transmitters on bidirectional lines.

Table 7 lists the on-chip parallel terminations available in Virtex-II devices. V_CCOmust be set according

to Table 3. Note that there is a V_CCOrequirement for GTL_DCI and GTLP_DCI, due to the on-chip

termination resistor.

Table 7: SelectI/O Buffers With On-Chip Parallel Termination

External

Termination

On-Chip

Termination

I/O Standard

SSTL3 Class I

SSTL3 Class II

SSTL2 Class I

SSTL2 Class II

HSTL Class I

HSTL Class II

HSTL Class III

HSTL Class IV

GTL

SSTL3_I

SSTL3_II

SSTL2_I

SSTL2_II

HSTL_I

HSTL_II

HSTL_III

HSTL_IV

GTL

SSTL3_I_DCI ¹

SSTL3_II_DCI ¹

SSTL2_I_DCI ¹

SSTL2_II_DCI ¹

HSTL_I_DCI

HSTL_II_DCI

HSTL_III_DCI

HSTL_IV_DCI

GTL_DCI

GTLP

GTLP_DCI

Notes:

1. SSTL Compatible

For further details, see the Virtex-II User Guide.

DS031-2 (v1.3) January 25, 2001

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Virtex-II 1.5V Field-Programmable Gate Arrays

Figure 11 provides examples illustrating the use of the HSTL_IV_DCI, HSTL_II_DCI, and SSTL2_DCI I/O standards.

HSTL_IV

HSTL_II

SSTL2_I

V

/2

V

/2

V

/2

V

R

CCO

R

Z

0

Z

0

HSTL_IV_DCI Transmitter

HSTL_II_DCI Transmitter

/2

SSTL2_I_DCI Transmitter

V

/2

V

CCO

R

V

CCO

R

2R

R

Z

0

2R

Virtex-II DCI

HSTL_IV_DCI Receiver

HSTL_II_DCI Receiver

/2

SSTL2_I_DCI Receiver

V

CCO

V

CCO

2R

R

2R

R

Z

0

Z

0

2R

Virtex-II DCI

HSTL_II_DCI Transmitter and Receiver

Virtex-II DCI

HSTL_IV_DCI Transmitter and Receiver

SSTL2_I_DCI Transmitter and Receiver

V

CCO

2R

R

2R

R

2R

Z

0

Z

0

2R

Virtex-II DCI

2R

Virtex-II DCI

ds031_65_110200

Figure 11: DCI Usage Examples

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Virtex-II 1.5V Field-Programmable Gate Arrays

Configurable Logic Blocks (CLBs)

The Virtex-II configurable logic blocks (CLB) are organized in an array and are used to build

combinatorial and synchronous logic designs. Each CLB element is tied to a switch matrix to

access the general routing matrix, as shown in Figure 12. A CLB element comprises 4 similar

slices, with fast local feedback within the CLB. The four slices are split in two columns of two slices

with two independent carry logic chains and one common shift chain.

COUT

TBUF X0Y1

TBUF X0Y0

Slice

X1Y1

Slice

X1Y0

COUT

Switch

Matrix

SHIFT

CIN

Slice

X0Y1

Slice

Fast

X0Y0

Connects

to neighbors

CIN

DS031_32_101600

Figure 12: Virtex-II CLB Element

Slice Description

Introduction

Each slice includes two 4-input function generators, carry logic, arithmetic logic gates, wide function

multiplexers and two storage elements. As shown in Figure 13, each 4-input function generator is

programmable as a 4-input LUT, 16 bits of distributed SelectRAM memory, or a 16-bit variable-tap

shift register element.

ORCY

RAM16

MUXFx

SRL16

Register

CY

LUT

G

RAM16

MUXF5

CY

SRL16

LUT

F

Arithmetic Logic

DS031_31_100900

Figure 13: Virtex-II Slice Configuration

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Virtex-II 1.5V Field-Programmable Gate Arrays

The output from the function generator in each slice drives both the slice output and the D input of the storage element.

Figure 14 shows a more detailed view of a single slice.

COUT

SHIFTIN

ORCY

SOPIN

SOPOUT

YB

0

Dual-Port

Shift-Reg

YBMUX

I

MUXCY

A4

G4

G3

G2

O

I

LUT

RAM

ROM

A3

A2

A1

WG4

WG3

WG2

WG1

G1

D

GYMUX

WG4

WG3

WG2

WG1

Y

G

DY

MC15

DI

XORG

FF

LATCH

WS

ALTDIG

DYMUX

CE

D

Q

G2

PROD

G1

Q

Y

MULTAND

CE

CLK CK

CYOG

BY

1

0

SR REV

BY

SLICEWE[2:0]

WSG

SR

SHIFTOUT

WE[2:0]

WE

DIG

CLK

MUXCY

O

I

WSF

CE

CLK

SR

Shared between

x & y Registers

CIN

DS031_01_110600

Figure 14: Virtex-II Slice (Top Half)

Configurations

Look-Up Table

Virtex-II function generators are implemented as 4-input look-up tables (LUTs). Four independent

inputs are provided to each of the two function generators in a slice (F and G). These function

generators are each capable of implementing any arbitrarily defined boolean function of four inputs.

The propagation delay is therefore independent of the function implemented. Signals from the

function generators can exit the slice (X or Y output), can input the XOR dedicated gate (see

arithmetic logic), or input the carry-logic multiplexer (see fast look-ahead carry logic), or feed the D

input of the storage element, or go to the MUXF5 (not shown in Figure 14).

In addition to the basic LUTs, the Virtex-II slice contains logic (MUXF5 and MUXFX multiplexers)

that combines function generators to provide any function of five, six, seven, or eight inputs. The

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MUXFX are either MUXF6, MUXF7 or MUXF8 according to the slice considered in the CLB.

Selected functions up to nine inputs (MUXF5 multiplexer) can be implemented in one slice. The

MUXFX can also be a MUXF6, MUXF7, or MUXF8 multiplexers to map any functions of six, seven,

or eight inputs and selected wide logic functions.

Register/Latch

The storage elements in a Virtex-II slice can be configured either as edge-triggered D-type flip-flops

or as level-sensitive latches. The D input can be directly driven by the X or Y output via the DX or

DY input, or by the slice inputs bypassing the function generators via the BX or BY input. The clock

enable signal (CE) is active High by default. If left unconnected, the clock enable for that storage

element defaults to the active state.

In addition to clock (CK) and clock enable (CE) signals, each slice has set and reset signals (SR

and BY slice inputs). SR forces the storage element into the state specified by the attribute

SRHIGH or SRLOW. SRHIGH forces a logic “1” when SR is asserted. SRLOW forces a logic “0”.

When SR is used, a second input (BY) forces the storage element into the opposite state. The reset

condition is predominant over the set condition. (See Figure 15.)

The initial state after configuration or global initial state is defined by a separate INIT0 and INIT1

attribute. By default, setting the SRLOW attribute sets INIT0, and setting the SRHIGH attribute sets

INIT1.

For each slice, set and reset can be set to be synchronous or asynchronous. Virtex-II devices also

have the ability to set INIT0 and INIT1 independent of SRHIGH and SRLOW.

The control signals clock (CLK), clock enable (CE) and set/reset (SR) are common to both storage

elements in one slice. All of the control signals have independent polarity. Any inverter placed on a

control input is automatically absorbed.

FFY

FF

LATCH

DY

YQ

Attribute

D

Q

CE

CK

SR REV

INIT1

INIT0

SRHIGH

SRLOW

BY

FFX

FF

LATCH

DX

D

XQ

Q

Attribute

CE

CK

SR REV

INIT1

INIT0

SRHIGH

SRLOW

CLK

SR

BX

Reset Type

SYNC

ASYNC

DS031_22_110600

Figure 15: Register / Latch Configuration in a Slice

The set and reset functionality of a register or a latch can be configured as follows:

•

No set or reset

Synchronous set

Synchronous reset

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Virtex-II 1.5V Field-Programmable Gate Arrays

•

Synchronous set and reset

Asynchronous set (preset)

Asynchronous reset (clear)

Asynchronous set and reset (preset and clear)

The synchronous reset has precedence over a set, and an asynchronous clear has precedence

over a preset.

Distributed SelectRAM Memory

Each function generator (LUT) can implement a 16 x 1-bit synchronous RAM resource called a

distributed SelectRAM element. The SelectRAM elements are configurable within a CLB to

implement the following:

•

Single-Port 16 x 8 bit RAM

Single-Port 32 x 4 bit RAM

Single-Port 64 x 2 bit RAM

Single-Port 128 x 1 bit RAM

Dual-Port 16 x 4 bit RAM

Dual-Port 32 x 2 bit RAM

Dual-Port 64 x 1 bit RAM

Distributed SelectRAM memory modules are synchronous (write) resources. The combinatorial

read access time is extremely fast, while the synchronous write simplifies high-speed designs. A

synchronous read can be implemented with a storage element in the same slice. The distributed

SelectRAM memory and the storage element share the same clock input. A Write Enable (WE)

input is active High, and is driven by the SR input.

Table 8 shows the number of LUTs (2 per slice) occupied by each distributed SelectRAM

configuration.

Table 8: Distributed SelectRAM Configurations

RAM

Number of LUTs

16 x 1S

16 x 1D

32 x 1S

32 x 1D

64 x 1S

64 x 1D

128 x 1S

1

2

4

8

Notes:

1. S = single-port configuration; D = dual-port configuration

For single-port configurations, distributed SelectRAM memory has one address port for

synchronous writes and asynchronous reads.

For dual-port configurations, distributed SelectRAM memory has one port for synchronous writes

and asynchronous reads and another port for asynchronous reads. The function generator (LUT)

has separated read address inputs (A1, A2, A3, A4) and write address inputs (WG1/WF1,

WG2/WF2, WG3/WF3, WG4/WF4).

In single-port mode, read and write addresses share the same address bus. In dual-port mode, one

function generator (R/W port) is connected with shared read and write addresses. The second

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function generator has the A inputs (read) connected to the second read-only port address and the

W inputs (write) shared with the first read/write port address.

Figure 16, Figure 17, and Figure 18 illustrate various example configurations.

RAM 16x1S

RAM

4

Output

D

A[3:0]

D

A[4:1]

4

WG[4:1]

Registered

Output

D

Q

WS

DI

(BY)

(optional)

WSG

(SR)

WE

CK

WE

WCLK

DS031_02_100900

Figure 16: Distributed SelectRAM (RAM16x1S)

RAM 32x1S

(BX)

A[4]

RAM

4

D

A[3:0]

G[4:1]

WG[4:1]

WS

DI

(BY)

(SR)

D

WSG

WE0

WE

Output

WE

WCLK

CK

Registered

Output

D

Q

F5MUX

WSF

WS

DI

(optional)

RAM

D

4

F[4:1]

WF[4:1]

DS031_03_110100

Figure 17: Single-Port Distributed SelectRAM (RAM32x1S)

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Virtex-II 1.5V Field-Programmable Gate Arrays

RAM 16x1D

dual_port

RAM

G[4:1]

4

DPRA[3:0]

DPO

D

A[3:0]

WG[4:1]

WS

DI

(BY)

D

WSG

WE

CK

dual_port

RAM

4

A[3:0]

G[4:1]

SPO

D

WG[4:1]

WS

DI

WSG

(SR)

WE

WCLK

WE

CK

DS031_04_110100

Figure 18: Dual-Port Distributed SelectRAM (RAM16x1D)

Similar to the RAM configuration, each function generator (LUT) can implement a 16 x 1-bit ROM.

Five configurations are available: ROM16x1, ROM32x1, ROM64x1, ROM128x1, and ROM256x1.

The ROM elements are cascadable to implement wider or/and deeper ROM. ROM contents are

loaded at configuration. Table 9 shows the number of LUTs occupied by each configuration.

Table 9: ROM Configuration

ROM

16 x 1

32 x 1

64 x 1

128 x 1

256 x 1

Number of LUTs

1

2

4

8 (1 CLB)

16 (2 CLBs)

Shift Registers

Each function generator can also be configured as a 16-bit shift register. The write operation is

synchronous with a clock input (CLK) and an optional clock enable, as shown in Figure 19. A

dynamic read access is performed through the 4-bit address bus, A[3:0]. The read is asynchronous,

however the storage element or flip-flop is available to implement a synchronous read. The storage

element should always be used with a constant address. For example, when building an 8-bit shift

register and configuring the addresses to point to the 7th bit, the 8th bit can be the flip-flop. The

overall system performance is improved by using the superior clock-to-out of the flip-flops.

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SRLC16

SHIFTIN

SHIFT-REG

4

Output

D

A[3:0]

D(BY)

A[4:1]

MC15

Registered

Output

D

Q

DI

WS

(optional)

WSG

CE (SR)

CLK

WE

CK

SHIFTOUT

DS031_05_110600

Figure 19: Shift Register Configurations

An additional dedicated connection between shift registers allows connecting the last bit of one shift

register to the first bit of the next, without using the ordinary LUT output. (See Figure 20.) Longer

shift registers can be built with dynamic access to any bit in the chain. The shift register chaining

and the MUXF5, MUXF6, and MUXF7 multiplexers allow up to a 128-bit shift register with

addressable access to be implemented in one CLB.

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1 Shift Chain

in CLB

DI

SRLC16

MC15

D

IN

FF

DI

SRLC16

D

FF

MC15

SLICE S3

SHIFTOUT

SHIFTIN

D

DI

FF

SRLC16

MC15

DI

D

FF

SRLC16

MC15

SLICE S2

SHIFTOUT

SHIFTIN

DI

D

FF

SRLC16

MC15

DI

SRLC16

D

MC15

SLICE S1

SHIFTOUT

FF

SHIFTIN

D

SRLC16

MC15

DI

D

FF

SRLC16

MC15

SLICE S0

CLB

OUT

CASCADABLE OUT

DS031_06_110200

Figure 20: Cascadable Shift Register

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Virtex-II 1.5V Field-Programmable Gate Arrays

Multiplexers

Virtex-II function generators and associated multiplexers can implement the following:

•

4:1 multiplexer in one slice

8:1 multiplexer in two slices

16:1 multiplexer in one CLB element (4 slices)

32:1 multiplexer in two CLB elements (8 slices)

Each Virtex-II slice has one MUXF5 multiplexer and one MUXFX multiplexer. The MUXFX

multiplexer implements the MUXF6, MUXF7, or MUXF8, as shown in Figure 21. Each CLB element

has two MUXF6 multiplexers, one MUXF7 multiplexer and one MUXF8 multiplexer. Examples of

multiplexers are shown in the Virtex-II User Guide. Any LUT can implement a 2:1 multiplexer.

MUXF8 combines

the two MUXF7 outputs

(Two CLBs)

G

F

Slice S3

MUXF6 combines the two MUXF5

outputs from slices S2 and S3

G

F

Slice S2

MUXF7 combines the two MUXF6

outputs from slices S0 and S2

G

F

Slice S1

MUXF6 combines the two MUXF6

outputs from slices S0 and S1

G

F

Slice S0

CLB

DS031_08_110200

Figure 21: MUXF5 and MUXFX multiplexers

Fast Lookahead Carry Logic

Dedicated carry logic provides fast arithmetic addition and subtraction. The Virtex-II CLB has two

separate carry chains, as shown in the Figure 22.

The height of the carry chains is two bits per slice. The carry chain in the Virtex-II device is running

upward. The dedicated carry path and carry multiplexer (MUXCY) can also be used to cascade

function generators for implementing wide logic functions.

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Virtex-II 1.5V Field-Programmable Gate Arrays

COUT

to S0 of the next CLB

to CIN of S2 of the next CLB

MUXCY

FF

O

I

LUT

(First Carry Chain)

SLICE S3

MUXCY

FF

CIN

COUT

MUXCY

O

I

FF

LUT

SLICE S2

MUXCY

O

I

FF

LUT

SLICE S1

MUXCY

CIN

COUT

(Second Carry Chain)

MUXCY

O

I

FF

LUT

SLICE S0

MUXCY

CIN

CLB

DS031_07_110200

Figure 22: Fast Carry Logic Path

Arithmetic Logic

The arithmetic logic includes an XOR gate that allows a 2-bit full adder to be implemented within a

slice. In addition, a dedicated AND (MULT_AND) gate (shown in Figure 14) improves the efficiency

of multiplier implementation.

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Sum of Products

Each Virtex-II slice has a dedicated OR gate named ORCY, ORing together outputs from the slices

carryout and the ORCY from an adjacent slice. The ORCY gate with the dedicated Sum of Products

(SOP) chain are designed for implementing large, flexible SOP chains. One input of each ORCY is

connected through the fast SOP chain to the output of the previous ORCY in the same slice row. The

second input is connected to the output of the top MUXCY in the same slice, as shown in Figure 23.

ORCY

SOP

4

LUT

MUXCY

Slice 1

Slice 3

Slice 1

Slice 3

MUXCY

4

LUT

MUXCY

Slice 0

Slice 2

Slice 0

Slice 2

MUXCY

V

MUXCY

V

MUXCY

V

MUXCY

V

CC

CLB

ds031_64_110300

Figure 23: Horizontal Cascade Chain

LUTs and MUXCYs can implement large AND gates or other combinatorial logic functions.

Figure 24 illustrates LUT and MUXCY resources configured as a 16-input AND gate.

OUT

4

MUXCY

0

1

LUT

“0”

Slice

4

MUXCY

0

“0”

16

AND

OUT

4

MUXCY

0

1

LUT

“0”

Slice

MUXCY

0

V_CC

DS031_41_110600

Figure 24: Wide-Input AND Gate (12 Inputs)

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Virtex-II 1.5V Field-Programmable Gate Arrays

3-State Buffers

Introduction

Each Virtex-II CLB contains two 3-state drivers (TBUFs) that can drive on-chip busses. Each 3-

state buffer has its own 3-state control pin and its own input pin.

Each of the four slices have access to the two 3-state buffers through the switch matrix, as shown

in Figure 25. TBUFs in neighboring CLBs can access slice outputs by direct connects. The outputs

of the 3-state buffers drive horizontal routing resources used to implement 3-state busses.

TBUF

Slice

S3

Switch

Matrix

Slice

S2

Slice

S1

Slice

S0

DS031_37_060700

Figure 25: Virtex-II 3-State Buffers

The 3-state buffer logic is implemented using AND-OR logic rather than 3-state drivers, so that

timing is more predictable and less load dependant especially with larger devices.

Locations / Organization

Four horizontal routing resources per CLB are provided for on-chip 3-state busses. Each 3-state

buffer has access alternately to two horizontal lines, which can be partitioned as shown in

Figure 26. The switch matrices corresponding to SelectRAM memory and multiplier or I/O blocks

are skipped.

Number of 3-State Buffers

Table 10 shows the number of 3-state buffers available in each Virtex-II device. The number of 3-

state buffers is twice the number of CLB elements.

Table 10: Virtex-II 3-State Buffers

3-State Buffers

per Row

Total Number

of 3-State Buffers

Device

XC2V40

16

128

256

XC2V80

XC2V250

XC2V500

XC2V1000

XC2V1500

XC2V2000

XC2V3000

XC2V4000

XC2V6000

XC2V8000

XC2V10000

32

768

48

1,536

2,560

3,840

5,376

7,168

11,520

16,896

23,296

30,720

64

80

96

112

144

176

208

240

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Virtex-II 1.5V Field-Programmable Gate Arrays

3 - state lines

Programmable

connection

Switch

matrix

CLB-II

Switch

matrix

CLB-II

DS031_09_032700

Figure 26: 3-State Buffer Connection to Horizontal Lines

CLB/Slice Configurations

Table 11 summarizes the logic resources in one CLB. All of the CLBs are identical and each CLB or

slice can be implemented in one of the configurations listed. Table 12 shows the available

resources in all CLBs.

Table 11: Logic Resources in One CLB

Arithmetic &

Carry-Chains Chains

SOP

Distributed

SelectRAM

Shift

Registers

Slices

LUTs

Flip-Flops

MULT_ANDs

TBUF

4

8

2

128 bits

2

Table 12: Virtex-II Logic Resources Available in All CLBs

CLB Array:

Row x

Column

Number

of

LUTs

Max Distributed

SelectRAM or Shift

Register (bits)

Number

of

Number

of

Number of

SOP

Chains¹

Number

of Slices

Device

Flip-Flops Carry-Chains¹

XC2V40

XC2V80

8 x 8

16 x 8

256

516

8,192

16,384

516

16

32

512

1,024

XC2V250

XC2V500

XC2V1000

XC2V1500

XC2V2000

XC2V3000

XC2V4000

XC2V6000

XC2V8000

XC2V10000

24 x 16

32 x 24

40 x 32

48 x 40

56 x 48

64 x 56

80 x 72

96 x 88

112 x 104

128 x 120

1,536

3,072

5,120

7,680

10,752

14,336

23,040

33,792

46,592

61,440

3,072

49,152

3,072

32

48

6,144

98,304

6,144

48

64

10,240

15,360

21,504

28,672

46,080

67,584

93,184

122,880

163,840

245,760

344,064

458,752

737,280

1,081,344

1,490,944

1,966,080

10,240

15,360

21,504

28,672

46,080

67,584

93,184

122,880

64

80

96

112

128

160

192

224

256

112

144

176

208

240

Notes:

1. The carry-chains and SOP chains can be split or cascaded.

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Virtex-II 1.5V Field-Programmable Gate Arrays

18-Kbit Block SelectRAM Resources

Introduction

Virtex-II devices incorporate large amounts of 18-Kbit block SelectRAM. These complement the

distributed SelectRAM resources that provide shallow RAM structures implemented in CLBs. Each

Virtex-II block SelectRAM is an 18-Kbit true dual-port RAM with two independently clocked and

independently controlled synchronous ports that access a common storage area. Both ports are

functionally identical.

Each port has the following types of inputs: Clock and Clock Enable, Write Enable, Set/Reset, and

Address, as well as separate Data/parity data inputs (for write) and Data/parity data outputs (for

read).

Operation is synchronous; the block SelectRAM behaves like a register. Control, address and data

inputs must (and need only) be valid during the set-up time window prior to a rising (or falling, a

configuration option) clock edge. Data outputs change as a result of the same clock edge.

Configuration

The Virtex-II block SelectRAM supports various configurations, including single- and dual-port

RAM and various data/address aspect ratios. Supported memory configurations for single- and

dual-port modes are shown in Table 13.

Table 13: Dual- and Single-Port Configurations

16K x 1 bit

8K x 2 bits

4K x 4 bits

2K x 9 bits

1K x 18 bits

512 x 36 bits

Single-Port Configuration

As a single-port RAM, the block SelectRAM has access to the 18-Kbit memory locations in any of

the 2K x 9-bit, 1K x 18-bit, or 512 x 36-bit configurations and to 16-Kbit memory locations in any of

the 16K x 1-bit, 8K x 2-bit, or 4K x 4-bit configurations. The advantage of the 9-bit, 18-bit and 36-bit

widths is the ability to store a parity bit for each eight bits. Parity bits must be generated or checked

externally in user logic. In such cases, the width is viewed as 8 + 1, 16 + 2, or 32 + 4. These extra

parity bits are stored and behave exactly as the other bits, including the timing parameters. Video

applications can use the 9-bit ratio of Virtex-II block SelectRAM memory to advantage.

Each block SelectRAM cell is a fully synchronous memory as illustrated in Figure 27. Input data bus

and output data bus widths are identical.

18-Kbit Block SelectRAM

DI

DIP

ADDR

WE

EN

SSR

CLK

DO

DOP

DS031_10_102000

Figure 27: 18-Kbit Block SelectRAM Memory in Single-Port Mode

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Virtex-II 1.5V Field-Programmable Gate Arrays

Dual-Port Configuration

As a dual-port RAM, each port of block SelectRAM has access to a common 18-Kbit memory

resource. These are fully synchronous ports with independent control signals for each port. The

data widths of the two ports can be configured independently, providing built-in bus-width

conversion.

Table 14 illustrates the different configurations available on ports A & B.

Table 14: Dual-Port Mode Configurations

Port A

Port B

Port A

Port B

Port A

Port B

Port A

Port B

Port A

Port B

Port A

Port B

16K x 1

8K x 2

16K x 1

8K x 2

16K x 1

4K x 4

16K x 1

2K x 9

16K x 1

1K x 18

8K x 2

16K x 1

512 x 36

8K x 2

4K x 4

2K x 9

1K x 18

4K x 4

512 x 36

4K x 4

2K x 9

1K x 18

2K x 9

512 x 36

2K x 9

1K x 18

512 x 36

1K x 18

512 x 36

If both ports are configured in either 2K x 9-bit, 1K x 18-bit, or 512 x 36-bit configurations, the 18-

Kbit block is accessible from port A or B. If both ports are configured in either 16K x 1-bit, 8K x 2-

bit. or 4K x 4-bit configurations, the 16 K-bit block is accessible from Port A or Port B. All other

configurations result in one port having access to an 18-Kbit memory block and the other port

having access to a 16 K-bit subset of the memory block equal to 16 Kbits.

Each block SelectRAM cell is a fully synchronous memory, as illustrated in Figure 28. The two ports

have independent inputs and outputs and are independently clocked.

18-Kbit Block SelectRAM

DIA

DIPA

ADDRA

WEA

ENA

SSRA

CLKA

DOA

DOPA

DIB

DIPB

ADDRB

WEB

ENB

SSRB

CLKB

DOB

DOPB

DS031_11_102000

Figure 28: 18-Kbit Block SelectRAM in Dual-Port Mode

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Port Aspect Ratios

Table 15 shows the depth and the width aspect ratios for the 18-Kbit block SelectRAM. Virtex-II block

SelectRAM also includes dedicated routing resources to provide an efficient interface with CLBs,

block SelectRAM, and multipliers.

Table 15: 18-Kbit Block SelectRAM Port Aspect Ratio

Width

Depth

16,384

8,192

4,096

2,048

1,024

512

Address Bus

ADDR[13:0]

ADDR[12:0]

ADDR[11:0]

ADDR[10:0]

ADDR[9:0]

Data Bus

DATA[0]

Parity Bus

N/A

1

2

DATA[1:0]

DATA[3:0]

DATA[7:0]

DATA[15:0]

DATA[31:0]

N/A

4

N/A

9

Parity[0]

Parity[1:0]

Parity[3:0]

18

36

ADDR[8:0]

Read/Write Operations

The Virtex-II block SelectRAM read operation is fully synchronous. An address is presented, and

the read operation is enabled by control signal ENA or ENB. Then, depending on clock polarity, a

rising or falling clock edge causes the stored data to be loaded into output registers.

The write operation is also fully synchronous. Data and address are presented, and the write

operation is enabled by control signals WEA or WEB in addition to ENA or ENB. Then, again

depending on the clock input mode, a rising or falling clock edge causes the data to be loaded into

the memory cell addressed.

A write operation performs a simultaneous read operation. There are three different options are

available, each set by configuration:

1. “WRITE_FIRST”

The “WRITE_FIRST” option is a transparent mode. The same clock edge that writes the data

input (DI) into the memory also transfers DI into the output registers DO as shown in Figure 29.

Internal

Memory

DO

Data_in

Data_out = Data_in

DI

CLK

WE

Data_in

New

Address

aa

RAM Contents

Data_out

Old

New

DS031_14_102000

Figure 29: WRITE_FIRST Mode

2. “READ_FIRST”

The “READ_FIRST” option is a read-before-write mode.

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The same clock edge that writes data input (DI) into the memory also transfers the prior content of

the memory cell addressed into the data output registers DO, as shown in Figure 30.

Internal

Memory

DO

Data_in

Prior stored data

DI

CLK

WE

Data_in

New

Address

aa

RAM Contents

Data_out

Old

New

Old

DS031_13_102000

Figure 30: READ_FIRST Mode

3. “NO_CHANGE”

The “NO_CHANGE” option maintains the content of the output registers, regardless of the write

operation. The clock edge during the write mode has no effect on the content of the data output

register DO. When the port is configured as “NO_CHANGE”, only a read operation loads a new

value in the output register DO, as shown in Figure 31.

Internal

Memory

DO

Data_in

No change during write

DI

CLK

WE

Data_in

Address

New

aa

RAM Contents

Data_out

Old

New

Last Read Cycle Content (no change)

DS031_12_102000

Figure 31: NO_CHANGE Mode

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Control Pins and Attributes

Virtex-II SelectRAM memory has two independent ports with the control signals described in

Table 16. All control inputs including the clock have an optional inversion.

Table 16: Control Functions

Control Signal

Function

CLK

EN

Read and Write Clock

Enable affects Read, Write, Set, Reset

Write Enable

WE

SSR

Set DO register to SRVAL (attribute)

Initial memory content is determined by the INIT_xx attributes. Separate attributes determine the

output register value after device configuration (INIT) and SSR is asserted (SRVAL). Both attributes

(INIT_B and SRVAL) are available for each port when a block SelectRAM resource is configured as

dual-port RAM.

Locations

Virtex-II SelectRAM memory blocks are organized in either four or six columns. The number of

blocks per column depends of the device array size and is equivalent to the number of CLBs in a

column divided by four. Column locations are shown in Table 17.

Table 17: SelectRAM Memory Floor Plan

SelectRAM Blocks

Device

Columns

Per Column

Total

4

XC2V40

XC2V80

2

4

6

2

4

8

XC2V250

XC2V500

XC2V1000

XC2V1500

XC2V2000

XC2V3000

XC2V4000

XC2V6000

XC2V8000

XC2V10000

6

24

8

32

10

12

14

16

20

24

28

32

40

48

56

96

120

144

168

192

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SelectRAM Blocks

ds031_38_101000

Figure 32: Block SelectRAM (2-column, 4-column, and 6-column)

Total Amount of SelectRAM Memory

Table 18 shows the amount of block SelectRAM memory available for each Virtex-II device. The 18-Kbit

SelectRAM blocks are cascadable to implement deeper or wider single- or dual-port memory resources.

Table 18: Virtex-II SelectRAM Memory Available

Total SelectRAM Memory

Device

Blocks

4

in Kbits

72

in Bits

73,728

XC2V40

XC2V80

8

144

147,456

442,368

589,824

737,280

884,736

1,032,192

1,769,472

2,211,840

2,654,208

3,096,576

3,538,944

XC2V250

XC2V500

XC2V1000

XC2V1500

XC2V2000

XC2V3000

XC2V4000

XC2V6000

XC2V8000

XC2V10000

24

432

32

576

40

720

48

864

56

1,008

1,728

2,160

2,592

3,024

3,456

96

120

144

168

192

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18-Bit x 18-Bit Multipliers

Introduction

A Virtex-II multiplier block is an 18-bit by 18-bit 2’s complement signed multiplier. Virtex-II devices

incorporate many embedded multiplier blocks. These multipliers can be associated with an 18-Kbit

block SelectRAM resource or can be used independently. They are optimized for high-speed

operations and have a lower power consumption compared to an 18-bit x 18-bit multiplier in slices.

Each SelectRAM memory and multiplier block is tied to four switch matrices, as shown in Figure 33.

Switch

Matrix

Switch

Matrix

18-Kbit block

SelectRAM

Switch

Matrix

Switch

Matrix

DS031_33_101000

Figure 33: SelectRAM and Multiplier Blocks

Association With Block SelectRAM Memory

The interconnect is designed to allow SelectRAM memory and multiplier blocks to be used at the

same time, but some interconnect is shared between the SelectRAM and the multiplier. Thus,

SelectRAM memory can be used only up to 18 bits wide when the multiplier is used, because the

multiplier shares inputs with the upper data bits of the SelectRAM memory.

This sharing of the interconnect is optimized for an 18-bit-wide block SelectRAM resource feeding

the multiplier. The use of SelectRAM memory and the multiplier with an accumulator in LUTs allows

for implementation of a digital signal processor (DSP) multiplier-accumulator (MAC) function, which

is commonly used in finite and infinite impulse response (FIR and IIR) digital filters.

Configuration

The multiplier block is an 18-bit by 18-bit signed multiplier (2's complement). Both A and B are 18-

bit-wide inputs, and the output is 36 bits. Figure 34 shows a multiplier block.

Multiplier Block

A[17:0]

MULT 18 x 18

P[35:0]

B[17:0]

DS031_40_100400

Figure 34: Multiplier Block

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Locations / Organization

Multiplier organization is identical to the 18-Kbit SelectRAM organization, because each multiplier

is associated with an 18-Kbit block SelectRAM resource.

Table 19: Multiplier Floor Plan

Multipliers

Device

Columns

Per Column

Total

4

XC2V40

XC2V80

2

4

6

2

4

8

XC2V250

XC2V500

XC2V1000

XC2V1500

XC2V2000

XC2V3000

XC2V4000

XC2V6000

XC2V8000

XC2V10000

6

24

8

32

10

12

14

16

20

24

28

32

40

48

56

96

120

144

168

192

Multiplier Blocks

DS031_39_101000

Figure 35: Multipliers (2-column, 4-column, and 6-column)

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In addition to the built-in multiplier blocks, the CLB elements have dedicated logic to implement

efficient multipliers in logic. (Refer to Configurable Logic Blocks (CLBs)).

Global Clock Multiplexer Buffers

Virtex-II devices have 16 clock input pins that can also be used as regular user I/Os. Eight clock

pads are on the top edge of the device, in the middle of the array, and eight are on the bottom edge,

as illustrated in Figure 36.

The global clock multiplexer buffer represents the input to dedicated low-skew clock tree distribution

in Virtex-II devices. Like the clock pads, eight global clock multiplexer buffers are on the top edge of

the device and eight are on the bottom edge.

8 clock pads

Virtex-II

Device

8 clock pads

DS031_42_101000

Figure 36: Virtex-II Clock Pads

Each global clock buffer can either be driven by the clock pad to distribute a clock directly to the

device, or driven by the Digital Clock Manager (DCM), discussed in Digital Clock Manager (DCM),

page 37. Each global clock buffer can also be driven by local interconnects. The DCM has clock

output(s) that can be connected to global clock buffer inputs, as shown in Figure 37.

Clock

Pad

Clock

Pad

I

CLKIN

Clock

Buffer

DCM

CLKOUT

I

0

Clock Distribution

Clock

Buffer

0

Clock Distribution

DS031_43_101000

Figure 37: Virtex-II Clock Distribution Configurations

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Global clock buffers are used to distribute the clock to some or all synchronous logic elements

(such as registers in CLBs and IOBs, and SelectRAM blocks.

Eight global clocks can be used in each quadrant of the Virtex-II device. Designers should consider

the clock distribution detail of the device prior to pin-locking and floorplanning (see the Virtex-II User

Guide).

Figure 38 shows clock distribution in Virtex-II devices.

8 BUFGMUX

NE

NW

8

8 BUFGMUX

8

NW

SW

NE

8 max

16 Clocks

8

SE

8 BUFGMUX

SW

8 BUFGMUX

DS031_45_120200

Figure 38: Virtex-II Clock Distribution

In each quadrant, up to eight clocks are organized in clock rows. A clock row supports up to 16 CLB

rows (eight up and eight down). For the largest devices a new clock row is added, as necessary.

To reduce power consumption, any unused clock branches remain static.

The global clock multiplexer buffers have two clock inputs, a select input, and a clock output. The

select input selects between I_Oand I₁without generating glitches.

The most common configuration option of this element is as a buffer. A BUFG function in this

(global buffer) mode, is shown in Figure 39.

BUFG

I

O

DS031_61_101200

Figure 39: Virtex-II BUFG Function

In Figure 40 the global buffer can also perform a clock enable function (clock gating). The CE input

is synchronized inside the BUFG so any change in CE is only effective when the clock input is Low.

This eliminates any glitches or runt pulses on the output, even when CE changes asynchronously

to the clock.

BUFGCE

I

O

CE

DS031_62_101200

Figure 40: Virtex-II BUFGCE Function

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The two clock inputs can be connected to any synchronous or asynchronous clock (from a clock

pad or DCM clock output). When the select input (S) is Low, the clock connected to the I₀input is

distributed, as shown in Figure 41. Setting S High, causes the clock connected to the I₁input to be

distributed.

The clock multiplexer can also switch between two unrelated clocks. The S input can be changed

asynchronously to both clocks. Internal synchronization switches away for the present clock when

it is low but switches to the new clock only after the subsequent falling edge.

BUFGMUX

I0

O

I1

S

DS031_63_112900

Figure 41: Virtex-II BUFGMUX Function

When S changes state, the transition on the output occurs without creating a runt pulse. The output

pulse is never shorter than the I₀or I₁input pulse. The S input has a setup requirement.

The global clock multiplexer buffers has two options:

•

Transition on Low clock states

•

Transition on High clock states

The transition on Low follows different steps, as illustrated in Figure 42.

Wait for Low

S

CLK0

Switch

CLK1

OUT

DS031_46_112900

Figure 42: Clock Multiplexer Waveform Diagram

•

The current clock is CLK0.

•

Once CLK0 is Low, the multiplexer output

stays Low, until CLK1 goes Low.

S is activated High (setup is required

before the next negative CLK0 edge).

When CLK1 transitions from High to Low,

the output switches to CLK1.

•

If CLK0 is currently High, the multiplexer

waits for the next negative edge.

No glitches or short pulses can appear on

the output.

The transition on High clock state is similar, with the positive edge of the second clock Low.

All Virtex-II devices have 16 global clock multiplexer buffers.

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Digital Clock Manager (DCM)

The Virtex-II DCM offers a wide range of powerful clock management features.

•

Clock De-skew: The DCM generates new system clocks (either internally or externally to the

FPGA), which are phase-aligned to the input clock.

Frequency Synthesis: The DCM generates a wide range of output clock frequencies,

performing very flexible clock multiplication and division.

Phase Shifting: The DCM provides both coarse phase shifting and fine-grained phase shifting

with dynamic phase shift control.

EMI Reduction: The DCM provides the capability to reduce electromagnetic interference

(EMI) by broadening the output clock frequency spectrum.

The DCM utilizes fully digital delay lines allowing robust high-precision control of clock phase and

frequency. It also utilizes fully digital feedback systems, operating dynamically to compensate for

temperature and voltage variations during operation.

Up to four DCM clock outputs can drive global clock multiplexer buffer inputs simultaneously (see

Figure 43). All DCM clock outputs can simultaneously drive general routing resources, including

routes to output buffers.

DCM

CLK0

CLKIN

CLK90

CLK180

CLKFB

CLK270

RST

CLK2X

CLK2X180

DSSEN

CLKDV

PSINCDEC

PSEN

CLKFX

CLKFX180

PSCLK

LOCKED

STATUS[7:0]

PSDONE

clock signal

control signal

DS031_67_112900

Figure 43: Digital Clock Manager

The DCM can be configured to delay the completion of the Virtex-II configuration process until after

the DCM has achieved lock. This guarantees that the chip does not begin operating until after the

system clocks generated by the DCM have stabilized.

The DCM has the following general control signals:

•

RST input pin: resets the entire DCM

LOCKED output pin: asserted High when all enabled DCM circuits have locked.

STATUS output pins (active High): shown in Table 20.

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Table 20: DCM Status Pins

Status Pin

Function

0

1

2

3

4

5

6

7

Phase Shift Overflow

CLKIN Stopped

N/A

Clock De-Skew

The DCM de-skews the output clocks relative to the input clock by automatically adjusting a digital

delay line. Additional delay is introduced so that clock edges arrive at internal registers and block

RAM synchronous to clock edges arriving at the input. Alternatively, external clocks, which are also

de-skewed relative to the input clock, can be generated for board-level routing. All DCM output

clocks are phase-aligned to CLK0 and, therefore, are also phase-aligned to the input clock.

To achieve clock de-skew, the CLKFB input must be connected, and its source must be either CLK0

or CLK2X. Note that CLKFB must always be connected, unless only the CLKFX or CLKFX180

outputs are used and de-skew is not required.

Frequency Synthesis

The DCM provides flexible methods for generating new clock frequencies. Each method has a

different operating frequency range and different AC characteristics. The CLK2X and CLK2X180

outputs can be used to double the clock frequency. The CLKDV output can be used to create

divided output clocks with division options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 7.5, 8, 9, 10,

11, 12, 13, 14, 15, and 16.

The CLKFX and CLKFX180 outputs can be used to produce clocks at the following frequency:

FREQ_CLKFX= (M/D) * FREQ_CLKIN

where M and D are two integers, each between 1 and 4096. By default, M=4 and D=1, which results

in a clock output frequency four times faster than the clock input frequency (CLKIN).

CLK2X180 is phase shifted 180 degrees relative to CLK2X. CLKFX180 is phase shifted 180 degrees

relative to CLKFX. All frequency synthesis outputs automatically have 50/50 duty cycles (with the

exception of the CLKDV output when performing a non-integer divide in high frequency mode).

Phase Shifting

The DCM provides additional control over clock skew through either coarse or fine-grained phase

shifting. The CLK0, CLK90, CLK180, and CLK270 outputs are each phase shifted by ¼ of the input

clock period relative to each other, allowing coarse phase adjustments.

Fine phase adjustment applies to all DCM output clocks when activated. The phase shift between

the rising edges of CLKIN and CLKFB is configured to be a specified fraction of the input clock

period, and it can be dynamically adjusted with the dedicated signals, PSINCDEC, PSEN, PSCLK,

and PSDONE. The phase shift value (PS) is specified as an integer between –255 and +255. The

amount of phase shift achieved is given by the equation:

Phase shift = (PS/256) * PERIOD_CLKIN

In variable mode, the PS value can be dynamically incremented or decremented according to

PSINCDEC synchronously to PSCLK, when the PSEN input is active. Figure 44 illustrates the

effects of fine phase shifting.

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Table 21 lists fine phase shifting control pins, when used in variable mode.

Table 21: Fine Phase Shifting Control Pins

Control Pin

PSINCDEC

PSEN

Direction

Function

in

Increment or decrement

Enable ± phase shift

Clock for phase shift

Active when completed

PSCLK

in

PSDONE

out

CLKIN

CLKFB

CLKOUT_PHASE_SHIFT

= NONE

CLKIN

CLKFB

CLKOUT_PHASE_SHIFT

= FIXED

(PS/256) x PERIOD

(PS negative)

(PS/256) x PERIOD

(PS positive)

CLKIN

CLKFB

CLKOUT_PHASE_SHIFT

= VARIABLE

(PS/256) x PERIOD

CLKIN

(PS/256) x PERIOD

CLKIN

(PS negative)

(PS positive)

DS031_48_110300

Figure 44: Fine Phase Shifting Effects

EMI Reduction

The DCM offers a Digital Spread Spectrum (DSS) feature that broadens the frequency spectrum of

the clock outputs. The spectrum spreading applies directly to the CLK0, CLK90, CLK180, and

CLK270 clock outputs when it is active. The other DCM clock outputs are affected to only a small

degree. Spreading the spectrum of the clock frequency reduces the electromagnetic interference

(EMI), or energy radiation, within the relevant frequency bandwidth window. This technique aids in

meeting FCC EMI regulations.

When enabled, spectrum spreading begins immediately after the LOCKED signal goes HIGH. The

DSSEN input can be used to enable/disable the feature during operation. Table 22 lists available

DSS options.

.

Table 22: DSS Options

Number of

Frequencies Added

Clock Period

Range

Mode

2

4

6

8

SPREAD_2

SPREAD_4

SPREAD_6

SPREAD_8

± 1 x DCM_TAP

± 2 x DCM_TAP

± 3 x DCM_TAP

± 4 x DCM_TAP

Notes:

1. DCM_TAP value is defined in the AC characteristics section

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Operating Modes

The frequency ranges of the DCM input and output clocks depend on the operating mode specified,

either low frequency mode or high frequency mode, according to Table 23 (for actual values, see

Virtex-II Switching Characteristics). The CLK2X, CLK2X180, CLK90, and CLK270 outputs are

not available in high frequency mode.

Table 23: DCM Frequency Ranges

Low-Frequency Mode

CLKIN Input CLK Output

CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_1X_HF

High-Frequency Mode

Output Clock

CLKIN Input CLK Output

CLK0, CLK180

CLK90, CLK270

CLK2X, CLK2X180

CLKDV

CLKIN_FREQ_DLL_LF CLKOUT_FREQ_1X_LF

CLKIN_FREQ_DLL_LF CLKOUT_FREQ_2X_LF

NA

CLKIN_FREQ_DLL_LF CLKOUT_FREQ_DV_LF CLKIN_FREQ_DLL_HF CLKOUT_FREQ_DV_HF

CLKIN_FREQ_FX_LF CLKOUT_FREQ_FX_LF CLKIN_FREQ_FX_HF CLKOUT_FREQ_FX_HF

CLKFX, CLKFX180

Locations/Organization

Virtex-II DCMs are placed on the top and bottom of each block RAM and multiplier column. The

number of DCMs depends on the device size, as shown in Table 24.

Table 24: DCM Organization

Device

XC2V40

Columns

DCMs

4

2

4

6

XC2V80

4

XC2V250

XC2V500

XC2V1000

XC2V1500

XC2V2000

XC2V3000

XC2V4000

XC2V6000

XC2V8000

XC2V10000

8

12

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Active Interconnect Technology

Local and global Virtex-II routing resources are optimized for speed and timing predictability, as well

as to facilitate IP cores implementation. Virtex-II Active Interconnect Technology is a fully buffered

programmable routing matrix. All routing resources are segmented to offer the advantages of a

hierarchical solution. Virtex-II logic features like CLBs, IOBs, block RAM, multipliers, and DCMs are

all connected to an identical switch matrix for access to global routing resources, as shown in

Figure 45.

Switch

Matrix

Switch

CLB

Matrix

Switch

Matrix

Switch

Matrix

18Kb

MULT

IOB

BRAM

18 x 18

Switch

Matrix

Switch

Matrix

DCM

Switch

Matrix

DS031_55_101000

Figure 45: Active Interconnect Technology

Each Virtex-II device can be represented as an array of switch matrixes with logic blocks attached,

as illustrated in Figure 46.

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

IOB

CLB

IOB

CLB

DCM

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

Switch

Matrix

DS031_34_110300

Figure 46: Routing Resources

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Place-and-route software takes advantage of this regular array to deliver optimum system

performance and fast compile times. The segmented routing resources are essential to guarantee

IP cores portability and to efficiently handle an incremental design flow that is based on modular

implementations. Total design time is reduced due to fewer and shorter design iterations.

Hierarchical Routing Resources

Most Virtex-II signals are routed using the global routing resources, which are located in horizontal

and vertical routing channels between each switch matrix.

As shown in Figure 46, Virtex-II has fully buffered programmable interconnections, with a number of

resources counted between any two adjacent switch matrix rows or columns. Fanout has minimal

impact on the performance of each net.

24 Horizontal Long Lines

24 Vertical Long Lines

120 Horizontal Hex Lines

120 Vertical Hex Lines

40 Horizontal Double Lines

40 Vertical Double Lines

16 Direct Connections

(total in all four directions)

8 Fast Connects

DS031_60_110200

Figure 47: Hierarchical Routing Resources

•

The long lines are bidirectional wires that distribute signals across the device. Vertical and

horizontal long lines span the full height and width of the device.

The hex lines route signals to every third or sixth block away in all four directions. Organized in

a staggered pattern, hex lines can only be driven from one end. Hex-line signals can be

accessed either at the endpoints or at the midpoint (three blocks from the source).

•

The double lines route signals to every first or second block away in all four directions.

Organized in a staggered pattern, double lines can be driven only at their endpoints. Double-

line signals can be accessed either at the endpoints or at the midpoint (one block from the

source).

•

The direct connect lines route signals to neighboring blocks: vertically, horizontally, and

diagonally.

The fast connect lines are the internal CLB local interconnections from LUT outputs to LUT

inputs.

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Dedicated Routing

In addition to the global and local routing resources, dedicated signals are available.

•

There are eight global clock nets per quadrant (see Global Clock Multiplexer Buffers).

Horizontal routing resources are provided for on-chip 3-state busses. Four partitionable bus lines

are provided per CLB row, permitting multiple busses within a row. (See 3-State Buffers.)

•

Two dedicated carry-chain resources per slice column (two per CLB column) propagate carry-

chain MUXCY output signals vertically to the adjacent slice. (See CLB/Slice Configurations.)

One dedicated SOP chain per slice row (two per CLB row) propagate ORCY output logic

signals horizontally to the adjacent slice. (See Sum of Products.)

One dedicated shift-chain per CLB connects the output of LUTs in shift-register mode to the

input of the next LUT in shift-register mode (vertically) inside the CLB. (See Shift Registers,

page 18.)

Creating a Design

Creating Virtex-II designs is easy with Xilinx development systems, supporting advanced design

capabilities including incremental synthesis, modular design, integrated logic analysis, and the

fastest place and route runtimes in the industry. This means designers get the performance they

need, quickly.

As a result of the ongoing cooperative development efforts between Xilinx and EDA Alliance

partners, designers can take advantage of the benefits provided by EDA technologies in the

programmable logic design process. Xilinx development systems are available in a number of easy

to use configurations within the Alliance Series and Foundation Series product families.

Alliance Series Solutions

Alliance Series solutions are designed to plug and play within a chosen design environment. Built

using industry standard data formats and netlists, these stable, flexible products also enable

Alliance EDA partners to deliver their best design automation capabilities to Xilinx customers,

providing incremental synthesis, modular design, and error navigation -- all features developed with

Xilinx EDA partners, for use with Xilinx development systems first.

Foundation Series Solutions

Foundation Series solutions feature Foundation Integrated Synthesis Environment (ISE) tools, a

family of products that deliver all of the benefits of true HDL-based design in a seamlessly

integrated design environment. An intuitive project navigator, as well as powerful HDL design and

two HDL synthesis tools, ensure that high-quality results are achieved quickly and easily. The

Foundation ISE product includes:

•

State Diagram entry using StateCAD XE

Automatic HDL Testbench generation using HDLBencher XE

HDL Simulation using ModelSim XE-starter (MXE-starter).

MXE Starter is particularly useful in demonstrating the seamless integration available between the

ISE design environment and ModelSim HDL Simulation tools.

Design Flow

Virtex-II design flow proceeds as follows:

•

Design Entry

Synthesis

Implementation

Verification

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Most programmable logic designers iterate through these steps several times in the process of

completing a design.

Design Entry

Xilinx development systems support the mainstream EDA design entry capabilities, ranging from

schematic design to advanced HDL design methodologies. Given the high densities of the Virtex-II

family, designs are most efficiently created using HDLs. To improve efficiency, many Xilinx

customers employ incremental, modular, and Intellectual Property (IP) design techniques. When

properly used, these techniques further accelerate the logic design process.

To enable designers to leverage existing investments in EDA tools, and to ensure high performance

design flows, Xilinx jointly develops tools with leading EDA vendors, including:

•

Aldec

Cadence

Exemplar

Mentor Graphics

Model Technology

Synopsys

Synplicity

VSS

Complete information on Alliance Series partners and their associated design flows is available

from the Xilinx Alliance Series web page:

www.xilinx.com/products/alliance.htm

Xilinx Foundation Series products offer schematic entry and HDL design capabilities as part of an

integrated design solution - enabling one-stop shopping. These capabilities are powerful, easy to

use, and they support the full portfolio of Xilinx programmable logic devices. HDL design

capabilities include a color-coded HDL editor with integrated language templates, state diagram

entry, and Core generation capabilities.

Synthesis

Alliance Series products are engineered to support advanced design flows with the industry's best

synthesis tools for:

•

Incremental synthesis

RTL floorplanning

Automated timing convergence

Direct physical mapping

The Xilinx Foundation ISE product family includes synthesis capabilities from both FPGA Express

and a proprietary synthesis tool referred to as Xilinx Synthesis Technology. Having two seamlessly

integrated synthesis engines within the Foundation ISE products provides an alternative set of

optimization techniques for designs, helping to ensure that Foundation ISE can meet even the

toughest timing requirements.

Both FPGA Express and Xilinx Synthesis Technology support the synthesis of VHDL and Verilog;

however, only FPGA Express enables mixed-language synthesis. Future releases of the ISE design

environment are planned to also integrate other third party synthesis tools, like Synplicity Synplify

and Exemplar's Leonardo Spectrum.

Design Implementation

The Alliance Series and Foundation Series development systems both include Xilinx timing-driven

implementation tools, frequently called “place and route” software. This robust suite of tools

enables the creation of an intuitive, flexible, tightly integrated design flow that efficiently bridges the

“logical” and “physical” design domains. This simplifies the task of defining a design, including its

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behavior, timing requirements, and optional layout (or floorplanning), as well as simplifying the task

of analyzing reports generated during the implementation process.

The Virtex-II implementation process is comprised of Synthesis, translation, mapping, place and

route, and configuration file generation. While the tools can be run individually, many designers

choose to run the entire implementation process with the click of a button. To assist those who

prefer to script their design flows, Xilinx provides Xflow, an automated single command line

process.

Design Verification

In addition to conventional design verification using static timing analysis or dynamic timing

analysis (simulation), powerful in-circuit debugging techniques using Xilinx ChipScope ILA

(Integrated Logic Analysis) is available. In these reconfigurable Xilinx FPGAs, designs can be

verified in real time without the need for extensive sets of software simulation vectors. The

development system supports both software simulation and in-circuit debugging techniques.

For simulation, the system extracts post-layout timing information from the design database, and

back-annotates this information into the netlist for use by the simulator. The back annotation

features a variety of patented Xilinx techniques, resulting in the industry’s most powerful simulation

flows. Alternatively, the user can verify timing-critical portions of a design using the TRCE® static

timing analyzer, or using a third party static timing analysis tool by exporting timing data in the

STAMP data format.

For in-circuit debugging, ChipScope ILA enables designers to analyze the real-time behavior of a

device while operating at full system speeds. Logic analysis commands and captured data are

transferred between the ChipScope software and ILA cores within the Virtex-II FPGA, using

industry standard JTAG protocols. These JTAG transactions are driven over an optional download

cable (MultiLINX or JTAG), connecting the Virtex device in the target system to a PC or workstation.

ChipScope ILA was designed to look and feel like a logic analyzer, making it easy to begin

debugging a design immediately. Modifications to the desired logic analysis can be downloaded

into the system in a matter of minutes.

Other Unique Features of Virtex-II Design Flow

Xilinx design flows feature a number of unique capabilities. Among these are efficient incremental

HDL design flows; a robust capability that is enabled by Xilinx exclusive hierarchical floorplanning

capabilities. Another powerful design capability only available in the Xilinx design flow is “Modular

Design”, part of the Xilinx suite of team design tools, which enables autonomous design,

implementation, and verification of design modules.

Incremental Synthesis

Xilinx unique hierarchical floorplanning capabilities enable designers to create a programmable

logic design by isolating design changes within one hierarchical “logic block”, and perform

synthesis, verification and implementation processes on that specific logic block. By preserving the

logic in unchanged portions of a design, Xilinx incremental design makes the high-density design

process more efficient.

Xilinx hierarchical floorplanning capabilities can be specified using the high-level floorplanner or a

preferred RTL floorplanner (see the Xilinx web site for a list of supported EDA partners). When used

in conjunction with one of the EDA partners’ floorplanners, higher performance results can be

achieved, as many synthesis tools use this more predictable detailed physical implementation

information to establish more aggressive and accurate timing estimates when performing their logic

optimizations.

Modular Design

Xilinx innovative modular design capabilities take the incremental design process one step further

by enabling the designer to delegate responsibility for completing the design, synthesis, verification,

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and implementation of a hierarchical “logic block” to an arbitrary number of designers - assigning a

specific region within the target FPGA for exclusive use by each of the team members.

This team design capability enables an autonomous approach to design modules, changing the

hand-off point to the lead designer or integrator from “my module works in simulation” to “my

module works in the FPGA”. This unique design methodology also leverages the Xilinx hierarchical

floorplanning capabilities and enables the Xilinx (or EDA partner) floorplanner to manage the

efficient implementation of very high-density FPGAs.

Configuration

Virtex-II devices are configured by loading application specific configuration data into the internal

configuration memory. Configuration is carried out using a subset of the device pins, some of which

are dedicated, while others can be re-used as general purpose inputs and outputs once

configuration is complete.

Depending on the system design, several configuration modes are supported, selectable via mode

pins. The mode pins M2, M1 and M0 are dedicated pins. An additional pin, HSWAP_EN is used in

conjunction with the mode pins to select whether user I/O pins have pull-ups during configuration.

By default, HSWAP_EN is tied High (internal pull-up) which shuts off the pull-ups on the user I/O

pins during configuration. When HSWAP_EN is tied Low, user I/Os have pull-ups during

configuration. Other dedicated pins are CCLK (the configuration clock pin), DONE, PROG_B, and

the boundary-scan pins: TDI, TDO, TMS, and TCK. Depending on the configuration mode chosen,

CCLK can be an output generated by the FPGA, or an input accepting an externally generated

clock. The configuration pins and boundary scan pins are independent of the V_CCO. The auxiliary

power supply (V_CCAUX) of 3.3V is used for these pins. (See Virtex-II DC Characteristics.)

A persist option is available which can be used to force the configuration pins to retain their

configuration function even after device configuration is complete. If the persist option is not

selected then the configuration pins with the exception of CCLK, PROG_B, and DONE can be used

as user I/O in normal operation. The persist option does not apply to the boundary-scan related

pins. The persist feature is valuable in applications which employ partial reconfiguration or

reconfiguration on the fly.

Configuration Modes

Virtex-II supports the following five configuration modes:

•

Slave-serial mode

Master-serial mode

Slave SelectMAP mode

Master SelectMAP mode

Boundary-Scan mode (IEEE 1532/IEEE 1149)

A detailed description of configuration modes is provided in the Virtex-II User Guide.

Slave-Serial Mode

In slave-serial mode, the FPGA receives configuration data in bit-serial form from a serial PROM or

other serial source of configuration data. The CCLK pin on the FPGA is an input in this mode. The

serial bitstream must be setup at the DIN input pin a short time before each rising edge of the

externally generated CCLK.

Multiple FPGAs can be daisy-chained for configuration from a single source. After a particular

FPGA has been configured, the data for the next device is routed internally to the DOUT pin. The

data on the DOUT pin changes on the rising edge of CCLK.

Slave-serial mode is selected by applying <111> to the mode pins (M2, M1, M0). A weak pull-up on

the mode pins makes slave serial the default mode if the pins are left unconnected.

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Master-Serial Mode

In master-serial mode, the CCLK pin is an output pin. It is the Virtex-II FPGA device that drives the

configuration clock on the CCLK pin to a Xilinx Serial PROM which in turn feeds bit-serial data to the

DIN input. The FPGA accepts this data on each rising CCLK edge. After the FPGA has been loaded,

the data for the next device in a daisy-chain is presented on the DOUT pin after the rising CCLK edge.

The interface is identical to slave serial except that an internal oscillator is used to generate the

configuration clock (CCLK). A wide range of frequencies can be selected for CCLK which always

starts at a slow default frequency. Configuration bits then switch CCLK to a higher frequency for the

remainder of the configuration.

Slave SelectMAP Mode

The SelectMAP mode is the fastest configuration option. Byte-wide data is written into the Virtex-II

FPGA device with a BUSY flag controlling the flow of data. An external data source provides a byte

stream, CCLK, an active Low Chip Select (CS_B) signal and a Write signal (RDWR_B). If BUSY is

asserted (High) by the FPGA, the data must be held until BUSY goes Low. Data can also be read

using the SelectMAP mode. If RDWR_B is asserted, configuration data is read out of the FPGA as

part of a readback operation.

After configuration, the pins of the SelectMAP port can be used as additional user I/O. Alternatively,

the port can be retained to permit high-speed 8-bit readback using the persist option.

Multiple Virtex-II FPGAs can be configured using the SelectMAP mode, and be made to start-up

simultaneously. To configure multiple devices in this way, wire the individual CCLK, Data, RDWR_B,

and BUSY pins of all the devices in parallel. The individual devices are loaded separately by

deasserting the CS_B pin of each device in turn and writing the appropriate data.

Master SelectMAP Mode

This mode is a master version of the SelectMAP mode. The device is configured byte-wide on a

CCLK supplied by the Virtex-II FPGA device. Timing is similar to the Slave SerialMAP mode except

that CCLK is supplied by the Virtex-II FPGA.

Boundary-Scan (JTAG, IEEE 1532) Mode

In boundary-scan mode, dedicated pins are used for configuring the Virtex-II device. The

configuration is done entirely through the IEEE 1149.1 Test Access Port (TAP). Virtex-II device

configuration using Boundary scan is compliant with IEEE 1149.1-1993 standard and the new IEEE

1532 standard for In-System Configurable (ISC) devices. The IEEE 1532 standard is backward

compliant with the IEEE 1149.1-1993 TAP and state machine. The IEEE Standard 1532 for In-

System Configurable (ISC) devices is intended to be programmed, reprogrammed, or tested on the

board via a physical and logical protocol.

Configuration through the boundary-scan port is always available, independent of the mode

selection. Selecting the boundary-scan mode simply turns off the other modes.

Table 25: Virtex-II Configuration Mode Pin Settings

2

Configuration Mode¹M2

M1

0

M0

0

CCLK Direction

Data Width

Serial D_OUT

Master Serial

0

1

0

1

Out

In

1

8

1

Yes

No

Slave Serial

1

Master SelectMAP

Slave SelectMAP

Boundary Scan

1

Out

In

1

0

1

N/A

Notes:

1. The HSWAP_EN pin controls the pullups. Setting M2, M1, and M0 selects the configuration mode, while

the HSWAP_EN pin controls whether or not the pullups are used.

2. Daisy chaining is possible only in modes where Serial D_OUTis used. For example, in SelectMAP modes,

the first device does NOT support daisy chaining of downstream devices.

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Table 26 lists the total number of bits required to configure each device.

Table 26: Virtex-II Bitstream Lengths

Device

XC2V40

# of Configuration Bits

338,208

597,408

XC2V80

XC2V250

XC2V500

XC2V1000

XC2V1500

XC2V2000

XC2V3000

XC2V4000

XC2V6000

XC2V8000

XC2V10000

1,591,584

2,557,856

3,749,408

5,166,240

6,808,352

9,589,408

14,220,192

19,752,096

26,185,120

33,519,264

Configuration Sequence

The configuration of Virtex-II devices is a three-phase process. First, the configuration memory is

cleared. Next, configuration data is loaded into the memory, and finally, the logic is activated by a

start-up process.

Configuration is automatically initiated on power-up unless it is delayed by the user. The INIT_B pin

can be held Low using an open-drain driver. An open-drain is required since INIT_B is a

bidirectional open-drain pin that is held Low by a Virtex-II FPGA device while the configuration

memory is being cleared. Extending the time that the pin is Low causes the configuration

sequencer to wait. Thus, configuration is delayed by preventing entry into the phase where data is

loaded.

The configuration process can also be initiated by asserting the PROG_B pin. The end of the

memory-clearing phase is signaled by the INIT_B pin going High, and the completion of the entire

process is signaled by the DONE pin going High. The Global Set/Reset (GSR) signal is pulsed after

the last frame of configuration data is written but before the start-up sequence. The GSR signal

resets all flip-flops on the device.

The default start-up sequence is that one CCLK cycle after DONE goes High, the global 3-state

signal (GTS) is released. This permits device outputs to turn on as necessary. One CCLK cycle

later, the Global Write Enable (GWE) signal is released. This permits the internal storage elements

to begin changing state in response to the logic and the user clock.

The relative timing of these events can be changed via configuration options in software. In

addition, the GTS and GWE events can be made dependent on the DONE pins of multiple devices

all going High, forcing the devices to start synchronously. The sequence can also be paused at any

stage, until lock has been achieved on any or all DCMs, as well as the DCI.

Readback

In this mode, configuration data from the Virtex-II FPGA device can be read back. Readback is

supported only in the SelectMAP (master and slave) and Boundary Scan mode.

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Along with the configuration data, it is possible to read back the contents of all registers, distributed

SelectRAM, and block RAM resources. This capability is used for real-time debugging. For more

detailed configuration information, see the Virtex-II User Guide.

Bitstream Encryption

Virtex-II devices have an on-chip decryptor using one or two sets of three keys for triple-key Data

Encryption Standard (DES) operation. Xilinx software tools offer an optional encryption of the

configuration data (bitstream) with a triple-key DES determined by the designer.

The keys are stored in the FPGA by JTAG instruction and retained by a battery connected to the

V_BATTpin, when the device is not powered. Virtex-II devices can be configured with the

corresponding encrypted bitstream, using any of the configuration modes described previously.

A detailed description of how to use bitstream encryption is provided in the Virtex-II User Guide.

Partial Reconfiguration

Partial reconfiguration of Virtex-II devices can be accomplished in either Slave SelectMAP mode or

Boundary-Scan mode. Instead of resetting the chip and doing a full configuration, new data is

loaded into a specified area of the chip, while the rest of the chip remains in operation. Data is

loaded on a column basis, with the smallest load unit being a configuration “frame” of the bitstream

(device size dependent).

Partial reconfiguration is useful for applications that require different designs to be loaded into the

same area of a chip, or that require the ability to change portions of a design without having to reset

or reconfigure the entire chip.

Power-Down Sequence

The power-down sequence enables a designer to set the device into a low-power, inactive state.

The sequence is initiated by pulling the PWRDWN_B pin Low.

If the PWRDWN_STAT option is selected using BitGen, the DONE pin can serve as the power-

down status pin. When asserted, power-down has completed. After a successful wake-up, the

status pin deasserts. While powered down, the only active pins are the PWRDWN_B and DONE.

All inputs are off and all outputs are 3-stated.

While in the POWERDOWN state, the Power On Reset (POR) circuit is still active, but it does not

reset the device if V_CCINT, V_CCO, or V_CCAUXfalls below its minimum value. The POR circuit waits

until the PWRDWN_B pin is released before resetting the device. Also, the PROG_B pin is not

sampled while the device is in the POWERDOWN state. The PROG_B pin becomes active when

the PWRDWN_B pin is released. Therefore, the device cannot be reset while in the POWERDOWN

state.

The wake-up sequence is the reverse of the power-down sequence.

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Revision History

This section records the change history for this module of the data sheet.

Date

Version

1.0

Revision

11/07/00

12/06/00

01/15/01

Early access draft.

Initial release.

1.1

1.2

Added values to the tables in the Virtex-II Performance Characteristics and Virtex-II

Switching Characteristics sections.

01/25/01

1.3

The data sheet was divided into four modules (per the current style standard). A note was

added to Table 1, “Supported Single-Ended I/O Standards,” on page 1.

Virtex-II Data Sheet

The Virtex-II Data Sheet contains the following modules:

•

DS031-1, Virtex-II 1.5V FPGAs: Introduction and Ordering Information (Module 1)

DS031-2, Virtex-II 1.5V FPGAs: Functional Description (Module 2)

DS031-3, Virtex-II 1.5V FPGAs: DC and Switching Characteristics (Module 3)

DS031-4, Virtex-II 1.5V FPGAs: Pinout Tables (Module 4)

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