XC2S15-6VQ100I [XILINX]
Spartan-II 2.5V FPGA Family:Introduction and Ordering Information; 的Spartan- II 2.5V FPGA系列：介绍和订购信息
| 型号： | XC2S15-6VQ100I |
| 厂家： | 
XILINX, INC |
| 描述： | Spartan-II 2.5V FPGA Family:Introduction and Ordering Information |
| 文件： | 总4页 (文件大小：44K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Spartan-II 2.5V FPGA Family:
Introduction and Ordering
Information
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DS001-1 (v2.3) November 1, 2001
Preliminary Product Specification
•
System level features
Introduction
-
SelectRAM+™ hierarchical memory:
The Spartan™-II 2.5V Field-Programmable Gate Array fam-
ily gives users high performance, abundant logic resources,
and a rich feature set, all at an exceptionally low price. The
six-member family offers densities ranging from 15,000 to
200,000 system gates, as shown in Table 1. System perfor-
mance is supported up to 200 MHz.
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·
·
16 bits/LUT distributed RAM
Configurable 4K bit block RAM
Fast interfaces to external RAM
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-
-
-
-
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-
-
-
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Fully PCI compliant
Low-power segmented routing architecture
Full readback ability for verification/observability
Dedicated carry logic for high-speed arithmetic
Dedicated multiplier support
Cascade chain for wide-input functions
Abundant registers/latches with enable, set, reset
Four dedicated DLLs for advanced clock control
Four primary low-skew global clock distribution nets
IEEE 1149.1 compatible boundary scan logic
Spartan-II devices deliver more gates, I/Os, and features
per dollar than other FPGAs by combining advanced pro-
cess technology with a streamlined Virtex-based architec-
ture. Features include block RAM (to 56K bits), distributed
RAM (to 75,264 bits), 16 selectable I/O standards, and four
DLLs. Fast, predictable interconnect means that successive
design iterations continue to meet timing requirements.
The Spartan-II family is
a
superior alternative to
•
•
Versatile I/O and packaging
mask-programmed ASICs. The FPGA avoids the initial cost,
lengthy development cycles, and inherent risk of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary (impossible with ASICs).
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-
-
-
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Low cost packages available in all densities
Family footprint compatibility in common packages
16 high-performance interface standards
Hot swap Compact PCI friendly
Zero hold time simplifies system timing
Features
Fully supported by powerful Xilinx development system
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Foundation ISE Series: Fully integrated software
Alliance Series: For use with third-party tools
Fully automatic mapping, placement, and routing
•
Second generation ASIC replacement technology
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Densities as high as 5,292 logic cells with up to
200,000 system gates
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Streamlined features based on Virtex architecture
Unlimited reprogrammability
Very low cost
Table 1: Spartan-II FPGA Family Members
CLB
Array
(R x C)
Maximum
Available
User I/O
Total
Distributed RAM
Bits
Total
Block RAM
Bits
Logic
Cells
System Gates
(Logic and RAM)
Total
CLBs
(1)
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
432
972
15,000
30,000
8 x 12
12 x 18
16 x 24
20 x 30
24 x 36
28 x 42
96
86
6,144
13,824
24,576
38,400
55,296
75,264
16K
24K
32K
40K
48K
56K
216
132
176
196
260
284
1,728
2,700
3,888
5,292
50,000
384
100,000
150,000
200,000
600
864
1,176
Notes:
1. All user I/O counts do not include the four global clock/user input pins. See details in Table 3, page 3.
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS001-1 (v2.3) November 1, 2001
www.xilinx.com
1
Preliminary Product Specification
1-800-255-7778
R
Spartan-II 2.5V FPGA Family: Introduction and Ordering Information
Spartan-II FPGAs are typically used in high-volume applica-
tions where the versatility of a fast programmable solution
adds benefits. Spartan-II FPGAs are ideal for shortening
product development cycles while offering a cost-effective
solution for high volume production.
General Overview
The Spartan-II family of FPGAs have a regular, flexible, pro-
grammable architecture of Configurable Logic Blocks
(CLBs), surrounded by a perimeter of programmable
Input/Output Blocks (IOBs). There are four Delay-Locked
Loops (DLLs), one at each corner of the die. Two columns
of block RAM lie on opposite sides of the die, between the
CLBs and the IOB columns. These functional elements are
interconnected by a powerful hierarchy of versatile routing
channels (see Figure 1).
Spartan-II FPGAs achieve high-performance, low-cost
operation through advanced architecture and semiconduc-
tor technology. Spartan-II devices provide system clock
rates up to 200 MHz. Spartan-II FPGAs offer the most
cost-effective solution while maintaining leading edge per-
formance. In addition to the conventional benefits of
high-volume programmable logic solutions, Spartan-II
FPGAs also offer on-chip synchronous single-port and
dual-port RAM (block and distributed form), DLL clock driv-
ers, programmable set and reset on all flip-flops, fast carry
logic, and many other features.
Spartan-II FPGAs are customized by loading configuration
data into internal static memory cells. Unlimited reprogram-
ming cycles are possible with this approach. Stored values
in these cells determine logic functions and interconnec-
tions implemented in the FPGA. Configuration data can be
read from an external serial PROM (master serial mode), or
written into the FPGA in slave serial, slave parallel, or
Boundary Scan modes.
The Xilinx XC17S00A PROM family is recommended for
serial configuration of Spartan-II FPGAs. The In-System
Programmable (ISP) XC18V00 PROM family is recom-
mended for parallel or serial configuration.
DLL
DLL
CLBs
CLBs
CLBs
CLBs
DLL
DLL
I/O LOGIC
XC2S15
DS001_01_091800
Figure 1: Basic Spartan-II Family FPGA Block Diagram
2
www.xilinx.com
DS001-1 (v2.3) November 1, 2001
1-800-255-7778
Preliminary Product Specification
R
Spartan-II 2.5V FPGA Family: Introduction and Ordering Information
Spartan-II Product Availability
Table 2 shows the package and speed grades available for
Spartan-II family devices. Table 3 shows the maximum user
I/Os available on the device and the number of user I/Os
available for each device/package combination. The four
global clock pins are usable as additional user I/Os when
not used as a global clock pin. These pins are not included
in user I/O counts.
Table 2: Spartan-II Package and Speed Grade Availability
Pins
100
144
144
208
256
456
Plastic
VQFP
Plastic
TQFP
Chip Scale
BGA
Plastic
PQFP
Fine Pitch
BGA
Fine Pitch
BGA
Type
Code
-5
Device
VQ100
TQ144
CS144
PQ208
-
FG256
FG456
XC2S15
C, I
C, I
C
C, I
-
-
-
-
-6
C
C
-
XC2S30
XC2S50
-5
C, I
C, I
C
C, I
C, I
C
-
-
-6
C
-
C
-
-
-
-5
C, I
C
C, I
C
C, I
C
-
-6
-
-
-
XC2S100
XC2S150
XC2S200
-5
-
C, I
C
-
C, I
C
C, I
C
C, I
C
C, I
C
C, I
C
-6
-
-
-5
-
-
-
C, I
C
C, I
C
-6
-
-
-
-5
-
-
-
C, I
C
C, I
C
-6
-
-
-
Notes:
1. C = Commercial, T = 0° to +85°C; I = Industrial, TJ = –40°C to +100°C.
J
(1)
Table 3: Spartan-II User I/O Chart
Available User I/O According to Package Type
Maximum
User I/O
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
VQ100
TQ144
CS144
PQ208
-
FG256
-
FG456
86
60
60
-
86
92
92
92
-
86
92
-
-
132
176
196
260
284
132
140
140
140
140
-
-
176
176
176
176
-
-
-
196
260
284
-
-
-
-
-
Notes:
1. All user I/O counts do not include the four global clock/user input pins.
DS001-1 (v2.3) November 1, 2001
www.xilinx.com
3
Preliminary Product Specification
1-800-255-7778
R
Spartan-II 2.5V FPGA Family: Introduction and Ordering Information
Ordering Information
Example:
XC2S50 -6 PQ 208 C
Device Type
Temperature Range
Number of Pins
Package Type
Speed Grade
Device Ordering Options
Device
XC2S15
XC2S30
XC2S50
XC2S100
XC2S150
XC2S200
Speed Grade
Number of Pins / Package Type
VQ100 100-pin Plastic Very Thin QFP
CS144 144-ball Chip-Scale BGA
TQ144 144-pin Plastic Thin QFP
PQ208 208-pin Plastic QFP
Temperature Range (T )
J
-5 Standard Performance
-6 Higher Performance
C = Commercial
I = Industrial
0°C to +85°C
–40°C to +100°C
FG256 256-ball Fine Pitch BGA
FG456 456-ball Fine Pitch BGA
Revision History
Version No.
Date
Description
2.0
09/18/00 Sectioned the Spartan-II Family data sheet into four modules. Added industrial temperature
range information.
2.1
2.2
2.3
10/31/00 Removed Power down feature.
03/05/01 Added statement on PROMs.
11/01/01 Update Product Availability chart. Minor text edits.
The Spartan-II Family Data Sheet
DS001-1, Spartan-II 2.5V FPGA Family: Introduction and Ordering Information (Module 1)
DS001-2, Spartan-II 2.5V FPGA Family: Functional Description (Module 2)
DS001-3, Spartan-II 2.5V FPGA Family: DC and Switching Characteristics (Module 3)
DS001-4, Spartan-II 2.5V FPGA Family: Pinout Tables (Module 4)
PN 011311
4
www.xilinx.com
DS001-1 (v2.3) November 1, 2001
1-800-255-7778
Preliminary Product Specification
相关型号：
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