XC17S200APDG8I [XILINX]
Configuration Memory, 1335840X1, Serial, CMOS, PDIP8, PLASTIC, DIP-8;
| 型号： | XC17S200APDG8I |
| 厂家： | 
XILINX, INC |
| 描述： | Configuration Memory, 1335840X1, Serial, CMOS, PDIP8, PLASTIC, DIP-8 OTP只读存储器 光电二极管 内存集成电路 |
| 文件： | 总8页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
Spartan-II/Spartan-IIE Family OTP
Configuration PROMs (XC17S00A)
0
5
DS078 (v1.10) June 25, 2007
Product Specification
Features
•
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams for
Spartan™-II/Spartan-IIE FPGA devices
•
•
•
Available in compact plastic 8-pin DIP, 8-pin VOIC,
20-pin SOIC, or 44-pin VQFP packages
Programming support by leading programmer
manufacturers
•
•
•
•
Simple interface to the Spartan device
Programmable reset polarity (active High or active Low)
Low-power CMOS floating gate process
3.3V PROM
Design support using the Xilinx Alliance and
Foundation™ series software packages
•
•
Guaranteed 20-year life data retention
Pb-free (RoHS-compliant) packaging available
Introduction
The XC17S00A family of PROMs provide an easy-to-use,
cost-effective method for storing Spartan-II/Spartan-IIE
device configuration bitstreams.
the appropriate number of clock pulses to complete the
configuration. Once configured, it disables the PROM.
When a Spartan device is in Slave Serial mode, the PROM
and the Spartan device must both be clocked by an
incoming signal.
When the Spartan device is in Master Serial mode, it
generates a configuration clock that drives the Spartan
PROM. A short access time after the rising clock edge, data
appears on the PROM DATA output pin that is connected to
For device programming, either the Xilinx Alliance or the
Spartan device design file into a standard HEX format which
is then transferred to most commercial PROM programmers.
the Spartan device D pin. The Spartan device generates
IN
Spartan-II/IIE FPGA
Configuration Bits
197,696
Compatible Spartan-II/IIE PROM
XC17S15A
XC2S15
XC2S30
336,768
559,200
XC17S30A
XC2S50
XC17S50A
XC2S100
XC2S150
XC2S200
XC2S50E
XC2S100E
XC2S150E(1)
XC2S200E
XC2S300E
XC2S400E
XC2S600E
781,216
XC17S100A
XC17S150A
XC17S200A
XC17S50A
1,040,096
1,335,840
630,048
863,840
XC17S100A
XC17S200A
XC17S200A
XC17S300A
XC17V04(2)
1,134,496
1,442,016
1,875,648
2,693,440
3,961,632
XC17V04(2)
Notes:
1. Due to the higher configuration bit requirements of the XC2S150E device, an XC17S200A PROM is required to configure this FPGA.
2. See XC17V00 series configuration PROMs data sheet at: http://direct.xilinx.com/bvdocs/publications/ds073.pdf
© 2000-2002, 2005, 2007 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS078 (v1.10) June 25, 2007
www.xilinx.com
Product Specification
1
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
Pin Description
Pins not listed are no connects.
8-pin
PDIP
20-pin
SOIC
(SO20)
44-pin
(PD8/PDG8)
Pin Name
VQFP
Pin Description
and
VOIC/TSOP
(VO8/VOG8)
(VQ44)
DATA
CLK
1
1
40
• Data output, High-Z state when either CE or OE are inactive. During
programming, the DATA pin is I/O. Note that OE can be programmed to
be either active High or active Low.
2
3
3
8
43
13
• Each rising edge on the CLK input increments the internal address
counter, if both CE and OE are active.
RESET/OE
(OE/RESET)
• When High, this input holds the address counter reset and puts the
DATA output in a high-impedance state. The polarity of this input pin is
programmable as either RESET/OE or OE/RESET. To avoid confusion,
this document describes the pin as RESET/OE, although the opposite
polarity is possible on all devices. When RESET is active, the address
counter is held at zero, and the DATA output is in a high-impedance
state. The polarity of this input is programmable. The default is active-
High RESET, but the preferred option is active Low RESET, because it
can be connected to the FPGAs INIT pin and a pull-up resistor.
• The polarity of this pin is controlled in the programmer interface. This
input pin is easily inverted using the Xilinx HW-130 programmer software.
Third-party programmers have different methods to invert this pin.
CE
4
10
15
• When High, this pin resets the internal address counter, puts the DATA
output in a high-impedance state, and forces the device into low-ICC
standby mode.
GND
VCC
5
11
18, 41
38, 35
• GND is the ground connection.
7, 8
18, 20
• The VCC pins are to be connected to the positive voltage supply.
Pinout Diagrams
1
2
3
4
8
DATA (D0)
CLK
VCC
PD8/PDG8
VO8/VOG8
Top View
7
6
5
VCC
NC
OE/RESET
CE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
33
32
31
30
29
28
27
26
25
24
23
GND
ds078_04_061805
VQ44
Top View
DATA(D0)
NC
1
2
3
4
5
6
7
8
9
20
VCC
NC
VCC
NC
NC
NC
NC
NC
NC
GND
9
10
11
19
18
17
16
15
14
13
12
11
CLK
NC
NC
NC
SO20
Top View
NC
OE/RESET
NC
CE
10
ds078_05_061805
ds073_06_061805
DS078 (v1.10) June 25, 2007
www.xilinx.com
Product Specification
2
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
configuration program from an external memory. The
XC17S00A PROM has been designed for compatibility with
the Master Serial mode.
Controlling PROMs
•
Connecting the Spartan device with the PROM:
•
The DATA output of the PROM drives the D input of
the lead Spartan device.
IN
Upon power-up or reconfiguration, the Spartan device
enters the Master Serial mode when the mode pins are set
to Master Serial mode. Data is read from the PROM
sequentially on a single data line. Synchronization is
provided by the rising edge of the temporary signal CCLK,
which is generated during configuration.
•
•
The Master Spartan device CCLK output drives the
CLK input of the PROM.
The RESET/OE input of the PROM is connected to the
INIT pin of the Spartan device and a pull-up resistor.
This connection assures that the PROM address
counter is reset before the start of any
Master Serial mode provides a simple configuration
interface (Figure 1). Only a serial data line, two control lines,
and a clock line are required to configure the Spartan
device. Data from the PROM is read sequentially, accessed
via the internal address and bit counters which are
incremented on every valid rising edge of CCLK.
(re)configuration, even when a reconfiguration is
initiated by a V glitch.
CC
•
The CE input of the PROM is connected to the DONE
pin of the Spartan device and a pull-up resistor. CE can
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
If the user-programmable, dual-function D pin on the
IN
Spartan device is used only for configuration, it must still be
held at a defined level during normal operation. The
Spartan-II/Spartan-IIE family takes care of this
automatically with an on-chip pull-up/down resistor or
keeper circuit.
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the Spartan device mode pins. In Master
Serial mode, the Spartan device automatically loads the
The one-time-programmable XC17S00A PROM in
Figure 1, page 3 supports automatic loading of
configuration programs. An early DONE inhibits the PROM
data output one CCLK cycle before the Spartan FPGA I/Os
become active.
Spartan-II/
Spartan-IIE
Master Serial
3.3V
V
V
CC
3.3V
M0
M1
M2
CC
DATA
CLK
DIN
CCLK
DONE
INIT
XC17S00A
PROM
CE
OE/RESET
Notes:
1. If the DriveDone configuration option is not active, pull up DONE with a 3.3 kΩ resistor.
DS078_01_061107
Figure 1: XC17S00A PROM Connections to FPGA in Master Serial Mode
DS078 (v1.10) June 25, 2007
Product Specification
www.xilinx.com
3
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high-impedance
state regardless of the state of the OE input.
Programming Spartan-II/Spartan-IIE
Family PROMs
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
V
CC
GND
RESET/
CE
OE
or
OE/
RESET
Address Counter
CLK
TC
EPROM
Cell
OE
Output
DATA
Matrix
DS030_02_011300
Figure 2: Simplified Block Diagram (does not show programming circuit)
Caution! Always tie the two VCC pins together.
Table 1: Truth Table for XC17S00A Control Inputs
Control Inputs
Outputs
Internal Address(2)
RESET(1)
CE
DATA
ICC
If address < TC: increment
If address > TC: don’t change
Active
High-Z
Active
Reduced
Inactive
Low
Active
Inactive
Active
Low
High
High
Held reset
Not changing
Held reset
High-Z
High-Z
High-Z
Active
Standby
Standby
Notes:
1. The XC17S00A RESET input has programmable polarity
2. TC = Terminal Count = highest address value. TC + 1 = address 0.
DS078 (v1.10) June 25, 2007
www.xilinx.com
Product Specification
4
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
XC17S15A, XC17S30A, XC17S50A, XC17S100A, XC17S150A, XC17S200A, and
XC17S300A
Absolute Maximum Ratings(1)
Symbol
VCC
Description
Value
Units
V
Supply voltage relative to GND
–0.5 to +4.0
VIN
Input voltage with respect to GND
Voltage applied to High-Z output
Storage temperature (ambient)
–0.5 to VCC +0.5
–0.5 to VCC +0.5
–65 to +150
V
VTS
V
TSTG
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Operating Conditions(1)
Symbol
VCC
Description
Commercial
Industrial
Min
3.0
3.0
1.0
Max
3.6
3.6
50
Units
V
Supply voltage relative to GND (TA = 0°C to +70°C)
Supply voltage relative to GND (TA = –40°C to +85° C)
VCC rise time from 0V to nominal voltage
V
TVCC
ms
Notes:
1. During normal read operation, both V pins must be connected together.
CC
2. At power-up, the device requires the V power supply to monotonically rise from 0V to nominal voltage within the specified V rise time.
CC
CC
If the power supply cannot meet this requirement, then the device may not perform a power-on-reset properly.
DC Characteristics Over Operating Condition
Symbol
VIH
Description
Min
2.0
0
Max
VCC
0.8
–
Units
V
High-level input voltage
Low-level input voltage
VIL
V
VOH
VOL
ICCA
ICCS
IL
High-level output voltage (IOH = –3 mA)
Low-level output voltage (IOL = +3 mA)
Supply current, active mode (at maximum frequency)
Supply current, standby mode
2.4
–
V
0.4
15
1
V
–
mA
mΑ
μA
pF
pF
–
Input or output leakage current
–10
–
10
10
10
CIN
Input Capacitance (VIN = GND, f = 1.0 MHz)
Output Capacitance (VIN = GND, f = 1.0 MHz)
COUT
–
DS078 (v1.10) June 25, 2007
www.xilinx.com
Product Specification
5
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
AC Characteristics Over Operating Condition(1)
T
CEH
CE
T
T
T
HCE
SCE
SCE
RESET/OE
CLK
T
HOE
T
T
HC
LC
T
CYC
T
T
DF
OE
T
T
CAC
OH
T
CE
DATA
T
OH
DS030_03_111502
Symbol
TOE
Description
Min
–
Max
Units
ns
RESET/OE to Data Delay
CE to Data Delay
45
60
80
–
TCE
–
ns
TCAC
TOH
CLK to Data Delay
–
ns
Data Hold From CE, RESET/OE, or CLK(2)
CE or RESET/OE to Data Float Delay(2,3)
Clock Periods
0
ns
TDF
–
50
–
ns
TCYC
TLC
100
50
50
25
0
ns
CLK Low Time(2)
–
ns
THC
CLK High Time(2)
–
ns
TSCE
THCE
THOE
TCEH
CE Setup Time to CLK (to guarantee proper counting)
CE Hold Time to CLK (to guarantee proper counting)
RESET/OE Hold Time (guarantees counters are reset)
CE High time (guarantees counters are reset)
–
ns
–
ns
25
20
–
ns
–
ns
Notes:
1. AC test load = 50 pF
2. Guaranteed by design, not tested.
3. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.
4. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
5. If T
6. If T
High < 2μs, T = 2 μs.
CEH
HOE
CE
High < 2μs, T = 2 μs.
CE
DS078 (v1.10) June 25, 2007
www.xilinx.com
Product Specification
6
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
Ordering Information
XC17S15A VO8 C
Operating Range/Processing
Device Number
C=Commercial (TA = 0° C to +70° C)
I=Industrial (TA = –40°C to +85° C)
XC17S15A
XC17S30A
XC17S50A
XC17S100A
XC17S150A
XC17S200A
XC17S300A
Package Type
PD8/PDG8=8-pin Plastic DIP
VO8/VOG8=8-pin Plastic Small-Outline Thin Package
SO20=20-pin Plastic Small-Outline Package
VQ44=44-pin Plastic Quad Flat Package
3.3V Valid Ordering Combinations
XC17S15APD8C
XC17S15AVO8C
XC17S15AVOG8C
XC17S15ASO20C
XC17S15APD8I
XC17S15AVO8I
XC17S15ASO20I
XC17S50APD8C
XC17S50APDG8C
XC17S50AVO8C
XC17S50AVOG8C
XC17S50ASO20C
XC17S50APD8I
XC17S50AVO8I
XC17S50ASO20I
XC17S150APD8C
XC17S150AVO8C
XC17S150ASO20C
XC17S150APD8I
XC17S150AVO8I
XC17S150ASO20I
XC17S30APD8C
XC17S30AVO8C
XC17S30ASO20C
XC17S30APD8I
XC17S30AVO8I
XC17S30ASO20I
XC17S100APD8C
XC17S100AVO8C
XC17S100AVOG8C
XC17S100ASO20C
XC17S100APD8I
XC17S100AVO8I
XC17S100ASO20I
XC17S200APD8C
XC17S200APDG8C
XC17S200AVO8C
XC17S200AVOG8C
XC17S200APD8I
XC17S200APDG8I
XC17S200AVO8I
XC17S200AVOG8I
XC17S200AVQ44C
XC17S200AVQ44I
XC17S300AVQ44C
XC17S300AVQ44I
DS078 (v1.10) June 25, 2007
www.xilinx.com
Product Specification
7
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
Marking Information
Due to the small size of the PROM package, the complete ordering part number cannot be marked on the package. The XC
prefix is deleted and the package code is simplified. Device marking is as follows.
17S15A V C
Operating Range/Processing
Device Marking
C=Commercial (TA = 0° C to +70° C)
I=Industrial (TA = –40°C to +85° C)
17S15A
17S30A
17S50A
17S100A
17S150A
17S200A
17S300A
Package Mark
P=8-pin Plastic DIP
V=8-pin Plastic Small-Outline Thin Package
S=20-pin Plastic Small-Outline Package
VQ=44-pin Plastic Quad Flat Package
G=8-pin Plastic Small-Outline Thin Package, Pb free (RoHS compliant)
H=8-pin Plastic DIP, Lead Free
Revision History
The following table shows the revision history for this document.
Date
Revision
1.0
Revision
09/14/00
11/13/00
04/07/01
Initial Xilinx release.
1.1
Updated configuration bits.
1.2
Added to features: “Guaranteed 20 year life data retention”, removed “Programming the FPGA with counters”
and related text.
06/20/01
10/09/01
1.3
1.4
Revised Figure 1 resistor values to match Spartan-II data sheet.
Added note for unlisted pins, changed ICCA and ICCS, and added power-on supply requirements and note
regarding power-on reset.
11/15/01
06/25/02
10/15/02
11/18/02
06/24/05
1.5
1.6
1.7
1.8
1.9
Updated for Spartan-IIE FPGA family.
Changed Table 1, page 4.
Changed Table 1, page 4. Added "Pinout Diagrams," page 2.
Added XC2S400E and XC2S600E to Compatible FPGAS table. Modified document title.
Added Pb-free information to the "Pinout Diagrams", "Ordering Information", "3.3V Valid Ordering
Combinations", and "Marking Information" figures. Removed TSOL from the "Absolute Maximum Ratings(1)"
table.
06/25/07
1.10
• Updated format.
• Added Pb-free (RoHS-compliant) packaging.
• Timing diagram removed from Figure 1, page 3.
• Part Numbers XC17S200APDG8I, and XC17S200AVOG8I added to "3.3V Valid Ordering Combinations,"
page 7.
DS078 (v1.10) June 25, 2007
www.xilinx.com
Product Specification
8
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