XC17256EVO8I [XILINX]
Configuration PROMs; 配置PROM
| 型号： | XC17256EVO8I |
| 厂家： | 
XILINX, INC |
| 描述： | Configuration PROMs |
| 文件： | 总13页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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B
L
R
XC1700E, XC1700EL, and XC1700L
Series Configuration PROMs
8
DS027 (v3.5) June 25, 2008
Product Specification
Features
•
One-time programmable (OTP) read-only memory
designed to store configuration bitstreams of Xilinx
FPGAs
•
•
•
XC1700E series are available in 5V and 3.3V versions
XC1700L series are available in 3.3V only
®
Available in compact plastic packages: 8-pin SOIC, 8-
pin VOIC, 8-pin PDIP, 20-pin SOIC, 20-pin PLCC, 44-
pin PLCC or 44-pin VQFP
•
Simple interface to the FPGA; requires only one user
I/O pin
•
•
Cascadable for storing longer or multiple bitstreams
•
•
Programming support by leading programmer
manufacturers
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
Design support using the Xilinx Alliance and
Foundation™ software packages
•
•
XC17128E/EL, XC17256E/EL, XC1701, and XC1700L
series support fast configuration
•
•
Guaranteed 20 year life data retention
Lead-free (Pb-free) packaging available
Low-power CMOS floating-gate process
Description
The XC1700 family of configuration PROMs provides an
easy-to-use, cost-effective method for storing large Xilinx
FPGA configuration bitstreams. See Figure 1 for a
simplified block diagram.
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA D pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. After configured, it disables the
IN
For device programming, either the Xilinx Alliance or
Foundation software compiles the FPGA design file into a
standard Hex format, which is then transferred to most
commercial PROM programmers.
X-Ref Target - Figure 1
V
CC
V
PP
GND
RESET/
CEO
CE
OE
or
OE/
RESET
Address Counter
CLK
TC
EPROM
Cell
OE
Output
DATA
Matrix
DS027_01_021500
Figure 1: Simplified Block Diagram (Does Not Show Programming Circuit)
© Copyright 1998-2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and
other countries. All other trademarks are the property of their respective owners.
DS027 (v3.5) June 25, 2008
www.xilinx.com
Product Specification
1
R
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
Pin Description
DATA
operation, this pin must be connected to V . Failure to do
so may lead to unpredictable, temperature-dependent
CC
Data output is in a high-impedance state when either CE or
OE are inactive. During programming, the DATA pin is I/O.
Note that OE can be programmed to be either active High or
active Low.
operation and severe problems in circuit debugging. Do not
leave V floating!
PP
VCC and GND
Positive supply and ground pins.
CLK
Each rising edge on the CLK input increments the internal
address counter, if both CE and OE are active.
PROM Pinouts
Pins not listed are "no connects."
"
RESET/OE
8-pin
PDIP
(PD8/
PDG8)
20-pin
SOIC
(SO8/
SOG8)
VOIC
(VO8/
VOG8)
When High, this input holds the address counter reset and
puts the DATA output in a high-impedance state. The
polarity of this input pin is programmable as either
RESET/OE or OE/RESET. To avoid confusion, this
document describes the pin as RESET/OE, although the
opposite polarity is possible on all devices. When RESET is
active, the address counter is held at "0", and puts the DATA
output in a high-impedance state. The polarity of this input
is programmable. The default is active High RESET, but the
preferred option is active Low RESET, because it can be
driven by the FPGAs INIT pin.
20-pin
PLCC
(PC20/
PCG20)
44-pin
VQFP
44-pin
PLCC
Pin Name
SOIC
(SO20)
(VQ44) (PC44)
DATA
1
2
1
3
2
4
40
43
2
5
CLK
RESET/OE
(OE/RESET)
3
8
6
13
19
The polarity of this pin is controlled in the programmer
interface. This input pin is easily inverted using the Xilinx
HW-130 Programmer. Third-party programmers have
different methods to invert this pin.
CE
4
5
6
7
8
10
11
13
18
20
8
15
18, 41
21
21
24, 3
27
GND
CEO
VPP
VCC
10
14
17
20
CE
35
41
38
44
When High, this pin disables the internal address counter,
puts the DATA output in a high-impedance state, and forces
Capacity
the device into low-I standby mode.
CC
Devices
Configuration Bits
4,194,304
2,097,152
1,048,576
524,288
CEO
XC1704L
XC1702L
Chip Enable output, to be connected to the CE input of the next
PROM in the daisy chain. This output is Low when the CE and
OE inputs are both active AND the internal address counter
has been incremented beyond its Terminal Count (TC) value.
In other words: when the PROM has been read, CEO follows
CE as long as OE is active. When OE goes inactive, CEO
stays High until the PROM is reset. Note that OE can be
programmed to be either active High or active Low.
XC1701/L
XC17512L
XC1736E
36,288
XC1765E/EL
XC17128E/EL
XC17256E/EL
65,536
131,072
262,144
VPP
Programming voltage. No overshoot above the specified
max voltage is permitted on this pin. For normal read
DS027 (v3.5) June 25, 2008
www.xilinx.com
Product Specification
2
R
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
Pinout Diagrams
7
8
9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
39
38
37
36
35
34
33
32
31
30
29
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
10
11
12
13
14
15
16
17
PC44
Top View
VQ44
Top View
9
10
11
DS027_05_090602
DS027_07_090602
DATA(D0)
CLK
1
8
7
6
5
VCC
VPP
CEO
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DATA(D0)
NC
VCC
NC
VPP
NC
NC
NC
NC
CEO
NC
PD8/PDG8
2
3
4
VO8/VOG8
SO8/SOG8
Top View
CLK
NC
NC
NC
OE/RESET
CE
SO20
Top
NC
OE/RESET
NC
View
DS027_06_060705
CE
GND
DS027_08_110102
18
NC
CLK
4
17
16
15
14
VPP
NC
NC
NC
OE/RESET
NC
5
6
7
8
PC20/PCG20
Top View
CEO
CE
DS027_09_060705
DS027 (v3.5) June 25, 2008
www.xilinx.com
Product Specification
3
R
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
Configuration
Xilinx FPGAs and Compatible PROMs
Configuration
Device
PROM
Device
PROM
Bits
Bits
XCV50E
XCV100E
XCV200E
XCV300E
XCV400E
XCV405E
XCV600E
XCV812E
XCV1000E
XCV1600E
XCV2000E
XCV2600E
XCV3200E
630,048
XC1701L
XC1701L
XC4003E
XC4005E
53,984
XC17128E(1)
XC17128E
XC17128E
XC17256E
XC17256E
XC17256E
XC1701
863,840
95,008
1,442,016
1,875,648
2,693,440
3,340,400
3,961,632
6,519,648
6,587,520
8,308,992
10,159,648
12,922,336
16,283,712
XC1702L
XC4006E
119,840
147,552
178,144
247,968
329,312
422,176
61,100
XC1702L
XC4008E
XC1704L
XC4010E
XC1704L
XC4013E
XC1704L
XC4020E
2 of XC1704L
2 of XC1704L
2 of XC1704L
3 of XC1704L
4 of XC1704L
4 of XC1704L
XC4025E
XC1701
XC4002XL
XC17128EL(1)
XC17256EL
XC17512L
XC17512L
XC17512L
XC1701L
XC1701
XC4005XL
151,960
283,424
393,632
521,880
668,184
668,184
832,528
832,528
1,014,928
1,215,368
1,433,864
1,924,992
2,686,136
3,373,448
XC4010XL
XC4013XL/XLA
XC4020XL/XLA
XC4028XL/XLA
XC4028EX
Notes:
1. The suggested PROM is determined by compatibility with the
higher configuration frequency of the Xilinx FPGA CCLK.
XC4036EX/XL/XLA
XC4036EX
XC1701L
XC1701
Designers using the default slow configuration frequency (CCLK)
can use the XC1765E or XC1765EL for the noted FPGA devices.
XC4044XL/XLA
XC4052XL/XLA
XC4062XL/XLA
XC4085XL/XLA
XC40110XV
XC40150XV
XC1701L
XC1702L
XC1702L
XC1702L
XC1704L
XC1704L
Controlling PROMs
Connecting the FPGA device with the PROM:
•
•
•
•
The DATA output(s) of the of the PROM(s) drives the
input of the lead FPGA device.
D
IN
The Master FPGA CCLK output drives the CLK input(s)
of the PROM(s).
XC1704L +
XC17512L
XC40200XV
XC40250XV
4,551,056
5,433,888
The CEO output of a PROM drives the CE input of the
next PROM in a daisy chain (if any).
XC1704L+
XC1702L
The RESET/OE input of all PROMs is best driven by
the INIT output of the lead FPGA device. This
connection assures that the PROM address counter is
reset before the start of any (re)configuration, even
XC5202
XC5204
XC5206
XC5210
XC5215
XCV50
42,416
70,704
XC1765E
XC17128E
XC17128E
XC17256E
XC17256E
XC1701L
XC1701L
XC1701L
XC1702L
XC1702L
XC1704L
XC1704L
106,288
165,488
237,744
559,200
781,216
1,040,096
1,335,840
1,751,808
2,546,048
3,607,968
when a reconfiguration is initiated by a V glitch.
CC
Other methods—such as driving RESET/OE from LDC
or system reset—assume the PROM internal power-
on-reset is always in step with the FPGA’s internal
power-on-reset. This may not be a safe assumption.
XCV100
XCV150
XCV200
XCV300
XCV400
XCV600
•
•
The PROM CE input can be driven from either the LDC
or DONE pins. Using LDC avoids potential contention
on the D pin.
IN
The CE input of the lead (or only) PROM is driven by
the DONE output of the lead FPGA device, provided
that DONE is not permanently grounded. Otherwise,
LDC can be used to drive CE, but must then be
unconditionally High during user operation. CE can
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
XC1704L +
XC1701L
XCV800
4,715,616
6,127,744
XC1704L +
XC1702L
XCV1000
DS027 (v3.5) June 25, 2008
www.xilinx.com
Product Specification
4
R
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
PROM does not reset its address counter, since it never
saw a High level on its OE input. The new configuration,
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending on
the state of the three FPGA mode pins. In Master Serial
mode, the FPGA automatically loads the configuration
program from an external memory. The Xilinx PROMs have
been designed for compatibility with the Master Serial mode.
therefore, reads the remaining data in the PROM and
interprets it as preamble, length count etc. Since the FPGA
is the master, it issues the necessary number of CCLK
24
pulses, up to 16 million (2 ) and DONE goes High.
However, the FPGA configuration is then completely wrong,
with potential contentions inside the FPGA and on its output
pins. This method must, therefore, never be used when
there is any chance of external reset during configuration.
Upon power-up or reconfiguration, an FPGA enters the
Master Serial mode whenever all three of the FPGA mode-
select pins are Low (M0=0, M1=0, M2=0). Data is read from
the PROM sequentially on a single data line. Synchronization
is provided by the rising edge of the temporary signal CCLK,
which is generated during configuration.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for
future FPGAs requiring larger configuration memories,
cascaded PROMs provide additional memory. After the last
bit from the first PROM is read, the next clock signal to the
PROM asserts its CEO output Low and disables its DATA
line. The second PROM recognizes the Low level on its CE
input and enables its DATA output. See Figure 2, page 6.
Master Serial Mode provides a simple configuration interface.
Only a serial data line and two control lines are required to
configure an FPGA. Data from the PROM is read sequentially,
accessed via the internal address and bit counters which are
incremented on every valid rising edge of CCLK.
After configuration is complete, the address counters of
all cascaded PROMs are reset if the FPGA RESET pin
goes Low, assuming the PROM reset polarity option has
been inverted.
If the user-programmable, dual-function D pin on the
IN
FPGA is used only for configuration, it must still be held at a
defined level during normal operation. The Xilinx FPGA
families take care of this automatically with an on-chip
default pull-up resistor.
To reprogram the FPGA with another program, the DONE
line goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention
between DATA and the configured I/O use of D .
Programming the FPGA With Counters
Unchanged upon Completion
IN
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high-impedance
state regardless of the state of the OE input.
When multiple FPGA-configurations for a single FPGA are
stored in a PROM, the OE pin should be tied Low. Upon
power-up, the internal address counters are reset and
configuration begins with the first program stored in
memory. Since the OE pin is held Low, the address
counters are left unchanged after configuration is complete.
Therefore, to reprogram the FPGA with another program,
the DONE line is pulled Low and configuration begins at the
last value of the address counters.
Programming
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
This method fails if a user applies RESET during the FPGA
configuration process. The FPGA aborts the configuration
and then restarts a new configuration, as intended, but the
Table 1: Truth Table for XC1700 Control Inputs
Control Inputs
Outputs
Internal Address
RESET
CE
DATA
CEO
ICC
If address < TC(1): increment
Active
High-Z
High
Low
Active
Reduced
Inactive
Low
If address > TC(2): don’t change
Active
Inactive
Active
Low
High
High
Held reset
Not changing
Held reset
High-Z
High-Z(3)
High-Z(3)
High
High
High
Active
Standby
Standby
Notes:
1. The XC1700 RESET input has programmable polarity.
2. TC = Terminal Count = highest address value. TC + 1 = address 0.
3. Pull DATA pin to GND or V to meet I
standby current.
CC
CCS
DS027 (v3.5) June 25, 2008
www.xilinx.com
Product Specification
5
R
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
X-Ref Target
-
Figure
2
V
CC
D
OUT
OPTIONAL
Daisy-chained
FPGAs with
Different
configurations
OPTIONAL
FPGA
Slave FPGAs
with Identical
Configurations
MODES(1)
V
CC
3.3V
V
DATA
CLK
V
PP
CC
DATA
CLK
D
IN
Cascaded
Serial
Memory
RESET
RESET
PROM
CCLK
DONE
INIT
CE
CEO
CE
OE/RESET
OE/RESET
(Low Resets the Address Pointer)
CCLK
(Output)
D
IN
D
OUT
(Output)
Notes:
1. For mode pin connections, refer to the appropriate FPGA data sheet.
2. The one-time-programmable PROM supports automatic loading of configuration programs.
3. Multiple devices can be cascaded to support additional FPGAs.
4. An early DONE inhibits the PROM data output one CCLK cycle before the FPGA I/Os become active.
DS027_02_111606
Figure 2: Master Serial Mode
DS027 (v3.5) June 25, 2008
www.xilinx.com
Product Specification
6
R
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
XC1701, XC1736E, XC1765E, XC17128E and XC17256E
Absolute Maximum Ratings
Symbol
VCC
VPP
Description
Conditions
–0.5 to +7.0
–0.5 to +12.5
–0.5 to VCC +0.5
–0.5 to VCC +0.5
–65 to +150
+125
Units
V
Supply voltage relative to GND
Supply voltage relative to GND
Input voltage relative to GND
V
VIN
V
VTS
Voltage applied to High-Z output
Storage temperature (ambient)
Junction temperature
V
TSTG
TJ
°C
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions (5V Supply)
Symbol
Description
Supply voltage relative to GND (TA = 0°C to +70°C)
Supply voltage relative to GND (TA = –40°C to +85°C)
Min
4.750
4.50
Max
5.25
5.50
Units
Commercial
Industrial
V
V
(1)
VCC
Notes:
1. During normal read operation VPP must be connect to V
CC.
DC Characteristics Over Operating Condition
Symbol
VIH
Description
Min
2
Max
VCC
0.8
–
Units
V
High-level input voltage
Low-level input voltage
VIL
0
V
VOH
VOL
High-level output voltage (IOH = –4 mA)
Low-level output voltage (IOL = +4 mA)
High-level output voltage (IOH = –4 mA)
Low-level output voltage (IOL = +4 mA)
Commercial
3.86
–
V
0.32
–
V
VOH
VOL
Industrial
3.76
–
V
0.37
10
V
ICCA
Supply current, active mode at maximum frequency
(XC1736E, XC1765E, XC17128E, and XC17256E)
–
mA
ICCA
ICCS
ICCS
Supply current, active mode at maximum frequency
(XC1701)
–
–
–
20
mA
μA
μA
Supply current, standby mode
(XC1736E, XC1765E, XC17128E, and XC17256E)
50(1)
100(1)
Supply current, standby mode
(XC1701)
IL
Input or output leakage current
–10
–
10
10
10
μA
pF
pF
CIN
Input capacitance (VIN = GND, f = 1.0 MHz)
Output capacitance (VIN = GND, f = 1.0 MHz)
COUT
–
Notes:
1.
I
standby current is specified for DATA pin that is pulled to V or GND.
CC
CCS
DS027 (v3.5) June 25, 2008
www.xilinx.com
Product Specification
7
R
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
XC1704L, XC1702L, XC1701L, XC17512L, XC1765EL, XC17128EL and XC17256EL
Absolute Maximum Ratings
Symbol
VCC
Description
Conditions
–0.5 to +7.0
Units
Supply voltage relative to GND
Supply voltage relative to GND
Input voltage relative to GND
V
V
VPP
–0.5 to +12.5
–0.5 to VCC +0.5
–0.5 to VCC +0.5
–65 to +150
VIN
V
VTS
Voltage applied to High-Z output
Storage temperature (ambient)
V
TSTG
°C
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
Operating Conditions (3V Supply)
Symbol
Description
Supply voltage relative to GND (TA = 0°C to +70°C)
Supply voltage relative to GND (TA = –40°C to +85°C)
Min
3.0
3.0
Max
3.6
Units
Commercial
Industrial
V
V
(1)
VCC
3.6
Notes:
1. During normal read operation VPP must be connect to V
CC.
DC Characteristics Over Operating Condition
Symbol
VIH
Description
Min
Max
VCC
0.8
–
Units
V
High-level input voltage
Low-level input voltage
2
0
VIL
V
VOH
VOL
High-level output voltage (IOH = –3 mA)
2.4
–
V
Low-level output voltage (IOL = +3 mA)
0.4
10
V
ICCA
Supply current, active mode (at maximum frequency) (XC1700L)
–
mA
Supply current, active mode (at maximum frequency)
(XC1765EL, XC17128EL, XC17256EL)
ICCA
ICCS
–
–
5
mA
Supply current, standby mode
(XC1701L, XC17512L, XC17256L, X1765EL, XC17128EL)
50(1)
μA
ICCS
IL
Supply current, standby mode (XC1702L, XC1704L)
Input or output leakage current
–
–10
–
350(1)
10
μA
μA
pF
pF
CIN
Input capacitance (VIN = GND, f = 1.0 MHz)
Output capacitance (VIN = GND, f = 1.0 MHz)
10
COUT
–
10
Notes:
1.
I
standby current is specified for DATA pin that is pulled to V or GND.
CC
CCS
DS027 (v3.5) June 25, 2008
www.xilinx.com
Product Specification
8
R
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
AC Characteristics Over Operating Condition
CE
T
T
T
HCE
SCE
SCE
RESET/OE
CLK
T
HOE
T
T
HC
LC
T
CYC
T
T
DF
OE
T
T
CAC
OH
T
CE
DATA
T
OH
DS027_03_021500
XC17128EL,
XC17256EL,
XC1704L,
XC1701,
XC17128E,
XC17256E
XC1736E,
XC1765E
XC1765EL
XC1702L,
Symbol
Description
Units
XC1701L,
XC17512L
Min
–
Max
25
45
45
50
–
Min
–
Max
30
45
45
50
–
Min
–
Max
Min
Max
40
60
200
50
–
TOE
TCE
OE to data delay
CE to data delay
CLK to data delay
45
60
80
50
–
–
–
ns
ns
ns
ns
ns
ns
ns
ns
–
–
–
TCAC
TDF
–
–
–
–
CE or OE to data float delay(2,3)
–
–
–
–
TOH
TCYC
TLC
Data hold from CE, OE, or CLK(3)
Clock periods
0
0
0
0
67
20
20
–
67
25
25
–
100
50
50
–
400
100
100
–
CLK Low time(3)
–
–
–
–
THC
CLK High time(3)
–
–
–
–
CE setup time to CLK
(to guarantee proper counting)
TSCE
THCE
20
0
–
–
–
25
0
–
–
–
25
0
–
–
–
40
0
–
–
–
ns
ns
ns
CE hold time to CLK
(to guarantee proper counting)
OE hold time
(guarantees counters are reset)
THOE
20
25
100
100
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
DS027 (v3.5) June 25, 2008
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Product Specification
9
R
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
AC Characteristics Over Operating Condition When Cascading
RESET/OE
CE
CLK
TCDF
DATA
(First PROM)
Last
Bit
First
Bit
TOCK
TOOE
TOCE
TOCE
CEO
(First PROM)
CE
(Cascaded
PROM)
TCCE
TCCE
DATA
(Cascaded
PROM)
First
Bit
Last
Bit
n –1
n
n
n +1
DS027_04_071204
XC1701,
XC17128EL,
XC17128E,
XC17256E,
XC1704L,
XC1702L
XC17256EL,
XC1701L,
XC1736E,
XC1765E
XC1765EL
Symbol
Description
Units
XC17512L
Min
–
Max
50
Min
–
Max
50
Min
Max
50
Min
–
Max
50
TCDF
TOCK
TOCE
TOOE
TCCE
CLK to data float delay(2,3)
CLK to CEO delay(3)
–
ns
ns
ns
ns
ns
–
30
–
30
–
–
–
–
30
35
30
60
–
30
CE to CEO delay(3)
–
35
–
35
–
35
RESET/OE to CEO delay(3)
–
30
–
30
–
30
CE to data delay when cascading
–
45
–
90
–
110
Notes:
1. AC test load = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
5. For cascaded PROMs:
- T min = T + T
+ FPGA data setup time (T
/T
).
CYC
OCK
CCE
DCC DSCK
Example: If the XC1701L is cascaded to configure an FPGA TDCC = 5 sec, then the actual TCYC min = 30 ns + 90 ns + 5 ns = 125 ns,
or max CLK frequency = 8 MHz.
- TCAC max = TOCK + TCCE
.
Example: For the XC1701L when cascading, the actual TCAC max = 30 ns + 90 ns = 120 ns.
DS027 (v3.5) June 25, 2008
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Product Specification
10
R
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
Ordering Information
XC1701L PC20 C
Device Number
Operating Range/Processing
XC1736E
(1)
C = Commercial (T = 0° to +70°C)
Package Type
A
XC1765E
XC1765EL
XC17128E
XC17128EL
XC17256E
XC17256EL
XC17512L
XC1701
I = Industrial (T = –40° to +85°C)
A
PD8/PDG8 = 8-pin Plastic DIP
SO8/SOG8 = 8-pin Plastic Small-Outline Package
VO8/VOG8 = 8-pin Plastic Small-Outline Thin Package
SO20 = 20-pin Plastic Small-Outline Package
PC20/PCG20 = 20-pin Plastic Leaded Chip Carrier
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
XC1701L
XC1704L
XC1702L
Notes:
1. G in the package-type codes designates Pb-free packaging.
Valid Ordering Combinations
XC1736EPD8C
XC1736EPDG8C
XC1736ESO8C
XC1736ESOG8C
XC1736EVO8C
XC1736EVOG8C
XC1736EPC20C
XC1736EPD8I
XC1765EPD8C
XC1765EPDG8C
XC1765ESO8C
XC1765ESOG8C
XC1765EVO8C
XC1765EPC20C
XC17128EPD8C
XC17128EPDG8C
XC17128EVO8C
XC17128EVOG8C
XC17128EPC20C
XC17128EPCG20C
XC17128EPD8I
XC17256EPD8C
XC17256EPDG8C
XC17256EVO8C
XC17256EPC20C
XC17256EPCG20C
XC1701PD8C
XC1701PC20C
XC1701SO20C
XC1701PD8I
XC1702LVQ44C
XC1702LPC44C
XC1704LVQ44C
XC1704LPC44C
XC1765EPD8I
XC1765ESO8I
XC17128EVO8I
XC17256EPD8I
XC17256EVO8I
XC17256EPC20I
XC1701PC20I
XC1701SO20I
XC1702LVQ44I
XC1702LPC44I
XC1704LVQ44I
XC1704LPC44I
XC17512LPD8C
XC17512LPC20C
XC17512LSO20C
XC17512LPD8I
XC17512LPC20I
XC17512LSO20I
XC1736ESO8I
XC1736EVO8I
XC1736EPC20I
XC17128EPC20I
XC1765EVO8I
XC1765EPC20I
XC1765ELPD8C
XC1765ELSO8C
XC1765ELSOG8C
XC1765ELVO8C
XC1765ELVOG8C
XC1765ELPC20C
XC1765ELPD8I
XC1765ELSO8I
XC1765ELVO8I
XC1765ELPC20I
XC17128ELPD8C
XC17128ELVO8C
XC17128ELPC20C
XC17128ELPD8I
XC17128ELVO8I
XC17128ELPC20I
XC17256ELPD8C
XC17256ELVO8C
XC17256ELPC20C
XC17256ELPD8I
XC17256ELVO8I
XC17256ELPC20I
XC1701LPD8C
XC1701LPDG8C
XC1701LPC20C
XC1701LPCG20C
XC1701LSO20C
XC1701LPD8I
XC1701LPDG8I
XC1701LPC20I
XC1701LPCG20I
XC1701LSO20I
DS027 (v3.5) June 25, 2008
www.xilinx.com
Product Specification
11
R
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
Marking Information
Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on
the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows:
1701L J C
Device Number
Operating Range/Processing
C = Commercial (T = 0° to +70°C)
1736E
1765E
Package Type
A
I = Industrial (T = –40° to +85°C)
A
P = 8-pin Plastic DIP
1765X(1)
17128E
17128X(1)
17256E
17256X(1)
1704L
H = 8-pin Plastic DIP, Pb-Free
S
(2) = 8-pin Plastic Small-Outline Package
O = 8-pin Plastic Small-Outline Package, Pb-Free
V = 8-pin Plastic Small-Outline Thin Package
G = 8-pin Plastic Small-Outline Thin Package, Pb-Free
S
(3) = 20-pin Plastic Small-Outline Package
1702L
1701
1701L
17512L
J = 20-pin Plastic Leaded Chip Carrier
E = 20-pin Plastic Leaded Chip Carrier, Pb-Free
VQ44 = 44-pin Plastic Quad Flat Package
PC44 = 44-pin Plastic Chip Carrier
Notes:
1. When marking the device number on the EL parts, an X is used in place of an EL.
2. For XC1700E/EL only.
3. For XC1700L only.
Revision History
The following table shows the revision history for this document.
.
Date
Version
Revision
7/14/98
1.1
Major revisions to include the XC1704L, XC1702L, and the XQ1701L devices, packages and operating
conditions. Also revised the timing specifications under "AC Characteristics Over Operating Condition,"
page 9.
9/8/98
2.0
2.1
Revised the marking information for the VQ44. Updated "DC Characteristics Over Operating Condition,"
page 7. Added references to the XC4000XLA and XC4000XV families in "Xilinx FPGAs and Compatible
PROMs," page 4 and Figure 2, page 6.
12/18/98
Added Virtex® FPGAs to "Xilinx FPGAs and Compatible PROMs," page 4. Added the PC44 package for
the XC1702L and XC1704L products.
1/27/99
7/8/99
2.2
2.3
3.0
Changed Military ICCS.
Changed ICCS standby on XC1702/XC1704 from 50 μA to 300 μA.
3/30/00
Combined data sheets XC1700E and XC1700L. Added DS027, removed Military Specs. Added Virtex-
E and EM references.
07/05/00
09/07/04
3.1
3.2
Added 4.7K resistor to Figure 2, updated format.
• Updated "Xilinx FPGAs and Compatible PROMs," page 4 and "Absolute Maximum Ratings," page 7.
Added "Pinout Diagrams," page 3.
• Added footnote to table in "AC Characteristics Over Operating Condition When Cascading," page 10,
defining TCCE when cascading, and redrew associated timing diagram.
DS027 (v3.5) June 25, 2008
www.xilinx.com
Product Specification
12
R
XC1700E, XC1700EL, and XC1700L Series Configuration PROMs
06/13/05
07/09/07
3.3
3.4
• Changed pinout diagrams to include Pb-free packages on "Pinout Diagrams," page 3.
• Deleted TSOL from the under "Absolute Maximum Ratings," page 7.
• Added VOG8 and PCG20 to "Ordering Information," page 11. Added XC1765ELVOG8C and
XC17256EPCG20 to "Valid Ordering Combinations," page 11. Added new packages types under
"Marking Information," page 12.
• Added Pb-free packages to "PROM Pinouts," page 2.
• Note added to Table 1, page 5.
• Under "XC1701, XC1736E, XC1765E, XC17128E and XC17256E", note added to "DC
Characteristics Over Operating Condition," page 7 and corrected XC1701 ICCA value.
• Under "XC1704L, XC1702L, XC1701L, XC17512L, XC1765EL, XC17128EL and XC17256EL", note
added to "DC Characteristics Over Operating Condition," page 8.
• Added SOG package to "Ordering Information," page 11.
• Added Pb-free order codes to "Valid Ordering Combinations," page 11.
• Added package type E to "Marking Information," page 12.
06/25/08
3.5
• Updated "Absolute Maximum Ratings," page 7, added junction temperature rating.
• Updated document template.
• Updated copyright statement.
• Added "Notice of Disclaimer," page 13.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
DS027 (v3.5) June 25, 2008
www.xilinx.com
Product Specification
13
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