TMSS_技术文档

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0

XC1800 Series of In-System

Programmable Configuration

PROMs

0

6*

September 17, 1999 (Version 1.3)

Preliminary Product Specification

Features

Description

•

In-system programmable 3.3V PROMs for configuration

of Xilinx FPGAs

Xilinx introduces the XC1800 series of in-system program-

mable configuration PROMs. Initial devices in this 3.3V

family are a 4 megabit, a 2 megabit, a 1 megabit, a 512

Kbit, a 256 Kbit, and a 128 Kbit PROM that provide an

easy-to-use, cost-effective method for re-programming and

storing large Xilinx FPGA or CPLD configuration bit-

streams.

-

Endurance of 10,000 program/erase cycles

Program/erase over full commercial voltage and

temperature range

•

IEEE Std 1149.1 boundary-scan (JTAG) support

Simple interface to the FPGA; could be configured to

use only one user I/O pin

Cascadable for storing longer or multiple bitstreams

Dual configuration modes

When the FPGA is in Master Serial mode, it generates a

configuration clock that drives the PROM. A short access

time after the rising CCLK, data is available on the PROM

DATA (D0) pin that is connected to the FPGA DIN pin. The

FPGA generates the appropriate number of clock pulses to

complete the configuration. When the FPGA is in Slave

Serial mode, the PROM and the FPGA are clocked by an

external clock.

•

-

Serial Slow/Fast configuration (up to 15 mHz).

Parallel

•

Low-power advanced CMOS FLASH process

5 V tolerant I/O pins accept 5 V, 3.3 V and 2.5 V signals.

3.3 V or 2.5 V output capability

Available in PC20, SO20, PC44 and VQ44 packages.

Design support using the Xilinx Alliance and

Foundation series software packages.

JTAG command initiation of standard FPGA

configuration.

When the FPGA is in Express or SelectMAP Mode, an

external oscillator will generate the configuration clock that

drives the PROM and the FPGA. After the rising CCLK

edge, data are available on the PROM’s DATA (D0-D7)

pins. The data will be clocked into the FPGA on the follow-

ing rising edge of the CCLK. Neither Express nor Select-

MAP utilize a Length Count, so a free-running oscillator

may be used. See Figure 5

•

Multiple devices can be concatenated by using the CEO

output to drive the CE input of the following device. The

clock inputs and the DATA outputs of all PROMs in this

chain are interconnected. All devices are compatible and

can be cascaded with other members of the family or with

the XC1700L one-time programmable Serial PROM family.

OE/Reset

CLK CE

TCK

Data

Control

and

JTAG

CEO

Serial

or

Parallel

Interface

TMS

TDI

Memory

D0 DATA

(Serial or Parallel

(Express/SelectMAP) Mode)

Data

Address

Interface

TDO

D1 - D7

Express Mode and

SelectMAP Interface

CF

99020300

Figure 1: XC1800 Series Block Diagram

September 17, 1999 (Version 1.3)

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XC1800 Series of In-System Programmable Configuration PROMs

Pinout and Pin Description

Table 1: Pin Names and Descriptions

Boundary

44-pin

VQFP

44-pin

PLCC

20-pin

SOIC & PLCC

Scan

Function

Pin Description

Name

Order

D0

D1

D2

D3

D4

D5

D6

D7

CLK

4

3

DATA OUT D0 is the DATA output pin to provide data

40

29

42

27

9

2

1

16

2

for configuring an FPGA in serial mode.

OUTPUT

ENABLE

6

5

DATA OUT D0- D7 are the output pins to provide par-

35

4

allel data for configuring a Xilinx FPGA in

express mode.

ENABLE

OUTPUT

2

1

DATA OUT

OUTPUT

ENABLE

8

7

DATA OUT

33

15

31

20

25

5

15

7*

OUTPUT

ENABLE

24

23

DATA OUT

OUTPUT

ENABLE

10

9

DATA OUT

25

14

19

43

14

9

OUTPUT

ENABLE

17

16

DATA OUT

OUTPUT

ENABLE

14

13

DATA OUT

12

3

OUTPUT

ENABLE

0

DATA IN Each rising edge on the CLK input incre-

ments the internal address counter if both

CE is low and OE/RESET is high.

20

19

DATA IN When Low, this input holds the address

counter reset and the DATA output at

high impedance.

OE/

RESET

DATA OUT

13

15

19

21

8

OUTPUT

ENABLE

18

15

CE

CF

DATA IN When CE is High, this pin puts the device

into standby mode. The DATA output pin

is at High impedance, and the device is in

low power standby mode.

10

22

21

DATA OUT Allows JTAG CONFIG instruction to ini-

10

16

7*

tiate FPGA configuration without power-

ing down FPGA.

DATA IN

2

September 17, 1999 (Version 1.3)

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XC1800 Series of In-System Programmable Configuration PROMs

Boundary

Scan

Order

Name

44-pin

VQFP

44-pin

PLCC

20-pin

SOIC & PLCC

Function

Pin Description

CEO

13

14

DATA OUT Chip Enable (CEO) output is connected

21

27

13

to the CE input of the next PROM in the

chain. This output is Low when the CE

ENABLE

OUTPUT

and OE/RESET inputs are active AND

the internal address counter has been in-

cremented beyond its Terminal Count

(TC) value. When the PROM has been

read, CEO will follow CE as long as OE/

RESET is High. When OE/RESET goes

Low, CEO stays High until the PROM is

brought out of reset by bringing OE/RE-

SET High. CEO can be programmed to

be either active High or active Low.

GND

TMS

GND is the ground connection.

6, 18, 28 & 3, 12, 24 &

11

5

41

34

MODE

The state of TMS on the rising edge of

5

11

SELECT TCK determines the state transitions at

the Test Access Port (TAP) controller.

TMS has an internal 50K ohm resistive

pull-up on it to provide a logic 1 to the de-

vice if the pin is not driven.

TCK

TDI

CLOCK

This pin is the JTAG test clock. It se-

quences the TAP controller and all the

JTAG test and programming electronics.

7

3

13

9

6

4

DATA IN This pin is the serial input to all JTAG in-

struction and data registers. TDI has an

internal 50K ohm resistive pull-up on it to

provide a logic 1 to the system if the pin is

not driven.

TDO

DATA OUT This pin is the serial output for all JTAG

instruction and data registers. TDO has

an internal 50k ohm resistive pull-up on it

to provide a logic 1 to the system if the pin

is not driven.

31

37

17

V_CC

Positive voltage supply of 3.3V for inter- 17, 35 & 38 23, 41 & 44

nal logic and input buffers.

18 & 20

19

V_CCO

Positive voltage supply connected to the 8, 16, 26 & 14, 22, 32 &

output voltage drivers.

36

42

*Programmable for Serial Mode only on 18512 and 1801.

September 17, 1999 (Version 1.3)

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XC1800 Series of In-System Programmable Configuration PROMs

Xilinx FPGAs and Compatible

PROMs

Capacity

Devices

1804

Configuration Bits

4,194,304

2,097,152

1,048,576

524,288

Device

XC4003E

Configuration Bits

53,984

PROM

XC18128

XC18256

XC18512

XC18128

XC18256

XC18512

XC1801

XC1802

XC1804

XC4005E

95,008

1802

XC4006E

119,840

1801

XC4008E

147,552

18512

18256

18128

XC4010E

178,144

262,144

XC4013E

247,968

131,072

XC4020E

329,312

XC4025E

422,176

XC4002XL

61,100

XC4005XL

151,960

XC4010XL

283,424

XC4013XL/XLA

XC4020XL/XLA

XC4028XL/XLA

XC4036XL/XLA

XC4044XL/XLA

XC4052XL/XLA

XC4062XL/XLA

XC4085XL/XLA

XC40110XV

XC40150XV

XC40200XV

393,632

521,880

668,184

832,528

1,014,928

1,215,368

1,433,864

1,924,992

2,686,136

3,373,448

4,551,056

XC1804 +

XC18512

XC40250XV

5,433,888

XC1804 +

XC1802

XCV50

XCV100

XCV150

XCV200

XCV300

XCV400

XCV600

XCV800

559,232

781,248

XC1801

XC1802

XC1804

1,041,128

1,335,872

1,751,840

2,546,080

3,608,000

4,715,648

XC1804 +

XC18512

XCV1000

6,127,776

XC1804 +

XC1802

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September 17, 1999 (Version 1.3)

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XC1800 Series of In-System Programmable Configuration PROMs

In-System Programming

Reliability and Endurance

One or more in-system programmable PROMs can be

daisy chained together and programmed in-system via the

standard 4-pin JTAG protocol as shown in Figure 2. In-sys-

tem programming offers quick and efficient design itera-

tions and eliminates unnecessary package handling or

socketing of devices. The Xilinx development system pro-

vides the programming data sequence using Xilinx JTAG

Programmer software and a download cable, a third-party

JTAG development system, a JTAG-compatible board

tester, or a simple microprocessor interface that emulates

the JTAG instruction sequence.

Xilinx in-system programmable products provide a mini-

mum endurance level of 10,000 in-system program/erase

cycles and a minimum data retention of 10 years. Each

device meets all functional, performance, and data reten-

tion specifications within this endurance limit.

Design Security

The Xilinx in-system programmable PROM devices incor-

porate advanced data security features to fully protect the

programming data against unauthorized reading. Table 2

shows the security setting available.

All outputs are 3-stated or held at clamp levels during in-

system programming.

The read security bit can be set by the user to prevent the

internal programming pattern from being read or copied via

JTAG. When set it allows device erase. Erasing the entire

device is the only way to reset the read security bit.

External Programming

Xilinx reprogrammable PROMs can also be programmed

by the Xilinx HW-130 device programmer. This provides the

added flexibility of using pre-programmed devices in

design, boundary-scan manufacturing tools, with an in-sys-

tem programmable option for future enhancements and

design changes.

Table 2: Data Security Options

Default

Set

Read Allowed

Program/Erase Allowed

Read Inhibited via JTAG

Erase Allowed

(a)

(b)

X5902

Figure 2: In-System Programming Operation (a) solder device to PCB and (b) Program using Download Cable

September 17, 1999 (Version 1.3)

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XC1800 Series of In-System Programmable Configuration PROMs

Security field, IR(3), will contain logic 1 if the device has

been programmed with the security option turned on; other-

wise, it will contain 0.

IEEE 1149.1 Boundary-Scan (JTAG)

The XC1800 family is fully compliant with the IEEE Std.

1149.1 Boundary-Scan, also known as JTAG. A Test

Access Port (TAP) and registers are provided to support all

required boundary scan instructions, as well as many of the

optional instructions specified by IEEE Std. 1149.1. In addi-

tion, the JTAG interface is used to implement in-system

programming (ISP) to facilitate configuration, erasure, and

verification operations on the XC1800 device.

IR(7:5) IR(4)

ISP

IR(3)

IR(2) IR(1:0)

0 1 ->TDO

TDI-> 0 0 0

Security

0

Status

Note: IR(1:0) = 01 is specified by IEEE Std. 1149.1

Figure 3: Instruction Register values loaded into IR

as part of an instruction scan sequence

Table 3 lists the required and optional boundary-scan

instructions supported in the XC1800. Refer to the IEEE

Std. 1149.1 specification for a complete description of

boundary-scan architecture and the required and optional

instructions.

Boundary Scan Register

The boundary-scan register is used to control and observe

the state of the device pins during the EXTEST, SAMPLE/

PRELOAD, and CLAMP instructions. Each output pin on

the XC1800 has two register stages that contribute to the

boundary-scan register, while each input pin only has one

register stage.

Table 3: Boundary Scan Instructions

Boundary- Binary Code

Description

Scan

(7:0)

Command

For each output pin, the register stage nearest to TDI con-

trols and observes the output state, and the second stage

closest to TDO controls and observes the 3-state enable

state of the pin.

Required Instructions

BYPASS

11111111 Enables BYPASS

SAMPLE/

PRELOAD

00000001 Enables boundary-scan

SAMPLE/PRELOAD

operation

For each input pin, the register stage controls and observes

the input state of the pin.

EXTEST

00000000 Enables boundary-scan

EXTEXT operation

Identification Registers

Optional Instructions

The IDCODE is a fixed, vendor-assigned value that is used

to electrically identify the manufacturer and type of the

device being addressed. The IDCODE register is 32-bits

wide. The IDCODE register can be shifted out for examina-

tion by using the IDCODE instruction.

CLAMP

11111010 Enables boundary-scan

CLAMP operation

HIGHZ

11111100 3-states all outputs

simultaneously

The IDCODE register has the following binary format:

vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1

where

IDCODE

11111110 Enables shifting out 32-

bit IDCODE

USERCODE

11111101 Enables shifting out 32-

bit USERCODE

v= the die version number

XC1800 Specific Instructions

f=the family code (50h for XC1800 family)

a=the ISP PROM product ID (06h for the XC1804)

c=the company code (49h for Xilinx)

CONFIG

11101110 Initiates FPGA

configuration by pulsing

CF pin low

Note: The LSB of the IDCODE register is always read as

logic 1 as defined by IEEE Std. 1149.1

Instruction Register

The Instruction Register (IR) for the XC1800 is 8-bits wide

and is connected between TDI and TDO during an instruc-

tion scan sequence. In preparation for an instruction scan

sequence, the instruction register is parallel loaded with a

fixed instruction capture pattern. This pattern is shifted out

onto TDO (LSB first), while an instruction is shifted into the

instruction register from TDI. The detailed composition of

the instruction capture pattern is illustrated in Figure 3.

Table 4: IDCODES Assigned to XC1800 devices

ISP-PROM

XC1801

IDCODE

05004093h

05006093h

XC1804

Table 4 lists the IDCODE register values for the XC1800

devices.

The ISP Status field, IR(4), contains logic 1 if the device is

currently in ISP mode; otherwise, it will contain 0. The

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September 17, 1999 (Version 1.3)

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XC1800 Series of In-System Programmable Configuration PROMs

The USERCODE instruction gives access to a 32-bit user

programmable scratch pad typically used to supply infor-

mation about the devices’s programmed contents. By using

the USERCODE instruction, a user-programmable identifi-

cation code can be shifted our for examination. This code is

loaded into the USERCODE register during programming

of the XC1800 device. If the device is blank or was not

loaded during programming, the USERCODE register will

contain FFFFFFFFh.

4-wire Test Access Port (TAP). This simplifies system

designs and allows standard Automatic Test Equipment to

perform both functions. The AC characteristics of the

XC1800 TAP are described as follows.

TAP Timing

Figure 4 shows the timing relationships of the TAP signals.

These TAP timing characteristics are identical for both

boundary-scan and ISP operations.

XC1800 TAP Characteristics

The XC1800 family performs both in-system programming

and IEEE 1149.1 boundary-scan (JTAG) testing via a single

TCKMIN

TCK

TMSH

TMSS

TMS

TDIS

TDIH

TDI

TDOV

TDOXZ

TDOZX

TDO

Figure 4: Test Access Port Timing

TAP AC Parameters

Table 5 shows the timing parameters for the TAP wave-

forms shown in Figure 4

Table 5: Test Access Port Timing Parameters (ns)

Symbol

Parameter

Min Max

TCKMIN TCK Minimum Clock Period

100

10

15

25

35

TMSS

TMSH

TDIS

TMS Setup Time

TMS Hold Time

TDI Setup Time

TDIH

TDI Hold Time

TDOZX

TDOXZ

TDOV

TDO Float to Valid Delay

TDI Valid to Float Delay

TDO Valid Delay

September 17, 1999 (Version 1.3)

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XC1800 Series of In-System Programmable Configuration PROMs

either automatically upon power up, or on command,

depending on the state of the three FPGA mode pins. In

Master Serial mode, the FPGA automatically loads the con-

figuration program from an external memory. Xilinx PROMs

are designed for compatibility with the Master Serial mode.

Controlling Configuration PROMs

Connecting the FPGA device with the configuration PROM.

•

The DATA output(s) of the of the PROM(s) drives the

DIN input of the lead FPGA device.

The Master FPGA CCLK output drives the CLK input(s)

of the PROM(s).

The CEO output of a PROM drives the CE input of the

next PROM in a daisy chain (if any).

The OE/RESET input of all PROMs is best driven by

the INIT output of the lead FPGA device. This

connection assures that the PROM address counter is

reset before the start of any (re)configuration, even

when a reconfiguration is initiated by a V_CCglitch.

Upon power-up or reconfiguration, an FPGA enters the

Master Serial mode whenever all three of the FPGA mode-

select pins are Low (M0=0, M1=0, M2=0). Data is read from

the PROM sequentially on a single data line. Synchroniza-

tion is provided by the rising edge of the temporary signal

CCLK, which is generated during configuration.

Master Serial Mode provides a simple configuration inter-

face. Only a serial data line and two control lines are

required to configure an FPGA. Data from the PROM is

read sequentially, accessed via the internal address and bit

counters which are incremented on every valid rising edge

of CCLK. If the user-programmable, dual-function DIN pin

on the FPGA is used only for configuration, it must still be

held at a defined level during normal operation. The Xilinx

FPGA families take care of this automatically with an on-

chip default pull-up resistor.

•

The PROM CE input can be driven from either the LDC

or DONE pins. Using LDC avoids potential contention

on the DIN pin. If the CE input of the first (or only)

PROM can be driven by the DONE output of the first

FPGA device, provided that DONE is not permanently

grounded. Otherwise, LDC can be used to drive CE, but

must then be unconditionally High during user

operation. CE can also be permanently tied Low, but

this keeps the DATA output active and causes an

unnecessary supply current of 10 mA maximum.

Express mode is similar to slave serial mode. The

DATA is clocked out of the SPROM one byte per CCLK

instead of one bit per CCLK cycle. To synchronize with

the FPGA the first byte of data is valid 20ns before the

second rising edge of CCLK and then on every

consecutive CCLK thereafter. Note: When

Programming the FPGA With Counters

Unchanged Upon Completion

•

When multiple FPGA-configurations for a single FPGA are

stored in a PROM, the OE/RESETpin should be tied Low.

Upon power-up, the internal address counters are reset

and configuration begins with the first program stored in

memory. Since the OE/RESETpin is held Low, the address

counters are left unchanged after configuration is com-

plete. Therefore, to reprogram the FPGA with another pro-

gram, the DONE line is pulled Low and configuration

begins at the last value of the address counters.

programming in Express mode, to accommodate the

4us set-up time on the INIT pin of the Spartan FPGA,

the first line of the configuration stream must not be

placed higher than the 3C byte address of the PROM.

Initiating FPGA Configuration

This method fails if a user applies OE/RESET during the

FPGA configuration process. The FPGA aborts the config-

uration and then restarts a new configuration, as intended,

but the PROM does not reset its address counter, since it

never saw a High level on its OE input. The new configura-

tion, therefore, reads the remaining data in the PROM and

interprets it as preamble, length count etc. Since the FPGA

is the master, it issues the necessary number of CCLK

pulses, up to 16 million (2²⁴) and DONE goes High. How-

ever, the FPGA configuration will be completely wrong, with

potential contentions inside the FPGA and on its output

pins. This method must, therefore, never be used when

there is any chance of external reset during configuration.

The XC1800 devices incorporate a pin named CF that is

controllable through the JTAG CONFIG instruction. Execut-

ing the CONFIG instruction through JTAG will pulse the CF

low for 300-500ns, which will reset the FPGA and initiate

configuration.

The CF pin must be connected to the PROGRAM pin on

the FPGA to use this feature.

Selecting Configuration Modes

The XC1800 accommodates serial and parallel methods of

configuration. The configuration modes are selectable

through a user control register in the XC1800 device. This

control register is accessible through JTAG, using the Xilinx

JTAG Programmer software.

Cascading Configuration PROMs

For multiple FPGAs configured as a daisy-chain, or for

FPGAs requiring larger configuration memories, cascaded

PROMs provide additional memory. Multiple XC1800

devices can be concatenated by using the CEO output to

drive the CE input of the following device. The clock inputs

and the data outputs of all XC1800 devices in the chain are

FPGA Master Serial Mode Summary

The I/O and logic functions of the Configurable Logic Block

(CLB) and their associated interconnections are estab-

lished by a configuration program. The program is loaded

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September 17, 1999 (Version 1.3)

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XC1800 Series of In-System Programmable Configuration PROMs

interconnected. After the last bit from the first PROM is

read, the next clock signal to the PROM asserts its CEO

output Low and disables its DATA line. The second PROM

recognizes the Low level on its CE input and enables its

DATA output. See Figure 5.

After configuration is complete, the address counters of all

cascaded PROMs are reset if the PROM OE/RESET pin

goes Low.

To reprogram the FPGA with another program, the DONE

line goes Low and configuration begins where the address

counters had stopped. In this case, avoid contention

between DATA and the configured I/O use of DIN.

September 17, 1999 (Version 1.3)

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XC1800 Series of In-System Programmable Configuration PROMs

Vcc

OPTIONAL

OUT

D

Daisy-chained

FPGAs with

Different

Configurations

FPGA

OPTIONAL

Slave FPGAs

with Identical

Configurations

MODES

Vcc

Vcco

V

CCO

CC

DATA

CLK

DIN

Cascaded

PROM

CLK

CCLK

DONE

INIT

FIRST

PROM

CEO

CE

OE/RESET

CF

OE/RESET

PROGRAM

(Low Resets the Address Pointer)

Master Serial Mode

I/O*

3.3V

Vcco

Vcc

CC

CS

WRITE

VIRTEX

Select MAP

M0

M1

M2

4.7k

External Osc

3.3V

4.7K

V

CCO

NC

BUSY

DONE

XC18xx

CLK

CCLK

D0-D7

8

D0-D7

CE

OE/RESET

PROGRAM

CEO

CF

INIT

Virtex Select MAP Mode

To Additional

Optional

Vcc

Daisy-Chained

Devices

M0

M1

DOUT

M0

M1

Vcco

Vcc

CS1

Optional

Daisy-Chained

Spartan XL

DOUT

Vcc

4k

Spartan XL

V

CC

V

CCO

8

CEO

D0-D7

CF

D0-D7

XC18xx

DONE

PROGRAM

INIT

PROGRAM DONE

CE

OE/RESET

CLK

INIT

CCLK

To Additional

Optional

Daisy-Chained

Devices

CCLK

Spartan XL Express Mode

*CS and WRITE must be pulled down to be used as I/O. One option is shown.

Figure 5: (a) Master Serial Mode (b) Virtex Select MAP Mode (c) Spartan XL Express Mode

10

September 17, 1999 (Version 1.3)

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XC1800 Series of In-System Programmable Configuration PROMs

pulse from the FPGA. OE/RESET is connected to an exter-

nal resistor to pull OE/RESET HIGH releasing the FPGA

INIT and allowing configuration to begin. OE/RESET is

held low until the XC1800 voltage reaches the operating

voltage range. If the power drops below 2.0 Volts, the

PROM will reset.

5V Tolerant I/Os

The I/Os on each re-programmable PROM are fully 5V tol-

erant even through the core power supply is 3.3 volts. This

allows 5V CMOS signals to connect directly to the PROM

inputs without damage. In addition, the 3.3V V_CCpower

supply can be applied before or after 5V signals are applied

to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins,

the core power supply (V_CC), and the output power supply

(V_CCO) may have power applied in any order. This makes

the PROM devices immune to power supply sequencing

issues.

Standby Mode

The PROM enters a low-power standby mode whenever

CE is asserted High. The output remains in a high imped-

ance state regardless of the state of the OE input. JTAG

pins TMS, TDI and TDO can be 3-state or high.

Reset Activation

On power up, OE/RESET is held low until the XC1800 is

active (1ms) and able to supply data after receiving a CCLK

Table 6: Truth Table for PROM Control Inputs

Control Inputs

Outputs

Internal Address

OE/RESET

Low

CE

Low

DATA

active

CEO

High

I_cc

active

if address < TC: increment

if address > TC: don’t change

3-state

Low

High

reduced

High

Low

High

Low

High

Held reset

active

standby

Note: TC = Terminal Count = highest address value. TC+1 = address 0.

September 17, 1999 (Version 1.3)

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XC1800 Series of In-System Programmable Configuration PROMs

Absolute Maximum Ratings

Symbol

Description

Supply voltage relative to GND

Value

-0.5 to +4.0

-0.5 to +5.5

-65 to +150

+260

Units

V

V_CC

V_IN

Input voltage with respect to GND

Voltage applied to 3-state output

Storage temperature (ambient)

Maximum soldering temperature (10 s @ 1/16 in.)

Junction Temperature

V

V_TS

V

T_STG

T_SOL

T_J

°C

+150

Notes

1:

Maximum DC undershoot below GND must be limited to either 0.5V or 10mA, whichever is easier to achieve. During

transitions, the device pins may undershoot to -2.0V or overshoot to +7.0V, provided this over- or undershoot lasts less then

10 ns and with the forcing current being limited to 200mA.

2:

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress

ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating

Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device

reliability.

Recommended Operating Conditions

Symbol

Parameter

Min

3.0

2.3

0

Max

3.6

Units

V_CCINT

Commercial

Industrial

Internal Voltage supply (T_A= 0°C to +70°C)

Internal Voltage supply (T_A= -40°C to +85°C)

V

3.6

V_CCO

Supply voltage for output drivers for 3.3V operation

Supply voltage for output drivers for 2.5V operation

Low-level input voltage

3.6

2.7

V_IL

V_IH

V_O

0.8

High-level input voltage

2.0

0

5.5

Output voltage

V_CCO

Quality and Reliability Characteristics

Symbol

t_DR

Description

Min

10

Max

Units

Years

Cycles

Volts

Data Retention

-

N_PE

Program/Erase Cycles (Endurance)

Electrostatic Discharge (ESD)

10,000

2,000

V_ESD

12

September 17, 1999 (Version 1.3)

R

XC1800 Series of In-System Programmable Configuration PROMs

DC Characteristics Over Operating Conditions

Test Conditions

Symbol

V_OH

Parameter

Min

2.4

Max

Units

V

High-level output voltage for 3.3 V outputs

High-level output voltage for 2.5 V outputs

Low-level output voltage for 3.3V outputs

Low-level output voltage for 2.5V outputs

Supply current, active mode

I_OH= -4 mA

I_OH= -500 µA

I_OL= 8 mA

90% V_CCO

V

V_OL

0.4

V

I_OL= 500 µA

V

I_CCA

at maximum

frequency

30.0

mA

I_CCS1

I_CCS2*

I_CCS3**

I_ILJ

Supply current, standby mode 1

Supply current, standby mode 2

Supply current, standby mode 3

JTAG pins TMS, TDI, and TDO

2.0

300

100

mA

µA

V_{CC =}MAX

-100

-10.0

V

_IN= GND

I_IL

Input leakage current

V_CC= Max

10.0

µA

pF

V

_IN= GND or V_CC

I_IH

Input & Output high-Z leakage current

Input and Output Capacitance

V_CC= Max

V_IN= GND or V_CC

C

_IN& C_OUT

V_IN= GND

f = 1.0 MHz

* 1801/18512/18256/18128 only, cascadable

**1801/18512/18256/18128 only, non-cascadable

September 17, 1999 (Version 1.3)

13

R

XC1800 Series of In-System Programmable Configuration PROMs

.AC Characteristics Over Operating Conditions

CE

9

10

9

T

HCE

SCE

RESET/OE

CLK

T

11

HOE

T

8

LC

7

T

HC

6

T

CYC

3

4

T

OE

1

5

T

DF

T

CAC

OH

T

2

CE

DATA

4

T

OH

99020801

Symbol

Description

Min

Max

30

45

Units

1

2

3

4

5

6

7

8

T_OE

T_CE

T_CAC

T_OH

T_DF

T_CYC

T_LC

T_HC

T_SCE

T_HCE

T_HOE

OE to Data Delay

CE to Data Delay

CLK to Data Delay

ns

45

Data Hold From CE, OE, or CLK

CE or OE to Data Float Delay²

Clock Periods

0

50

67

25

0

CLK Low Time³

CLK High Time³

9

10

11

CE Setup Time to CLK (to guarantee proper counting)

CE Hold Time to CLK (to guarantee proper counting)

OE Hold Time (guarantees counters are reset)

25

Notes: 1. AC test load = 50 pF

2. Float delays are measured with 5 pF AC loads. Transition is measured at +/- 200mV from steady state active levels.

3. Guaranteed by design, not tested.

4. All AC parameters are measured with V_IL= 0.0 V and V_IH= 3.0 V.

14

September 17, 1999 (Version 1.3)

R

XC1800 Series of In-System Programmable Configuration PROMs

AC Characteristics Over Operating Condition When Cascading

RESET/OE

CE

CLK

T

12

CDF

Last Bit

First Bit

DATA

CEO

T

13

T

OOE

OCK

15

T

OCE

14

OCE

99020800

Symbol

T_CDF

Description

Min

Max

Units

12

13

14

15

CLK to Data Float Delay^{2, 3}

CLK to CEO Delay³

50

30

35

30

ns

T_OCK

T_OCE

CE to CEO Delay³

T_OOE

RESET/OE to CEO Delay³

Notes: 1. AC test load = 50 pF

2. Float delays are measured with 5 pF AC loads. Transition is measured at +/- 200mV from steady state active levels.

3. Characterized but not 100% tested.

4. All AC parameters are measured with V_IL= 0.0 V and V_IH= 3.0 V.

September 17, 1999 (Version 1.3)

15

R

XC1800 Series of In-System Programmable Configuration PROMs

Ordering Information

XC1804 VQ44 C

Device Number

Operating Range/Processing

XC1804

XC1802

XC1801

XC18512

XC18256

XC18128

C = Commercial (T_A= 0° to +70°C)

I

= Industrial (T_A= –40° to +85°C)

Package Type

VQ44=44-Pin Plastic Quad Flat Package

PC44=44-Pin Plastic Chip Carrier

SO20=20-Pin Small-Outline Package

PC20=20-Pin Plastic Leaded Chip Carrier

Valid Ordering Combinations

XC1804VQ44C

XC1804PC44C

XC1804VQ44I

XC1804PC44I

XC1802VQ44C

XC1802PC44C

XC1802VQ44I

XC1802PC44I

XC1801SO20C

XC1801PC20C

XC1801SO20I

XC1801PC20I

XC18512SO20C

XC18512PC20C

XC18512SO20I

XC18512PC20I

XC18256SO20C

XC18256PC20C

XC18256SO20I

XC18256PC20I

XC18128SO20C

XC18128PC20C

XC18128SO20I

XC18128PC20I

Marking Information

XC1804 VQ44 C

44-Pin Package

Device Number

XC1804

XC1802

Operating Range/Processing

C = Commercial (T_A= 0° to +70°C)

Package Type

I

= Industrial (T_A= –40° to +85°C)

VQ44=44-Pin Plastic Quad Flat Package

PC44=44-Pin Plastic, Leaded Chip Carrier

1801 S C

20-Pin Package

Device Number

Operating Range/Processing

C = Commercial (T_A= 0° to +70°C)

XC1801

XC18512

XC18256

XC18128

Package Type

S=20-Pin Small-Outline Package

J=20-Pin Plastic Leaded Chip Carrier

I

= Industrial (T_A= –40° to +85°C)

Revision Control

Date

2/9/99

8/23/99

9/1/99

9/16/99

Version

Revision

1.0

1.1

1.2

1.3

First publication of this early access specification

Edited text, changed marking, added CF and parallel load

Corrected JTAG order, Security and Endurance data.

Corrected SelectMAP diagram, control inputs, reset polarity. Added JTAG and CF

description, 256 Kbit and 128 Kbit devices.

16

September 17, 1999 (Version 1.3)


型号：	TMSS
厂家：	XILINX, INC
描述：	XC1800 Series of In-System Programmable Configuration PROMs XC1800系列在系统可编程配置PROM的可编程只读存储器
文件：	总16页 (文件大小：116K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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