5962-9850901NUB [XILINX]
Field Programmable Gate Array, PBGA352, PLASTIC, BGA-352;
| 型号： | 5962-9850901NUB |
| 厂家： | 
XILINX, INC |
| 描述： | Field Programmable Gate Array, PBGA352, PLASTIC, BGA-352 栅 |
| 文件： | 总19页 (文件大小：543K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
R
QPRO™ XQ4000XL Series QML
High-Reliability FPGAs
0
0*
DS029 (v1.2) February 9, 2000
•
•
Highest Capacity — Over 130,000 Usable Gates
Additional Routing Over XQ4000E
XQ4000X Series Features
•
Certified to MIL-PRF-38535 Appendix A QML (Qualified
Manufacturer Listing)
-
almost twice the routing capacity for high-density
designs
•
•
Ceramic and plastic packages
Also available under the following standard microcircuit
drawings (SMD)
•
•
•
Buffered Interconnect for Maximum Speed
New Latch Capability in Configurable Logic Blocks
Improved VersaRing™ I/O Interconnect for Better Fixed
Pinout Flexibility
-
-
-
-
XQ4013XL 5962-98513
XQ4036XL 5962-98510
XQ4062XL 5962-98511
XQ4085XL 5962-99575
-
Virtually unlimited number of clock signals
•
Optional Multiplexer or 2-input Function Generator on
Device Outputs
5V tolerant I/Os
•
For more information contact the Defense Supply
Center Columbus (DSCC)
•
•
0.35 µm SRAM process
http://www.dscc.dla.mis/v/va/smd/smdsrch.html
•
•
Available in -3 speed
System featured Field-Programmable Gate Arrays
Introduction
XQ4000X Series high-performance, high-capacity Field
Programmable Gate Arrays (FPGAs) provide the benefits
of custom CMOS VLSI, while avoiding the initial cost, long
development cycle, and inherent risk of a conventional
masked gate array.
-
SelectRAM™ memory: on-chip ultra-fast RAM with
-
-
synchronous write option
dual-port RAM option
-
-
-
-
-
-
-
Abundant flip-flops
Flexible function generators
Dedicated high-speed carry logic
Wide edge decoders on each edge
Hierarchy of interconnect lines
Internal 3-state bus capability
Eight global low-skew clock or signal distribution
networks
The result of thirteen years of FPGA design experience and
feedback from thousands of customers, these FPGAs com-
bine architectural versatility, on-chip Select-RAM memory
with edge-triggered and dual-port modes, increased speed,
abundant routing resources, and new, sophisticated
soft-ware to achieve fully automated implementation of
complex, high-density, high-performance designs.
•
•
•
•
System Performance beyond 50 MHz
Flexible Array Architecture
Low Power Segmented Routing Architecture
Systems-Oriented Features
Refer to the complete Commercial XC4000X Series Field
Programmable Gate Arrays Data Sheet for more informa-
tion on device architecture and timing, and the latest Xilinx
databook for package pinouts other than the CB228
(included in this data sheet). (Pinouts for XQ4000XL device
are identical to XC4000XL.)
-
IEEE 1149.1-compatible boundary scan logic
support
-
-
-
Individually programmable output slew rate
Programmable input pull-up or pull-down resistors
12 mA Sink Current Per XQ4000XL Output
•
•
Configured by Loading Binary File
Unlimited reprogrammability
Readback Capability
-
-
-
Program verification
Internal node observability
•
Development System runs on most common computer
platforms
-
-
-
- Interfaces to popular design environments
- Fully automatic mapping, placement and routing
- Interactive design editor for design optimization
DS029 (v1.2) February 9, 2000
1
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
Table 1: XQ4000X Series High Reliability Field Progammable Gate Arrays
Max Logic Max. RAM
Gates Bits
(No RAM) (No Logic) (Logic and RAM)*
Typical Gate
Range
Logic
Cells
CLB
Matrix
Total
CLBs
Number of
Flip-Flops
Max.
User I/O
Device
Packages
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
2432
3078
5472
7448
13,000
36,000
62,000
85,000
18,432
41,472
73,728
100,352
10,000-30,000
22,000-65,000
40,000-130,000
55,000-180,000
24x24
36x36
48x48
56x56
576
1,536
3,168
5,376
7,168
192
288
384
448
PG223, CB228,
PQ240, BG256
1,296
2,304
3,136
PG411, CB228,
HQ240, BG352
PG475, CB228,
HQ240, BG432
PG475, CB228,
HQ240, BG432
* Maximum values of typical gate range includes 20% to 30% of CLBs used as RAM.
XQ4000XL Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:
Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or families.
Values are subject to change. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered final.
All specifications subject to change without notice.
Additional Specifications
Except for pin-to-pin input and output parameters, the a.c. parameter delay specifications included in this document are
derived from measuring internal test patterns. All specifications are representative of worst-case supply voltage and junction
temperature conditions. The parameters included are common to popular designs and typical applications. For design
considerations requiring more detailed timing information, see the appropriate family a.c. supplements available on the
Xilinx WEBLINX at http://www.xilinx.com.
Absolute Maximum Ratings
Symbol
Description
Units
V
V
Supply voltage relative to GND
-0.5 to 4.0
-0.5 to 5.5
-0.5 to 5.5
50
CC
V
Input voltage relative to GND (Note 1)
V
IN
V
Voltage applied to 3-state output (Note 1)
Longest Supply Voltage Rise Time from 1 V to 3V
Storage temperature (ambient)
V
TS
V
T
ms
°C
°C
°C
°C
CCt
-65 to +150
+260
STG
SOL
T
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
Ceramic Package
Plastic Package
+150
T
Junction temperature
J
+125
Note 1: Maximum DC overshoot or undershoot above Vcc or below GND must be limited to either 0.5 V or 10 mA, whichever is easier to
achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to + 7.0 V, provided this over- or undershoot lasts
less than 10 ns and with the forcing current being limited to 200 mA.
Note 2: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress rat-
ings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is
not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
2
DS029 (v1.2) February 9, 2000
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
Recommended Operating Conditions
Symbol
Description
Min
Max
Units
Supply voltage relative to GND, T = -55°C to
Plastic
3.0
3.6
V
J
+125°C
V
CC
Supply voltage relative to GND, T = -55°C to
Ceramic
3.0
3.6
V
C
+125°C
V
High-level input voltage
Low-level input voltage
Input signal transition time
50% of V
0
5.5
30% of V
250
V
V
IH
CC
V
IL
CC
T
ns
IN
Note 1: At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per ×C.
Note 2: Input and output measurement threshold is ~50% of VCC
.
XQ4000XL DC Characteristics Over Recommended Operating Conditions
Symbol
Description
High-level output voltage @ I = -4.0 mA, V min (LVTTL)
Min
2.4
Max
Units
V
OH
CC
V
OH
High-level output voltage @ I = -500 µA, (LVCMOS)
90% V
V
OH
CC
Low-level output voltage @ I = 12.0 mA, V min (LVTTL) (Note 1)
0.4
V
V
OL
CC
OL
DR
Low-level output voltage @ I = 1500 µA, (LVCMOS)
10% V
V
OL
CC
V
Data Retention Supply Voltage (below which configuration data may be lost)
Quiescent FPGA supply current (Note 2)
2.5
-10
V
I
5
mA
µA
pF
pF
mA
mA
mA
CCO
I
Input or output leakage current
+10
10
L
BGA, PQ, HQ, packages
Input capacitance (sample tested)
C
IN
PGA packages
16
I
Pad pull-up (when selected) @ V = 0 V (sample tested)
0.02
0.02
0.3
0.25
0.15
2.0
RPU
RPD
in
I
Pad pull-down (when selected) @ V = 3.6 V (sample tested)
in
I
Horizontal Longline pull-up (when selected) @ logic Low
RLL
Note 1: With up to 64 pins simultaneously sinking 12 mA.
Note 2: With no output current loads, no active input or Longline pull-up resistors, all I/O pins Tri-stated and floating.
DS029 (v1.2) February 9, 2000
3
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock distribution is faster; when multiple clock lines per column are driven
from the same global clock, the delay is longer. For more specific, more precise, and worst-case guaranteed data, reflecting
the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development System)
and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from the static
timing analyzer report. All timing parameters assume worst-case operating conditions (supply voltage and junction
temperature).
Speed Grade
Device
-3
-1
Units
Description
Symbol
Max
Max
From pad through Global Low Skew buffer, to any clock K
T
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
3.6
4.8
6.3
-
-
-
-
ns
ns
ns
ns
GLS
5.7
From pad through Global Early buffer, to any IOB clock. Values are for
BUFGE #s 1, 2, 5 and 6. Add 1 - 2 ns for BUFGE #s 3, 4, 7 and 8 and
for all CLB clock Ks driven from any of the 8 BUFGEs, or consult TRCE.
T
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
2.4
3.1
4.9
-
-
-
-
ns
ns
ns
ns
GE
4.7
4
DS029 (v1.2) February 9, 2000
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL CLB Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XQ4000XL devices and expressed in nanoseconds unless otherwise noted.
Speed Grade
Symbol
-3
-1
Units
Description
Combinatorial Delays
Min
Max
Min
Max
F/G inputs to X/Y outputs
F/G inputs via H’ to X/Y outputs
F/G inputs via transparent latch to Q outputs
C inputs via SR/H0 via H to X/Y outputs
C inputs via H1 via H to X/Y outputs
C inputs via DIN/H2 via H to X/Y outputs
TILO
TIHO
TITO
THH0O
THH1O
THH2O
1.6
2.7
2.9
2.5
2.4
2.5
1.5
1.3
2.2
2.2
2.8
1.9
2.0
1.1
ns
ns
ns
ns
ns
ns
ns
C inputs via EC, DIN/H2 to YQ, XQ output (bypass) TCBYP
CLB Fast Carry Logic
Operand inputs (F1, F2, G1, G4) to COUT
Add/Subtract input (F3) to COUT
Initialization inputs (F1, F3) to COUT
CIN through function generators to X/Y outputs
CIN to COUT, bypass function generators
Carry Net Delay, COUT to CIN
TOPCY
TASCY
TINCY
TSUM
TBYP
2.7
3.3
2.0
2.8
0.26
0.32
2.0
2.5
1.5
2.4
0.20
0.25
ns
ns
ns
ns
ns
ns
TNET
Sequential Delays
Clock K to Flip-Flop outputs Q
Clock K to Latch outputs Q
TCKO
TCKLO
2.1
2.1
1.6
1.6
ns
ns
Setup Time before Clock K
F/G inputs
F/G inputs via H
C inputs via H0 through H
C inputs via H1 through H
C inputs via H2 through H
C inputs via DIN
C inputs via EC
C inputs via S/R, going Low (inactive)
CIN input via F/G
TICK
1.1
2.2
2.0
1.9
2.0
0.9
1.0
0.6
2.3
3.4
0.9
1.7
1.6
1.4
1.6
0.7
0.8
0.5
1.9
2.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIHCK
THH0CK
THH1CK
THH2CK
TDICK
TECCK
TRCK
TCCK
TCHCK
CIN input via F/G and H
Hold Time after Clock K
F/G inputs
F/G inputs via H
C inputs via SR/H0 through H
C inputs via H1 through H
C inputs via DIN/H2 through H
C inputs via DIN/H2
TCKI
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
TCKIH
TCKHH0
TCKHH1
TCKHH2
TCKDI
TCKEC
TCKR
C inputs via EC
C inputs via SR, going Low (inactive)
Clock
Clock High time
Clock Low time
TCH
TCL
3.0
3.0
2.5
2.5
ns
ns
Set/Reset Direct
Width (High)
Delay from C inputs via S/R, going High to Q
TRPW
TRIO
3.0
2.5
ns
ns
3.7
2.8
Global Set/Reset
TMRW
TMRQ
FTOG
19.8
15.0
ns
Minimum GSR Pulse Width
Delay from GSR input to any Q
Toggle Frequency (MHz) (for export control)
See page 14 for TRRI values per device.
166 200
MHz
DS029 (v1.2) February 9, 2000
5
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. All timing
parameters assume worst-case operating conditions (supply voltage and junction temperature). Values apply to all
XQ4000XL devices and are expressed in nanoseconds unless otherwise noted.
Speed Grade
Size Symbol
-3
-1
Single Port RAM
Units
Min
Max
Min
Max
Write Operation
Address write cycle time (clock K period)
16x2
32x1
T
T
9.0
9.0
7.7
7.7
ns
ns
WCS
WCTS
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
16x2
32x1
T
T
4.5
4.5
3.9
3.9
ns
ns
WPS
WPTS
16x2
32x1
T
T
2.2
2.2
1.7
1.7
ns
ns
ASS
ASTS
16x2
32x1
T
T
0
0
0
0
ns
ns
AHS
AHTS
16x2
32x1
T
T
2.0
2.5
1.7
2.1
ns
ns
DSS
DSTS
16x2
32x1
T
T
0
0
0
0
ns
ns
DHS
DHTS
16x2
32x1
T
T
2.0
1.8
1.6
1.5
ns
ns
WSS
WSTS
16x2
32x1
T
T
0
0
0
0
ns
ns
WHS
WHTS
Data valid after clock K
16x2
32x1
T
T
6.8
8.1
5.8
6.9
ns
ns
WOS
WOTS
Read Operation
Address read cycle time
16x2
32x1
T
T
4.5
6.5
2.6
3.8
ns
ns
RC
RCT
Data Valid after address change (no Write Enable)
Address setup time before clock K
16x2
32x1
T
T
1.6
2.7
1.3
2.2
ns
ns
ILO
IHO
16x2
32x1
T
T
1.3
2.3
0.9
1.7
ns
ns
ICK
IHCK
6
DS029 (v1.2) February 9, 2000
R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
Speed Grade
Size Symbol
-3
-1
Unit
s
Dual Port RAM
Write Operation
Min Max Min Max
Address write cycle time (clock K period)
Clock K pulse width (active edge)
Address setup time before clock K
Address hold time after clock K
DIN setup time before clock K
DIN hold time after clock K
WE setup time before clock K
WE hold time after clock K
Data valid after clock K
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
T
T
T
T
T
T
T
T
T
9.0
4.5
2.5
0
2.5
0
7.7
3.9
1.7
0
2.0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
WCDS
WPDS
ASDS
AHDS
DSDS
DHDS
WSDS
WHDS
WODS
1.8
0
1.6
0
7.8
6.7
Note 1: Timing for16 x1 RAM option is identical to16 x 2 RAM.
DS029 (v1.2) February 9, 2000
7
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL CLB RAM Synchronous (Edge-Triggered) Write Timing
TWPS
WCLK (K)
TWSS
TWHS
TDHS
TAHS
WE
TDSS
DATA IN
TASS
ADDRESS
DATA OUT
TILO
TILO
TWOS
OLD
NEW
DS029_01_011300
XQ4000XL CLB Dual-Port RAM Synchronous (Edge-Triggered) Write Timing
TWPDS
WCLK (K)
TWSS
TWHS
WE
TDHDS
TDSDS
DATA IN
TASDS
TAHDS
ADDRESS
DATA OUT
TILO
TILO
TWODS
OLD
NEW
DS029_02_011300
8
DS029 (v1.2) February 9, 2000
R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
XQ4000XL Output Flip-Flop, Clock to Out
Speed Grade
Device
-3
-1
Units
Description
Symbol
Max
Max
Global Low Skew Clock to Output using OFF
T
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
8.6
9.8
11.3
-
-
-
-
ns
ns
ns
ns
ICKOF
9.5
Global Early Clock to Output using OFF
Values are for BUFGE #s 3, 4, 7, and 8. Add
1.4 ns for BUFGE #s 1, 2, 5, and 6.
T
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
7.4
8.1
9.9
-
-
-
-
ns
ns
ns
ns
ICKEOF
8.5
For output SLOW option add
OFF = Output Flip Flop
T
All Devices
3.0
3.0
ns
SLOW
Note 1: Listed above are representative values where one global clock input drives one vertical clock line in each
accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Note 2: Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads,
see graph below.
XQ4000XL Output Mux, Clock to Out
Speed Grade
Device
-3
-1
Units
Description
Symbol
Max
Max
Global Low Skew Clock to Output using OFF
T
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
8.8
10.0
11.4
-
-
-
-
ns
ns
ns
ns
ICKOF
ICKEOF
SLOW
Global Early Clock to Output using OFF. Val- T
ues are for BUFGE #s 3, 4, 7, and 8. Add 1.4
ns for BUFGE #s 1, 2, 5, and 6.
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
7.6
8.2
10.0
-
-
-
-
ns
ns
ns
ns
For output SLOW option add
OFF = Output Flip Flop
T
All Devices
3.0
3.0
ns
Note 1: Listed above are representative values where one global clock input drives one vertical clock line in each
accessible column, and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Note 2: Output timing is measured at ~50% VCC threshold with 50 pF external capacitive load. For different loads,
see graph below.
DS029 (v1.2) February 9, 2000
9
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QPRO™ XQ4000XL Series QML High-Reliability FPGAs
Capacitive Load Factor
Figure 1 shows the relationship between I/O output delay
3
and load capacitance. It allows a user to adjust the speci-
fied output delay if the load capacitance is different than
50 pF. For example, if the actual load capacitance is
2
120 pF, add 2.5 ns to the specified delay. If the load capac-
itance is 20 pF, subtract 0.8 ns from the specified output
1
delay.
0
Figure 1 is usable over the specified operating conditions of
voltage and temperature and is independent of the output
-1
slew rate control.
-2
0
20
40
60
80
100
120
140
Capacitance (pF)
DS029_03_011300
Figure 1: Delay Factor at Various Capacitive Loads
10
DS029 (v1.2) February 9, 2000
R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
XQ4000XL Global Low Skew Clock, Set-Up and Hold
Speed Grade
Device
-3
-1
Units
Description
Input Setup and Hold Times Using
Global Low Skew Clock and IFF
No Delay
Symbol
Min
Min
T
/T
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
1.2 / 3.2
1.2 / 5.5
1.2 / 7.0
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PSN PHN
0.9 / 7.1
Partial Delay
T
/T
6.1 / 0.0
6.4 / 1.0
6.7 / 1.2
-
-
-
-
PSP PHP
9.8 / 1.2
Full Delay
T
/T
6.4 / 0.0
6.6 / 0.0
6.8 / 0.0
-
-
-
-
PSD PHD
9.6 / 0.0
IFF = Input Flip-Flop or Latch
Note 1: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest
distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer (TRCE) to deter-
mine the setup and hold times under given design conditions.
DS029 (v1.2) February 9, 2000
11
R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL BUFGE #s 3, 4, 7, & 8 Global Early Clock, Set-up and Hold for IFF and FCL
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
Speed Grade
Device
-3
-1
Description
Input Setup and Hold Times
No Delay
Global Early Clock and IFF
Global Early Clock and FCL
Symbol
Min
Min
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
1.2 / 4.7
1.2 / 6.7
1.2 / 8.4
-
-
-
-
T
T
/T
PSEN PHEN
/T
PFSEN PFHEN
0.9 / 6.6
Partial Delay
Global Early Clock and IFF
Global Early Clock and FCL
5.4 / 0.0
6.4 / 0.8
8.4 / 1.5
-
-
-
-
T
T
/T
PSEP PHEP
/T
PFSEP PFHEP
11.0 / 0.0
Full Delay
Global Early Clock and IFF
12.0 / 0.0
13.8 / 0.0
13.1 / 0.0
-
-
-
-
T
/T
PSED PHED
13.6 / 0.0
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
Note 1: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest dis-
tance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE) to determine the
setup and hold times under given design conditions.
12
DS029 (v1.2) February 9, 2000
R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL BUFGE #s 1, 2, 5, & 6 Global Early Clock, Set-up and Hold for IFF and FCL
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading. For more specific, more precise, and worst-case guaranteed data,
reflecting the actual routing structure, use the values provided by the static timing analyzer (TRCE in the Xilinx Development
System) and back-annotated to the simulation netlist. These path delays, provided as a guideline, have been extracted from
the static timing analyzer report. Values are expressed in nanoseconds unless otherwise noted.
Speed Grade
Device
-3
-1
Description
Symbol
Min
Min
Input Setup and Hold Times
No Delay
Global Early Clock and IFF
Global Early Clock and FCL
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
1.2 / 4.7
1.2 / 6.7
1.2 / 8.4
-
-
-
-
T
T
/T
PSEN PHEN
/T
PFSEN PFHEN
0.9 / 6.6
Partial Delay
Global Early Clock and IFF
Global Early Clock and FCL
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
6.4 / 0.0
7.0 / 0.0
9.0 / 0.8
-
-
-
-
T
T
/T
PSEP PHEP
/T
PFSEP PFHEP
12.6 / 0.0
Full Delay
Global Early Clock and IFF
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
10.0 / 0.0
12.2 / 0.0
13.1 / 0.0
-
-
-
-
T
/T
PSED PHED
13.6 / 0.0
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
Note 1: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the fur-
thest distance and a reference load of one clock pin per two IOBs. Use the static timing analyzer(TRCE)
to determine the setup and hold times under given design conditions.
DS029 (v1.2) February 9, 2000
13
R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature).
Speed Grade
Device
-3
-1
Units
Description
Symbol
Min
Min
Clocks
Clock Enable (EC) to Clock (IK)
Delay from FCL enable (OK) active edge to IFF clock (IK)
active edge
T
T
All devices
All devices
0.3
1.7
0.3
1.7
ns
ns
ECIK
OKIK
Setup Times
Pad to Clock (IK), no delay
Pad to Clock (IK), via transparent Fast Capture Latch, no
delay
T
T
All devices
All devices
1.7
2.3
1.7
2.3
ns
ns
PICK
PICKF
Pad to Fast Capture Latch Enable (OK), no delay
Hold Times
T
All devices
All devices
0.7
0
0.7
0
ns
ns
POCK
All Hold Times
Global Set/Reset
Minimum GSR Pulse Width
Delay from GSR input to any Q
T
T
All devices
XQ4013XL
XQ4036XL
XQ4062XL
XQ4085XL
19.8
15.9
22.5
29.1
-
19.8
-
-
ns
ns
ns
ns
ns
MRW
RRI
-
26.0
Max
1.6
2.6
3.1
1.8
1.9
3.6
Propagation Delays
Max
1.6
Pad to I1, I2
T
T
All devices
All devices
All devices
All devices
All devices
All devices
ns
ns
ns
ns
ns
ns
PID
PLI
Pad to I1, I2 via transparent input latch, no delay
2.6
Pad to I1, I2 via transparent FCL and input latch, no delay T
3.1
PFLI
Clock (IK) to I1, I2 (flip-flop)
T
T
T
1.8
1.9
3.6
IKRI
IKLI
Clock (IK) to I1, I2 (latch enable, active Low)
FCL Enable (OK) active edge to I1, I2
(via transparent standard input latch)
IFF = Input Flip-Flop or Latch, FCL = Fast Capture Latch
OKLI
14
DS029 (v1.2) February 9, 2000
R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
XQ4000XL IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature). For Propagation Delays, slew-rate = fast unless
otherwise noted. Values are expressed in nanoseconds unless otherwise noted.
Speed Grade
Symbol
-3
-1
Units
Description
Min
Max
Min
Max
Clocks
Clock High
Clock Low
T
T
3.0
3.0
2.5
2.5
ns
ns
CH
CL
Propagation Delays
Clock (OK) to Pad
Output (O) to Pad
3-state to Pad hi-Z (slew-rate independent)
3-state to Pad active and valid
Output (O) to Pad via Fast Output MUX
Select (OK) to Pad via Fast MUX
T
T
T
T
T
T
5.0
4.1
4.4
4.1
5.5
5.1
3.8
3.1
3.0
3.3
4.2
3.9
ns
ns
ns
ns
ns
ns
OKPOF
OPF
TSHZ
TSONF
OFPF
OKFPF
Setup and Hold Times
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
T
T
T
T
0.5
0.0
0.0
0.3
0.3
0.0
0.0
0.1
ns
ns
ns
ns
OOK
OKO
ECOK
OKEC
Global Set/Reset
Minimum GSR pulse width
Delay from GSR input to any Pad
XQ4013XL
T
T
19.8
15.0
ns
MRW
RPO
20.5
27.1
33.7
-
-
-
-
ns
ns
ns
ns
XQ4036XL
XQ4062XL
XQ4085XL
29.5
Slew Rate Adjustment
For output SLOW option add
T
3.0
2.0
ns
SLOW
Note 1: Output timing is measured at ~50% VCC threshold, with 50 pF external capacitive loads.
DS029 (v1.2) February 9, 2000
15
R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
Pinouts
CB228 Package for
XQ4013XL/4036XL/4062XL/4085XL
PIN_NAME
CB228
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PIN_NAME
CB228
VTT
VSS
P1
BUFGP_TL_A16_GCK1_IO
P2
A17_IO
IO
P3
P4
IO
P5
TDI_IO
TCK_IO
IO
P6
P7
P8
BUFGS_BL_GCK2_IO
IO
P9
M1
IO
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
VSS
IO
M0
IO
VCC
IO
M2
VSS
IO_FCLK1
IO
BUFGP_BL_GCK3_IO
HDC_IO
IO
TMS_IO
IO
IO
IO
IO
LDC_IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VSS
VSS
VCC
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
VCC
IO
IO
/ERR_INIT_IO
IO
VCC
VSS
IO
IO
IO_FCLK2
VSS
IO
16
DS029 (v1.2) February 9, 2000
R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
PIN_NAME
CB228
P89
PIN_NAME
CB228
P137
P138
P139
P140
P141
P142
P143
P144
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
P155
P156
P157
P158
P159
P160
P161
P162
P163
P164
P165
P166
P167
P168
P169
P170
P171
P172
P173
P174
P175
P176
P177
P178
P179
P180
P181
P182
P183
P184
IO
IO
IO
IO
IO
IO
VCC
IO
IO
IO
IO
VSS
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
P90
IO
P91
IO
P92
D4_IO
IO
P93
P94
VCC
VSS
D3_IO
/RS_IO
IO
P95
P96
P97
P98
P99
IO
P100
P101
P102
P103
P104
P105
P106
P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
IO
IO
D2_IO
IO
VCC
IO
IO_FCLK4
IO
IO
VSS
IO
IO
BUFGS_BR_GCK4_IO
IO
VSS
IO
DONE
IO
VCC
IO
/PROG
D1_IO
D7_IO
BUSY_/RDY_RCLK_IO
BUFGP_BR_GCK5_IO
IO
IO
IO
IO
D0_DIN_IO
IO
BUFGS_TR_GCK6_DOUT_IO
IO
CCLK
D6_IO
IO
VCC
TDO
IO
VSS
IO
A0_/WS_IO
IO
BUFGP_TR_GCK7_A1_IO
IO
IO
VSS
IO
IO
CSI_A2_IO
IO
A3_IO
IO
IO_FCLK3
IO
IO
D5_IO
/CS0_IO
IO
IO
IO
IO
DS029 (v1.2) February 9, 2000
17
R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
PIN_NAME
CB228
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
P199
P200
P201
P202
P203
P204
P205
P206
P207
P208
P209
P210
P211
P212
P213
P214
P215
P216
P217
P218
P219
P220
P221
P222
P223
P224
P225
P226
P227
P228
IO
VSS
IO
IO
IO
IO
VCC
A4_IO
A5_IO
IO
IO
A21_IO
A20_IO
A6_IO
A7_IO
VSS
VCC
A8_IO
A9_IO
A19_IO
A18_IO
IO
IO
A10_IO
A11_IO
VCC
IO
IO
IO
IO
VSS
IO
IO
IO
IO
A12_IO
A13_IO
IO
IO
IO
IO
A14_IO
BUFGS_TL_GCK8_A15_IO
VCC
18
DS029 (v1.2) February 9, 2000
R
QPRO™ XQ4000XL Series QML High-Reliability FPGAs
Ordering Information
Example for QPRO™ military temperature part:
XQ 4062XL -3 PG 475 M
Mil-PRF-38535
(QML) Processed
Temperature Range
M = Military Ceramic (T = -55 C to +125 C)
o
o
C
N = Military Plastic (T = -55°C to +125°C)
J
Device Type
XQ4085XL
XQ4062XL
XQ4036XL
XQ4013XL
Number of Pins
Speed Grade
-3
-1 (XQ4085XL only)
Package Type
CB = Top Brazed Ceramic Quad Flat Pack
PG = Ceramic Pin Grid Array
PQ/HQ = Plastic Quad Flat Back
BG = Plastic Ball Grid Array
Example for SMD part:
5962 98511 01 Q X C
Generic Standard
Microcircuit Drawing (SMD)
Prefix
Lead Finish
C = Gold
B = Solder
Device Type
XQ4028EX = 98509
XQ4013XL = 98513
XQ4036XL = 98510
XQ4062XL = 98511
XQ4085XL = 99575
Package Type
X = Pin Grid
Y = Ceramic Quad Flat Pack (Base Mark)
Z = Ceramic Quad Flat Pack (Lid Mark)
T = Plastic Quad Flat Pack
U = Plastic Ball Grid
Speed Grade
01 = -4 for XQ4028EX
01 = -3 for XQ4103XL/4036XL/4062XL
01 = -1 for XQ4085XL
Q = QML Certified
N = QML Plastic (N - Grade)
Revision Control
Date
5/98
Version
1.0
Description
Original document release.
1/99
1.1
Addition of new packages, clarification of parameters.
Addition of XQ4085XL -1 speed grade part
2/9/00
1.2
DS029 (v1.2) February 9, 2000
19
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