X9417WV24I-2.7_技术文档

APPLICATION NOTES

A V A I L A B L E

AN99 • AN115 • AN120 • AN124 • AN133 • AN134 • AN135

Low Noise/Low Power/2-Wire Bus

X9417

Dual Digitally Controlled Potentiometers (XDCP^™)

FEATURES

DESCRIPTION

• Two potentiometers in one package

• 2-wire serial interface

• Register oriented format

—Direct Read/Write/Transfer Wiper Position

—Store as many as Four Positions per

Potentiometer

The X9417 integrates two digitally controlled

potentiometers (XDCP) on a monolithic CMOS

integrated microcircuit.

The digitally controlled potentiometer is implemented

using 63 resistive elements in a series array. Between

each element are tap points connected to the wiper

terminal through switches. The position of the wiper on

the array is controlled by the user through the 2-wire

bus interface. Each potentiometer has associated with

it a volatile Wiper Counter Register (WCR) and 4

nonvolatile Data Registers (DR0:DR3) that can be

directly written to and read by the user. The contents

of the WCR controls the position of the wiper on the

resistor array through the switches. Power up recalls

the contents of DR0 to the WCR.

• Power supplies

—V

= 2.7V to 5.5V

CC

—V+ = 2.7V to 5.5V

—V– = –2.7V to –5.5V

• Low power CMOS

—Standby current < 1µA

—Ideal for Battery Operated Applications

• High reliability

—Endurance–100,000 Data Changes per Bit per

Register

—Register Data Retention–100 years

• 8-bytes of nonvolatile memory

• 2.5KΩ, 10KΩ resistor array

• Resolution: 64 taps each potentiometer

• 24-pin plastic DIP, 24-lead TSSOP and 24-lead

SOIC packages

The XDCP can be used as a three-terminal

potentiometer or as a two-terminal variable resistor in

a wide variety of applications including control,

parameter adjustments, and signal processing.

BLOCK DIAGRAM

V

V+

V-

CC

SS

R0 R1

R2 R3

V

/R

H0 H0

Wiper

Counter

Register

(WCR)

V

/R

L0 L0

WP

/R

SCL

W0 W0

SDA

A0

A1

A2

Interface

and

Control

8

Circuitry

V

/R

A3

W1 W1

Data

R0 R1

R2 R3

V

/R

Wiper

Counter

Register

(WCR)

H1 H1

Resistor

Array

XDCP1

V

/R

L1 L1

Characteristics subject to change without notice. 1 of 21

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X9417

PIN DESCRIPTIONS

Host Interface Pins

Serial Clock (SCL)

PIN CONFIGURATION

DIP/SOIC

V+

V

1

24

23

22

21

20

19

18

17

16

5

CC

NC

A0

NC

A3

SCL

NC

R

/V

2

3

L0 L0

The SCL input is used to clock data into and out of the

X9417.

R

H0 H0

/V

R

4

5

W0 W0

A2

Serial Data (SDA)

WP

6

X9417

SDA

7

SDA is a bidirectional pin used to transfer data into

and out of the device. It is an open drain output and

may be wire-ORed with any number of open drain or

open collector outputs. An open drain output requires

the use of a pull-up resistor. For selecting typical

values, refer to the guidelines for calculating typical

values on the bus pull-up resistors graph.

A1

8

R

/V

9

L1 L1

R

/V

10

H1 H1

NC

V-

R

/V

11

12

14

13

W1 W1

V

SS

TSSOP

Device Address (A –A )

0

3

WP

A2

V

SDA

A1

1

2

3

24

23

22

21

20

19

18

17

16

15

14

13

The Address inputs are used to set the least

signiﬁcant 4 bits of the 8-bit slave address. A match in

the slave address serial data stream must be made

with the Address input in order to initiate

communication with the X9417. A maximum of 16

devices may occupy the 2-wire serial bus.

/R

R

/V

W0 W0

L1 L1

V

/R

4

5

R

/V

H0 H0

H1 H1

/R

R

/V

L0 L0

W1 W1

V

6

7

CC

SS

X9417

NC

V+

A0

NC

8

9

Potentiometer Pins

10

V-

SCL

A3

11

12

V /R (V /R —V /R ), V /R (V /R —V /R )

H

H0 H0

H1 H1

L

L0 L0

L1 L1

NC

The V /R and V /R inputs are equivalent to the

H

L

terminal connections on either end of a mechanical

potentiometer.

PIN NAMES

Symbol

V /R (V /R —V /R )

W1 W1

W

W0 W0

Description

The wiper outputs are equivalent to the wiper output of

a mechanical potentiometer.

SCL

Serial Clock

Serial Data

SDA

A0-A3

Hardware Write Protect Input (WP)

Device Address

The WP pin when low prevents nonvolatile writes to

the Data Registers.

V

/R –V /R

,

Potentiometer Pins

(terminal equivalent)

H0 H0 H1 H1

/R –V /R

L0 L0 L1 L1

V

/R –V /R

Potentiometer Pins

(wiper equivalent)

W0 W0 W1 W1

Analog Supplies V+, V-

The Analog Supplies V+, V- are the supply voltages

for the XDCP analog section.

WP

Hardware Write Protection

Analog Supplies

V+,V-

V

System Supply Voltage

System Ground

CC

SS

NC

No Connection

Characteristics subject to change without notice. 2 of 21

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X9417

PRINCIPLES OF OPERATION

The X9417 will respond with an acknowledge after

recognition of a start condition and its slave address

and once again after successful receipt of the

command byte. If the command is followed by a data

byte the X9417 will respond with a ﬁnal acknowledge.

The X9417 is

a

highly integrated microcircuit

incorporating two resistor arrays and their associated

registers and counters and the serial interface logic

providing direct communication between the host and

the XDCP potentiometers.

Array Description

The X9417 is comprised of two resistor arrays. Each

array contains 63 discrete resistive segments that are

connected in series. The physical ends of each array

are equivalent to the ﬁxed terminals of a mechanical

Serial Interface

The X9417 supports a bidirectional bus oriented

protocol. The protocol deﬁnes any device that sends

data onto the bus as a transmitter and the receiving

device as the receiver. The device controlling the

transfer is a master and the device being controlled is

the slave. The master will always initiate data transfers

and provide the clock for both transmit and receive

operations. Therefore, the X9417 will be considered a

slave device in all applications.

potentiometer (V /R and V /R inputs).

H

L

At both ends of each array and between each resistor

segment is a CMOS switch connected to the wiper

(V /R ) output. Within each individual array only one

W

switch may be turned on at a time. These switches are

controlled by the Wiper Counter Register (WCR). The

six bits of the WCR are decoded to select, and enable,

one of sixty-four switches.

Clock and Data Conventions

Data states on the SDA line can change only during

The WCR may be written directly, or it can be changed

by transferring the contents of one of four associated

Data Registers into the WCR. These Data Registers

and the WCR can be read and written by the host

system.

SCL LOW periods (t

). SDA state changes during

LOW

SCL HIGH are reserved for indicating start and stop

conditions.

Start Condition

All commands to the X9417 are preceded by the start

condition, which is a HIGH to LOW transition of SDA

Device Addressing

Following a start condition the master must output the

address of the slave it is accessing. The most

signiﬁcant four bits of the slave address are the device

type identiﬁer (refer to Figure 1 below). For the X9417

this is ﬁxed as 0101[B].

while SCL is HIGH (t

). The X9417 continuously

HIGH

monitors the SDA and SCL lines for the start condition

and will not respond to any command until this

condition is met.

Stop Condition

Figure 1. Slave Address

All communications must be terminated by a stop

condition, which is a LOW to HIGH transition of SDA

while SCL is HIGH.

Device Type

Identifier

Acknowledge

0

1

0

1

A3

A2

A1

A0

Acknowledge is a software convention used to provide

a positive handshake between the master and slave

devices on the bus to indicate the successful receipt of

data. The transmitting device, either the master or the

slave, will release the SDA bus after transmitting eight

bits. The master generates a ninth clock cycle and

during this period the receiver pulls the SDA line LOW

to acknowledge that it successfully received the eight

bits of data.

Device Address

The next four bits of the slave address are the device

address. The physical device address is deﬁned by the

state of the A –A inputs. The X9417 compares the

serial data stream with the address input state; a

successful compare of all four address bits is required

for the X9417 to respond with an acknowledge. The

0

3

A –A inputs can be actively driven by CMOS input

0

3

signals or tied to V or V

.

CC

SS

Characteristics subject to change without notice. 3 of 21

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X9417

Acknowledge Polling

point to one of the two pots and when applicable they

point to one of four associated registers. The format is

shown below in Figure 2.

The disabling of the inputs, during the internal

nonvolatile write operation, can be used to take

advantage of the typical 5ms EEPROM write cycle

time. Once the stop condition is issued to indicate the

end of the nonvolatile write command the X9417

initiates the internal write cycle. ACK polling can be

initiated immediately. This involves issuing the start

condition followed by the device slave address. If the

X9417 is still busy with the write operation no ACK will

be returned. If the X9417 has completed the write

operation an ACK will be returned, and the master can

then proceed with the next operation.

Figure 2. Instruction Byte Format

Register

Select

I3

I2

I1

I0

R1 R0

0

P0

Wiper Counter

Register Select

Instructions

Flow 1. ACK Polling Sequence

The four high order bits deﬁne the instruction. The next

two bits (R1 and R0) select one of the four registers

that is to be acted upon when a register oriented

instruction is issued. The last bits (P0) select which

one of the two potentiometers is to be affected by the

instruction. Bit 1 is deﬁned to be 0.

Nonvolatile Write

Command Completed

Enter ACK Polling

Four of the nine instructions end with the transmission

of the instruction byte. The basic sequence is

illustrated in Figure 3. These two-byte instructions

exchange data between the wiper counter register and

one of the data registers. A transfer from a Data

Register to a Wiper Counter Register is essentially a

write to a static RAM. The response of the wiper to this

Issue

START

Issue Slave

Issue STOP

Address

action will be delayed t

counter register (current wiper position), to a Data

Register is a write to nonvolatile memory and takes a

. A transfer from the wiper

WRL

ACK

Returned?

NO

minimum of t

to complete. The transfer can occur

YES

WR

between one of the two potentiometers and one of its

associated registers; or it may occur globally, wherein

the transfer occurs between both of the potentiometers

and one of their associated registers.

NO

Further

Operation?

YES

Four instructions require a three-byte sequence to

complete. These instructions transfer data between the

host and the X9417; either between the host and one

of the Data Registers or directly between the host and

the wiper counter register. These instructions are:

Read Wiper Counter Register (read the current wiper

position of the selected pot), write Wiper Counter

Register (change current wiper position of the selected

pot), read Data Register (read the contents of the

selected nonvolatile register) and write Data Register

(write a new value to the selected Data Register). The

sequence of operations is shown in Figure 4.

Issue

Instruction

Issue STOP

Proceed

Instruction Structure

The next byte sent to the X9417 contains the instruction

and register pointer information. The four most

signiﬁcant bits are the instruction. The next four bits

Characteristics subject to change without notice. 4 of 21

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X9417

Figure 3. Two-Byte Instruction Sequence

SCL

SDA

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3 I2

I1 I0 R1 R0

0

P0

A

C

K

S

T

O

P

The Increment/Decrement command is different from

the other commands. Once the command is issued and

the X9417 has responded with an acknowledge, the

master can clock the selected wiper up and/or down in

one segment steps; thereby, providing a ﬁne tuning

resistor segment towards the V /R terminal. Similarly,

H H

for each SCL clock pulse while SDA is LOW, the

selected wiper will move one resistor segment towards

the V /R terminal. A detailed illustration of the

L

sequence and timing for this operation are shown in

Figures 5 and 6 respectively.

capability to the host. For each SCL clock pulse (t

)

HIGH

while SDA is HIGH, the selected wiper will move one

Table 1. Instruction Set

Instruction Set

Instruction

Read Wiper Counter

Register

I

R

0

R

0

P

0

P

Operation

1/0 Read the contents of the Wiper Counter Register

pointed to by P

3

2

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Write Wiper Counter

Register

0

1/0 Write new value to the Wiper Counter Register

pointed to by P

0

Read Data Register

1/0 1/0

1/0 Read the contents of the Data Register pointed to

by P and R –R

0

1

0

Write Data Register

1/0 Write new value to the Data Register pointed to by

P and R –R

0

1

0

XFR Data Register to

Wiper Counter Register

1/0 Transfer the contents of the Data Register pointed

to by P and R –R to its associated Wiper Counter

0

1

0

Register

XFR Wiper Counter

Register to Data Register

1

0

1

0

1

0

1

0

1

0

1

0

1/0 1/0

0

1/0 Transfer the contents of the Wiper Counter Register

pointed to by P to the Data Register pointed to by

0

R –R

1

0

Global XFR Data

Registers to Wiper

Counter Registers

0

Transfer the contents of the Data Registers pointed

to by R –R of both pots to their respective Wiper

Counter Registers

1

0

Global XFR Wiper

Counter Registers to

Data Register

Transfer the contents of both Wiper Counter

Registers to their respective data Registers pointed

to by R –R of both pots

1

0

Increment/Decrement

Wiper Counter Register

0

1/0 Enable Increment/decrement of the Wiper Counter

Register pointed to by P

0

Note: (7) 1/0 = data is one or zero

Characteristics subject to change without notice. 5 of 21

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X9417

Figure 4. Three-Byte Instruction Sequence

SCL

SDA

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3 I2

I1 I0 R1 R0 0 P0

A

C

K

0

D5 D4 D3 D2 D1 D0

A

C

K

S

T

O

P

Figure 5. Increment/Decrement Instruction Sequence

SCL

SDA

X

S

T

A

R

T

0

1

0

1

A3 A2 A1 A0

A

C

K

I3 I2

I1 I0 R1 R0

0

P0

A

C

K

I

D

E

C

1

S

T

I

D

N

C

1

N

C

2

N

C

n

E

C

n

O

P

Figure 6. Increment/Decrement Timing Limits

INC/DEC

CMD

Issued

t

WRID

SCL

SDA

Voltage Out

V

/R

W

Characteristics subject to change without notice. 6 of 21

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X9417

Figure 7. Acknowledge Response from Receiver

SCL from

Master

1

8

9

Data Output

from Transmitter

Data Output

from Receiver

START

Acknowledge

Figure 8. Detailed Potentiometer Block Diagram

Serial Data Path

Serial

Bus

Input

V /R

H H

From Interface

Circuitry

C

o

u

n

t

Register 0

Register 2

Register 1

8

6

Parallel

Bus

Input

e

r

Wiper

D

e

c

o

d

e

Register 3

Counter

Register

(WCR)

INC/DEC

Logic

If WCR = 00[H] then V /R = V /R

W

L

UP/DN

If WCR = 3F[H] then V /R = V /R

H

W

H

V /R

Modified SCL

L

CLK

V

/R

W

Characteristics subject to change without notice. 7 of 21

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X9417

DETAILED OPERATION

Register Descriptions

Both XDCP potentiometers share the serial interface

and share a common architecture. Each potentiometer

has a Wiper Counter Register and four Data Registers.

A detailed discussion of the register organization and

array operation follows.

Data Registers, (6-Bit), Nonvolatile

D5

NV

D4

NV

D3

NV

D2

NV

D1

NV

D0

NV

(MSB)

(LSB)

Wiper Counter Register

Four 6-bit Data Registers for each XDCP. (eight 6-bit

registers in total).

The X9417 contains two wiper counter registers, one

for each XDCP potentiometer. The Wiper Counter

Register can be envisioned as a 6-bit parallel and

serial load counter with its outputs decoded to select

one of sixty-four switches along its resistor array. The

contents of the WCR can be altered in four ways: it

may be written directly by the host via the write Wiper

Counter Register instruction (serial load); it may be

written indirectly by transferring the contents of one of

four associated Data Registers via the XFR Data

Register instruction (parallel load); it can be modiﬁed

one step at a time by the Increment/Decrement

instruction. Finally, it is loaded with the contents of its

Data Register zero (DR0) upon power-up.

– {D5~D0}: These bits are for general purpose not

volatile data storage or for storage of up to four

different wiper values.The contents of Data Register

0 are automatically moved to the Wiper Counter

Register on power-up.

Wiper Counter Register, (6-Bit), Volatile

WP5

V

WP4

V

WP3

V

WP2

V

WP1

V

WP0

V

(MSB)

(LSB)

One 6-bit wiper counter register for each XDCP. (Four

6-bit registers in total.)

The WCR is a volatile register; that is, its contents are

lost when the X9417 is powered-down. Although the

register is automatically loaded with the value in DR0

upon power-up, it should be noted this may be

different from the value present at power-down.

– {D5~D0}:These bits specify the wiper position of the

respective XDCP. The Wiper Counter Register is

loaded on power-up by the value in Data Register 0.

The contents of the WCR can be loaded from any of

the other Data Register or directly. The contents of

the WCR can be saved in a DR.

Data Registers

Each potentiometer has four nonvolatile Data

Registers. These can be read or written directly by the

host and data can be transferred between any of the

four Data Registers and the Wiper Counter Register. It

should be noted all operations changing data in one of

these registers is a nonvolatile operation and will take

a maximum of 10ms.

If the application does not require storage of multiple

settings for the potentiometer, these registers can be

used as regular memory locations that could possibly

store system parameters or user preference data.

Characteristics subject to change without notice. 8 of 21

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X9417

Instruction Format

Notes: (1) “MACK”/”SACK”: stands for the acknowledge sent by the master/slave.

(2) “A3 ~ A0”: stands for the device addresses sent by the master.

(3) “X”: indicates that it is a “0” for testing purpose but physically it is a “don’t care” condition.

(4) “I”: stands for the increment operation, SDA held high during active SCL phase (high).

(5) “D”: stands for the decrement operation, SDA held low during active SCL phase (high).

Read Wiper Counter Register (WCR)

S device type

device

addresses

instruction

opcode

WCR

addresses

wiper position

(sent by slave on SDA)

S

A

C

K

S

A

C

K

M S

A T

C O

K P

T

A

R

T

identifier

W W W W W W

0 0 P P P P P P

A A A A

P

0

1

0

1

0

1

0

3

2 1 0

5

4 3 2 1 0

Write Wiper Counter Register (WCR)

S device type

device

addresses

instruction

opcode

WCR

addresses

wiper position

(sent by master on SDA)

S

A

C

K

S

A

C

K

S S

A T

C O

K P

T

A

R

T

identifier

W W W W W W

0 0 P P P P P P

A A A A

P

0

1

0

1

0

1

0

3

2 1 0

5

4 3 2 1 0

Read Data Register (DR)

S device type device

instruction DR and WCR

wiper position/data

(sent by slave on SDA)

S

A

C

K

S

M S

T

A

R

T

identifier

addresses

opcode

addresses

A

C

K

A T

C O

K P

W W W W W W

0 0 P P P P P P

A A A A

R

1

R

0

P

0

1

0

1

0

1

3

2 1 0

5

4 3 2 1 0

Write Data Register (DR)

S device type

device

addresses

instruction DR and WCR

wiper position/data

(sent by master on SDA)

S

S S

T

A

R

T

identifier

opcode

addresses

A

C

K

A

C

K

A T HIGH-VOLTAGE

C O WRITE CYCLE

K P

W W W W W W

0 0 P P P P P P

A A A A

R

1

R

0

1

0

1

0

P0

3

2

1

0

5

4 3 2 1 0

XFR Data Register (DR) to Wiper Counter Register (WCR)

S device type

device

addresses

instruction DR and WCR

S

A

C

K

S S

T

A

R

T

identifier

opcode

addresses

A T

C O

K P

A A A A

R

1

R

0

P

0

1

0

1

0

1

0

3

2

1

0

Characteristics subject to change without notice. 9 of 21

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X9417

XFR Wiper Counter Register (WCR) to Data Register (DR)

S device type

device

addresses

instruction DR and WCR

S

A

C

K

S S

T

A

R

T

identifier

opcode

addresses

A T HIGH-VOLTAGE

C O WRITE CYCLE

K P

A A A A

R

1

R

0

P

0

1

0

1

1 1 1 0

3

2 1 0

Increment/Decrement Wiper Counter Register (WCR)

S

T

A

R

T

device type

identifier

device

addresses

instruction

opcode

WCR

addresses

increment/decrement

(sent by master on SDA)

A

S

A

C

K

S

T

O

P

C

K

A A A A

P

0

I/ I/

D D

I/ I/

D D

0

1

0

1

0

1

0

.

3

2 1 0

Global XFR Data Register (DR) to Wiper Counter Register (WCR)

S

T

A

R

T

device type

identifier

device

addresses

instruction

opcode

DR

addresses

S

A

C

K

S S

A

T

C O

K P

A A A A

R R

1 0

0

1

0

1

0

1

0 0

3

2

1

0

Global XFR Wiper Counter Register (WCR) to Data Register (DR)

S device type

device

addresses

instruction

opcode

DR

addresses

S

A

C

K

S S

A T

C O

K P

T

A

R

T

identifier

HIGH-VOLTAGE

WRITE CYCLE

A A A A

R R

1 0

0

1

0

1

0

0 0

3

2

1

0

SYMBOL TABLE

Guidelines for Calculating Typical Values of Bus

Pull-Up Resistors

WAVEFORM

INPUTS

OUTPUTS

120

V

I

CC MAX

OL MIN

R

=

=1.8KΩ

MIN

Must be

steady

Will be

steady

100

80

t

R

=

MAX

C

BUS

May change

from Low to

High

Will change

from Low to

High

Max.

Resistance

60

40

20

0

May change

from High to

Low

Will change

from High to

Low

Min.

Resistance

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

0

20 40 60 80 100 120

N/A

Center Line

is High

Impedance

Bus Capacitance (pF)

Characteristics subject to change without notice. 10 of 21

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X9417

ABSOLUTE MAXIMUM RATINGS

COMMENT

Temperature under bias....................–65°C to +135°C

Storage temperature.........................–65°C to +150°C

Voltage on SDA, SCL or any address

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only; functional operation of the

device (at these or any other conditions above those

listed in the operational sections of this speciﬁcation) is

not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device

reliability.

input with respect to V ......................... –1V to +7V

SS

Voltage on V+ (referenced to V ) ........................ 10V

SS

Voltage on V- (referenced to V ) ........................ -10V

SS

(V+) – (V-) ............................................................. 12V

Any V /R , V /R , V /R ............................. V- to V+

H

L

W

Lead temperature (soldering, 10 seconds) ........300°C

I

(10 seconds) ................................................. 6mA

W

RECOMMENDED OPERATING CONDITIONS

Temperature

Commercial

Industrial

Min.

0°C

Max.

+70°C

+85°C

Device

X9417

Supply Voltage (V ) Limits

CC

5V 10%

–40°C

X9417-2.7

2.7V to 5.5V

ANALOG CHARACTERISTICS (Over recommended operating conditions unless otherwise stated.)

Limits

Symbol

Parameter

End to end resistance tolerance

Power rating

Min.

Typ.

Max.

+20

50

Unit

%

Test Conditions

25°C, each pot

–20

mW

mA

Ω

I

Wiper current

–3

+3

W

R

Wiper resistance

150

40

250

100

+5.5

-4.5

-2.7

V+

V+, V- = 3V

V+, V- = 5V

W

Ω

V+

V-

Voltage on V+ pin

Voltage on V- pin

X9417

+4.5

+2.7

-5.5

V-

V

X9417-2.7

X9417

V

X9417-2.7

V

Voltage on any V /R , V /R , V /R

V

TERM

H

L

W

Noise

Resolution ⁽⁴⁾

-120

1.6

dBV

%

Ref: 1kHz

See Note 4

(4)

Absolute linearity ⁽¹⁾

Relative linearity ⁽²⁾

–1

+1

MI⁽³⁾

V

—V

w(n)(actual) w(n)(expected)

(4)

–0.2

+0.2

V

—[V

]

w(n + 1)

w(n) + MI

Temperature Coefficient of R

300

ppm/°C See Note 4

20 ppm/°C See Note 4

TOTAL

Ratiometric Temperature Coefficient

Potentiometer Capacitances

C /C /C

10/10/25

0.1

pF

See Circuit #3,

Spice Macromodel

H

L

W

I

R , R , R Leakage Current

10

µA

V

= V– to V+. Device is in

IN

AL

H

L

W

Stand-by mode.

Characteristics subject to change without notice. 11 of 21

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X9417

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol

Parameter

Min.

Typ.

Max.

Unit

Test Conditions

I

V

supply current

1

mA

f = 400kHz, SDA = Open,

SCL

Other Inputs = V

SS

CC1

CC

(nonvolatile write)

I

V

supply current

100

µA

f

= 400kHz, SDA = Open,

SCL

CC2

CC

(move wiper, write, read)

Other Inputs = V

SS

I

V

current (standby)

1

µA

V

SCL = SDA = V , Addr. = V

CC SS

SB

CC

I

Input leakage current

Output leakage current

Input HIGH voltage

Input LOW voltage

Output LOW voltage

10

V

= V to V

SS CC

LI

IN

I

= V to V

SS CC

LO

OUT

V

x 0.7

V

+ 0.5

IH

CC

V

–0.5

V

x 0.1

CC

V

IL

V

0.4

V

I

= 3mA

OL

Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used

as a potentiometer.

(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-

ometer. It is a measure of the error in step size.

(3) MI = RTOT/63 or (R —R )/63, single pot

H

L

ENDURANCE AND DATA RETENTION

Parameter

Minimum endurance

Data retention

Min.

100,000

100

Unit

Data changes per bit per register

Years

CAPACITANCE

Symbol

Test

Max.

Unit

pF

Test Conditions

(4)

C

Input/output capacitance (SDA)

8

6

V

= 0V

I/O

(4)

C

Input capacitance (A0, A1, A2, A3, and SCL)

pF

V

IN

POWER-UP TIMING

Symbol

Parameter

Min.

Typ.

Max.

1

Unit

(5)

t

Power-up to initiation of read operation

Power-up to initiation of write operation

ms

PUR

(5)

t

5

PUW

(6)

t V

V Power up ramp rate

CC

0.2

50

V/msec

R

CC

Power Up Requirements (Power up sequencing can affect correct recall of the wiper registers)

The preferred power-on sequence is as follows: First V , then V+ and V–, and then the potentiometer pins, R ,

CC

H

R , and R . Voltage should not be applied to the potentiometer pins before V+ or V– is applied. The V ramp rate

L

W

CC

speciﬁcation should be met, and any glitches or slope changes in the V

line should be held to <100mV if possi-

CC

ble. Also, V should not reverse polarity by more than 0.5V. Recall of wiper position will not be complete until V

,

CC

V+ and V– reach their ﬁnal value.

Notes: (4) This parameter is periodically sampled and not 100% tested

(5) t

and t

are the delays required from the time the third (last) power supply (V , V+ or V-) is stable until the speciﬁc

PUR

PUW CC

instruction can be issued.These parameters are periodically sampled and not 100% tested.

(6) This is not guaranteed or tested parameter and should only be used as a guidance.

Characteristics subject to change without notice. 12 of 21

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X9417

A.C. TEST CONDITIONS

Circuit #3 SPICE Macro Model

Input pulse levels

V

x 0.1 to V x 0.9

CC

R

TOTAL

Input rise and fall times

Input and output timing level

10ns

R

L

H

C

V

x 0.5

L

CC

C

H

C

W

10pF

EQUIVALENT A.C. LOAD CIRCUIT

10pF

25pF

5V

2.7V

R

W

1533Ω

SDA Output

100pF

AC TIMING (over recommended operating conditions)

Symbol Parameter

Min.

Max.

Unit

kHz

ns

f

Clock frequency

400

SCL

t

Clock cycle time

2500

600

1300

600

100

30

CYC

t

Clock high time

HIGH

t

Clock low time

LOW

t

Start setup time

SU:STA

HD:STA

SU:STO

t

Start hold time

t

Stop setup time

t

SDA data input setup time

SDA data input hold time

SCL and SDA rise time

SCL and SDA fall time

SU:DAT

HD:DAT

t

300

900

R

t

F

t

SCL low to SDA data output valid time

SDA data output hold time

5

50

1300

0

AA

t

DH

T

Noise suppression time constant at SCL and SDA inputs

Bus free time (prior to any transmission)

WP, A0, A1, A2 and A3 setup time

I

t

BUF

t

SU:WPA

HD:WPA

t

WP, A0, A1, A2 and A3 hold time

0

Characteristics subject to change without notice. 13 of 21

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X9417

HIGH-VOLTAGE WRITE CYCLE TIMING

Symbol

Parameter

Typ.

Max.

Unit

t

High-voltage write cycle time (store instructions)

5

10

ms

WR

XDCP TIMING

Symbol

Parameter

Min. Max. Unit

t

Wiper response time after the third (last) power supply is stable

Wiper response time after instruction issued (all load instructions)

10

µs

WRPO

t

WRL

t

Wiper response time from an active SCL/SCK edge (increment/decrement instruction)

WRID

Note: (8) A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undeﬁned region of the falling

edge of SCL.

TIMING DIAGRAMS

START and STOP Timing

g

(START)

(STOP)

t

F

R

SCL

SDA

t

SU:STO

SU:STA

HD:STA

t

F

R

Input Timing

t

CYC

HIGH

SCL

SDA

t

LOW

t

BUF

SU:DAT

HD:DAT

Output Timing

SCL

SDA

t

DH

AA

Characteristics subject to change without notice. 14 of 21

REV 1.1.4 7/22/02

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X9417

XDCP Timing (for All Load Instructions)

(STOP)

SCL

SDA

LSB

t

WRL

V

/R

W

XDCP Timing (for Increment/Decrement Instruction)

SCL

Wiper Register Address

Inc/Dec

SDA

t

WRID

V

/R

W

Write Protect and Device Address Pins Timing

(START)

(STOP)

SCL

...

(Any Instruction)

...

SDA

...

t

SU:WPA

HD:WPA

WP

A0, A1

A2, A3

Characteristics subject to change without notice. 15 of 21

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X9417

APPLICATIONS INFORMATION

Basic Configurations of Electronic Potentiometers

+V

R

V

R

V

/R

W

I

Three terminal Potentiometer;

Variable voltage divider

Two terminal Variable Resistor;

Variable current

Application Circuits

Noninverting Amplifier

Voltage Regulator

V

+

–

S

V

V (REG)

O

317

O

IN

R

1

R

2

I

adj

R

1

2

V

= (1+R /R )V

V

(REG) = 1.25V (1+R /R )+I

R

adj

O

2

1

S

O

2

1

2

Offset Voltage Adjustment

Comparator with Hysteresis

R

2

1

V

–

+

S

V

S

O

100KΩ

–

+

V

O

TL072

R

1

2

10KΩ

+12V

V

= {R /(R +R )} V (max)

1 1 2 O

UL

LL

10KΩ

-12V

= {R /(R +R )} V (min)

1

2

O

Characteristics subject to change without notice. 16 of 21

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X9417

Application Circuits (continued)

Attenuator

Filter

C

V

+

–

S

R

V

R

1

2

O

–

R

V

O

V

+

S

R

3

R

2

R

4

All R = 10kΩ

S

R

1

G

= 1 + R /R

2 1

V

= G V

S

O

fc = 1/(2pRC)

-1/2 ≤ G ≤ +1/2

Inverting Amplifier

Equivalent L-R Circuit

R

2

1

V

S

R

2

C

1

–

+

V

+

–

S

V

O

R

1

3

Z

IN

V = G V

O

S

G = - R /R

2

1

Z

= R + s R (R + R ) C = R + s Leq

2 2 1 3 1 2

IN

(R + R ) >> R

1

3

2

Function Generator

C

R

1

2

–

+

R

}

A

B

frequency ∝ R , R , C

1

2

amplitude ∝ R , R

A

B

Characteristics subject to change without notice. 17 of 21

REV 1.1.4 7/22/02

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X9417

PACKAGING INFORMATION

24-Lead Plastic Dual In-Line Package Type P

1.265 (32.13)

1.230 (31.24)

0.557 (14.15)

0.530 (13.46)

Pin 1 Index

Pin 1

0.080 (2.03)

0.065 (1.65)

1.100 (27.94)

Ref.

0.162 (4.11)

0.140 (3.56)

Seating

Plane

0.030 (0.76)

0.015 (0.38)

0.150 (3.81)

0.125 (3.18)

0.110 (2.79)

0.090 (2.29)

0.065 (1.65)

0.040 (1.02)

0.022 (0.56)

0.014 (0.36)

0.625 (15.87)

0.600 (15.24)

0°

15°

Typ. 0.010 (0.25)

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

Characteristics subject to change without notice. 18 of 21

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X9417

PACKAGING INFORMATION

24-Lead Plastic Small Outline Gull Wing Package Type S

0.393 (10.00)

0.290 (7.37)

0.299 (7.60)

0.420 (10.65)

Pin 1 Index

Pin 1

0.014 (0.35)

0.020 (0.50)

0.598 (15.20)

0.610 (15.49)

(4X) 7°

0.092 (2.35)

0.105 (2.65)

0.003 (0.10)

0.012 (0.30)

0.050 (1.27)

0.050"Typical

0.010 (0.25)

0.020 (0.50)

X 45°

0.050"

Typical

0° – 8°

0.009 (0.22)

0.013 (0.33)

0.420"

0.015 (0.40)

0.050 (1.27)

0.030" Typical

24 Places

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

Characteristics subject to change without notice. 19 of 21

REV 1.1.4 7/22/02

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X9417

PACKAGING INFORMATION

24-Lead Plastic, TSSOP Package Type V

.026 (.65) BSC

.169 (4.3)

.177 (4.5)

.252 (6.4) BSC

.303 (7.70)

.311 (7.90)

.047 (1.20)

.0075 (.19)

.0118 (.30)

.002 (.06)

.005 (.15)

.010 (.25)

Gage Plane

(7.72)

(4.16)

0°–8°

Seating Plane

.020 (.50)

.030 (.75)

(1.78)

(0.42)

Detail A (20X)

(0.65)

ALL MEASUREMENTS ARE TYPICAL

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

Characteristics subject to change without notice. 20 of 21

REV 1.1.4 7/22/02

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X9417

Ordering Information

X9417

Y

P

T

V

Limits

CC

Device

Blank = 5V 10%

–2.7 = 2.7 to 5.5V

Temperature Range

Blank = Commercial = 0°C to +70°C

I = Industrial = –40°C to +85°C

Package

P24 = 24-Lead Plastic DIP

S24 = 24-Lead SOIC

V24 = 24-Lead TSSOP

Potentiometer Organization

Pot 0 Pot 1

W =

Y =

10KΩ 10KΩ

2.5KΩ 2.5KΩ

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemniﬁcation provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,

express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.

Xicor, Inc. makes no warranty of merchantability or ﬁtness for any purpose. Xicor, Inc. reserves the right to discontinue production and change speciﬁcations and prices

at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.

TRADEMARK DISCLAIMER:

Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All

others belong to their respective owners.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;

4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;

5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection

and correction, redundancy and back-up features to prevent such an occurrence.

Xicor’s products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to

perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a signiﬁcant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life

support device or system, or to affect its safety or effectiveness.

Characteristics subject to change without notice. 21 of 21

REV 1.1.4 7/22/02

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型号：	X9417WV24I-2.7
厂家：	XICOR INC.
描述：	Digital Potentiometer, 2 Func, 10000ohm, 2-wire Serial Control Interface, 64 Positions, CMOS, PDSO24, PLASTIC, TSSOP-24 光电二极管转换器电阻器
文件：	总21页 (文件大小：385K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

X9417WV24I-2.7 [XICOR]

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