X9252WV24I-2.7 [XICOR]
Quad Digitally-Controlled (XDCP) potentiometer; 四路数字控制（ XDCP ）电位计
| 型号： | X9252WV24I-2.7 |
| 厂家： | 
XICOR INC. |
| 描述： | Quad Digitally-Controlled (XDCP) potentiometer |
| 文件： | 总21页 (文件大小：126K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
New Feature
Low Power + Quad 256-tap +
2-Wire bus + Up/Down interface
Dual Interface
Quad Digitally-Controlled (XDCPTM) Potentiometer X9252
FEATURES
DESCRIPTION
• Quad solid state potentiometer
The X9252 integrates 4 digitally controlled potentio-
meters (XDCP) on a monolithic CMOS integrated
circuit.
• 256 wiper tap points–0.4% resolution
• 2-wire serial interface for Write, Read, and
transfer operations of the potentiometer
• Up/down interface for individual potentiometers
• Wiper resistance: 40Ω typical
• Non-volatile storage of wiper positions
• Power On Recall. Loads saved wiper position on
Power-Up.
The digitally controlled potentiometers are imple-
mented using 255 resistive elements in a series array.
Between each pair of elements are tap points con-
nected to wiper terminals through switches. The posi-
tion of each wiper on the array is controlled by the user
through the Up/Down (U/D) or 2-wire bus interface.
The wiper of each potentiometer has an associated
volatile Wiper Counter Register (WCR) and four non-
volatile Data Registers (DRs) that can be directly writ-
ten to and read by the user. The contents of the WCR
controls the position of the wiper on the resistor array
though the switches. At power-up, the device recalls
the contents of the default data registers DR00, DR10,
DR20, DR30, to the corresponding WCR.
• Standby current < 20µA Max
• Maximum wiper current: 3mA
• V : 2.7V to 5.5V operation
CC
• 2.8kΩ,10kΩ, 50kΩ, 100kΩ version of total pot
resistance
• Endurance: 100, 000 data changes per bit per
register
• 100 yr. data retention
• 24-Lead TSSOP
Each DCP can be used as a three-terminal potentio-
meter or as a two terminal variable resistor in a wide
variety of applications including the programming of
bias voltages, the implementation of ladder networks,
and three resistor programmable networks.
FUNCTIONAL DIAGRAM
R
R
H3
R
R
V
H1
H2
H0
CC
A2
2-Wire
Interface
A1
A0
DCP1
DCP3
DCP2
DCP0
WCR1
DR10
WCR3
DR30
WCR2
DR20
WCR0
DR00
DR11
DR12
DR13
DR31
DR32
DR33
DR21
DR22
DR23
DR01
DR02
DR03
POWER UP,
INTERFACE
CONTROL
AND
SDA
SCL
STATUS
Up-Down
Interface
DS0
DS1
CS
U/D
V
R
R
L3
R
R
SS
R
R
R
W3
WP
R
W0
L1
L2
L0
W1
W2
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X9252
PIN CONFIGURATION
TSSOP
24
23
22
DS1
SCL
DS0
A0
1
2
3
4
5
6
R
R
L2
W3
21
20
19
18
17
16
R
R
H2
H3
R
R
W2
L3
CS
U/D
X9252
V
V
SS
CC
7
8
R
R
W1
L0
R
9
R
H1
H0
10
R
R
L1
W0
15
14
13
A1
11
12
A2
SDA
WP
ORDERING INFO
Ordering Number
X9252YV24-2.7
X9252YV24I-2.7
X9252WV24-2.7
X9252WV24I-2.7
X9252UV24-2.7
X9252UV24I-2.7
X9252TV24-2.7
X9252TV24I-2.7
RTOTAL
Package
Operating Temperature Range
0°C to 70°C
2.8kΩ
2.8kΩ
10kΩ
10kΩ
50kΩ
50kΩ
100kΩ
100kΩ
24-lead TSSOP
24-lead TSSOP
24-lead TSSOP
24-lead TSSOP
24-lead TSSOP
24-lead TSSOP
24-lead TSSOP
24-lead TSSOP
-40°C to +85°C
0°C to 70°C
-40°C to +85°C
0°C to 70°C
-40°C to +85°C
0°C to 70°C
-40°C to +85°C
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X9252
PIN ASSIGNMENTS
TSSOP pin
Symbol
DS0
A0
Brief Description
DCP select for Up/Down interface.
1
2
Device Address for 2-wire bus.
Wiper terminal of DCP3.
High terminal of DCP3.
3
RW3
RH3
RL3
U/D
4
5
Low terminal of DCP3.
6
Increment/Decrement for Up/Down interface.
System Supply Voltage
7
VCC
RL0
RH0
RW0
A2
8
Low terminal of DCP0.
9
High terminal of DCP0.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Wiper terminal of DCP0.
Device Address for 2-wire bus.
Hardware Write Protect
WP
SDA
A1
Serial Data Input/Output for 2-wire bus.
Device Address for 2-wire bus.
Low terminal of DCP1.
RL1
RH1
RW1
VSS
CS
High terminal of DCP1.
Wiper terminal DCP1.
System ground
Chip select for Up/Down interface.
Wiper terminal of DCP2.
High terminal of DCP2.
RW2
RH2
RL2
SCL
DS1
Low terminal of DCP2.
Serial Clock for 2-wire bus.
DCP select for Up/Down interface.
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X9252
ABSOLUTE MAXIMUM RATINGS
COMMENT
Junction Temperature under bias ......–65°C to +135°C
Storage temperature .........................–65°C to +150°C
Voltage at any digital interface pin
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; the functional operation of
the device (at these or any other conditions above
those listed in the operational sections of this specifica-
tion) is not implied. Exposure to absolute maximum rat-
ing conditions for extended periods may affect device
reliability.
with respect to V ..................................–1V to +7V
SS
V
............................................................–1V to +7V
CC
Voltage at any DCP pin with
respect to V ..........................................-1V to V
SS
CC
Lead temperature (soldering, 10 seconds).........300°C
I
(10 seconds) ................................................. 6mA
W
RECOMMENDED OPERATING CONDITIONS
Temp
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Device
Supply Voltage (V
)
(4) Limits
CC
X9252
2.7V to 5.5V
–40°C
ANALOG CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Limits
Symbol
Parameter
Min. Typ.(4) Max. Unit
Test Conditions
R
End to end resistance
2.8, 10,
50, 100
kΩ
Y, W, U, T versions respectively
TOTAL
End to end resistance tolerance -20
Power rating
+20
50
%
mW
%
25°C, each DCP
R
DCP to DCP resistance
matching
0.75
50
2.0
TOTAL
Matching
(5)
I
Wiper current
-3.0
Vss
+3.0
150
mA
See test circuit
W
R
Wiper resistance
Ω
W
V
CC
Wiper current =
Ref: 1kHz
R
TOTAL
V
Voltage on any DCP pin
Noise(5)
Vcc
V
dBV
%
TERM
-120
0.4
Resolution
Absolute linearity(1)
Relative linearity(2)
–1
+1
MI(3)
MI(3)
ppm/°C
–0.3
+0.3
V(R )=V(R )=V(R )=V(R )=V
CC
Temperature coefficient of
resistance(5)
300
H0
L0
H1
L1
H2
L2
H3
L3
V(R )=V(R )=V(R )=V(R )=V
SS
Ratiometric Temperature(5)
Coefficient
–20
+20 ppm/°C
C /C /C
Potentiometer Capacitance(5)
10/10/25
0.1
pF
See equivalent circuit
Voltage at pin from V to V
CC
H
L
W
I
Leakage on DCP pins
10
µA
OL
SS
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X9252
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Max.
3
Symbol
Parameter
supply current
(Volatile write/read)
Min.
Units
mA
Test Conditions
f = 400kHz;SDA = Open; (for 2-Wire,
Active, Read and Volatile Write States
only)
I
V
CC1
CC
SCL
I
I
V
supply current
3
5
mA
mA
f
= 200kHz; (for U/D interface,
CC2
CC
SCL
(active)
increment, decrement)
V
supply current
f
SCL
= 400kHz; SDA = Open;
CC3
CC
(nonvolatile write)
(for 2-Wire, Active, Nonvolatile Write State
only)
I
I
V
current (standby)
20
10
µA
µA
V
V
= +5.5V; V = V or V ; SDA =
IN SS CC
SB
CC
CC
CC
; (for 2-Wire, Standby State only)
Leakage current, bus
interface pins
-10
Voltage at pin from V to V
SS CC
L
V
V
V
Input HIGH voltage
Input LOW voltage
V
x 0.7
V + 1
CC
V
V
V
IH
IL
CC
–1
V
x 0.3
CC
SDA pin output LOW
voltage
0.4
I
= 3mA
OL
OL
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Units
Data changes per bit
Years
CAPACITANCE
Symbol
Test
Input / Output capacitance (SDA)
Max.
8
6
Units
pF
Test Conditions
(5)
C
C
V
= 0V
OUT
IN/OUT
(5)
IN
Input capacitance (SCL, WP, DS0, DS1, CS, U/D,
A2, A1 and A0)
pF
V
= 0V
IN
POWER-UP TIMING
Symbol
(5)(9)
Parameter
Power Up Delay from V power up (V
CC
Max.
2
Units
ms
t
D
CC
above 2.7V) to wiper position recall com-
pleted, and communication interfaces ready
for operation.
A.C. TEST CONDITIONS
Input Pulse Levels
V
x 0.1 to V x 0.9
CC
CC
Input rise and fall times
10ns
Input and output timing threshold level
External load at pin SDA
V
x 0.5
CC
2.3kΩ to V and 100 pF to V
CC
SS
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X9252
2-WIRE INTERFACE TIMING(S)
Symbol
Parameter
Min.
Max.
Units
kHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Clock Frequency
Clock High Time
Clock Low Time
400
SCL
600
1300
600
600
600
100
30
HIGH
ns
LOW
Start Condition Setup Time
ns
SU:STA
HD:STA
SU:STO
SU:DAT
HD:DAT
Start Condition Hold Time
ns
Stop Condition Setup Time
ns
SDA Data Input Setup Time
ns
SDA Data Input Hold Time
ns
(5)
SCL and SDA Rise Time
300
300
0.9
ns
R
(5)
F
SCL and SDA Fall Time
ns
(5)
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
µs
AA
0
ns
DH
(5)
Pulse Width Suppression Time at SCL and SDA inputs
Bus Free Time (Prior to Any Transmission)
A0, A1, A2 and WP Setup Time
A0, A1, A2 and WP Hold Time
50
ns
IN
(5)
1200
600
ns
BUF
(5)
(5)
ns
SU:WPA
600
ns
HD:WPA
SDA vs. SCL Timing
t
t
t
t
R
F
HIGH
LOW
SCL
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
SDA
(Input Timing)
t
t
t
BUF
AA
DH
SDA
(Output Timing)
WP, A0, A1, and A2 Pin Timing
STOP
START
SCL
Clk 1
SDA IN
t
t
HD:WP
SU:WP
WP, A0, A1, or A2
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X9252
INCREMENT/DECREMENT TIMING
Limits
Typ.(4)
Units
Symbol
Parameter
Min.
600
600
600
2.5
2.5
1
Max.
t
t
t
t
t
t
CS to SCL Setup
ns
ns
ns
µs
µs
µs
CI
(5)
SCL HIGH to U/D, DS0 or DS1 change
U/D, DS0 or DS1 to SCL setup
SCL LOW period
ID
DI
IL
(5)
SCL HIGH period
IH
IC
SCL inactive to CS inactive (Nonvolatile Store
Setup Time)
t
t
t
t
CS deselect time (STORE)
10
1
ms
µs
µs
µs
µs
CPHS
(5)
CS deselect time (NO STORE)
CPHNS
(5)
SCL to R change
W
100
500
500
IW
SCL cycle time
5
CYC
(5)
t , t
SCL input rise and fall time
R
F
Increment/Decrement Timing
CS
t
CYC
t
CPHNS
t
t
t
t
t
CPHS
CI
IL
IH
IC
90% 90%
10%
SCL
t
t
t
t
R
ID
DI
F
U/D
DS0, DS1
t
IW
(3)
MI
R
W
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X9252
HIGH-VOLTAGE WRITE CYCLE TIMING
Symbol
Parameter
Non-volatile write cycle time
Typ.
Max.
Units
(8)(5)
t
5
10
ms
WC
XDCP TIMING
Symbol
Parameter
Min.
Max.
Units
(5)
t
SCL rising edge to wiper code changed, wiper response time after
instruction issued (all load instructions)
5
20
µs
WRL
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [V(R
)–V(R
)]/MI
W(n)(expected)
W(n)(actual)
V(R
) = n(V(R )-V(R ))/255 + V(R ), with n from 0 to 255.
W(n)(expected)
H L L
(2) Relative linearity is a measure of the error in step size between taps = [V(R
)–(V(R
) + MI)]/MI , with n from 0 to 254
W(n+1)
W(n)
(3) 1 Ml = Minimum Increment = [V(R )–V(R )]/255.
H
L
(4) Typical values are for T = 25°C and nominal supply voltage.
A
(5) This parameter is not 100% tested.
(6) Ratiometric temperature coefficient = (V(R
n from 0 to 255.
)
–V(R
)
)/[V(R
)
(T1–T2)] x 106, with T1 & T2 being 2 temperatures, and
W T1(n)
W T1(n)
W T2(n)
(7) Measured with wiper at tap position 255, R grounded, using test circuit.
L
(8) t
is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used. It is the time
WC
from a valid STOP condition at the end of a write sequence of a 2-wire interface write operation, or from the rising edge of CS of a
valid “Store” operation of the Up/Down interface, to the end of the self-timed internal nonvolatile write cycle.
(9) The recommended power up sequence is to apply V /V first, then the potentiometer voltages. During power up, the data sheet
CC SS
parameters for the DCP do not fully apply until t after V
reaches its final value. In order to prevent unwanted tap position
D
CC
changes, or an inadvertant store, bring the CS pin high before or concurrently with the V pin on power up.
CC
Test Circuit
Equivalent Circuit
R
TOTAL
Test Point
R
R
L
H
C
W
C
C
L
H
R
W
Force
Current
R
W
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X9252
PIN DESCRIPTIONS
UP OR DOWN CONTROL (U/D)
The U/D input pin is held HIGH during increment oper-
ations and held LOW during decrement operations.
Bus Interface Pins
SERIAL DATA INPUT/OUTPUT (SDA)
DCP SELECT (DS1-DS0)
The SDA is a bidirectional serial data input/output pin for
the 2-wire interface. It receives device address, operation
code, wiper register address and data from a 2-wire
external master device at the rising edge of the serial
clock SCL, and it shifts out data after each falling edge of
the serial clock SCL.
The DS1-DS0 select one of the four DCPs for an Up/
Down interface operation.
HARDWARE WRITE PROTECT INPUT (WP)
When the WP pin is set low, “write” operations to non
volatile DCP Data Registers are disabled. This
includes both 2-wire interface non-volatile “Write”, and
Up/Down interface “Store” operations.
SDA requires an external pull-up resistor, since it’s an
open drain output.
SERIAL CLOCK (SCL)
DCP Pins
This input is the serial clock of the 2-wire and Up/Down
interface.
R
, R , R , R , R , R , R , AND R
L0 H1 L1 H2 L2 H3 L3
H0
These pins are equivalent to the terminal connections
on mechanical potentiometers. Since there are 4
DCPs, there is one set of R and R for each DCP.
DEVICE ADDRESS (A2–A0)
The Address inputs are used to set the least significant
3 bits of the 8-bit 2-wire interface slave address. A
match in the slave address serial data stream must be
made with the Address input pins in order to initiate
communication with the X9252. A maximum of 8
devices may occupy the 2-wire serial bus.
H
L
R
, R , R , AND R
W1 W2 W3
W0
The wiper pins are equivalent to the wiper terminal of
mechanical potentiometers. Since there are four
DCPs, there are 4 R pins.
W
CHIP SELECT (CS)
When the CS pin is low, increment or decrement
operations are possible using the SCL and U/D pins.
The 2-wire interface is disabled at this time. When CS
is high, the 2-wire interface is enabled.
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X9252
PRINCIPLES OF OPERATION
Within each individual array only one switch may be
turned on at a time.
The X9252 is an integrated circuit incorporating four
resistor arrays, their associated registers and counters,
and the serial interface logic providing direct communi-
cation between the host and the digitally controlled
potentiometers. This section provides detail description
of the following:
These switches are controlled by a Wiper Counter
Register (WCR). The 8-bits of the WCR (WCR[7:0])
are decoded to select and enable one of 256 switches
(see Table 1). Note that each wiper has a dedicated
WCR. When all bits of a WCR are zeroes, the switch
closest to the corresponding R pin is selected. When
all bits of a WCR are ones, the switch closest to the
L
– Resistor Array
– Up/Down Interface
– 2-wire Interface
corresponding R pin is selected.
H
The WCR is volatile and may be written directly. There
are four non-volatile Data Registers(DR) associated
with each WCR. Each DR can be loaded into WCR. All
DRs and WCRs can be read or written.
Resistor Array Description
The X9252 is comprised of four resistor arrays. Each
array contains 255 discrete resistive segments that are
connected in series. The physical ends of each array
are equivalent to the fixed terminals of a mechanical
Power Up and Down Requirements
During power up, CS must be high, to avoid inadvert-
ant “store” operations. At power up, the contents of
Data Registers DR00, DR10, DR20, and DR30, are
loaded into the corresponding wiper counter register.
potentiometer (R and R inputs). (See Figure 1.)
Hi
Li
At both ends of each array and between each resistor
segment is a switch connected to the wiper (R ) pin.
Wi
Figure 1. Detailed Block Diagram of one DCP
i = 0, 1, 2, and 3
255
254
WCR[7:0]
= FF hex
R
Hi
Four
Volatile
Non-Volatile
8-bit
Data
Wiper
Registers
Counter
DRi0, DRi1,
Register
DRi2, and
WCRi
253
252
DRi3
One
of
256
Decoder
WP
SCL
SDA
A2, A1, A0
CS
Interface Control and
Volatile Status Register (SR)
2
1
0
(Shared by the Four DCPs)
U/D
DS1, DS0
WCR[7:0]
= 00 hex
R
R
Li
Wi
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X9252
UP/DOWN INTERFACE OPERATION
The state of U/D may be changed while CS remains
LOW. This allows the host system to enable the device
and then move the wiper up and down until the proper
trim is attained. The 2-wire interface is disabled while
CS remains LOW.
The SCL, U/D, CS, DS0 and DS1 inputs control the
movement of the wiper along the resistor array. With
CS set LOW the device is selected and enabled to
respond to the U/D and SCL inputs. HIGH to LOW
transitions on SCL will increment or decrement
(depending on the state of the U/D input) a wiper
counter register selected by DS0 and DS1. The output
of this counter is decoded to select one of 256 wiper
positions along the resistor array.
Table 1. DCP Selection for Up/Down Control
DS1
DS0
Selected DCP
DCP0
0
0
1
1
0
1
0
1
DCP1
The value of the counter is stored in nonvolatile Data
Registers DRi0 whenever CS transitions HIGH while
the SCL and WP inputs are HIGH. “i” indicates the
DCP number selected with pins DS1 and DS0. During
a “Store” operation bits DRSel1 and DRSel0 in the
Status Register must be both “0”, which is their power
up default value. Other combinations are reserved and
must not be used.
DCP2
DCP3
MODE SELECTION FOR UP/DOWN CONTROL
CS
SCL U/D
Mode
The system may select the X9252, move the wiper,
and deselect the device without having to store the lat-
est wiper position in nonvolatile memory. After the
wiper movement is performed as described above and
once the new position is reached, the system must
keep SCL LOW while taking CS HIGH. The new wiper
postion will be maintained until changed by the system
or until a power-down/up cycle recalled the previousely
stored data.
L
H
Wiper Up
L
L
Wiper Down
H
X
Store Wiper Position to non-
volatile memory if WP pin is
high. No store, return to stand-
by, if WP pin is low.
H
X
L
L
L
X
X
H
L
Standby
No Store, Return to Standby
Wiper Up (not recommended)
This procedure allows the system to always power-up
to a preset value stored in nonvolatile memory; then
during system operation minor adjustments could be
made. The adjustments might be based on user prefer-
ence, system parameter changes due to temperaure
drift, etc.
Wiper Down
(not recommended)
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X9252
2-WIRE SERIAL INTERFACE
Protocol Overview
Serial Clock and Data
Data states on the SDA line can change only while
SCL is LOW. SDA state changes while SCL is HIGH
are reserved for indicating START and STOP
conditions. See Figure 2. On power up of the X9252,
the SDA pin is in the input mode.
The device supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter, and the receiving
device as the receiver. The device controlling the
transfer is called the master and the device being
controlled is called the slave. The master always
initiates data transfers, and provides the clock for both
transmit and receive operations. The X9252 operates
as a slave in all applications.
Serial Start Condition
All commands are preceded by the START condition,
which is a HIGH to LOW transition of SDA while SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the START condition and does not
respond to any command until this condition has been
met. See Figure 2.
All 2-wire interface operations must begin with a
START, followed by a Slave Address byte. The Slave
Address selects the X9252, and specifies if a Read or
Write operation is to be performed.
Serial Stop Condition
All communications must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA
while SCL is HIGH.The STOP condition is also used to
place the device into the Standby power mode after a
read sequence. A STOP condition can only be issued
after the transmitting device has released the bus. See
Figure 2.
All Communication over the 2-wire interface is
conducted by sending the MSB of each byte of data
first.
Figure 2. Valid Data Changes, Start, and Stop Conditions
SCL
SDA
START
DATA
DATA
DATA
STOP
STABLE CHANGE STABLE
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X9252
Serial Acknowledge
If a write operation is selected, the device responds
with an ACK after the receipt of each subsequent
eight-bit word.
An ACK (Acknowledge), is a software convention used
to indicate a successful data transfer. The transmitting
device, either master or slave, releases the bus after
transmitting eight bits. During the ninth clock cycle, the
receiver pulls the SDA line LOW to acknowledge the
reception of the eight bits of data. See Figure 3.
In the read mode, the device transmits eight bits of
data, releases the SDA line, and then monitors the line
for an ACK. The device continues transmitting data if
an ACK is detected. The device terminates further data
transmissions if an ACK is not detected. The master
must then issue a STOP condition to place the device
into a known state.
The device responds with an ACK after recognition of a
START condition followed by a valid Slave Address
byte. A valid Slave Address byte must contain the
Device Type Identifier 0101, and the Device Address
bits matching the logic state of pins A2, A1, and A0.
See Figure 4.
Figure 3. Acknowledge Response From Receiver
SCL from
Master
1
8
9
SDA Output from
Transmitter
SDA Output from
Receiver
START
ACK
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X9252
Slave Address Byte
then no ACK is returned. If the high voltage cycle is
completed, an ACK is returned and the master can
then proceed with a new Read or Write operation.
(Refer to figure 5.)
Following a START condition, the master must output a
Slave Address Byte (Refer to figure 4.). This byte
includes three parts:
– The four MSBs (SA7-SA4) are the Device Type
Identifier, which must always be set to 0101 in order
to select the X9252.
Figure 5. Acknowledge Polling Sequence
Byte load completed by issuing
STOP. Enter ACK Polling
– The next three bits (SA3-SA1) are the Device
Address bits (AS2-AS0). To access any part of the
X9252’s memory, the value of bits AS2, AS1, and
AS0 must correspond to the logic levels at pins A2,
A1, and A0 respectively.
Issue START
– The LSB (SA0) is the R/W bit. This bit defines the
operation to be performed on the device being
addressed. When the R/W bit is “1”, then a Read
operation is selected. A “0” selects a Write operation.
Issue STOP
Issue Slave Address
Byte (Read or Write)
Figure 4. Slave Address (SA) Format
NO
ACK returned?
YES
SA7 SA6
SA3 SA2
SA5 SA4
SA1
SA0
0
1
0
1
AS2 AS1 AS0 R/W
High Voltage
complete. Continue command
sequence.
NO
Device Type
Identifier
Device
Address
Read or
Write
Slave Address
Bit(s)
YES
Issue STOP
Description
Continue normal Read or Write
command sequence
SA7–SA4
SA3–SA1
SA0
Device Type Identifier
Device Address
Read or Write Operation Select
PROCEED
Nonvolatile Write Acknowledge Polling
After a nonvolatile write command sequence is
correctly issued (including the final STOP condition),
the X9252 initiates an internal high voltage write cycle.
This cycle typically requires 5 ms. During this time, any
Read or Write command is ignored by the X9252.
Write Acknowledge Polling is used to determine
whether a high voltage write cycle is completed.
2-WIRE SERIAL INTERFACE OPERATION
X9252 Digital Potentiometer Register Organization
Refer to the Functional Diagram on page 1. There are
four Digitally Controlled Potentiometers, referred to as
DCPi, i=0,1,2,3. Each potentiometer has one volatile
Wiper Control Register(WCR) with the corresponding
number, WCRi, i=0,1,2,3. Each potentiometer also has
four nonvolatile registers to store wiper position or
general data, these are numbered DRi0, DRi1, DRi2
and DRi3, i=0,1,2,3.
During acknowledge polling, the master first issues a
START condition followed by a Slave Address Byte.
The Slave Address Byte contains the X9252’s Device
Type Identifier and Device Address. The LSB of the
Slave Address (R/W) can be set to either 1 or 0 in this
case. If the device is busy within the high voltage cycle,
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X9252
The registers are organized in five pages of four, with
one page consisting of the WCRi (i=0-3), a second
page containing the DRi0 (i=0-3), a third page contain-
ing the DRi1, and so forth. These pages can be written
to four bytes at at time. In this manner all four potenti-
ometer WCRs can be updated in a single serial write
(see “Page Write Operation” on page 17), as well as all
four registers of a given page in the DR array.
Table 2. Status Register Contents for WCR and DR
Selection for 2-Wire Interface
Register Selected DRSel1 DRSel0 NVEnable
WCRi
DRi0
DRi1
DRi2
DRi3
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
The unique feature of the X9252 device is that writing
or reading to a Data Register of a given DCP automati-
cally updates/moves the WCR of that DCP with the
content of the DR. In this manner data can be moved
from a particular DCP register to that DCP’s WCR just
by performing a 2-wire read operation. Simulta-
neously, that data byte can be utilized by the host.
Note: X means either 0 or 1, i = 0,1,2, or 3
DCP Addressing for 2-wire Interface
Once the register number has been selected by a 2-
wire instruction, then the DCP number is determined
by the Address Byte of the following instruction. Note
again that this enables a complete page write of the
DRs of all four potentiometers at once. The register
addresses accessible in the X9252 include:
Status Register Organization
The Status Register (SR) is used in read and write
operations to select the appropriate DCP register.
Before any DCP register can be accessed, the SR
must be set to the correct value. It is accessed by
setting the Address Byte to 07h (Write Slave Address,
followed by Byte Address 07h). The SR is volatile and
defaults to 00h on power up. It is an 8-bit register
containing three control bits in the 3 LSBs as follows:
Table 3. Addressing for 2-wire Interface Address
Byte
Address (hex)
Contents
DCP 0
0
1
2
3
4
5
6
7
DCP 1
DCP 2
DCP 3
7
6
5
4
3
2
1
0
Not Used
Not Used
Not Used
Status Register
Reserved
DRSel1 DRSel0 NVEnable
Bits DRSel0 and DRSel1 determine which Data Regis-
ter of a DCP is selected in a given operation. NVEn-
able is used to select the volatile WCR if “0”, and one
of the nonvolatile DCP registers if “1”. Table 2 shows
this register organization. “Store” operations using the
Up/Down interface require that bits DRSel1 and
DRSel0 are set to “0”.
All other address bits in the Address Byte must be set
to “0” during 2-wire write operations and their value
should be ignored when read.
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X9252
Byte Write Operation
For example, to write 3Ahex to the Data Register 1 of
DCP2 the following sequence is required:
For any Byte Write operation, the X9252 requires the
Slave Address byte, an Address Byte, and a Data Byte
(See Figure 6). After each of them, the X9252
responds with an ACK. The master then terminates the
transfer by generating a STOP condition. At this time, if
the write operation is to a volatile register (WCR, or
SR), the X9252 is ready for the next read or write
operation. If the write operation is to a nonvolatile
register (DR), and the WP pin is high, the X9252
begins the internal write cycle to the nonvolatile
memory. During the internal nonvolatile write cycle, the
X9252 does not respond to any requests from the
master.The SDA output is at high impedance.
START
Slave Address 0101 0000
ACK
(Hardware Address = 000,
and a Write command)
(Indicates Status Register
address)
Address Byte
ACK
Data Byte
ACK
0000 0111
0000 0011
(Data Register 1 and
NVEnable selected)
STOP
START
Slave Address 0101 0000
ACK
Address Byte
ACK
(Hardware address = 000,
Write command)
(Access DCP2)
0000 0010
The SR bits and WP pin determine the register being
accessed through the 2-wire interface. See Table 1 on
page 11.
Data Byte
ACK
0011 1010 (Write Data Byte 3Ah)
As noted before, that any write operation to a Data
Register (DR), also writes to the WCR of the corre-
sponding DCP.
STOP
During the sequence of this example, WP pin must be
high, and A0, A1, and A2 pins must be low. When com-
pleted, the DR21 register will be set to 3Ah, and also
the WCR2.
Figure 6. Byte Write Sequence
Write
S
t
a
r
Signals from
the Master
S
t
o
p
Data
Byte
Address
Byte
Slave
Address
t
Signal at SDA
01 0 1
0
Signals from
the Slave
A
C
K
A
C
K
A
C
K
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X9252
Page Write Operation
constant. When the counter reaches the end of the
page (DR3i, 03hex), it “rolls over” and goes back to the
first byte of the same page (DR0i, 00hex).
As stated previously, the memory is organized as a
single Status Register (SR), and four pages of four
registers each. Each page contains one Data Register
for each DCP. The order of the bytes within a page is
DR0i, followed by DR1i, followed by DR2i, and then
DR3i, with i being the Data Register number (0, 1, 2, or
3). Normally a page write operation will be used to
efficiently update all four data registers and WCR in a
single write command, starting at DCP0 and finishing
with DCP3.
For example, if the master writes 3 bytes to a page
starting at location DR22, the first 2 bytes are written to
locations DR22 and DR32, while the last byte is written
to locations DR02. Afterwards, the DCP counter would
point to location DR12. If the master supplies more
than 4 bytes of data, then new data overwrites the
previous data, one byte at a time.
The master terminates the loading of Data Bytes by
In order to perform a Page Write operation to the mem-
ory array, the NVEnable bit in the SR must first be set
to “1”.
issuing
a
STOP condition, which initiates the
nonvolatile write cycle. As with the Byte Write
operation, all inputs are disabled until completion of the
internal write cycle. If the WP pin is high, the
nonvolatile write cycle doesn’t start and the bytes are
discarded.
A Page Write operation is initiated in the same manner
as the byte write operation; but instead of terminating
the write cycle after the first data byte is transferred,
the master can transmit up to 4 bytes (See Figure 7).
After the receipt of each byte, the X9252 responds with
an ACK, and the internal DCP address counter is
incremented by one. The page address remains
Notice that the Data Bytes are also written to the WCR
of the corresponding DCPs, therefore in the above
example, WCR2, WCR3, and WCR0 are also written.
Figure 7. Page Write Operation
Write
2 < n < 4
S
Signals from
t
S
t
o
p
the Master
Address
Byte
Slave
Address
a
r
Data Byte (1)
Data Byte (n)
t
Signal at SDA
01 0 1
0
Signals from
the Slave
A
C
K
A
C
K
A
C
K
A
C
K
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X9252
Move/Read Operation
Bytes as long as the master responds with an ACK
during the SCL cycle following the eigth bit of each
byte. The master terminates the Move/Read operation
(issuing a STOP condition) following the last bit of the
last Data Byte.
The Move/Read operation simultaneously reads the
contents of a Data Register (DR) and moves the
contents into the corresponding DCP’s WCR. If the
DRs of more than one DCP are read, then the WCRs
of all those DCPs are updated with the content of their
corresponding DR. Move/Read operation consists of a
one byte, or three byte instruction followed by one or
more Data Bytes (See Figure 8). To read an arbitrary
byte, the master initiates the operation issuing the
following sequence: a START, the Slave Address byte
with the R/W bit set to “0”, an Address Byte, a second
START, and a second Slave Address byte with the R/W
bit set to “1”. After each of the three bytes, the X9252
responds with an ACK. Then the X9252 transmits Data
The first byte being read is determined by the current
DCP address and by the Status Register bits,
according to Table 2 on page 15. If more than one byte
is read, the DCP address is incremented by one after
each byte, in the same way as during a Page Write
operation. After reaching DCP3, the DCP address
“rolls over” to DCP0.
On power up, the Address pointer is set to the Data
Register 0 of DCP0.
Figure 8. Move/Read Sequence
One or more Data Bytes
S
t
a
r
S
t
a
r
Slave
Address
with
Slave
Address
with
Signals
from the
Master
S
t
o
p
A
C
K
A
C
K
Address
Byte
R/W=0
R/W=1
t
t
Signal at
SDA
01 0 1
01 0 1
1
0
A
C
K
A
C
K
A
C
K
Signals from
the Slave
Last Read
Data Byte
First Read
Data Byte
Setting the Current Address
Current Address Read
Random Address Read
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X9252
APPLICATIONS INFORMATION
Basic Configurations of Electronic Potentiometers
+V
R
V
R
RW
I
Three terminal Potentiometer;
Variable voltage divider
Two terminal Variable Resistor;
Variable current
Application Circuits
Noninverting Amplifier
Voltage Regulator
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
adj
R
R
1
2
V
= (1+R /R )V
V
(REG) = 1.25V (1+R /R )+I
R
adj 2
O
2
1
S
O
2
1
Offset Voltage Adjustment
Comparator with Hysterisis
R
R
2
1
V
–
+
S
V
S
V
O
+5V
100KΩ
–
+
V
O
TL072
R
R
1
2
10KΩ
10KΩ
V
= {R /(R +R )} V (max)
1 1 2 O
UL
RL = {R /(R +R )} V (min)
L
1
1
2
O
10KΩ
+5V
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X9252
Application Circuits (continued)
Attenuator
Filter
C
V
+
–
S
R
V
R
R
2
O
1
3
–
+
R
V
O
V
S
R
2
R
4
R
= R = R = R = 10kΩ
2 3 4
1
R
1
G
= 1 + R /R
2 1
V
= G V
S
O
O
fc = 1/(2πRC)
-1/2 ≤ G ≤ +1/2
Inverting Amplifier
Equivalent L-R Circuit
R
R
2
1
V
S
R
2
C
1
–
+
V
+
–
S
V
O
R
R
1
3
Z
IN
V
= G V
S
O
G = - R /R
2
1
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
(R + R ) >> R
1
3
2
Function Generator
C
R
R
1
2
–
+
–
+
R
R
}
A
}
B
frequency ∝ R , R , C
1
2
amplitude ∝ R , R
A
B
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X9252
PACKAGING INFORMATION
24-Lead Plastic, TSSOP, Package Code V24
.026 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.303 (7.70)
.311 (7.90)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.06)
.005 (.15)
.010 (.25)
Gage Plane
(7.72)
(4.16)
0°–8°
Seating Plane
.020 (.50)
.030 (.75)
(1.78)
(0.42)
Detail A (20X)
(0.65)
ALL MEASUREMENTS ARE TYPICAL
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
©Xicor, Inc. 2003 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, BiasLock and XDCP are also trademarks of
Xicor, Inc. All others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 21 of 21
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