X76F641XE-2 [XICOR]
Flash Card, 8KX8, SMART CARD MODULE-8;
| 型号： | X76F641XE-2 |
| 厂家： | 
XICOR INC. |
| 描述： | Flash Card, 8KX8, SMART CARD MODULE-8 时钟 内存集成电路 |
| 文件： | 总16页 (文件大小：494K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO 7816 Compatible
64K
8K x 8 + 32 x 8
X76F641
Secure SerialFlash
FEATURES
DESCRIPTION
• 64-bit password security
—Five 64-bit passwords for read, program and
reset
• 8192 byte+32 byte password protected arrays
—Separate read passwords
—Separate write passwords
—Reset password
The X76F641 is a Password Access Security Supervi-
sor, containing one 65536-bit Secure SerialFlash array
and one 256-bit Secure SerialFlash array. Access to
each memory array is controlled by five 64-bit pass-
words each. These passwords protect read and write
operations of the memory array. A separate RESET
password is used to reset the passwords and clear the
memory arrays in the event the read and write pass-
words are lost.
• Programmable passwords
• Retry counter register
—Allows 8 tries before clearing of both arrays
—Password protected reset
• 32-bit response to reset (RST input)
• 32 byte sector program
• 400kHz clock rate
The X76F641 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA).
• 2-wire serial interface
• Low power CMOS
—2.0 to 5.5V operation
—Standby current less than 1µA
—Active current less than 3 mA
• High reliability endurance:
—100,000 write cycles
• Data retention: 100 years
• Available in:
The X76F641 also features a synchronous response
to reset providing an automatic output of a hard-wired
32-bit data stream conforming to the industry standard
for memory cards.
The X76F641 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000
cycles and a minimum data retention of 100 years.
—8-lead EIAJ SOIC
—SmartCard module
BLOCK DIAGRAM
8K Byte
SerialFlash Array
Array 0
(Password Protected)
Data Transfer
Array Access
SCL
SDA
Enable
Interface
Logic
32 Byte
SerialFlash Array
Array 1
Password Array
and Password
(Password Protected)
Verification Logic
RST
Reset
Response Register
Retry Counter
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X76F641
PIN DESCRIPTIONS
Serial Clock (SCL)
If the X76F641 is in a nonvolatile write cycle a “no
ACK” (SDA = High) response will be issued in
response to loading of the command byte. If a stop is
issued prior to the nonvolatile write cycle, the write
operation will be terminated and the part will reset and
enter into standby mode.
The SCL input is used to clock all data into and out of
the device.
Serial Data (SDA)
The basic sequence is illustrated in Figure 1.
SDA is a true three state serial data input/output pin.
During a read cycle, data is shifted out on this pin. Dur-
ing a write cycle, data is shifted in on this pin. In all
other cases, this pin is in a high impedance state.
PIN NAMES
Symbol
SDA
Description
Serial Data Input/Output
Serial Clock Input
Reset Input
Reset (RST)
SCL
RST is a device reset pin. When RST is pulsed high
the X76F641 will output 32 bits of fixed data, which
conforms to the standard for “synchronous response to
reset”. The part must not be in a write cycle for the
response to reset to occur. See Figure 11. If there is
power interrupted during the Response to Reset, the
response to reset will be aborted and the part will
return to the standby state. The response to reset is
“mask programmable” only!
RST
V
Supply Voltage
Ground
CC
V
SS
NC
No Connect
PIN CONFIGURATION
Smart Card
DEVICE OPERATION
There are two primary modes of operation for the
X76F641; protected READ and protected WRITE. Pro-
tected operations must be performed with one of four
8-byte passwords.
EIAJ SOIC
V
V
CC
SS
1
2
8
7
6
5
RST
NC
SCL
NC
SDA
NC
3
4
The basic method of communication for the device is
generating a start condition, then transmitting a com-
mand, followed by the correct password. All parts will
be shipped from the factory with all passwords equal to
‘0’. The user must perform ACK Polling to determine
the validity of the password, before starting a data
transfer (see Acknowledge Polling.) The data transfer
can occur only after the correct password is accepted
and an ACK polling has been performed.
GND
V
CC
RST
NC
SCL
NC
SDA
NC
After each transaction is completed, the X76F641 will
reset and enter into a standby mode. This will also be
the response if an unsuccessful attempt is made to
access a protected array.
To ensure the correct communication, RST must
remain LOW under all conditions except when running
a “Response to Reset sequence”.
Data is transferred in 8-bit segments, with each trans-
fer being followed by an ACK, generated by the receiv-
ing device.
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X76F641
Figure 1. X76F641 Device Operation
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figure 2 and Figure 3.
Load Command Byte
Load 8-Byte
Password
Start Condition
All commands are preceeded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F641 continuously monitors the SDA
and SCL lines for the start condition, and will not
respond to any command until this condition is met.
Verify Password
Acceptance by
Use of Password ACK Polling
A start may be issued to terminate the input of a con-
trol byte or the input data to be written. This will reset
the device and leave it ready to begin a new read or
write command. Because of the push/pull output, a
start cannot be generated while the part is outputting
data. Starts are inhibited while a write is in progress.
Load 2 Byte Address
Read/Write
Data Bytes
Stop Condition
Two or Data ACK Polling
All communications must be terminated by a stop con-
dition. The stop condition is a LOW to HIGH transition
of SDA when SCL is HIGH. The stop condition is also
used to reset the device during a command or data
input sequence and will leave the device in the standby
power mode. As with starts, stops are inhibited when
outputting data and while a write is in progress.
Retry Counter
The X76F641 contains a retry counter. The retry
counter allows 8 accesses with an invalid password
before any action is taken. The counter will increment
with any combination of incorrect passwords. If the
retry counter overflows, all memory areas are cleared
and the device is locked, thereby preventing any read
or write array password matches. The passwords are
unaffected. If a correct password is received prior to
retry counter overflow, the retry counter is reset and
access is granted. In order to reset the operation of a
locked up device, a special reset command must be
used with a RESET password.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data.
The X76F641 will respond with an acknowledge after rec-
ognition of a start condition and its slave address. If both
the device and a write condition have been selected, the
X76F641 will respond with an acknowledge after the
receipt of each subsequent eight-bit word.
Device Protocol
The X76F641 supports a bidirectional bus oriented
protocol. The protocol defines any device that sends
data onto the bus as a transmitter, and the receiving
device as a receiver. The device controlling the transfer
is a master and the device being controlled is the
slave. The master will always initiate data transfers and
provide the clock for both transmit and receive opera-
tions. Therefore, the X76F641 will be considered a
slave in all applications.
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X76F641
Reset Device Command
Issuing a valid reset device command (with reset pass-
word) to the device resets and re-enables the retry
counter and re-enables the other commands. Again,
the passwords are not affected.
The reset device command is used to clear the retry
counter and reactivate the device. When the reset
device command is used prior to the retry counter
overflow, the retry counter is reset and no arrays or
passwords are affected. If the retry counter has over-
flowed, all memory areas are cleared and all com-
mands are blocked and the retry counter is disabled.
Reset Password Command
A reset password command will clear both arrays and
set all passwords to all zero.
Figure 2. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 3. Definition of Start and Stop Conditions
SCL
SDA
START Condition
STOP Condition
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X76F641
Table 1. X76F641 Instruction Set
1st Byte 1st Byte After 2nd Byte After
Password
Used
After Start
Password
Password
Low address
Low address
Low address
Low address
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
not used
Command Description
Read (Array 0)
1000 0000 High Address
1000 1000 High Address
1001 0000 High Address
1001 1000 High Address
Read 0
Read 1
Write 0
Write 1
Read 0
Read 1
Write 0
Write 1
Reset
Read (Array 1)
Sector Write (Array 0)
Sector Write (Array 1)
1010 0000
1010 1000
1011 0000
1011 1000
1100 0000
1110 0000
1110 1000
1111 0000
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
not used
Change Read 0 Password
Change Read 1 Password
Change Write 0 Password
Change Write 1 Password
Change Reset Password
Reset Password command
Reset Device command
ACK Polling command (Ends password operation)
Reserved
Reset
not used
not used
Reset
not used
not used
None
All the rest
Note: Illegal command codes will be disregarded.The part will respond with a “no-ACK” to the illegal byte and then return to the standby mode.
All write/read operations require a password.
PROGRAM OPERATIONS
Sector Programming
bytes transferred as illustrated in Figure 4. Up to 32
bytes may be transferred. After the last byte to be
transferred is acknowledged, a stop condition is
issued, which starts the nonvolatile write cycle.
The sector program mode requires issuing the 8-bit
write command followed by the password, the pass-
word ACK command, the address and then the data
Figure 4. Sector Programming
Write
Password
Write
Password
Wait t
7
Command
0
WC
OR
Repeated
ACK Polling
Command
SDA
S
If ACK, then
Password Matches
ACK Polling
Command
Data 0
S
Data 31
Wait t
WC
S
Data ACK Polling
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X76F641
ACK Polling
with. In order to continue the transaction, the X76F641
requires the master to perform an ACK polling with the
specific code of F0h. As with regular Acknowledge
polling, the user can either time out for 10ms and then
issue the ACK polling once, or continuously loop as
described in the flow.
Once a stop condition is issued to indicate the end of
the host’s write sequence, the X76F641 initiates the
internal nonvolatile write cycle. In order to take advan-
tage of the typical 5ms write cycle, ACK polling can
begin immediately. This involves issuing the start con-
dition followed by the new command code of 8 bits (1st
byte of the protocol.) If the X76F641 is still busy with
the nonvolatile write operation, it will issue a “no-ACK”
in response. If the nonvolatile write operation has com-
pleted, an “ACK” will be returned. The host can then
proceed with the rest of the protocol.
Password ACK Polling Sequence
Password Load
Completed Enter
ACK Polling
Data ACK Polling Sequence
Issue START
Write Sequence Completed
Enter ACK Polling
Issue Password
ACK Command
Issue START
NO
ACK
Returned?
Issue New
Command Code
YES
PROCEED
NO
ACK
Returned?
If the password is correct, an “ACK” will be returned
once the nonvolatile cycle is over. This is in response
to the ACK polling cycle immediately following the
“ACK”.
YES
PROCEED
If the password inserted is incorrect, a “no ACK” will be
returned even if the nonvolatile cycle is over. Therefore,
the user cannot be certain that the password is incor-
rect until the 10ms write cycle time has elapsed.
After the password sequence, there is always a nonvol-
atile write cycle. This is done to discourage random
guesses of the password if the device is being tampered
Figure 5. Acknowledge Polling
8th CLK
of 8th
Pwd. Byte
8th
CLK
‘ACK’
CLK
SCL
‘ACK’
CLK
8th Bit
SDA
‘ACK’
START
Condition
ACK or
No ACK
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X76F641
READ OPERATIONS
command/address/password sequence. A random
read of the array 1 can access all locations without
another password command sequence.
Read operations are initiated in the same manner as
write operations, but with a different command code.
Sequential Read
Random Read
The host can read sequentially within an array after the
password acceptance sequence. The data output is
sequential, with the data from address n followed by
the data from n+1.The address counter for read opera-
tions increments all address bits, allowing the entire
memory array contents to be serially read during one
operation. At the end of the address space (address
1FFFh for array 0, 1Fh for array 1), the counter “rolls
over” to address 0 and the X76F641 continues to out-
put data for each acknowledge received. Refer to Fig-
ure 7 for the address, acknowledge and data transfer
sequence. An acknowledge must follow each 8-bit data
transfer. After the last bit has been read, a stop condi-
tion is generated without a preceding acknowledge.
The master issues the start condition and a read
instruction and password, performs password ACK
polling, then issues the word address. Once the pass-
word has been acknowledged and first byte has been
read, another start can be issued, followed by a new 8-
bit address. Random reads are allowed, but only the
low order 8 bits can change. This limits random reads
to a 256 byte block. Therefore, with a single password
cycle, only a 256 byte block of array 0 may be
accessed randomly. To randomly access another block
of array 0, a stop must be issued, followed by a new
Figure 6. Random Read
Read
Password
Read
Password
Wait t
7
Command
0
WC
OR
Repeated
ACK Polling
Command
SDA
S
If ACK, then
Password Matches
ACK Polling
Command
S
S
S
Data Y
Data X
Figure 7. Sequential Read
Read
Password
7
Read
Password
0
Wait t
WC
Command
OR
Repeated
ACK Polling
Command
SDA
S
If ACK, then
Password Matches
ACK Polling
Command
S
S
Data X
Data 0
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X76F641
PASSWORDS
stop bit. After this time, it cannot be determined if the
password has been loaded correctly, without trying the
new password. To determine if the new password has
been loaded correctly the data ACK polling command
is issued immediately following the stop bit. If it returns
an ACK, then the two passes of the new password
entry do not match. If it returns a “no ACK” then the
passwords match and a high voltage cycle is in
progress. The high voltage cycle is complete when a
subsequent data ACK command returns an “ACK”.
The sequence in Figure 8 shows how to change (pro-
gram) the passwords. The programming of passwords
is done twice (prior to the nonvolatile write cycle) in
order to verify that the new password is consistent.
After the 8 bytes are entered in the second pass, a
comparison takes place. A mismatch will cause the
part to reset and enter into the standby mode.
Data ACK polling can be used to determine if a pass-
word has been loaded correctly; however, the data
ACK command must be issued less than 2ms after the
There is no way to read any of the passwords.
Figure 8. Change Passwords
Old
Password
Old
Password
Command
7
Wait t
WC
0
OR
Repeated
ACK Polling
Command
SDA
S
If ACK, then
Password Matches
New
Password
7
ACK Polling
Command
Two Bytes of “0”
S
Data ACK
Polling
New
New
Password
Password
Password
0
7
0
If immediate ACK,
then New Password error
S
If immediate NACK,
followed by ACK after ~5ms
then New Password OK
Figure 9. Reset Password
Wait t
WC
If ACK, then
Device Reset
OR
Repeated
ACK Polling
Command
Reset
Reset
Password
0
Password
7
Reset Password
Command
ACK Polling
Command
SDA
S
S
S
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X76F641
Figure 10. Reset Device
Wait t
WC
If ACK, then
Device reset
OR
Repeated
Reset
Password
0
Reset
Password
7
ACK Polling
Command
Reset Device
Command
ACK Polling
Command
SDA
S
S
S
RESPONSE TO RESET (DEFAULT = 19 41 AA 55)
the RST pulse (meeting the t
speck.) in the middle
NOL
of an ISO transaction, it will output the 32 bit sequence
again (starting at bit 0). Otherwise, this aborts the ISO
operation and the part returns to standby state. If the
RST is pulsed HIGH and the CLK is outside the RST
pulse (in the middle of an ISO transaction), this aborts
the ISO operation and the part returns to standby state.
The ISO Response to reset is controlled by the RST
and CLK pins. When RST is pulsed high during a clock
pulse, the device will output 32 bits of data, one bit per
clock, and it resets to the standby state. This conforms
to the ISO standard for “synchronous response to
reset”. The part must not be in a write cycle for the
response to reset to occur.
If power is interrupted during the Response to Reset, it
will be aborted and the part will return to the standby
state. A Response to Reset is not available during a
nonvolatile write cycle.
After initiating a nonvolatile write cycle, the RST pin
must not be pulsed until the nonvolatile write cycle is
complete. If not, the ISO response will not be acti-
vated. If the RST is pulsed HIGH and the CLK is within
Figure 11. Response to RESET (RST)
RST
SCK
0
0
1
0
1
0
0
0
0
1
1
0
1
0
1
1
0
1
0
0
0
1
0
0
0
0
1 1
0
0
1
1
SO
MSB
LSB
LSB
LSB
MSB
MSB LSB
MSB
2
3
Byte
0
1
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X76F641
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias ................... –65°C to +135°C
Storage temperature ........................–65°C to +150°C
Voltage on any pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those
listed in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
respect to V .........................................–1V to +7V
SS
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds).........300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Extended
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage
X76F641
Limits
4.5V to 5.5V
2.0V to 3.6V
–20°C
X76F641 – 2.0
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Unit
Test Conditions
= V x 0.1/V x 0.9 Levels @ 400 kHz,
I
V
Supply Current
(Read)
1
mA
f
SCL
CC1
CC
CC
CC
SDA = Open
RST = V
SS
(3)
I
V
Supply Current
3
mA
f
= V x 0.1/V x 0.9 Levels @ 400 kHz,
CC2
CC
SCL CC CC
(Write)
SDA = Open
RST = V
SS
(1)
(1)
I
I
V
Supply Current
50
1
µA
µA
V
= V x 0.1, V = V x 0.9
SB1
CC
IL
CC
IH
CC
(Standby)
f
= 400 kHz, f
= 400 kHz
SCL
SDA
V
Supply Current
V
= V
= V
SB2
CC
SDA
SCC CC
(Standby)
Other = GND or V –0.3V
CC
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
10
10
µA
µA
V
V
V
V
V
V
V
= V to V
SS CC
LI
IN
I
= V to V
SS CC
LO
OUT
(2)
V
–0.5
V
x 0.3
= 5.5V
= 5.5V
= 2.0V
= 2.0V
IL1
CC
CC
CC
CC
CC
(2)
V
V
V
V
x 0.7 V + 0.5
V
IH1
CC
CC
(2)
–0.5
V
x 0.1
CC
V
IL2
(2)
V
x 0.9 V + 0.5
CC
V
IH2
CC
V
0.4
V
I
= 3mA
OL
OL
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V
A
CC
Symbol
Test
Max.
Unit
Conditions
(3)
C
Output Capacitance (SDA)
8
6
pF
pF
V
= 0V
= 0V
OUT
I/O
(3)
C
Input Capacitance (RST, SCL)
V
IN
IN
Notes: (1) Must perform a stop command after a read command prior to measurement
(2) V min. and V max. are for reference only and are not tested.
IL
IH
(3) This parameter is periodically sampled and not 100% tested.
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X76F641
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
5V
3V
Input rise and fall times
Input and output timing level
Output load
10ns
1533Ω
1.3KΩ
V
x 0.5
CC
Output
Output
100pF
100pF
100pF
AC CHARACTERISTICS
AC Specifications (Over the recommended operating conditions)
Symbol Parameter
Min.
Typ.(1) Max. Unit
f
SCL clock frequency
0
400 kHz
ns
SCL
(1)
IN
t
Pulse width of spikes which must be suppressed by the input filter
SCL LOW to SDA data out valid
Time the bus must be free before a new transmit can start
Clock LOW time
50
100
0.3
t
0.1
0.9
µs
µs
µs
µs
µs
µs
ns
ns
µs
ns
ns
ns
AA
t
1.3
BUF
t
1.3
LOW
t
Clock HIGH time
0.6
HIGH
t
Start condition setup time
0.6
SU:STA
HD:STA
SU:DAT
HD:DAT
SU:STO
t
t
Start condition hold time
0.6
200
Data in setup time
t
t
Data in hold time
10
Stop condition setup time
0.6
t
Data output hold time
50
300
DH
(2)
(2)
t
SDA and SCL Rise time
20 + 0.1 x C
20 + 0.1 x C
300
300
R
b
b
t
SDA and SCL Fall time
F
f
SCL clock frequency during response to reset
Device select to RST active
400 kHz
SCL_RST
t
200
500
2.25
1.25
1.25
1.25
0
ns
ns
µs
µs
µs
µs
SR
t
RST to SCL non-overlap
NOL
t
RST high time
RST
t
Response to reset setup time
Clock LOW during response to reset
Clock HIGH during response to reset
RST LOW to SDA valid during response to reset
CLK LOW to SDA valid during response to reset
Device deselect to SDA high impedance
SU:RST
t
LOW_RST
t
HIGH_RST
t
t
500
500
500
ns
ns
ns
RDV
CDV
0
t
0
DHZ
Notes: (1) Typical values are for T = 25°C and V = 5.0V
A
CC
(2) C = Total Capacitance of one bus line in pf.
b
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X76F641
RESET AC SPECIFICATIONS
Power Up Timing
Symbol
Parameter
Min.
Typ.(2)
Max.
Unit
ms
(1)
t
Time from power up to read
Time from power up to write
1
5
PUR
(1)
t
ms
PUW
Notes: (1) Delays are measured from the time V
is stable until the specified operation can be initiated. These parameters are periodically
CC
sampled and not 100% tested.
(2) Typical values are for T = 25°C and V = 5.0V
A
CC
Nonvolatile Write Cycle Timing
Symbol
Parameter
Min.
Typ.(1)
Max.
Unit
(1)
t
Write cycle time
5
10
ms
WC
Note: (1) t
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
WC
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
TIMING DIAGRAMS
Bus Timing
t
t
t
t
LOW
R
F
HIGH
SCL
SDA IN
t
SU:DAT
t
t
t
SU:STO
SU:STA
HD:DAT
t
HD:STA
t
t
t
BUF
AA
DH
SDA OUT
Write Cycle Timing
SCL
SDA
8th Bit of Last Byte
ACK
t
WC
STOP
Condition
START
Condition
Characteristics subject to change without notice. 12 of 16
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X76F641
RST Timing Diagram—Response to a Synchronous Reset
RST
t
RST
t
t
HIGH_RST
2nd
t
NOL
NOL
1st
3rd
CLK
Pulse
CLK
I/O
CLK
CLK
Pulse
t
Pulse
LOW_RST
t
SU:RST
t
t
CDV
RDV
Data Bit (2)
Data Bit (1)
RST
CLK
I/O
Data Bit (N+1)
(N+2)
Data Bit (N)
GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS
100
V
CCMAX
80
60
40
20
R
= -------------------------- = 1 . 8 KΩ
MIN
I
R
MAX
OLMIN
t
R
R
= -----------------
C
MAX
R
BUS
MIN
20 40 60 80 100
t
= maximum allowable SDA rise time
R
Bus Capacitance in pF
Characteristics subject to change without notice. 13 of 16
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X76F641
PACKAGING INFORMATION
8-Lead Plastic, 0.200" Wide Small Outline
Gullwing Package Typ “A” (EIAJ SOIC)
0.020 (.508)
0.012 (.305)
.330 (8.38)
.300 (7.62)
.213 (5.41)
.205 (5.21)
Pin 1 ID
.050 (1.27) BSC
.212 (5.38)
.203 (5.16)
.080 (2.03)
.070 (1.78)
.013 (.330)
.004 (.102)
.010 (.254)
.007 (.178)
0°–8° Ref.
.035 (.889)
.020 (.508)
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice. 14 of 16
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X76F641
PACKAGING INFORMATION
8 Pad Chip on Board Smart Card Module Type X
8 Contact Module
11.4
6 Contact Module
8
0.15
0.2
1.215
1.3
1.3
2.54
2.54
35mm TAPE
35mm TAPE
1.422
Reject
Punch
Position
8.82
23.02
35
NOTE: ALL MEASUREMENTS IN MILLIMETERS
Characteristics subject to change without notice. 15 of 16
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X76F641
Ordering Information
X76F641
X
X
–X
Device
V
Limits
CC
Blank = 5V 10%
2.0 = 2.0V to 3.6V
Temperature Range
Blank = Commercial = 0°C to +70°C
E = Extended = –20°C to +85°C
Package
A = 8-Lead SOIC (EIAJ)
H = Die in Waffle Packs
W = Die in Wafer Form
X = Smart Card Module
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 16 of 16
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