X76F102X-2 [XICOR]
The X76F102 is a Password Access Security Supervisor, containing one 896-bit Secure SerialFlash array; 该X76F102是一个密码访问安全监控器，包含一个896位安全SerialFlash阵列
| 型号： | X76F102X-2 |
| 厂家： | 
XICOR INC. |
| 描述： | The X76F102 is a Password Access Security Supervisor, containing one 896-bit Secure SerialFlash array |
| 文件： | 总18页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ISO 7816 Compatible
1K
128 x 8 bit
X76F102
Secure SerialFlash
FEATURES
DESCRIPTION
• 64-bit Password Security
• One Array (112 Bytes)Two Passwords (16 Bytes)
—Read Password
—Write Password
• Programmable Passwords
• Retry Counter Register
—Allows 8 tries before clearing of the array
• 32-bit Response to Reset (RST Input)
• 8 byte Sector Write mode
• 1MHz Clock Rate
The X76F102 is a Password Access Security Supervisor,
containing one 896-bit Secure SerialFlash array. Access
to the memory array can be controlled by two 64-bit
passwords. These passwords protect read and write
operations of the memory array.
The X76F102 features a serial interface and software
protocol allowing operation on a popular two wire bus.
The bus signals are a clock Input (SCL) and a bidirec-
tional data input and output (SDA).
• 2 wire Serial Interface
• Low Power CMOS
—2.0 to 5.5V operation
—Standby current Less than 1µA
—Active current less than 3 mA
• High Reliability Endurance:
—100,000 Write Cycles
• Data Retention: 100 years
• Available in:
The X76F102 also features a synchronous response to
reset providing an automatic output of a hard-wired 32-bit
data stream conforming to the industry standard for
memory cards.
TM
The X76F102 utilizes Xicor’s proprietary Direct Write
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
—8 lead PDIP, SOIC, MSOP, TSSOP, and Smart
Card Module
FUNCTIONAL DIAGRAM
Retry Counter
Data Transfer
SCL
Erase Logic
Array Access
SDA
Interface
Enable
Logic
112 Byte
EEPROM Array
Password Array
and Password
Verification Logic
RST
ISO Reset
Response Register
1
Xicor, Inc. 1999 Patents Pending
9900-5004.2 1/26/99 EP
Characteristics subject to change without notice
1
X76F102
PIN DESCRIPTIONS
Serial Clock (SCL)
If the X76F102 is in a nonvolatile write cycle a “no ACK”
(SDA=High) response will be issued in response to load-
ing of the command byte. If a stop is issued prior to the
nonvolatile write cycle the write operation will be termi-
nated and the part will reset and enter into a standby
mode.
The SCL input is used to clock all data into and out of the
device.
Serial Data (SDA)
SDA is an open drain serial data input/output pin. During
a read cycle, data is shifted out on this pin. During a write
cycle, data is shifted in on this pin. In all other cases, this
pin is in a high impedance state.
PIN NAMES
Symbol
SDA
Description
Serial Data Input/Output
Serial Clock Input
Reset Input
Reset (RST)
SCL
RST
Vcc
Vss
NC
RST is a device reset pin. When RST is pulsed high the
X76F102 will output 32 bits of fixed data which conforms
to the standard for “synchronous response to reset”. The
part must not be in a write cycle for the response to reset
to occur. See Figure 7. If there is power interrupted dur-
ing the Response to Reset, the response to reset will be
aborted and the part will return to the standby state. The
response to reset is "mask programmable" only!
Supply Voltage
Ground
No Connect
PIN CONFIGURATION
PDIP
The basic sequence is illustrated in Figure 1.
V
RST
SCL
CC
1
2
8
7
6
5
NC
DEVICE OPERATION
3
4
SDA
NC
NC
The X76F102 memory array consists of fourteen 8-byte
sectors. Read or write access to the array always begins
at the first address of the sector. Read operations then
can continue indefinitely. Write operations must total 8
bytes.
Vss
SOIC
Smart Card Module
V
V
SS
1
8
CC
GND
NC
V
CC
2
RST
NC
7
6
5
There are two primary modes of operation for the
X76F102; Protected READ and protected WRITE. Pro-
tected operations must be performed with one of two
8-byte passwords.
RST
3
4
SCL
NC
SDA
NC
SCL
NC
SDA
NC
MSOP
The basic method of communication for the device is
generating a start condition, then transmitting a com-
mand, followed by the correct password. All parts will be
shipped from the factory with all passwords equal to ‘0’.
The user must perform ACK Polling to determine the
validity of the password, before starting a data transfer
(see Acknowledge Polling.) Only after the correct pass-
word is accepted and a ACK polling has been performed,
can the data transfer occur.
V
V
SS
1
8
CC
NC
NC
NC
2
7
6
5
RST
3
4
SCL
SDA
TSSOP
SCL
RST
SDA
NC
V
CC
1
2
8
NC
NC
To ensure the correct communication, RST must remain
LOW under all conditions except when running a
“Response to Reset sequence”.
7
6
5
3
4
V
SS
Data is transferred in 8-bit segments, with each transfer
being followed by an ACK, generated by the receiving
device.
2
X76F102
After each transaction is completed, the X76F102 will
reset and enter into a standby mode.This will also be the
response if an unsuccessful attempt is made to access a
protected array.
Clock and Data Conventions
Data states on the SDA line can change only during SCL
LOW. SDA changes during SCL HIGH are reserved for
indicating start and stop conditions. Refer to Figure 2 and
Figure 3.
Figure 1. X76F102 Device Operation
Start Condition
All commands are preceeded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X76F102 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition is met.
LOAD COMMAND/ADDRESS BYTE
LOAD 8-BYTE
PASSWORD
A start may be issued to terminate the input of a control
byte or the input data to be written. This will reset the
device and leave it ready to begin a new read or write
command. Because of the push/pull output, a start can-
not be generated while the part is outputting data. Starts
are inhibited while a write is in progress.
VERIFY PASSWORD
ACCEPTANCE BY
USE OF ACK POLLING
Stop Condition
READ/WRITE
DATA
All communications must be terminated by a stop condi-
tion. The stop condition is a LOW to HIGH transition of
SDA when SCL is HIGH. The stop condition is also used
to reset the device during a command or data input
sequence and will leave the device in the standby power
mode. As with starts, stops are inhibited when outputting
data and while a write is in progress.
BYTES
Retry Counter
The X76F102 contains a retry counter. The retry counter
allows 8 accesses with an invalid password before any
action is taken. The counter will increment with any com-
bination of incorrect passwords. If the retry counter over-
flows, the memory area and both of the passwords are
cleared to "0". If a correct password is received prior to
retry counter overflow, the retry counter is reset and
access is granted.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data.
The X76F102 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write condition have been
selected, the X76F102 will respond with an acknowledge
after the receipt of each subsequent eight-bit word.
Device Protocol
The X76F102 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter and the receiving device as
a receiver. The device controlling the transfer is a master
and the device being controlled is the slave. The master
will always initiate data transfers and provide the clock for
both transmit and receive operations. Therefore, the
X76F102 will be considered a slave in all applications.
3
X76F102
Figure 2. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 3. Definition of Start and Stop Conditions
SCL
SDA
Start Condition
Stop Condition
Table 1. X76F102 Instruction Set
Command
Password
after Start
Command Description
used
1 0 0 S3 S2 S1 S00
Sector Write
Sector Read
Write
1 0 0 S3 S2 S1 S0 1
Read
Write
Write
None
1 1 1 1 1 1 0 0
1 1 1 1 1 1 1 0
0 1 0 1 0 1 0 1
Change Write Password
Change Read Password
Password ACK Command
Illegal command codes will be disregarded. The part will respond with a “no-ACK” to the illegal byte and then return to
the standby mode. All write/read operations require a password.
PROGRAM OPERATIONS
Sector Write
which starts the nonvolatile write cycle. If more or less
than 8 bytes are transferred, the data in the sector
remains unchanged.
The sector write mode requires issuing the 8-bit write
command followed by the password and then the data
bytes transferred as illustrated in figure 4. The write com-
mand byte contains the address of the sector to be writ-
ten. Data is written starting at the first address of a sector
and eight bytes must be transferred. After the last byte to
be transferred is acknowledged a stop condition is issued
ACK Polling
Once a stop condition is issued to indicate the end of the
host’s write sequence, the X76F102 initiates the internal
nonvolatile write cycle. In order to take advantage of the
typical 5ms write cycle, ACK polling can begin immedi-
ately. This involves issuing the start condition followed by
4
X76F102
the new command code of 8 bits (1st byte of the proto-
col.) If the X76F102 is still busy with the nonvolatile write
operation, it will issue a “no-ACK” in response. If the non-
volatile write operation has completed, an “ACK” will be
returned and the host can then proceed with the rest of
the protocol.
Password ACK Polling Sequence
PASSWORD LOAD
COMPLETED
ENTER ACK POLLING
ISSUE START
Data ACK Polling Sequence
Write sequence completed
Enter ACK Polling
ISSUE
PASSWORD
ACK COMMAND
ISSUE START
ACK
NO
RETURNED?
ISSUE NEW
COMMAND
CODE
YES
PROCEED
NO
ACK
RETURNED?
YES
READ OPERATIONS
PROCEED
Read operations are initiated in the same manner as
write operations but with a different command code.
Sector Read
After the password sequence, there is always a nonvola-
tile write cycle. This is done to discourage random
guesses of the password if the device is being tampered
with. In order to continue the transaction, the X76F102
requires the master to perform a password ACK polling
sequence with the specific command code of 55h. As
with regular Acknowledge polling the user can either time
out for 10ms, and then issue the ACK polling once, or
continuously loop as described in the flow.
With sector read, a sector address is supplied with the
read command. Once the password has been acknowl-
edged data may be read from the sector. An acknowl-
edge must follow each 8-bit data transfer. A read
operation always begins at the first byte in the sector, but
may stop at any time. Random accesses to the array are
not possible. Continuous reading from the array will
return data from successive sectors. After reading the
last sector in the array, the address is automatically set to
the first sector in the array and data can continue to be
read out. After the last bit has been read, a stop condition
is generated without sending a preceding acknowledge.
If the password that was inserted was correct, then an
“ACK” will be returned once the nonvolatile cycle in
response to the passwrod ACK polling sequence is over.
If the password that was inserted was incorrect, then a
“no ACK” will be returned even if the nonvolatile cycle is
over. Therefore, the user cannot be certain that the pass-
word is incorrect until the 10ms write cycle time has
elapsed.
5
X76F102
Figure 4. Sector Write Sequence (Password Required)
Write
Password
7
Write
Password
0
Host
Commands
WRITE
COMMAND
Wait tWC
OR
Password
ACK
SDA
S
X76F102
Response
Command
If ACK, Then
Password Matches
Host
Commands
Password ACK
COMMAND
Wait tWC
Data ACK Polling
. . .
P
S
X76F102
Responce
Figure 5. Acknowledge Polling
SCL
SDA
8th clk.
of 8th
pwd. byte
8th
‘ACK’
clk
‘ACK’
clk
clk
8th bit
‘ACK’
START
condition
ACK or
no ACK
Figure 6. Sector Read Sequence (Password Required)
Read
Password
7
Read
Password
Host
Commands
READ
COMMAND
Wait tWC
OR
0
Password
ACK
SDA
S
X76F102
Response
Command
If ACK, Then
Password Matches
Host
Commands
Password ACK
COMMAND
. . .
P
S
Data n
Data 0
X76F102
Responce
6
X76F102
PASSWORDS
standard for “synchronous response to reset”. The part
must not be in a write cycle for the response to reset to
occur.
Passwords are changed by sending the "change read
password" or "change write password" commands in a
normal sector write operation. A full eight bytes contain-
ing the new password must be sent, following successful
transmission of the current write password and a valid
password ACK response. The user can use a repeated
ACK Polling command to check that a new password has
been written correctly. An ACK indicates that the new
password is valid.
After initiating a nonvolatile write cycle the RST pin must
not be pulsed until the nonvolatile write cycle is complete.
If not, the ISO response will not be activated. If the RST
is pulsed HIGH and the CLK is within the RST pulse
(meet the t
spec.) in the middle of an ISO transaction,
NOL
it will output the 32 bit sequence again (starting at bit 0).
Otherwise, this aborts the ISO operation and the part
returns to standby state. If the RST is pulsed HIGH and
the CLK is outside the RST pulse (in the middle of an
ISO transaction), this aborts the ISO operation and the
part returns to standby state.
There is no way to read any of the passwords.
RESPONSE TO RESET (DEFAULT = 19 02 AA 55)
The ISO Response to reset is controlled by the RST and
CLK pins. When RST is pulsed high during a clock pulse,
the device will output 32 bits of data, one bit per clock,
and it resets to the standy state.This conforms to the ISO
If there is power interrupted during the Response to
Reset, the response to reset will be aborted and the part
will return to the standby state. A Response to Reset is
not available during a nonvolatile write cycle.
Figure 7. Response to RESET (RST)
RST
SCK
0
1
0
1
0
0
1
0
1
0
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
SO
MSB
LSB
LSB
MSB
MSB LSB
MSB
LSB
2
3
Byte
0
1
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias ..................... –65°C to +135°C
Storage Temperature ..........................–65°Cto+150°C
Voltage on any Pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Respect to V .......................................–1V to +7V
SS
D.C. Output Current..................................................5mA
Lead Temperature
(Soldering, 10 seconds).................................. 300°C
7
X76F102
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
X76F102
Limits
Temp
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
4.5V to 5.5V
2.0V to 5.5V
X76F102 – 2
–40°C
7025 FM T06
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz,
SDA = Open
RST = VSS
VCC Supply Current
(Read)
ICC1
1
mA
fSCL = VCC x 0.1/VCC x 0.9 Levels @ 400 KHz,
SDA = Open
RST = VSS
VCC Supply Current
(Write)
(3)
3
mA
ICC2
VIL = VCC x 0.1, VIH = VCC x 0.9
VCC Supply Current
(Standby)
(1)
1
1
µA
µA
ISB1
fSCL = 400 KHz, fSDA = 400 KHz
VSDA = VSCC = VCC
VCC Supply Current
(Standby)
(1)
ISB2
Other = GND or VCC–0.3V
ILI
V
IN = VSS to VCC
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
µA
µA
V
ILO
VOUT = VSS to VCC
10
(2)
V
CC x 0.1
–0.5
VIL
(2)
V
CC x 0.9 VCC + 0.5
Input HIGH Voltage
Output LOW Voltage
V
V
VIH
VOL
IOL = 3mA
0.4
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
(3)
Test
Max.
Units
Conditions
I/O = 0V
IN = 0V
V
Output Capacitance (SDA)
8
pF
COUT
(3)
V
Input Capacitance (RST, SCL)
6
pF
CIN
NOTES:(1) Must perform a stop command after a read command prior to measurement
(2) V min. and V max. are for reference only and are not tested.
IL
IH
(3) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
V
CC x 0.1 to VCC x 0.9
Input Pulse Levels
5V
3V
Input Rise and Fall Times
10ns
1.53KW
1.3KW
100pF
Input and Output Timing
Level
VCC x 0.5
100pF
OUTPUT
OUTPUT
100pF
Output Load
8
X76F102
AC CHARACTERISTICS
(T = -40˚C to +85˚C, V = +3.0V to +5.5V, unless otherwise specified.)
A
CC
Symbol
Parameter
Min
0
Max
1
Units
MHz
µs
fSCL
SCL Clock Frequency
tAA(2)
SCL LOW to SDA Data Out Valid
0.1
0.9
Time the Bus Must Be Free Before a New Transmission Can
Start
tBUF
1.2
µs
tHD:STA
tLOW
Start Condition Hold Time
Clock LOW Period
0.6
1.2
0.6
0.6
10
µs
µs
µs
µs
ns
ns
ns
tHIGH
Clock HIGH Period
tSU:STA
tHD:DAT
tSU:DAT
tR
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
100
(1)
(1)
SDA and SCL Rise Time
300
300
20+0.1XCb
tF
SDA and SCL Fall Time
ns
µs
µs
ns
ns
ns
µs
ns
20+0.1XCb
tSU:STO
tDH
Stop Condition Setup Time
Data Out Hold Time
0.6
0
tNOL
tRDV
tCDV
tRST
tSU:RST
RST to SCL Non-Overlap
500
0
RST LOW to SDA Valid During Response to Reset
CLK LOW to SDA Valid During Response to Reset
RST High Time
450
450
0
1.5
500
RST Setup Time
Notes: 1. C = total capacitance of one bus line in pF
b
2.
t
= 1.1µs Max below V = 3.0V.
AA CC
RESET AC SPECIFICATIONS
Power Up Timing
(2)
Symbol
Parameter
Min.
Typ
Max.
Units
(1)
Time from Power Up to Read
Time from Power Up to Write
1
mS
mS
tPUR
(1)
5
tPUW
Notes: 1. Delays are measured from the time V is stable until the specified operation can be initiated.These parameters are periodically sampled
CC
and not 100% tested.
2. Typical values are for T = 25˚C and V = 5.0V
A
CC
Nonvolatile Write Cycle Timing
Symbol
Parameter
Min.
Typ.(1)
Max.
Units
(1)
Write Cycle Time
5
10
mS
tWC
Notes: 1.
t
is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle.
WC
It is the minimum cycle time to be allowed for any nonvolatile write by the user, unless Acknowledge Polling is used.
9
X76F102
Bus Timing
t
t
t
t
HIGH
LOW
R
F
SCL
t
t
t
t
t
SU:STA
HD:STA
HD:DAT
SU:DAT
SU:STO
SDA IN
t
t
t
AA
DH
BUF
SDA OUT
Write Cycle Timing
SCL
8th bit of last byte
ACK
SDA
t
WC
Stop
Condition
Start
Condition
RST Timing Diagram – Response to a Synchronous Reset
RST
t
RST
t
t
HIGH_RST
t
NOL
NOL
1st
clk
pulse
2nd
clk
3rd
CLK
I/O
clk
pulse
pulse
t
LOW_RST
t
SU:RST
t
t
CDV
RDV
DATA BIT (2)
DATA BIT (1)
10
X76F102
GUIDELINES FOR CALCULATING TYPICAL VALUES OF BUS PULL UP RESISTORS
100
V
CCMAX
80
60
40
20
R
= ------------------------- = 1.8KΩ
MIN
I
R
MAX
OLMIN
t
R
R
= -----------------
C
MAX
R
BUS
MIN
20 40 60 80 100
Bus capacitance in pF
t
= maximum allowable SDA rise time
R
11
X76F102
8-LEAD MINIATURE SMALL OUTLINE GULL WING PACKAGE TYPE M
0.118 ± 0.002
(3.00 ± 0.05)
0.012 + 0.006 / -0.002
0.0256 (0.65) TYP
(0.30 + 0.15 / -0.05)
R 0.014 (0.36)
0.118 ± 0.002
(3.00 ± 0.05)
0.030 (0.76)
0.0216 (0.55)
7° TYP
0.036 (0.91)
0.032 (0.81)
0.040 ± 0.002
(1.02 ± 0.05)
0.008 (0.20)
0.004 (0.10)
0.150 (3.81)
0.007 (0.18)
REF.
0.005 (0.13)
0.193 (4.90)
REF.
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
12
X76F102
8-LEAD PLASTIC DUAL IN-LINE PACKAGETYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.060 (1.52)
0.300
(7.62) REF.
0.020 (0.51)
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.065 (1.65)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0.015 (0.38)
MAX.
0°
TYP 0.010 (0.25)
.
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
13
X76F102
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7∞
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050" TYPICAL
X 45∞
0.050"
TYPICAL
0∞– 8∞
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14
X76F102
8-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.114 (2.9)
.122 (3.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
(7.72)
DetailA (20X)
(4.16)
(1.78)
(0.42)
.031 (.80)
.041 (1.05)
All MEASUREMENTS ARE TYPICAL
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
15
X76F102
X76F102 8 PAD CHIP ON BOARD SMART CARD MODULE TYPE X
0.465 ± 0.002
(11.81 ± 0.05)
0.088 (2.24) MIN EPOXY
FREE AREA (TYP.)
0.285 (7.24) MAX.
SEE NOTE 7 SHT. 2
R. 0.078 (2.00)
0.069 (1.75) MIN EPOXY
FREE AREA (TYP
.)
0.270 (6.86) MAX.
SEE NOTE 7 SHT.2
0.420± 0.002
(10.67 ± 0.05)
A
A
0.008± 0.001
(0.20 ± 0.03)
0.210 ± 0.002
(5.33 ± 0.05)
0.233± 0.002
(5.92 ± 0.05)
DIE
0.0235 (0.60) MAX.
SECTION A-A
GLOB SIZE
0.015 (0.38) MAX.
0.008 (0.20) MAX.
FR4 TAPE
SEE DETAIL SHEET 3
COPPER, NICKEL PLATED, GOLD FLASH
0.174 ± 0.002
(4.42 ± 0.05)
0.146 ± 0.002
(3.71 ± 0.05)
R.0.013 (0.33) (8x)
Vcc
RST
SCL
NC
Vss
NC
0.105± 0.002
TYP.
(2.67 ± 0.05)
(8x)
SDA
NC
0.105 ± 0.002
(8x)
(2.67 ± 0.05)
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
16
X76F102
8 CONTACT MODULE
6 CONTACT MODULE
11.4
8
0.15
0.2
1.215
1.3
1.3
2.54
2.54
35mm TAPE
35mm TAPE
1.422
REJECT
PUNCH
POSITION
8.82
23.02
35
NOTE: ALL MEASUREMENTS IN MILLIMETERS
17
X76F102
ORDERING INFORMATION
X76F102
X
X
–X
Device
V
Limits
CC
Blank = 5V ±10%
2.0 = 2.0V to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial= –40°C to +85°C
Package
S8 = 8-Lead SOIC
M8 = 8-Lead MSOP
P = 8-Lead PDIP
V8 - 8-Lead TSSOP
H = Die in Waffle Packs
W = Die in Wafer Form
X = Smart Card Module
Part Mark Convention
8-Lead SOIC/PDIP
8-Lead MSOP
Blank = 8-Lead SOIC
X76F102 X
XX
EYWW
XXX
ACG = 2.0 to 5.5V, 0 to +70°C
ACH = 2.0 to 5.5V, -40 to +85°C
ABS = 4.5 to 5.5V, 0 to +70°C
ABT = 4.5 to 5.5V, -40 to +85°C
F = 2.0 to 5.5V, 0 to +70°C
G = 2.0 to 5.5V, -40 to +85°C
Blank = 4.5 to 5.5V, 0 to +70°C
I = 4.5 to 5.5V, -40 to +85°C
LIMITEDWARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of
Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth
herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of
merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifica-
tions and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No
other circuits, patents, licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265;
4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652;
4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should
design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an
occurence.
18
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