X5001V8-2.7 [XICOR]
CPU Supervisor; CPU监控器
| 型号： | X5001V8-2.7 |
| 厂家： | 
XICOR INC. |
| 描述： | CPU Supervisor |
| 文件： | 总19页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X5001
CPU Supervisor
Features
DESCRIPTION
• 200ms Power On Reset Delay
• Low Vcc Detection and Reset Assertion
—Five Standard ResetThreshold Voltages
—Adjust Low Vcc ResetThreshold Voltage using
special programming sequence
—Reset Signal Valid to Vcc=1V
• Selectable Nonvolatile WatchdogTimer
—0.2, 0.6, 1.4 seconds
This device combines three popular functions, Power on
Reset, Watchdog Timer, and Supply Voltage Supervision
in one package. This combination lowers system cost,
reduces board space requirements, and increases reli-
ability.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. During a system failure,
the device will respond with a RESET signal after a
selectable time-out interval. The user selects the interval
from three preset values. Once selected, the interval
does not change, even after cycling the power.
—Off selection
—Select settings through software
• Long Battery Life With Low Power Consumption
—<50µA Max Standby Current,Watchdog On
—<1µA Max Standby Current,Watchdog Off
• 2.7V to 5.5V Operation
The user’s system is protected from low voltage condi-
tions by the device’s low Vcc detection circuitry. When
Vcc falls below the minimum Vcc trip point, the system is
reset. RESET is asserted until Vcc returns to proper
operating levels and stabilizes. Five industry standard
• SPI Mode 0 interface
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Watchdog Change Latch
• High Reliability
• Available Packages
—8-LeadTSSOP
—8-Lead SOIC
—8 Pin PDIP
V
thresholds are available, however, Xicor’s unique
TRIP
circuits allow the thresold to be reprogrammed to meet
custom requirements or to fine-tune the threshold for
applications requiring higher precision.
The device utilizes Xicor’s proprietary Direct WriteTM cell
for the Watchdog TImer control bits and the V
stor-
TRIP
age element, providing a minimum endurance of
100,000 write cycles and a minimum data retention of
100 years.
Block Diagram
RESET
WATCHDOG
TRANSITION
DETECTOR
WATCHDOG
TIMER
SI
DATA
REGISTER
RESET &
WATCHDOG
TIMEBASE
SO
COMMAND
DECODE &
CONTROL
LOGIC
SCK
CS/WDI
POWER ON/
LOW VOLTAGE
RESET
V
+
-
CC
GENERATION
V
TRIP
7036 FRM 01
Xicor, Inc. 1994, 1995, 1996, 1998 Patents Pending
7078 1.1 8/9/99 CM
Characteristics subject to change without notice
1
X5001
PIN DESCRIPTION
PIN
PIN
(SOIC/PDIP)
TSSOP
Name
Function
Chip Select Input.CS HIGH, deselects the device and the SO output pin is at
a high impedance state. Unless a nonvolatile write cycle is underway, the de-
vice will be in the standby power mode. CS LOW enables the device, placing it
in the active power mode. Prior to the start of any operation after power up, a
HIGH to LOW transition on CS is required
1
1
CS/WDI
Watchdog Input.A HIGH to LOW transition on the WDI pin restarts the Watch-
dog timer.The absence of a HIGH to LOW transition within the watchdog time-
out period results in RESET/RESET going active.
Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data
out on this pin.The falling edge of the serial clock (SCK) clocks the data out.
2
5
2
8
SO
SI
Serial Input.SI is a serial data input pin.Input all opcodes, byte addresses, and
memory data on this pin.The rising edge of the serial clock (SCK) latches the
input data. Send all opcodes (Table 1), addresses and data MSB first.
Serial Clock.The Serial Clock controls the serial bus timing for data input and
output.The rising edge of SCK latches in the opcode, address, or watchdog
bits present on the SI pin.The falling edge of SCK changes the data output on
the SO pin.
6
3
9
6
SCK
V
Program Enable.When V is LOW, the V
point is fixed at the last
TRIP
PE
TRIP
V
valid programmed level.To readjust the V
be pulled to a high voltage (15-18V).
level, requires that the VPE pin
PE
TRIP
V
4
8
7
Ground
SS
V
14
Supply Voltage
CC
Reset Output.RESET is an active LOW, open drain output which goes active
whenever Vcc falls below the minimum Vcc sense level. It will remain active un-
tilVcc rises above the minimumVcc sense level for 200ms.RESET goes active
if the Watchdog Timer is enabled and CS/WDI remains either HIGH or LOW
longer than the selectable Watchdog time-out period. A falling edge of CS/WDI
will reset the Watchdog Timer. RESET goes active on power up at 1V and re-
mains active for 200ms after the power supply stabilizes.
7
13
RESET
NC
3-5,10-12
No internal connections
Figure 1. PIN CONFIGURATION
8 Lead TSSOP
8 Lead SOIC/PDIP
V
1
2
3
4
8
7
6
5
CS/WDI
SO
RESET
SCK
SI
1
2
3
4
8
7
6
5
CC
VCC
RESET
SCK
SI
V
PE
CS/WDI
SO
V
SS
V
V
SS
PE
2
X5001
PRINCIPLES OF OPERATION
Power On Reset
To set the new V
threshold voltage to the Vcc pin and tie the W pin to the
programming voltage V . Then a V
voltage, apply the desired V
TRIP TRIP
PE
programming
P
TRIP
command sequence is sent to the device over the SPI
interface. This V programming sequence consists of
pulling CS LOW, then clocking in data 03h, 00h and 01h.
This is followed by bringing CS HIGH then LOW and
clocking in data 02h, 00h, and 01h (in order) and bringing
Application of power to the X5001 activates a Power On
Reset Circuit. This circuit goes active at 1V and pulls the
RESET/RESET pin active. This signal prevents the sys-
tem microprocessor from starting to operate with insuffi-
cient voltage or prior to stabilization of the oscillator.When
TRIP
CS HIGH. This initiates the V
programming
TRIP
Vcc exceeds the device V
value for 200ms (nominal)
TRIP
sequence.V is brought LOW to end the operation.
P
the circuit releases RESET, allowing the processor to
begin executing code.
Resetting the V
Voltage
TRIP
This procedure is used to set the V
to a “native” volt-
TRIP
Low voltage monitoring
age level. For example, if the current V
is 4.4V and
must be 4.0V, then the V must be
TRIP
TRIP
the new V
During operation, the X5001 monitors the V
level and
TRIP
CC
reset. When V
is reset, the new V
is something
asserts RESET if supply voltage falls below a preset mini-
mum V .The RESET signal prevents the microproces-
TRIP
TRIP
less than 1.7V. This procedure must be used to set the
voltage to a lower value.
TRIP
sor from operating in a power fail or brownout condition.
The RESET signal remains active until the voltage drops
below 1V. It also remains active until Vcc returns and
To reset the V
voltage, apply greater than 3V to the
TRIP
Vcc pin and tie the W pin to the programming voltage
PE
exceeds V
for 200ms.
TRIP
Vp. Then a V
command sequence is sent to the
TRIP
device over the SPI interface. This V
programming
TRIP
watchdog timer
sequence consists of pulling CS LOW, then clocking in
data 03h, 00h and 01h. This is followed by bringing CS
HIGH then LOW and clocking in data 02h, 00h, and 03h
The Watchdog Timer circuit monitors the microprocessor
activity by monitoring the WDI input. The microprocessor
must toggle the CS/WDI pin periodically to prevent a
RESET signal. The CS/WDI pin must be toggled from
HIGH to LOW prior to the expiration of the watchdog time-
out period. The state of two nonvolatile control bits in the
Watchdog Register determine the watchdog timer period.
(in order) and bringing CS HIGH. This initiates the V
TRIP
programming sequence. V is brought LOW to end the
P
operation.
VccThreshold Reset Procedure
The X5001 is shipped with a standard Vcc threshold
(V
) voltage. This value will not change over normal
TRIP
operating and storage conditions. However, in applica-
tions where the standard V is not exactly right, or if
TRIP
higher precision is needed in the V
value, the X5001
TRIP
threshold may be adjusted. The procedure is described
below, and requires the application of a high voltage con-
trol signal.
Setting the V
Voltage
TRIP
This procedure is used to set the V
to a higher volt-
TRIP
age value. For example, if the current V
is 4.4V and
TRIP
the new V
is 4.6V, this procedure will directly make
TRIP
the change. If the new setting is to be lower than the cur-
rent setting, then it is necessary to reset the trip point
before setting the new value.
3
X5001
Figure 2. Sample V
Reset Circuit
TRIP
4.7K
V
P
RESET
uC
1
2
3
4
8
7
6
5
Adjust
Run
X5001
SCK
SI
V
Adj.
TRIP
SO
CS
Figure 3. Set V
Level Sequence (Vcc=desired V value. )
TRIP
TRIP
V
= 15-18V
PE
V
PE
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23
SCK
SI
16 BITS
16 BITS
03h
0001h
02h
0001h
Figure 4. Reset V
Level Sequence (Vcc > 3V. )
TRIP
V
= 15-18V
PE
V
PE
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23
SCK
SI
16 BITS
16 BITS
03h
0001h
02h
0003h
4
X5001
Figure 5. Vtrip Programming Sequence
Vtrip Programming
Execute
Reset Vtrip
Sequence
Set Vcc = Vcc applied =
Desired Vtrip
Execute
Set Vtrip
Sequence
New Vcc applied =
Old Vcc applied + Error
New Vcc applied =
Old Vcc applied - Error
Apply 5V to Vcc
Execute
Reset Vtrip
Sequence
Decrement Vcc
(Vcc = Vcc - 50mV)
NO
RESET pin
goes active?
YES
Error < 0
Error > 0
Measured Vtrip -
Desired Vtrip
Error = 0
DONE
5
X5001
spi Interface
Watchdog Change Latch
The Watchdog Change Latch must be SET before a Write
Watchdog Timer Operation is initiated. The Enable
Watchdog Change (EWDC) instruction will set the latch
and the Disable Watchdog Change (DWDC) instruction
will reset the latch (See Figure 2.) This latch is automati-
cally reset upon a power-up condition and after the com-
pletion of a valid nonvolatile write cycle.
The device is designed to interface directly with the syn-
chronous Serial Peripheral Interface (SPI) of many popu-
lar microcontroller families.
The device monitors the CS/WDI line and asserts RESET
output if there is no activity within user selctable time-out
period. The device also monitors the Vcc supply and
asserts the RESET if Vcc falls below a preset minimum
Read WatchdogTimer Register Operation
(V
). The device contains an 8-bit Watchdog Timer
TRIP
Register to control the watchdog time-out period.The cur-
rent settings are accessed via the SI and SO pins.
If there is not a nonvolatile write in progress, the Read
Watchdog Timer instruction returns the setting of the
watchdog timer control bits. The other bits are reserved
and will return ’0’when read. See Figure 3.
All instructions (Table 1) and data are transferred MSB
first. Data input on the SI line is latched on the first rising
edge of SCK after CS goes LOW. Data is output on the
SO line by the falling edge of SCK. SCK is static, allowing
the user to stop the clock and then start it again to resume
operations where left off.
If a nonvolatile write is in progress, the Read Watchdog
Timer Register Instruction returns a HIGH on SO. When
the nonvolatile write cycle is completed, a seperate Read
Watchdog Timer instruction should be used to determine
the current status of the Watchdog control bits.
WatchdogTimer Register
RESET Operation
7
0
6
0
5
0
4
3
2
0
1
0
0
0
The RESET (X5001) output is designed to go LOW
WD WD
1
0
whenever V has dropped below the minimum trip point
CC
and/or the Watchdog timer has reached its programmable
time-out limit.
WatchdogTimer Control Bits
The Watchdog Timer Control bits, WD and WD , select
the Watchdog Time-out Period. These nonvolatile bits are
programmed with the Set Watchdog Timer (SWDT)
instruction.
0
1
The RESET output is an open drain output and requires a
pull up resistor.
Operational Notes
The device powers-up in the following state:
Watchdog Control Bits
WatchdogTime-out
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
• The Watchdog Change Latch is reset.
WD1
WD0
(Typical)
1.4 Seconds
600 Milliseconds
200 Milliseconds
Disabled
0
0
1
1
0
1
0
1
• The RESET Signal is active for t
.
PURST
Data Protection
Write Watchdog Register Operation
The following circuitry has been included to prevent inad-
vertent writes:
Changing the Watchdog Timer Register is a two step pro-
cess. First, the change must be enabled with by setting
the Watchdog Change Latch (see below). This instruction
is followed by the Set Watchdog Timer (SWDT) instruc-
tion, which includes the data to be written (Figure 5). Data
bits 3 and 4 contain the Watchdog settings and data bits
0, 1, 2, 5, 6 and 7 must be “0” .
• A EWDC instruction must be issued to enable a change
to the watchdog timeout setting.
• CS must come HIGH at the proper clock count in order
to implement the requested changes to the watchdog
timeout setting.
6
X5001
Table 1. Instruction Set Definition
Instruction Format
Instruction Name and Operation
0000 0110
0000 0100
0000 0001
EWDC: Enable Watchdog Change Operation
DWDC: Disable Watchdog Change Operation
SWDT: Set WatchdogTimer control bits:
Instruction followed by contents of register: 000(WD ) (WD )000
1
0
See Watchdog Timer Settings and Figure 3.
0000 0101
RWDT: Read WatchdogTimer control bits
Notes: Instructions are shown with MSB in leftmost position. Instructions are transferred MSB first.
7038 FRM T03
Figure 1. Read WatchdogTimer setting
CS
0
1
2
3
4
5
6
7
...
...
...
SCK
SI
RWDT
INSTRUCTION
W
D
1
W
D
0
SO
Figure 2. Enable Watchdog Change/Disable Watchdog Change Sequence
CS
0
1
2
3
4
5
6
7
SCK
INSTRUCTION
(1 BYTE)
SI
HIGH IMPEDANCE
SO
7
X5001
Figure 3. Write WatchdogTimer Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
SCK
INSTRUCTION
DATA BYTE
4
6
5
3
SI
W
D
1
W
D
0
HIGH IMPEDANCE
SO
Figure 4. Read Nonvolatile Status (Option 1) (Used to determine end of Watchdog Timer store operation)
CS
0
1
2
3
4
5
6
7
SCK
SI
RWDT
INSTRUCTION
NONVOLATILE WRITE IN PROGRESS
SO
SO HIGH During 1st bit while
in the Nonvolatile write cycle
Figure 5. Read Nonvolatile Status (Option 2) (Used to determine end of Watchdog Timer store operation)
CS
0
1
2
3
4
5
6
7
SCK
SI
RWDT
INSTRUCTION
NONVOLATILE WRITE IN PROGRESS
SO
SO HIGH During
Nonvolatile write cycle
8
X5001
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias ........................–65°Cto+135°C
Storage Temperature .............................–65°Cto+150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Voltage on any Pin with Respect to V ....... –1.0V to +7V
SS
D.C. Output Current ....................................................5mA
Lead Temperature (Soldering, 10 seconds)............300°C
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
Max.
Voltage Option
–1.8
Supply Voltage Limits
1.8V to 3.6V
Commercial
0°C
+70°C
7036 FRM T07
–2.7 or -2.7A
2.7V to 5.5V
–4.5 or -4.5A
4.5V to 5.5V
PT= Package, Temperature
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Units
Test Conditions
Min. Typ. Max.
SCK = V x 0.1/V x 0.9 @ 5MHz,
SO = Open
CC
CC
I
V
V
Write Current (Active)
5
mA
CC1
CC
SCK = V x 0.1/V x 0.9 @ 5MHz,
CC
CC
I
Read Current (Active)
0.4
mA
CC2
CC
SO = Open
I
V
V
V
Standby Current WDT=OFF
Standby Current WDT=ON
Standby Current WDT=ON
1
µA CS = V , V = V or V , V = 5.5V
CC IN SS CC CC
SB1
CC
CC
CC
I
50
20
µA CS = V , V = V or V , V = 5.5V
CC IN SS CC CC
SB2
I
µA CS = V , V = V or V , V =3.6V
CC IN SS CC CC
SB3
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
0.1
0.1
10
10
µA
µA
V
V
= V to V
LI
IN SS CC
I
V
= V to V
LO
OUT SS CC
(1)
–0.5
V
x0.3
CC
V
V
IL
(1)
Input HIGH Voltage
V
x0.7
V
+0.5
CC
V
CC
IH
V
Output LOW Voltage
Output LOW Voltage
Output LOW Voltage
Output HIGH Voltage
Output HIGH Voltage
Output HIGH Voltage
Reset Output LOW Voltage
0.4
V
V
> 3.3V, I = 2.1mA
OL1
CC OL
V
0.4
0.4
V
2V < V < 3.3V, I = 1mA
CC OL
OL2
V
V
VCC ≤ 2V, I = 0.5mA
OL
OL3
V
V
V
V
–0.8
–0.4
–0.2
V
V > 3.3V, I = –1.0mA
CC OH
OH1
CC
CC
CC
V
V
2V < VCC ≤ 3.3V, I = –0.4mA
OH2
OH
V
V
VCC ≤ 2V, I = –0.25mA
OH3
OH
V
0.4
V
I
= 1mA
OLRS
OL
POWER-UPTIMING
Symbol
Parameter
Min.
Max.
Units
ms
(2)
1
5
Power-up to Read Operation
Power-up to Write Operation
t
PUR
(2)
ms
t
PUW
CAPACITANCE T = +25°C, f = 1MHz,V = 5V.
A
CC
Symbol
Test
Max.
Units
pF
Conditions
(2)
OUT
8
6
V
= 0V
Output Capacitance (SO, RESET)
Input Capacitance (SCK, SI, CS)
C
OUT
(2)
IN
pF
V
= 0V
C
IN
Notes: (1) V min. and V max. are for reference only and are not tested.
IL
IH
(2) This parameter is periodically sampled and not 100% tested.
9
X5001
Figure 1. EQUIVALENT A.C. LOAD CIRCUIT
A.C.TEST CONDITIONS
3V
5V
V
x 0.1 to V x 0.9
Input Pulse Levels
CC
CC
Input Rise and Fall Times
Input and Output Timing Level
10ns
3.3KΩ
1.64KΩ
V
x0.5
CC
OUTPUT
1.64KΩ
RESET
30pF
100pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data InputTiming
1.8V–3.6V
2.7V–5.5V
Symbol
Parameter
Clock Frequency
Min.
Max.
Min.
0
Max.
Units
f
0
1
2
MHz
ns
SCK
t
Cycle Time
1000
400
400
400
400
100
100
500
200
200
200
200
50
CYC
t
CS Lead Time
CS Lag Time
ns
LEAD
t
ns
LAG
t
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Input Rise Time
Input Fall Time
CS Deselect Time
Write Cycle Time
ns
WH
t
ns
WL
t
ns
SU
t
50
ns
H
(3)
t
2
2
2
2
µs
RI
(3)
t
µs
ns
FI
t
250
150
CS
(4)
t
10
10
ms
WC
Data OutputTiming
Symbol
1.8V–3.6V
2.7V–5.5V
Parameter
Min.
Max.
1
Min.
Max.
Units
f
Clock Frequency
0
0
2
MHz
ns
SCK
t
Output Disable Time
Output Valid from Clock Low
Output Hold Time
400
400
200
200
DIS
t
ns
V
t
0
0
ns
HO
(3)
t
Output Rise Time
300
300
150
150
ns
RO
(3)
t
Output Fall Time
ns
FO
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) t is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal
WC
nonvolatile write cycle.
10
X5001
Figure 1. Data OutputTiming
CS
tCYC
tWH
tLAG
SCK
tV
MSB OUT
tHO
tWL
tDIS
SO
SI
MSB–1 OUT
LSB OUT
ADDR
LSB IN
Figure 2. Data InputTiming
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
tRI
tFI
SI
MSB IN
LSB IN
HIGH IMPEDANCE
SO
Figure 1. SymbolTable
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
11
X5001
Figure 1. Power-Up and Power-DownTiming
VTRIP
VTRIP
VCC
tPURST
0 Volts
tPURST
tF
tRPD
tR
RESET (X5001)
RESET OutputTiming
Symbol
Parameter
Min.
Typ.
Max.
Units
Reset Trip Point Voltage, X5001PT-4.5A
Reset Trip Point Voltage, X5001PT-4.5
Reset Trip Point Voltage, X5001PT-2.7A
Reset Trip Point Voltage, X5001PT-2.7
Reset Trip Point Voltage, X5001PT-1.8
4.50
4.25
2.85
2.55
1.70
4.75
4.50
3.00
2.70
1.80
4.63
4.38
2.92
2.63
1.75
V
V
t
TRIP
Power-up Reset Timeout
100
200
280
500
ms
ns
ns
ns
V
PURST
(5)
V
V
V
Detect to Reset/Output
Fall Time
t
CC
CC
CC
RPD
(5)
t
0.1
0.1
1
F
(5)
Rise Time
t
R
V
Reset Valid V
CC
RVALID
Notes: (5) This parameter is periodically sampled and not 100% tested.
PT = Package, Temperature
Figure 2. CS vs. RESETTiming
CS
tCST
RESET
tWDO
tRST
tWDO
tRST
RESET OutputTiming
Symbol
Parameter
Min.
Typ.
Max.
Units
Watchdog Timeout Period,
WD = 1, WD = 0
1
0
100
450
1
200
600
1.4
300
800
2
ms
ms
sec
t
WDO
WD = 0, WD = 1
1
0
WD = 0, WD = 0
1
0
t
CS Pulse Width to Reset the Watchdog
Reset Timeout
400
100
ns
CST
t
200
300
ms
RST
12
X5001
V
ProgrammingTiming Diagram
TRIP
Vcc
(V
V
TRIP
)
TRIP
t
t
THD
TSU
V
P
V
PE
t
t
t
VPH
VPS
VPO
t
PCS
CS
t
RP
SCK
SI
0001h or
0003h
03h
0001h
02h
13
X5001
V
Programming Parameters
TRIP
Parameter
Description
Min
Max
Units
t
V
V
V
V
V
V
V
Program Enable Voltage Setup time
1
µs
VPS
TRIP
TRIP
TRIP
TRIP
TRIP
TRIP
TRIP
t
Program Enable Voltage Hold time
Programming CS inactive time
Setup time
1
1
µs
µs
VPH
t
PCS
t
1
µs
TSU
t
Hold (stable) time
10
ms
ms
THD
t
Write Cycle Time
10
WC
Program Enable Voltage Off time
t
0
us
VPO
(Between successive adjustments)
V
Program Recovery Period
TRIP
t
10
ms
RP
(Between successive adjustments)
V
V
Programming Voltage
15
18
V
V
P
V
Programmed Voltage Range
1.7
5.0
TRAN
TRIP
Initial V
Program Voltage accuracy
TRIP
V
V
V
V
-0.1
-25
-25
-25
+0.4
+25
+25
+25
V
ta1
(Vcc applied - V
) (Programmed at 25oC.)
TRIP
Subsequent V
Program Voltage accuracy
TRIP
mV
mV
mV
ta2
tr
[(Vcc applied - V ) - V
. Programmed at 25oC.)
ta1
TRIP
V
Program Voltage repeatability
TRIP
(Successive program operations. Programmed at 25oC.)
V
Program variation after programming (0-75oC).
TRIP
tv
(Programmed at 25oC.)
V
Programming parameters are periodically sampled and are not 100% Tested.
TRIP
14
X5001
Vcc Supply Current vs. Temperature (I
)
t
t
t
vs. Voltage/Temperature (WD1,0=1,1)
SB
WDO
1.85
20
18
Watchdog Timer On (Vcc = 5V)
17
1.80
1.75
1.70
1.65
1.60
14
15
–40°C
Watchdog Timer On (Vcc = 3V)
11
1.55
1.50
1.45
1.40
25°C
90°C
Watchdog Timer Off (Vcc = 3V, 5V)
1.0
90C
0.55
0.35
1.7
3.1
Voltage
4.5
–40C
25C
Temp (c)
V
vs. Temperature (programmed at 25°C)
vs. Voltage/Temperature (WD1,0=1,0)
WDO
TRIP
5.025
0.85
Vtrip=5V
5.000
0.80
4.975
3.525
–40°C
0.75
Vtrip=3.5V
Vtrip=2.5V
25°C
3.500
3.475
0.70
90°C
2.525
2.500
2.475
0.65
0.60
1.7
3.1
4.5
0
25
85
Voltage
Temperature
t
vs. Temperature
vs. Voltage/Temperature (WD1,0 0=0,1)
PURST
WDO
280
275
270
265
260
255
250
245
240
0.30
0.29
0.28
0.27
0.26
0.25
0.24
0.23
0.22
0.21
0.20
–40°C
25°C
90°C
235
–40
1.7
3.1
Voltage
4.5
25
90
Degrees °C
15
X5001
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7∞
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050" TYPICAL
X 45∞
0.050"
TYPICAL
0∞– 8∞
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
16
X5001
8-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.114 (2.9)
.122 (3.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0∞– 8∞
Seating Plane
.019 (.50)
.029 (.75)
DetailA (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
17
X5001
Ordering Information
PART NUMBER
RESET (Active LOW)
Operating
Temperature Range
Vcc Range
Vtrip Range
Package
8 pin PDIP
8L SOIC
0oC - 70oC
0oC - 70oC
0oC - 70oC
0oC - 70oC
0oC - 70oC
0oC - 70oC
0oC - 70oC
0oC - 70oC
0oC - 70oC
X5001P-4.5A
X5001S8-4.5A
X5001V8-4.5A
X5001P
4.5-5.5V
4.5.4.75
4.25.4.5
8L TSSOP
8 pin PDIP
8L SOIC
4.5-5.5V
X5001S8
8L TSSOP
8L SOIC
X5001V8
2.7-5.5V
2.7-5.5V
2.85-3.0
2.55-2.7
X5001S8-2.7A
X5001S8-2.7
X5001V8-2.7
8L SOIC
8L TSSOP
18
X5001
Part Mark Information
8-Lead TSSOP
8-Lead SOIC
X5001
YWW XX
YWW
XXXXX
501AG = 1.8 to 3.6V, 0 to +70°C, V
501AH = 1.8 to 3.6V, -40 to +85°C, V
=1.7-1.8V
=1.7-1.8V
AG = 1.8 to 3.6V, 0 to +70°C, V
AH = 1.8 to 3.6V, -40 to +85°C, V
=1.7-1.8V
=1.7-1.8V
TRIP
TRIP
TRIP
TRIP
501F = 2.7 to 5.5V, 0 to +70°C, V
501G = 2.7 to 5.5V, -40 to +85°C, V
501AN = 2.7 to 5.5V, 0 to +70°C, V
=2.55-2.7V
=2.55-2.7V
F = 2.7 to 5.5V, 0 to +70°C, V
G = 2.7 to 5.5V, -40 to +85°C, V
=2.55-2.7V
=2.55-2.7V
TRIP
TRIP
TRIP
TRIP
=2.85-3.0V
TRIP
AN = 2.7 to 5.5V, 0 to +70°C, V
AP = 2.7 to 5.5V, -40 to +85°C, V
=2.85-3.0V
TRIP
501AP = 2.7 to 5.5V, -40 to +85°C, V
=2.85-3.0V
=4.25-4.5V
TRIP
=2.85-3.0V
TRIP
501 = 4.5 to 5.5V, 0 to +70°C, V
TRIP
Blank = 4.5 to 5.5V, 0 to +70°C, V
=4.25-4.5V
TRIP
501I = 4.5 to 5.5V, -40 to +85°C, V
501AL = 4.5 to 5.5V, 0 to +70°C, V
501AM = 4.5 to 5.5V, -40 to +85°C, V
=4.25-4.5V
=4.5-4.75V
TRIP
TRIP
I = 4.5 to 5.5V, -40 to +85°C, V
AL = 4.5 to 5.5V, 0 to +70°C, V
AM = 4.5 to 5.5V, -40 to +85°C, V
=4.25-4.5V
TRIP
TRIP
=4.5-4.75V
=4.5-4.75V
=4.5-4.75V
TRIP
TRIP
YWW = year/work week device is packaged.
LIMITEDWARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no
warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices
from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue
production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976.
Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appro-
priate error detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and
whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure
of the life support device or system, or to affect its safety or effectiveness.
19
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