X28HC256JI-90T1 [XICOR]
EEPROM, 32KX8, 90ns, Parallel, CMOS, PQCC32, PLASTIC, LCC-32;
| 型号： | X28HC256JI-90T1 |
| 厂家： | 
XICOR INC. |
| 描述： | EEPROM, 32KX8, 90ns, Parallel, CMOS, PQCC32, PLASTIC, LCC-32 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总23页 (文件大小：190K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256K
32K x 8 Bit
X28HC256
5 Volt, Byte Alterable EEPROM
FEATURES
DESCRIPTION
• Access time: 70ns
• Simple byte and page write
—Single 5V supply
—No external high voltages or V control circuits
—Self-timed
The X28HC256 is a second generation high perfor-
mance CMOS 32K x 8 EEPROM. It is fabricated with
Xicor’s proprietary, textured poly floating gate technol-
ogy, providing a highly reliable 5 Volt only nonvolatile
memory.
PP
—No erase before write
—No complex programming algorithms
—No overerase problem
• Low power CMOS
—Active: 60mA
—Standby: 500µA
• Software data protection
—Protects data against system level inadvertent
writes
• High speed page write capability
• Highly reliable Direct Write™ cell
—Endurance: 1,000,000 cycles
—Data retention: 100 years
• Early end of write detection
—DATA polling
The X28HC256 supports a 128-byte page write opera-
tion, effectively providing a 24µs/byte write cycle, and
enabling the entire memory to be typically rewritten in
less than 0.8 seconds. The X28HC256 also features
DATA Polling and Toggle Bit Polling, two methods of
providing early end of write detection. The X28HC256
also supports the JEDEC standard Software Data Pro-
tection feature for protecting against inadvertent writes
during power-up and power-down.
Endurance for the X28HC256 is specified as a mini-
mum 1,000,000 write cycles per byte and an inherent
data retention of 100 years.
—Toggle bit polling
BLOCK DIAGRAM
256Kbit
EEPROM
Array
X Buffers
Latches and
Decoder
A –A
0
14
Address
Inputs
I/O Buffers
and Latches
Y Buffers
Latches and
DECODER
I/O –I/O
0
7
Data Inputs/Outputs
CE
OE
WE
Control
Logic and
Timing
V
CC
SS
V
Characteristics subject to change without notice. 1 of 23
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X28HC256
PIN CONFIGURATION
TSOP
Plastic DIP
CERDIP
Flat Plastic
SOIC
LCC
PLCC
A
A
A
A
A
A
A
I/O
I/O
I/O
NC
V
SS
NC
I/O
I/O
I/O
I/O
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
3
4
5
2
1
0
0
1
2
6
A
A
A
28
27
26
25
24
23
22
21
20
19
18
17
7
12
14
A
A
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
14
12
4
3
2
1
32 31 30
WE
NC
V
A
A
A
A
A
A
A
5
29
A
6
5
4
3
2
1
0
8
A
X28HC256
A
A
A
A
A
A
A
A
13
7
6
5
4
3
2
1
0
CC
6
7
28
27
A
9
NC
A
8
3
4
5
6
7
WE
A
11
A
9
A
13
NC
OE
8
9
26
25
A
8
A
X28HC256
(Top View)
11
A
9
OE
A
CE
11
A
10
11
24
23
X28HC256
10
A
OE
10
A
10
CE
I/O
CE
I/O
12
13
22
21
NC
I/O
7
10
11
12
13
14
7
I/O
0
6
PGA
14 15 16 17 18 19 20
I/O
I/O
I/O
I/O
I/O
I/O
6
5
4
3
0
1
2
I/O
12
I/O
13
I/O
I/O
17
I/O
18
1
2
3
5
6
7
15
I/O
V
I/O
A
10
V
I/O
I/O
19
0
0
2
SS
4
SS
11
14
16
A
A
CE
20
A
10
21
1
9
7
5
8
X28HC256
A
A
OE
22
A
23
3
4
11
8
6
A
A
2
V
A
9
24
A
25
5
12
7
CC
28
A
A
WE
27
A
13
26
A
6
14
4
3
1
(Bottom View)
PIN DESCRIPTIONS
Addresses (A –A )
Write Enable (WE)
The Write Enable input controls the writing of data to
the X28HC256.
0
14
The Address inputs select an 8-bit memory location
during a read or write operation.
PIN NAMES
Symbol
A –A
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Chip Enable (CE)
0
14
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, power consump-
tion is reduced.
I/O –I/O
0
7
WE
CE
OE
Output Enable (OE)
The Output Enable input controls the data output buff-
ers, and is used to initiate read operations.
V
CC
V
Ground
SS
Data In/Data Out (I/O –I/O )
0
7
NC
No Connect
Data is written to or read from the X28HC256 through
the I/O pins.
Characteristics subject to change without notice. 2 of 23
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X28HC256
DEVICE OPERATION
Read
Write Operation Status Bits
The X28HC256 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
nates bus contention in a system environment. The
data bus will be in a high impedance state when either
OE or CE is HIGH.
Figure 1. Status Bit Assignment
I/O DP TB
5
4
3
2
1
0
Write
Write operations are initiated when both CE and WE
are LOW and OE is HIGH. The X28HC256 supports
both a CE and WE controlled write cycle. That is, the
address is latched by the falling edge of either CE or
WE, whichever occurs last. Similarly, the data is
latched internally by the rising edge of either CE or
WE, whichever occurs first. A byte write operation,
once initiated, will automatically continue to comple-
tion, typically within 3ms.
Reserved
Toggle Bit
DATA Polling
DATA Polling (I/O )
7
The X28HC256 features DATA Polling as a method to
indicate to the host system that the byte write or page
write cycle has completed. DATA Polling allows a sim-
ple bit test operation to determine the status of the
X28HC256. This eliminates additional interrupt inputs
or external hardware. During the internal programming
cycle, any attempt to read the last byte written will pro-
Page Write Operation
The page write feature of the X28HC256 allows the
entire memory to be written in typically 0.8 seconds.
Page write allows up to one hundred twenty-eight
bytes of data to be consecutively written to the
X28HC256, prior to the commencement of the internal
programming cycle. The host can fetch data from
another device within the system during a page write
operation (change the source address), but the page
duce the complement of that data on I/O (i.e., write
data = 0xxx xxxx, read data = 1xxx xxxx). Once the
7
programming cycle is complete, I/O will reflect true
7
data.
Toggle Bit (I/O )
6
address (A through A ) for each subsequent valid
7
14
The X28HC256 also provides another method for
determining when the internal write cycle is complete.
During the internal programming cycle I/O will toggle
write cycle to the part during this operation must be the
same as the initial page address.
6
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to one hundred twenty-
seven bytes in the same manner as the first byte was
written. Each successive byte load cycle, started by
the WE HIGH to LOW transition, must begin within
100µs of the falling edge of the preceding WE. If a sub-
sequent WE HIGH to LOW transition is not detected
within 100µs, the internal automatic programming
cycle will commence. There is no page write window
limitation. Effectively the page write window is infinitely
wide, so long as the host continues to access the
device within the byte load cycle time of 100µs.
from HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease, and the device will be
accessible for additional read and write operations.
Characteristics subject to change without notice. 3 of 23
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X28HC256
DATA POLLING I/O
7
Figure 2. DATA Polling Bus Sequence
Last
Write
WE
CE
OE
V
IH
V
HIGH Z
OH
I/O
7
V
OL
X28HC256
Ready
A –A
An
An
An
An
An
An
An
0
14
Figure 3. DATA Polling Software Flow
DATA Polling can effectively halve the time for writing to
the X28HC256. The timing diagram in Figure 2 illus-
trates the sequence of events on the bus. The software
flow diagram in Figure 3 illustrates one method of
implementing the routine.
Write Data
No
Writes
Complete?
Yes
Save Last Data
and Address
Read Last
Address
IO
7
No
Compare?
Yes
X28HC256
Ready
Characteristics subject to change without notice. 4 of 23
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X28HC256
THE TOGGLE BIT I/O
6
Figure 4. Toggle Bit Bus Sequence
Last
Write
WE
CE
OE
V
HIGH Z
OH
I/O
6
*
*
V
X28C512/513
Ready
OL
* I/O Beginning and ending state of I/O will vary.
6
6
Figure 5. Toggle Bit Software Flow
HARDWARE DATA PROTECTION
¬
The X28HC256 provides two hardware features that
protect nonvolatile data from inadvertent writes.
Last Write
Yes
– Default V
Sense—All write functions are inhibited
CC
when V
is 3.5V typically.
CC
– Write Inhibit—Holding either OE LOW, WE HIGH, or
CE HIGH will prevent an inadvertent write cycle during
power-up and power-down, maintaining data integrity.
Load Accum
From Addr n
SOFTWARE DATA PROTECTION
The X28HC256 offers a software-controlled data pro-
tection feature. The X28HC256 is shipped from Xicor
with the software data protection NOT ENABLED; that
is, the device will be in the standard operating mode. In
this mode data should be protected during power-up/
down operations through the use of external circuits.
The host would then have open read and write access
Compare
Accum with
Addr n
No
Compare
ok?
of the device once V was stable.
CC
Yes
The X28HC256 can be automatically protected during
power-up and power-down (without the need for exter-
nal circuits) by employing the software data protection
feature. The internal software data protection circuit is
enabled after the first write operation, utilizing the soft-
ware algorithm. This circuit is nonvolatile, and will
remain set for the life of the device unless the reset
command is issued.
X28C256
Ready
The Toggle Bit can eliminate the chore of saving and
fetching the last address and data in order to implement
DATA Polling. This can be especially helpful in an array
comprised of multiple X28HC256 memories that is
frequently updated. The timing diagram in Figure 4
illustrates the sequence of events on the bus. The soft-
ware flow diagram in Figure 5 illustrates a method for
polling the Toggle Bit.
Once the software protection is enabled, the X28HC256 is
also protected from inadvertent and accidental writes in the
powered-up state. That is, the software algorithm must be
issued prior to writing additional data to the device.
Characteristics subject to change without notice. 5 of 23
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X28HC256
SOFTWARE ALGORITHM
The three-byte sequence opens the page write window,
enabling the host to write from one to one hundred
twenty-eight bytes of data. Once the page load cycle
has been completed, the device will automatically be
returned to the data protected state.
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific
addresses. Refer to Figure 6 and 7 for the sequence.
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
V
CC
(V
)
CC
0V
Data
Address
AAA
5555
55
2AAA
A0
5555
Writes
ok
Write
Protected
t
WC
CE
≤ t
Byte
or
Age
BLC MAX
WE
Figure 7. Write Sequence for Software Data
Protection
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithm is used and data has been written, the
X28HC256 will automatically disable further writes
unless another command is issued to cancel it. If no
further commands are issued the X28HC256 will be
write protected during power-down and after any sub-
sequent power-up.
Write Data AA
to Address
5555
Write Data 55
to Address
2AAA
Note: Once initiated, the sequence of write operations
should not be interrupted.
Write Data A0
to Address
5555
Byte/Page
Load Enabled
Write Data XX
to Any
Address
Optional
Byte/Page
Load Operation
Write Last
Byte to
Last Address
After t
WC
Re-Enters Data
Protected State
Characteristics subject to change without notice. 6 of 23
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X28HC256
RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence
V
CC
AAA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
Standard
Operating
Mode
Data
Address
t
WC
CE
WE
Figure 9. Write Sequence for resetting Software
Data Protection
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
an EEPROM programmer, the following six step algo-
rithm will reset the internal protection circuit. After t
the X28HC256 will be in standard operating mode.
,
WC
Write Data AA
to Address
5555
Note: Once initiated, the sequence of write operations
should not be interrupted.
Write Data 55
to Address
2AAA
SYSTEM CONSIDERATIONS
Because the X28HC256 is frequently used in large
memory arrays, it is provided with a two line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipa-
tion, and eliminate the possibility of contention where
multiple I/O pins share the same bus.
Write Data 80
to Address
5555
Write Data AA
to Address
5555
To gain the most benefit, it is recommended that CE be
decoded from the address bus and be used as the pri-
mary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation, this assures that all deselected devices
are in their standby mode, and that only the selected
device(s) is/are outputting data on the bus.
Write Data 55
to Address
2AAA
Because the X28HC256 has two power modes,
standby and active, proper decoupling of the memory
array is of prime concern. Enabling CE will cause tran-
sient current spikes. The magnitude of these spikes is
dependent on the output capacitive loading of the l/Os.
Therefore, the larger the array sharing a common bus,
the larger the transient spikes. The voltage peaks
associated with the current transients can be sup-
pressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recommended
Write Data 20
to Address
5555
After t
,
WC
Re-Enters
Unprotected
State
Characteristics subject to change without notice. 7 of 23
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X28HC256
that a 0.1µF high frequency ceramic capacitor be used
between V
and V
at each device. Depending on
CC
SS
the size of the array, the value of the capacitor may
have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between V
and V
for
CC
SS
each eight devices employed in the array. This bulk
capacitor is employed to overcome the voltage droop
caused by the inductive effects of the PC board traces.
Characteristics subject to change without notice. 8 of 23
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X28HC256
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only; functional operation of the
device (at these or any other conditions above those indi-
cated in the operational sections of this specification) is
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
X28HC256 ...................................... –10°C to +85°C
X28HC256I, X28HC256M............. –65°C to +135°C
Storage temperature ........................ –65°C to +150°C
Voltage on any pin with
respect to V
........................................–1V to +7V
SS
D.C. output current ............................................. 10mA
Lead temperature (soldering, 10 seconds)........ 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
+125°C
Supply Voltage
Limits
X28HC256
5V ±10%
–40°C
–55°C
Military
D.C. OPERATING CHARACTERISTICS (Over recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min. Typ.(7)
Max.
Unit
Test Conditions
I
V
active current
30
60
mA CE = OE = V , WE = V , All I/O’s = open,
CC
CC
IL
IH
(TTL Inputs)
address inputs = .4V/2.4V levels @ f = 10MHz
I
I
V
standby current
1
2
mA CE = V , OE = V , All I/O’s = open, other
SB1
SB2
CC
IH
IL
(TTL Inputs)
inputs = V
IH
V
standby current
200
500
µA
CE = V – 0.3V, OE = GND, All I/Os = open,
CC
CC
(CMOS Inputs)
other inputs = V – 0.3V
CC
I
Input leakage current
Output leakage current
Input LOW voltage
Input HIGH voltage
Output LOW voltage
Output HIGH voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
I
= V to V , CE = V
SS CC IH
LO
OUT
(2)
V
–1
2
0.8
lL
(2)
V
V
+ 1
V
IH
CC
V
0.4
V
I
I
= 6mA
OL
OL
V
2.4
V
= –4mA
OH
OH
Notes: (1) Typical values are for T = 25°C and nominal supply voltage.
A
(2) V min. and V max. are for reference only and are not tested.
IL
IH
POWER-UP TIMING
Symbol
Parameter
Max.
Unit
µs
(3)
PUR
t
Power-up to read
Power-up to write
100
5
(3)
PUW
t
ms
Note: (3) This parameter is periodically sampled and not 100% tested.
Characteristics subject to change without notice. 9 of 23
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X28HC256
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
Test
Max.
10
Unit
pF
Conditions
(9)
I/O
C
Input/output capacitance
Input capacitance
V
= 0V
= 0V
I/O
(9)
IN
C
6
pF
V
IN
ENDURANCE AND DATA RETENTION
Parameter
Endurance
Min.
1,000,000
100
Max.
Unit
Cycles
Years
Data retention
A.C. CONDITIONS OF TEST
SYMBOL TABLE
Input pulse levels
0V to 3V
WAVEFORM
INPUTS
OUTPUTS
Input rise and fall times
Input and output timing levels
5ns
Must be
steady
Will be
steady
1.5V
MODE SELECTION
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
CE
L
OE WE
Mode
Read
Write
I/O
Power
active
active
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
L
H
X
H
L
D
OUT
L
D
IN
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
H
X
Standby and High Z standby
write inhibit
N/A
Center Line
is High
Impedance
X
X
L
X
H
Write inhibit
Write inhibit
—
—
—
—
X
EQUIVALENT A.C. LOAD CIRCUIT
5V
1.92KΩ
OUTPUT
1.37KΩ
30pF
Characteristics subject to change without notice. 10 of 23
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X28HC256
A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read Cycle Limits
X28HC256-70 X28HC256-90 X28HC256-12 X28HC256-15
Symbol
Parameter
Read cycle time
Min. Max. Min. Max. Min. Max. Min. Max. Unit
(5)
RC
t
70
90
120
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
(5)
CE
t
Chip enable access time
Address access time
70
70
35
90
90
40
120
120
50
150
150
50
(5)
AA
t
t
Output enable access time
CE LOW to active output
OE LOW to active output
CE HIGH to high Z output
OE HIGH to high Z output
Output hold from address change
OE
(4)
LZ
t
0
0
0
0
0
0
0
0
(4)
OLZ
t
(4)
HZ
t
35
35
40
40
50
50
50
50
(4)
OHZ
t
t
0
0
0
0
OH
Read Cycle
t
RC
Address
CE
t
CE
t
OE
OE
V
IH
WE
t
t
OHZ
OLZ
t
t
t
t
HZ
LZ
OH
AA
HIGH Z
Data Valid
Data Valid
Data I/O
Notes: (4) t min., t , t
min. and t
are periodically sampled and not 100% tested, t and t
are measured with CL = 5pF, from the
OHZ
LZ
HZ OLZ
OHZ
HZ
point when CE, OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
(5) For faster 256K products, refer to X28VC256 product line.
Characteristics subject to change without notice. 11 of 23
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X28HC256
Write Cycle Limits
Symbol
Parameter
Min.
Typ.(6)
Max.
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
µs
µs
(7)
WC
t
Write cycle time
Address setup time
Address hold time
Write setup time
Write hold time
3
5
t
0
50
0
AS
AH
CS
CH
t
t
t
0
t
CE pulse width
50
0
CW
t
OE HIGH setup time
OE HIGH hold time
WE pulse width
OES
t
0
OEH
t
50
50
WP
(8)
WPH
t
WE HIGH recovery (page write only)
Data valid
t
t
1
DV
Data setup
50
0
DS
t
Data hold
DH
(8)
DW
t
Delay to next write after polling is true
Byte load cycle
10
t
0.15
100
BLC
Notes: (6) Typical values are for T = 25°C and nominal supply voltage.
A
(7) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
WC
time the device requires to automatically complete the internal write operation.
(8) t and t are periodically sampled and not 100% tested.
WPH
DW
WE Controlled Write Cycle
t
WC
Address
t
t
AH
AS
t
t
CS
CH
CE
OE
t
t
OEH
OES
t
WP
WE
Data In
Data Out
Data Valid
t
t
DH
DS
HIGH Z
Characteristics subject to change without notice. 12 of 23
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X28HC256
CE Controlled Write Cycle
t
WC
Address
CE
t
t
AH
AS
t
CW
t
OES
OE
t
OEH
t
t
t
CS
CH
WE
Data Valid
Data In
t
DS
DH
HIGH Z
Data Out
Page Write Cycle
OE(9)
CE
t
t
BLC
WP
WE
t
WPH
Address(10)
Last Byte
Byte n+2
I/O
Byte 0
Byte 1
Byte 2
Byte n
Byte n+1
t
WC
*For each successive write within the page write operation, A –A should be the same or
7
15
writes to an unknown address could occur.
Notes: (9) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE
HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively per-
forming a polling operation.
(10)The timings shown above are unique to page write operations. Individual byte load operations within the page write must conform to
either the CE or WE controlled write cycle timing.
Characteristics subject to change without notice. 13 of 23
REV 1.1 2/1/01
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X28HC256
DATA Polling Timing Diagram(11)
Address
CE
A
A
A
n
n
n
WE
t
t
OEH
OES
OE
t
DW
D
= X
D
= X
D
= X
OUT
I/O
7
IN
OUT
t
WC
Toggle Bit Timing Diagram(11)
CE
WE
t
OES
t
OEH
OE
t
DW
HIGH Z
I/O
*
6
*
t
WC
* I/O beginning and ending state will vary, depending upon actual t
.
WC
6
Note: (11)Polling operations are by definition read cycles and are therefore subject to read cycle timings.
Characteristics subject to change without notice. 14 of 23
REV 1.1 2/1/01
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X28HC256
PACKAGING INFORMATION
28-Lead Ceramic Flat Pack Type F
0.019 (0.48)
0.015 (0.38)
Pin 1 Index
1
28
0.050 (1.27) BSC
0.740 (18.80)
Max.
0.045 (1.14) Max.
0.440 (11.18)
Max.
0.130 (3.30)
0.090 (2.29)
0.006 (0.15)
0.003 (0.08)
0.370 (9.40)
0.250 (6.35)
Typ. 0.300 2 Plcs.
0.045 (1.14)
0.025 (0.66)
0.180 (4.57)
Min.
0.030 (0.76)
Min.
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 15 of 23
REV 1.1 2/1/01
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X28HC256
PACKAGING INFORMATION
28-Lead Ceramic Pin Grid Array Package Type K
12
11
9
13
10
8
15
14
17
16
20
22
24
27
18
19
21
23
25
26
A
A
0.008 (0.20)
0.050 (1.27)
7
6
5
2
28
1
NOTE: LEADS 4,12,18 & 26
4
3
0.080 (2.03)
0.070 (1.78)
Typ. 0.100 (2.54)
All Leads
0.080 (2.03) 4 Corners
0.070 (1.78)
0.110 (2.79)
0.090 (2.29)
0.072 (1.83)
Pin 1 Index
0.062 (1.57)
0.020 (0.51)
0.016 (0.41)
0.660 (16.76)
0.640 (16.26)
A
A
0.185 (4.70)
0.175 (4.44)
0.561 (14.25)
0.541 (13.75)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 16 of 23
REV 1.1 2/1/01
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X28HC256
PACKAGING INFORMATION
28-Lead Plastic Dual In-Line Package Type P
1.470 (37.34)
1.400 (35.56)
0.557 (14.15)
0.510 (12.95)
Pin 1 Index
Pin 1
0.085 (2.16)
0.040 (1.02)
1.300 (33.02)
Ref.
0.160 (4.06)
0.125 (3.17)
Seating
Plane
0.030 (0.76)
0.015 (0.38)
0.160 (4.06)
0.120 (3.05)
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.040 (1.02)
0.022 (0.56)
0.014 (0.36)
0.625 (15.88)
0.590 (14.99)
0°
15°
Typ. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
Characteristics subject to change without notice. 17 of 23
REV 1.1 2/1/01
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X28HC256
PACKAGING INFORMATION
28-Lead Plastic Small Outline Gull Wing Package Type S
0.299 (7.59)
0.290 (7.37)
0.419 (10.64)
0.394 (10.01)
0.020 (0.508)
0.014 (0.356)
0.713 (18.11)
0.697 (17.70)
0.105 (2.67)
0.092 (2.34)
Base Plane
Seating Plane
0.012 (0.30)
0.003 (0.08)
0.050 (1.270)
BSC
0.050"Typical
0.0200 (0.5080)
0.0100 (0.2540)
X 45°
0.050"
Typical
0.013 (0.32)
0.008 (0.20)
0° – 8°
0.42" Max.
0.0350 (0.8890)
0.0160 (0.4064)
0.030"Typical
28 Places
FOOTPRINT
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
Characteristics subject to change without notice. 18 of 23
REV 1.1 2/1/01
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X28HC256
PACKAGING INFORMATION
32-Lead Hermetic Dual In-Line Package Type D
1.690 (42.95)
Max.
0.610 (15.49)
0.500 (12.70)
Pin 1
0.005 (0.13) Min.
0.100 (2.54) Max.
Seating
Plane
0.232 (5.90) Max.
0.060 (1.52)
0.015 (0.38)
0.150 (3.81) Min.
0.200 (5.08)
0.125 (3.18)
0.065 (1.65)
0.023 (0.58)
0.014 (0.36)
Typ. 0.018 (0.46)
0.033 (0.84)
0.110 (2.79)
Typ. 0.055 (1.40)
0.090 (2.29)
Typ. 0.100 (2.54)
0.620 (15.75)
0.590 (14.99)
Typ. 0.614 (15.60)
0°
15°
0.015 (0.38)
0.008 (0.20)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 19 of 23
REV 1.1 2/1/01
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X28HC256
PACKAGING INFORMATION
32-Pad Ceramic Leadless Chip Carrier Package Type E
0.300 (7.62)
BSC
0.150 (3.81) BSC
0.020 (0.51) x 45° Ref.
0.015 (0.38)
0.003 (0.08)
0.095 (2.41)
0.075 (1.91)
Pin 1
0.022 (0.56)
DIA.
0.006 (0.15)
0.055 (1.39)
0.045 (1.14)
0.200 (5.08)
BSC
0.015 (0.38)
TYP. (4) PLCS.
Min.
0.028 (0.71)
0.022 (0.56)
(32) Plcs.
0.040 (1.02) x 45° Ref.
Typ. (3) Plcs.
0.050 (1.27) BSC
0.088 (2.24)
0.050 (1.27)
0.458 (11.63)
0.442 (11.22)
0.458 (11.63)
––
0.120 (3.05)
0.060 (1.52)
0.558 (14.17)
––
0.560 (14.22)
0.540 (13.71)
0.400 (10.16)
BSC
Pin 1 Index Corner
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
Characteristics subject to change without notice. 20 of 23
REV 1.1 2/1/01
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X28HC256
PACKAGING INFORMATION
32-Lead Plastic Leaded Chip Carrier Package Type J
0.030" Typical
32 Places
0.050"
Typical
0.420 (10.67)
0.050"
Typical
0.510"
Typical
0.400"
0.050 (1.27) Typ.
0.300"
Ref.
0.410"
FOOTPRINT
0.021 (0.53)
0.013 (0.33)
Typ. 0.017 (0.43)
Seating Plane
0.045 (1.14) x 45°
±0.004 Lead
CO – Planarity
—
0.015 (0.38)
0.495 (12.57)
0.485 (12.32)
Typ. 0.490 (12.45)
0.095 (2.41)
0.060 (1.52)
0.140 (3.56)
0.100 (2.45)
Typ. 0.136 (3.45)
0.453 (11.51)
0.447 (11.35)
Typ. 0.450 (11.43)
0.048 (1.22)
0.042 (1.07)
0.300 (7.62)
Ref.
Pin 1
0.595 (15.11)
0.585 (14.86)
Typ. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
Typ. 0.550 (13.97)
0.400
Ref.
(10.16)
3° Typ.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
Characteristics subject to change without notice. 21 of 23
REV 1.1 2/1/01
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X28HC256
PACKAGING INFORMATION
32-Lead Thin Small Outline Package (TSOP) Type T
See Note 2
12.50 (0.492)
12.30 (0.484)
Pin #1 Ident.
O 0.76 (0.03)
0.50 (0.0197) BSC
See Note 2
8.02 (0.315)
7.98 (0.314)
0.26 (0.010)
0.14 (0.006)
1.18 (0.046)
1.02 (0.040)
0.17 (0.007)
0.03 (0.001)
Seating
Plane
0.58 (0.023)
0.42 (0.017)
14.15 (0.557)
13.83 (0.544)
14.80 ± 0.05
(0.583 ± 0.002)
0.30 ± 0.05
(0.012 ± 0.002)
Solder Pads
Typical
32 Places
15 Eq. Spc. 0.50 ± 0.04
0.0197 ± 0.016 = 7.50 ± 0.06
(0.295 ± 0.0024) Overall
Tol. Non-Cumulative
0.17 (0.007)
0.03 (0.001)
0.50 ± 0.04
1.30 ± 0.05
(0.0197 ± 0.0016)
(0.051 ± 0.002)
FOOTPRINT
NOTE:
1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
Characteristics subject to change without notice. 22 of 23
REV 1.1 2/1/01
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X28HC256
Ordering Information
X28HC256
X
X
-X
Access Time
–70 = 70ns
–90 = 90ns
–12 = 120ns
–15 = 150ns
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = MIL-STD-883
Package
P = 28-Lead Plastic DIP
D = 28-Lead CERDIP
J = 32-Lead PLCC
S = 28-Lead plastic SOIC
E = 32-Pad LCC
K = 28-Pin grid array
F = 28-Lead flat pack
T = 32-Lead TSOP
©Xicor, Inc. 2000 Patents Pending
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices
at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691;
5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection
and correction, redundancy and back-up features to prevent such an occurrence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 23 of 23
REV 1.1 2/1/01
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