X28C256DM-25 [XICOR]
5 Volt, Byte Alterable E2PROM; 5伏，可变的字节E2PROM
| 型号： | X28C256DM-25 |
| 厂家： | 
XICOR INC. |
| 描述： | 5 Volt, Byte Alterable E2PROM |
| 文件： | 总24页 (文件大小：114K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
256K
X28C256
32K x 8 Bit
5 Volt, Byte Alterable E2PROM
FEATURES
DESCRIPTION
2
• Access Time: 200ns
• Simple Byte and Page Write
— Single 5V Supply
—No External High Voltages or V Control
Circuits
— Self-Timed
The X28C256 is an 32K x 8 E PROM, fabricated with
Xicor’s proprietary, high performance, floating gate
CMOS technology. Like all Xicor programmable non-
volatile memories the X28C256 is a 5V only device. The
X28C256 features the JEDEC approved pinout for byte-
widememories,compatiblewithindustrystandardRAMs.
PP
—No Erase Before Write
—No Complex Programming Algorithms
—No Overerase Problem
• Low Power CMOS:
The X28C256 supports a 64-byte page write operation,
effectively providing a 78µs/byte write cycle and en-
abling the entire memory to be typically written in less
than 2.5 seconds. The X28C256 also features DATA
and Toggle Bit Polling, a system software support
scheme used to indicate the early completion of a write
cycle. In addition, the X28C256 includes a user-optional
software data protection mode that further enhances
Xicor’s hardware write protect capability.
—Active: 60mA
—Standby: 200µA
• Software Data Protection
— Protects Data Against System Level
Inadvertent Writes
• High Speed Page Write Capability
™
• Highly Reliable Direct Write Cell
2
Xicor E PROMs are designed and tested for applica-
— Endurance: 100,000 Write Cycles
— Data Retention: 100 Years
• Early End of Write Detection
— DATA Polling
tions requiring extended endurance. Inherent data re-
tention is greater than 100 years.
—Toggle Bit Polling
PIN CONFIGURATION
LCC
PLCC
PLASTIC DIP
CERDIP
FLAT PACK
SOIC
TSOP
A
A
A
I/O
I/O
I/O
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
A
A
A
A
A
A
NC
V
NC
2
1
0
0
1
2
3
4
5
6
7
12
14
A14
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
4
3
2
1
32 31 30
A
2
WE
12
A
A
A
A
A
A
A
5
6
7
8
9
29
28
27
26
25
24
23
22
21
A
A
A
6
5
4
3
2
1
0
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
3
A
13
9
4
A
8
A
9
NC
11
5
V
SS
NC
NC
OE
A
X28C256
6
A
9
11
X28C256
CC
I/O
10
11
12
13
14
15
16
7
OE
3
4
5
6
7
X28C256
I/O
I/O
I/O
I/O
WE
10
11
12
13
10
8
A
10
A
A
A
A
13
8
9
CE
I/O
9
CE
NC
7
10
11
12
13
14
I/O
7
I/O
6
I/O
5
I/0
4
CE
11
I/O
I/O
0
6
A
I/O
0
I/O
1
I/O
2
OE
10
14 15 16 17 18 19 20
3855 ILL F23
V
I/O
3
SS
3855 FHD F03
3855 FHD F02
© Xicor, Inc. 1991, 1995 Patents Pending
3855-1.9 8/1/97 T1/C0/D8 EW
Characteristics subject to change without notice
1
X28C256
PIN DESCRIPTIONS
PIN NAMES
Symbol
A –A
Addresses (A –A )
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
0
14
The Address inputs select an 8-bit memory location
during a read or write operation.
0
14
I/O –I/O
0
7
WE
CE
OE
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
writeoperations.WhenCEisHIGH,powerconsumption
is reduced.
V
CC
V
SS
Ground
Output Enable (OE)
NC
No Connect
TheOutputEnableinputcontrolsthedataoutputbuffers
and is used to initiate read operations.
3855 PGM T01
PIN CONFIGURATION
Data In/Data Out (I/O –I/O )
0
7
PGA
Data is written to or read from the X28C256 through the
I/O pins.
I/O
12
I/O
13
I/O
3
15
I/O
17
I/O
18
1
2
5
6
I/O
11
A
10
V
14
I/O
16
I/O
19
0
0
SS
4
7
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C256.
A
A
A
A
CE
20
A
21
1
3
2
4
10
11
9
7
8
6
X28C256
OE
22
A
23
A
A
V
28
A
24
A
25
5
6
12
7
CC
9
8
5
4
2
3
A
A
A
WE
27
A
13
26
14
1
3855 FHD F04
BOTTOM VIEW
FUNCTIONAL DIAGRAM
256K-BIT
E PROM
ARRAY
X BUFFERS
LATCHES AND
DECODER
2
A –A
0
14
ADDRESS
INPUTS
I/O BUFFERS
AND LATCHES
Y BUFFERS
LATCHES AND
DECODER
I/O –I/O
0
7
DATA INPUTS/OUTPUTS
CE
OE
WE
CONTROL
LOGIC AND
TIMING
V
CC
V
SS
3855 FHD F01
2
X28C256
DEVICE OPERATION
Read
Write Operation Status Bits
The X28C256 provides the user two write operation
status bits. These can be used to optimize a system
write cycle time. The status bits are mapped onto the
I/O bus as shown in Figure 1.
Read operations are initiated by both OE and CE LOW.
The read operation is terminated by either CE or OE
returning HIGH. This two line control architecture elimi-
natesbuscontentioninasystemenvironment. Thedata
bus will be in a high impedance state when either OE or
CE is HIGH.
Figure 1. Status Bit Assignment
Write
I/O DP TB
5
4
3
2
1
0
Write operations are initiated when bothCE and WE are
LOWandOEisHIGH.TheX28C256supportsbothaCE
and WE controlled write cycle. That is, the address is
latchedbythefallingedgeofeitherCEorWE,whichever
occurslast. Similarly, thedataislatchedinternallybythe
rising edge of either CE or WE, whichever occurs first.
A byte write operation, once initiated, will automatically
continue to completion, typically within 5ms.
RESERVED
TOGGLE BIT
DATA POLLING
3855 FHD F11
DATA Polling (I/O )
7
The X28C256 features DATA Polling as a method to
indicate to the host system that the byte write or page
writecyclehascompleted.DATAPollingallowsasimple
bittestoperationtodeterminethestatusoftheX28C256,
eliminating additional interrupt inputs or external hard-
ware. During the internal programming cycle, any at-
tempt to read the last byte written will produce the
Page Write Operation
The page write feature of the X28C256 allows the entire
memory to be written in 2.5 seconds. Page write allows
twotosixty-fourbytesofdatatobeconsecutivelywritten
to the X28C256 prior to the commencement of the
internal programming cycle. The host can fetch data
from another device within the system during a page
write operation (change the source address), but the
complement of that data on I/O (i.e. write data = 0xxx
7
xxxx, read data = 1xxx xxxx). Once the programming
cycle is complete, I/O will reflect true data. Note: If the
X28C256 is in the protected state and an illegal write
operation is attempted DATA Polling will not operate.
7
page address (A through A ) for each subsequent
6
14
valid write cycle to the part during this operation must be
the same as the initial page address.
Toggle Bit (I/O )
6
The page write mode can be initiated during any write
operation. Following the initial byte write cycle, the host
can write an additional one to sixty-three bytes in the
samemannerasthefirstbytewaswritten. Eachsucces-
sive byte load cycle, started by the WE HIGH to LOW
transition, must begin within 100µs of the falling edge of
the preceding WE. If a subsequent WE HIGH to LOW
transition is not detected within 100µs, the internal
automatic programming cycle will commence. There is
no page write window limitation. Effectively the page
write window is infinitely wide, so long as the host
continuestoaccessthedevicewithinthebyteloadcycle
time of 100µs.
The X28C256 also provides another method for deter-
mining when the internal write cycle is complete. During
the internal programming cycle I/O will toggle from
HIGH to LOW and LOW to HIGH on subsequent
attempts to read the device. When the internal cycle is
complete the toggling will cease and the device will be
accessible for additional read or write operations.
6
3
X28C256
DATA POLLING I/O
7
Figure 2. DATA Polling Bus Sequence
LAST
WRITE
WE
CE
OE
V
IH
V
HIGH Z
OH
I/O
7
V
OL
X28C256
READY
A –A
0
14
An
An
An
An
An
An
An
3855 FHD F12
Figure 3. DATA Polling Software Flow
DATA Polling can effectively halve the time for writing to
the X28C256. The timing diagram in Figure 2 illustrates
the sequence of events on the bus. The software flow
diagraminFigure3illustratesonemethodofimplement-
ing the routine.
WRITE DATA
NO
WRITES
COMPLETE?
YES
SAVE LAST DATA
AND ADDRESS
READ LAST
ADDRESS
IO
NO
7
COMPARE?
YES
X28C256
READY
3855 FHD F13
4
X28C256
THE TOGGLE BIT I/O
6
Figure 4. Toggle Bit Bus Sequence
LAST
WRITE
WE
CE
OE
V
OH
HIGH Z
I/O
6
*
*
V
OL
X28C256
READY
* Beginning and ending state of I/O will vary.
6
3855 FHD F14
Figure 5. Toggle Bit Software Flow
TheToggleBitcaneliminatethesoftwarehousekeeping
chore of saving and fetching the last address and data
written to a device in order to implement DATA Polling.
This can be especially helpful in an array comprised of
multiple X28C256 memories that is frequently updated.
The timing diagram in Figure 4 illustrates the sequence
of events on the bus. The software flow diagram in
Figure 5 illustrates a method for polling the Toggle Bit.
LAST WRITE
LOAD ACCUM
FROM ADDR n
COMPARE
ACCUM WITH
ADDR n
NO
COMPARE
OK?
YES
X28C256
READY
3855 FHD F15
5
X28C256
HARDWARE DATA PROTECTION
The X28C256 can be automatically protected during
power-upandpower-downwithouttheneedforexternal
circuits by employing the software data protection fea-
ture. The internal software data protection circuit is
enabled after the first write operation utilizing the soft-
warealgorithm. Thiscircuitisnonvolatileandwillremain
set for the life of the device unless the reset command
is issued.
The X28C256 provides three hardware features (com-
patible with X28C64) that protect nonvolatile data from
inadvertent writes.
• Noise Protection—A WE pulse typically less than
20ns will not initiate a write cycle.
• Default V Sense—All write functions are inhibited
CC
when V is ≤3.5V typically.
CC
Once the software protection is enabled, the X28C256
is also protected from inadvertent and accidental writes
in the powered-up state. That is, the software algorithm
must be issued prior to writing additional data to the
device.
• Write Inhibit—Holding either OE LOW, WE HIGH,
or CE HIGH will prevent an inadvertent write cycle
during power-up and power-down, maintaining data
integrity.
SOFTWARE DATA PROTECTION
Software Algorithm
The X28C256 offers a software controlled data protec-
tionfeature.TheX28C256isshippedfromXicorwiththe
software data protection NOT ENABLED; that is, the
device will be in the standard operating mode. In this
mode data should be protected during power-up/-down
operations through the use of external circuits. The host
would then have open read and write access of the
Selecting the software data protection mode requires
the host system to precede data write operations by a
series of three write operations to three specific ad-
dresses. Refer to Figure 6 and 7 for the sequence. The
three-byte sequence opens the page write window
enabling the host to write from one to sixty-four bytes of
data.* Once the page load cycle has been completed,
the device will automatically be returned to the data
protected state.
device once V was stable.
CC
*Note: Once the three-byte sequence is issued it
must be followed by a valid byte or page write
operation.
6
X28C256
SOFTWARE DATA PROTECTION
Figure 6. Timing Sequence—Byte or Page Write
V
(V
)
CC
CC
0V
DATA
AA
55
2AAA
A0
5555
t
t
WC
WRITE
PROTECTED
WPH2
ADDR. 5555
WRITES
OK
CE
≤t
BYTE
OR
PAGE
BLC MAX
WE
3855 FHD F16
Figure 7. Write Sequence for
Software Data Protection
Regardless of whether the device has previously been
protected or not, once the software data protection
algorithmisusedanddatahasbeenwritten,theX28C256
will automatically disable further writes unless another
command is issued to cancel it. If no further commands
are issued the X28C256 will be write protected during
power-down and after any subsequent power-up.
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITE DATA A0
TO ADDRESS
5555
BYTE/PAGE
LOAD ENABLED
WRITE DATA XX
TO ANY
ADDRESS
WRITE LAST
BYTE TO
LAST ADDRESS
AFTER t
RE-ENTERS DATA
WC
PROTECTED STATE
3855 FHD F17
7
X28C256
RESETTING SOFTWARE DATA PROTECTION
Figure 8. Reset Software Data Protection Timing Sequence
V
CC
STANDARD
OPERATING
MODE
DATA AA
ADDR. 5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
≥t
WC
CE
WE
3855 FHD F18
Figure 9. Software Sequence to
Deactivate Software Data Protection
In the event the user wants to deactivate the software
data protection feature for testing or reprogramming in
2
WRITE DATA AA
TO ADDRESS
5555
an E PROM programmer, the following six step algo-
rithm will reset the internal protection circuit. After t
the X28C256 will be in standard operating mode.
,
WC
Note: Onceinitiated,thesequenceofwriteoperations
should not be interrupted.
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 80
TO ADDRESS
5555
WRITE DATA AA
TO ADDRESS
5555
WRITE DATA 55
TO ADDRESS
2AAA
WRITE DATA 20
TO ADDRESS
5555
3855 FHD F19
8
X28C256
SYSTEM CONSIDERATIONS
prime concern. Enabling CE will cause transient current
spikes. The magnitude of these spikes is dependent on
the output capacitive loading of the I/Os. Therefore, the
larger the array sharing a common bus, the larger the
transient spikes. The voltage peaks associated with the
current transients can be suppressed by the proper
selection and placement of decoupling capacitors. As a
minimum, it is recommended that a 0.1µF high fre-
BecausetheX28C256isfrequentlyusedinlargememory
arrays it is provided with a two line control architecture
for both read and write operations. Proper usage can
provide the lowest possible power dissipation and elimi-
nate the possibility of contention where multiple I/O pins
share the same bus.
quency ceramic capacitor be used between V
and
To gain the most benefit it is recommended that CE be
decoded from the address bus and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation this assures that all deselected devices
are in their standby mode and that only the selected
device(s) is outputting data on the bus.
CC
V
SS
at each device. Depending on the size of the array,
the value of the capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between V and V for each
CC
SS
eight devices employed in the array. This bulk capacitor
is employed to overcome the voltage droop caused by
the inductive effects of the PC board traces.
Because the X28C256 has two power modes, standby
and active, proper decoupling of the memory array is of
Normalized Active Supply Current
vs. Ambient Temperature
Normalized Standby Supply Current
vs. Ambient Temperature
1.4
1.4
V
= 5V
V
= 5V
CC
CC
1.2
1.0
0.8
0.6
1.2
1.0
0.8
0.6
–55
+25
+125
–55
+25
+125
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
3855 FHD F20.1
3855 FHD F21.1
9
X28C256
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicatedintheoperationalsectionsofthisspecificationis
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
X28C256...................................... –10°C to +85°C
X28C256I, X28C256M............... –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Voltage on any Pin with
Respect to V
....................................... –1V to +7V
SS
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds).............................. 300°C
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
Limits
Temperature
Min.
Max.
X28C256
5V ±10%
Commercial
Industrial
Military
0°C
+70°C
+85°C
3855 PGM T03.1
–40°C
–55°C
+125°C
3855 PGM T02.1
D.C. OPERATING CHARACTERISTICS (over recommended operating conditions, unless otherwise specified)
Limits
(1)
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
CE = OE = V , WE = V ,
I
V
Current (Active)
30
60
mA
CC
CC
IL
IH
(TTL Inputs)
All I/O’s = Open, Address
Inputs = .4V/2.4V @ f = 5MHz
I
I
V
Current (Standby)
1
2
mA
CE = V , OE = V
IH IL
All I/O’s = Open, Other Inputs = V
SB1
CC
(TTL Inputs)
IH
(2)
V
CC
Current (Standby)
200
500
µA
CE = V – 0.3V, OE = V
IL
SB2
CC
(CMOS Inputs)
All I/O’s = Open,
Other Inputs = V – 0.3V
CC
I
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
V
V
= V to V
SS CC
LI
IN
= V to V , CE = V
IH
LO
OUT
SS
CC
(3)
V
V
V
V
–1
2
0.8
lL
(3)
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
+ 1
V
IH
CC
0.4
V
I
I
= 2.1mA
OL
OL
2.4
V
= –400µA
OH
OH
3855 PGM T04.2
Notes: (1) Typical values are for T = 25°C and nominal supply voltage and are not tested
A
(2) I
max. of 200µA available from Xicor. Contact local sales office and reference X28C256 C7125.
SB2
(3) V min. and V max. are for reference only and are not tested.
IL
IH
10
X28C256
ENDURANCE AND DATA RETENTION
Parameter
Min.
Units
Endurance
100,000
100
Cycles
Years
Data Retention
3855 PGM T05.3
POWER-UP TIMING
Symbol
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max.
Units
(4)
t
t
100
5
µs
PUR
(4)
ms
PUW
3855 PGM T06
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
Parameter
Max.
Units
Test Conditions
(4)
C
C
Input/Output Capacitance
Input Capacitance
10
6
pF
pF
V
V
= 0V
= 0V
I/O
I/O
(4)
IN
IN
3855 PGM T07.1
A.C. CONDITIONS OF TEST
MODE SELECTION
Input Pulse Levels
0V to 3V
CE
L
OE
L
WE
H
Mode
Read
Write
I/O
Power
Active
D
D
OUT
IN
Input Rise and
Fall Times
L
H
L
Active
10ns
1.5V
H
X
X
Standby and
Write Inhibit
High Z
Standby
Input and Output
Timing Levels
3855 PGM T08.1
X
X
L
X
H
Write Inhibit
Write Inhibit
—
—
—
X
—
3855 PGM T09
Note: (4) This parameter is periodically sampled and not 100% tested.
EQUIVALENT A.C. LOAD CIRCUIT
SYMBOL TABLE
5V
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
1.92KΩ
OUTPUT
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
1.37KΩ
100pF
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
3855 FHD F22.3
N/A
Center Line
is High
Impedance
11
X28C256
A.C. CHARACTERISTICS (over recommended operating conditions, unless otherwise specified)
Read Cycle Limits
X28C256-20 X28C256-25
X28C256
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Units
t
t
t
t
t
t
t
t
t
Read Cycle Time
200
250
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
RC
CE
AA
OE
Chip Enable Access Time
Address Access Time
200
200
80
250
250
100
300
300
100
Output Enable Access Time
CE LOW to Active Output
OE LOW to Active Output
CE HIGH to High Z Output
OE HIGH to High Z Output
(5)
0
0
0
0
0
0
LZ
(5)
OLZ
(5)
50
50
50
50
50
50
HZ
(5)
OHZ
OH
Output Hold from
Address Change
0
0
0
3855 PGM T10.1
Read Cycle
t
RC
ADDRESS
CE
t
CE
t
OE
OE
V
IH
WE
t
t
OLZ
OHZ
t
t
t
LZ
OH
HZ
HIGH Z
DATA I/O
DATA VALID
DATA VALID
t
AA
3855 FHD F05
Note: (5) t min., t , t
min., and t
are peridocally sampled and not 100% tested. t and t
are measured, with C = 5pF, from
OHZ L
LZ
HZ OLZ
OHZ
HZ
the point when CE or OE return HIGH (whichever occurs first) to the time when the outputs are no longer driven.
12
X28C256
WRITE CYCLE LIMITS
(9)
Min.
(6)
Typ.
Symbol
Parameter
Max.
Units
(7)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
Address Setup Time
Address Hold Time
Write Setup Time
Write Hold Time
CE Pulse Width
OE HIGH Setup Time
OE HIGH Hold Time
WE Pulse Width
WE HIGH Recovery
SDP WE Recovery
Data Valid
5
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
µs
WC
AS
0
150
0
AH
CS
0
CH
100
10
10
100
50
1
CW
OES
OEH
WP
WPH
WPH2
DV
(8)
1
Data Setup
50
10
10
1
DS
Data Hold
DH
Delay to Next Write
Byte Load Cycle
DW
(9)
100
µs
BLC
3855 PGM T11.1
WE Controlled Write Cycle
t
WC
ADDRESS
t
t
AS
AH
t
t
CS
CH
CE
OE
t
t
OES
t
OEH
t
WP
WE
DV
DATA IN
DATA OUT
DATA VALID
t
t
DS
DH
HIGH Z
3855 FHD F06
Notes: (6) Typical values are for T = 25°C and nominal supply voltage.
A
(7) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
WC
time the device requires to automatically complete the internal write operation.
(8) t is the normal page write operation WE recovery time. t is the WE recovery time needed only after the end of issuing
WPH
WPH2
the three-byte SDP command sequence and before writing the first byte of data to the array. Refer to Figure 6 which illustrates
the t requirement.
WPH2
(9) For faster t
and t
, refer to X28HC256 or X28VC256.
BLC
WC
13
X28C256
CE Controlled Write Cycle
t
WC
ADDRESS
t
t
AH
AS
t
CW
CE
t
OES
OE
t
OEH
t
t
CH
CS
WE
t
DV
DATA IN
DATA VALID
t
t
DH
DS
HIGH Z
DATA OUT
3855 FHD F07
Page Write Cycle
OE(10)
CE
t
t
BLC
WP
WE
t
WPH
ADDRESS* (11)
I/O
LAST BYTE
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
BYTE n+2
t
WC
*For each successive write within the page write operation, A –A should be the same or
14
6
writes to an unknown address could occur.
3855 FHD F08
Notes: (10) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE
HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively
performing a polling operation.
(11) The timings shown above are unique to page write operations. Individual byte load operations within the page write must
conform to either the CE or WE controlled write cycle timing.
14
X28C256
(12)
DATA Polling Timing Diagram
An
An
An
ADDRESS
CE
WE
t
t
OEH
OES
OE
t
DW
=X
D
=X
D
=X
D
I/O
7
IN
OUT
OUT
t
WC
3855 FHD F09
(12)
Toggle Bit Timing Diagram
CE
WE
t
t
OES
OEH
OE
t
DW
HIGH Z
I/O
6
*
*
t
WC
* Starting and ending state of I/O will vary, depending upon actual t
.
6
WC
3855 FHD F10
Note: (12) Polling operations are by definition read cycles and are therefore subject to read cycle timings.
15
X28C256
PACKAGING INFORMATION
28-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
1.470 (37.34)
1.400 (35.56)
0.557 (14.15)
0.510 (12.95)
PIN 1 INDEX
PIN 1
0.085 (2.16)
0.040 (1.02)
1.300 (33.02)
REF.
0.160 (4.06)
0.125 (3.17)
SEATING
PLANE
0.030 (0.76)
0.015 (0.38)
0.160 (4.06)
0.120 (3.05)
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.040 (1.02)
0.022 (0.56)
0.014 (0.36)
0.625 (15.88)
0.590 (14.99)
0°
TYP. 0.010 (0.25)
15°
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F04
16
X28C256
PACKAGING INFORMATION
28-LEAD HERMETIC DUAL IN-LINE PACKAGE TYPE D
1.490 (37.85) MAX.
0.610 (15.49)
0.500 (12.70)
PIN 1
0.005 (0.127) MIN.
0.100 (2.54) MAX.
SEATING
PLANE
0.232 (5.90) MAX.
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
0.125 (3.18)
0.150 (3.81) MIN.
0.110 (2.79)
0.090 (2.29)
0.065 (1.65)
0.038 (0.97)
0.023 (0.58)
0.014 (0.36)
TYP. 0.100 (2.54)
TYP. 0.055 (1.40)
TYP. 0.018 (0.46)
0.620 (15.75)
0.590 (14.99)
TYP. 0.614 (15.60)
0°
0.015 (0.38)
0.008 (0.20)
15°
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F08
17
X28C256
PACKAGING INFORMATION
32-LEAD PLASTIC LEADED CHIP CARRIER PACKAGE TYPE J
0.030" TYPICAL
32 PLACES
0.050"
0.420 (10.67)
TYPICAL
0.050"
TYPICAL
0.510"
TYPICAL
0.400"
0.050 (1.27) TYP.
0.300"
REF
0.410"
FOOTPRINT
0.021 (0.53)
0.013 (0.33)
TYP. 0.017 (0.43)
SEATING PLANE
±0.004 LEAD
CO – PLANARITY
—
0.045 (1.14) x 45°
0.015 (0.38)
0.095 (2.41)
0.495 (12.57)
0.485 (12.32)
TYP. 0.490 (12.45)
0.060 (1.52)
0.140 (3.56)
0.453 (11.51)
0.100 (2.45)
TYP. 0.136 (3.45)
0.447 (11.35)
TYP. 0.450 (11.43)
0.048 (1.22)
0.042 (1.07)
0.300 (7.62)
REF.
PIN 1
0.595 (15.11)
0.585 (14.86)
TYP. 0.590 (14.99)
0.553 (14.05)
0.547 (13.89)
TYP. 0.550 (13.97)
0.400
REF.
(10.16)
3° TYP.
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. DIMENSIONS WITH NO TOLERANCE FOR REFERENCE ONLY
3926 FHD F13
18
X28C256
PACKAGING INFORMATION
32-PAD CERAMIC LEADLESS CHIP CARRIER PACKAGE TYPE E
0.300 (7.62)
BSC
0.150 (3.81) BSC
0.020 (0.51) x 45° REF.
0.015 (0.38)
0.003 (0.08)
0.095 (2.41)
0.075 (1.91)
PIN 1
0.022 (0.56)
DIA.
0.006 (0.15)
0.055 (1.39)
0.200 (5.08)
BSC
0.045 (1.14)
TYP. (4) PLCS.
0.015 (0.38)
MIN.
0.028 (0.71)
0.040 (1.02) x 45° REF.
0.022 (0.56)
(32) PLCS.
TYP. (3) PLCS.
0.050 (1.27) BSC
0.458 (11.63)
0.088 (2.24)
0.050 (1.27)
0.442 (11.22)
0.120 (3.05)
0.458 (11.63)
––
0.060 (1.52)
0.558 (14.17)
––
0.560 (14.22)
0.540 (13.71)
0.400 (10.16)
BSC
PIN 1 INDEX CORNER
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. TOLERANCE: ±1% NLT ±0.005 (0.127)
3926 FHD F14
19
X28C256
PACKAGING INFORMATION
28-LEAD CERAMIC FLAT PACK TYPE F
0.019 (0.48)
0.015 (0.38)
PIN 1 INDEX
1
28
0.050 (1.27) BSC
0.740 (18.80)
MAX.
0.045 (1.14) MAX.
0.440 (11.18)
MAX.
0.130 (3.30)
0.090 (2.29)
0.006 (0.15)
0.003 (0.08)
0.370 (9.40)
0.250 (6.35)
0.045 (1.14)
0.025 (0.66)
TYP. 0.300 2 PLCS.
0.180 (4.57)
MIN.
0.030 (0.76)
MIN.
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F16
20
X28C256
PACKAGING INFORMATION
28-LEAD CERAMIC PIN GRID ARRAY PACKAGE TYPE K
12
11
9
13
10
8
15
14
17
16
20
22
24
27
18
19
21
23
25
26
A
A
0.008 (0.20)
0.050 (1.27)
7
6
5
2
28
1
NOTE: LEADS 4,12,18 & 26
4
3
0.080 (2.03)
0.070 (1.78)
TYP. 0.100 (2.54)
ALL LEADS
4 CORNERS
0.080 (2.03)
0.070 (1.78)
0.110 (2.79)
0.090 (2.29)
0.072 (1.83)
0.062 (1.57)
PIN 1 INDEX
0.020 (0.51)
0.016 (0.41)
0.660 (16.76)
0.640 (16.26)
A
A
0.185 (4.70)
0.175 (4.44)
0.561 (14.25)
0.541 (13.75)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F15
21
X28C256
PACKAGING INFORMATION
28-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.299 (7.59)
0.290 (7.37)
0.419 (10.64)
0.394 (10.01)
0.020 (0.508)
0.014 (0.356)
0.713 (18.11)
0.697 (17.70)
0.105 (2.67)
0.092 (2.34)
BASE PLANE
SEATING PLANE
0.012 (0.30)
0.003 (0.08)
0.050 (1.270)
BSC
0.050" TYPICAL
0.0200 (0.5080)
X 45°
0.0100 (0.2540)
0.050"
TYPICAL
0.013 (0.32)
0.008 (0.20)
0° – 8°
0.42" MAX
0.0350 (0.8890)
0.0160 (0.4064)
0.030" TYPICAL
28 PLACES
FOOTPRINT
NOTES:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. FORMED LEAD SHALL BE PLANAR WITH RESPECT TO ONE ANOTHER WITHIN 0.004 INCHES
3926 FHD F17
22
X28C256
PACKAGING INFORMATION
32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) TYPE T
SEE NOTE 2
12.50 (0.492)
12.30 (0.484)
PIN #1 IDENT.
O 0.76 (0.03)
0.50 (0.0197) BSC
SEE NOTE 2
8.02 (0.315)
7.98 (0.314)
0.26 (0.010)
0.14 (0.006)
1.18 (0.046)
1.02 (0.040)
0.17 (0.007)
0.03 (0.001)
SEATING
PLANE
0.58 (0.023)
0.42 (0.017)
14.15 (0.557)
13.83 (0.544)
14.80 ± 0.05
(0.583 ± 0.002)
0.30 ± 0.05
(0.012 ± 0.002)
SOLDER PADS
TYPICAL
32 PLACES
15 EQ. SPC. 0.50 ± 0.04
0.0197 ± 0.016 = 7.50 ± 0.06
(0.295 ± 0.0024) OVERALL
TOL. NON-CUMULATIVE
0.17 (0.007)
0.03 (0.001)
0.50 ± 0.04
(0.0197 ± 0.0016)
1.30 ± 0.05
(0.051 ± 0.002)
FOOTPRINT
NOTE:
1. ALL DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES IN PARENTHESES).
3926 ILL F38.1
23
X28C256
ORDERING INFORMATION
X28C256
X
X
-X
Access Time
–20 = 200ns
–25 = 250ns
Blank = 300ns
–35 = 350ns
Device
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
MB = MIL-STD-883
Package
P = 28-Lead Plastic DIP
D = 28-Lead Cerdip
J = 32-Lead PLCC
E = 32-Pad LCC
F = 28-Lead Flat Pack
K = 28-Lead Pin Grid Array
S = 28-Lead Plastic SOIC
T = 32-Lead TSOP
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
24
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