X25C02MI [XICOR]
SPI Serial E2PROM; SPI串行E2PROM
| 型号： | X25C02MI |
| 厂家： | 
XICOR INC. |
| 描述： | SPI Serial E2PROM |
| 文件： | 总14页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
APPLICATION NOTES
A V A I L A B L E
AN9 • AN18 • AN31 • AN37 • AN40
2K
X25C02
256 x 8 Bit
SPI Serial E2PROM
FEATURES
DESCRIPTION
The X25C02 is a CMOS 2048-bit serial E2PROM, inter-
nallyorganizedas256x8. TheX25C02featuresaserial
interface and software protocol allowing operation on a
simple three-wire bus. The bus signals are a clock input
(SCK) plus separate data in (SI) and data out (SO) lines.
Access to the device is controlled through a chip select
(CS) input, allowing any number of devices to share the
same bus.
• 1MHz Clock Rate
• 256 X 8 Bits
—4 Byte Page Mode
• Low Power CMOS
—150µA Standby Current
—2mA Active Current
• 5V Power Supply
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down protection circuitry
—Write Latch
The X25C02 also features two additional inputs that
provide the end user with added flexibility. By asserting
the HOLD input, theX25C02willignoretransitionsonits
inputs, thus allowing the host to service higher priority
interrupts.TheWPinputcanbeusedasahardwireinput
to the X25C02 disabling all write attempts, thus provid-
ing a mechanism for limiting end user capability of
altering the memory.
—Write Protect Pin
• Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• High Reliability
—Endurance: 100,000 cycles per byte
—Data Retention: 100 Years
—ESD protection: 2000V on all pins
• Available Packages
The X25C02 utilizes Xicor’s proprietary Direct Write™
cell, providing a minimum endurance of 100,000 cycles
per byte and a minimum data retention of 100 years.
—8-Lead MSOP
—8-Lead PDlP
—8-Lead SOIC
FUNCTIONAL DIAGRAM
SO
COMMAND
DECODE
AND
CONTROL
LOGIC
SI
64
X
256 BYTE ARRAY
(64 X 32)
DECODE
LOGIC
SCK
CS
HOLD
4
8
WRITE
CONTROL
AND
Y DECODE
DATA REGISTER
TIMING
LOGIC
WP
3843 FHD F01
™
Direct Write is a trademark of Xicor, Inc.
©Xicor, Inc. 1994, 1995, 1996 Patents Pending
3843-1.6 6/10/96 T5/C1/D1 NS
Characteristics subject to change without notice
1
X25C02
PIN DESCRIPTIONS
Serial Output (SO)
in the standby power mode. CS LOW enables the
X25C02,placingitintheactivepowermode.Itshouldbe
noted that after power-up, a HIGH to LOW transition on
CS is required prior to the start of any operation.
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
Write Protect (WP)
When WP is LOW, nonvolatile writes to the X25C02 are
disabled, but the part otherwise functions normally.
WhenWP isheldHIGH, allfunctions, includingnonvola-
tile writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25C02. If the
internal write cycle has already been initiated, WP going
LOW will have no affect on a write.
Serial Input (SI)
SI is the serial data input pin. All data, opcodes, byte
addresses, and data to be written to the memory are
input on this pin. Data is latched by the rising edge of the
serial clock.
Serial Clock (SCK)
Hold (HOLD)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin are sampled or latched on the rising edge
of the clock input, while data on the SO pin change after
the falling edge of the clock input.
HOLD is used in conjunction with the CS pin to select the
device.Oncethepartisselectedandaserialsequenceis
underway, HOLD may be used to pause the serial
communication with the controller without resetting
the serial sequence. To pause, HOLD must be brought
LOW while SCK is LOW. To resume communication,
HOLD is brought HIGH, again while SCK is LOW. If the
pause feature is not used, HOLD should be held HIGH
at all times.
Chip Select (CS)
When CS is HIGH, the X25C02 is deselected and the
SO output pin is at HIGH impedance and unless an
internal write operation is underway, the X25C02 will be
PIN CONFIGURATION
PIN NAMES
Symbol
CS
SO
Description
Chip Select Input
Serial Output
Serial Input
MSOP/DIP/SOIC
CS
SO
WP
1
2
3
4
8
7
6
5
V
CC
SI
HOLD
SCK
SI
X25C02
SCK
WP
VSS
Serial Clock Input
Write Protect Input
Ground
V
SS
VCC
HOLD
Supply Voltage
Hold Input
3843 FHD F02.2
3843 PGM T01
2
X25C02
PRINCIPLES OF OPERATION
the clock and then resume operations. If the clock line is
shared with other peripheral devices on the SPI bus, the
usercanasserttheHOLD inputtoplacetheX25C02into
a“PAUSE”condition.AfterreleasingHOLD,theX25C02
will resume operation from the point when HOLD was
first asserted.
The X25C02 is a 256 x 8 E2PROM designed to interface
directly with the synchronous serial peripheral interface
(SPI) of many popular microcontroller families.
The X25C02 contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
therisingSCK. CS mustbeLOWandtheHOLD andWP
inputs must be HIGH during the entire operation.
Write Enable (WREN) and Write Disable (WRDI)
The X25C02 contains a “write enable” latch. This latch
must be SET before a write operation will be completed
internally. The WREN instruction will set the latch and
the WRDI instruction will reset the latch. This latch is
automatically reset upon a power-up condition and after
the completion of a byte or page write cycle. The latch is
also reset if WP is brought LOW.
Table 1 contains a list of the instructions and their
opcodes. All instructions, addresses and data are trans-
ferred MSB first.
DatainputissampledonthefirstrisingedgeofSCKafter
CS goes LOW. SCK is static, allowing the user to stop
Table 1. Instruction Set
Instruction Name
WREN
Instruction Format*
0000 0110
Operation
Set the Write Enable Latch (Enable Write Operations)
Reset the Write Enable Latch (Disable Write Operations)
WRDI
0000 0100
Read Data from Memory Array beginning at selected ad-
dress
READ
0000 0011
0000 0010
Write Data to Memory Array beginning at Selected Address
(1 to 4 Bytes)
WRITE
3843 PGM T02
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
3
X25C02
DEVICE OPERATION
Clock and Data Timing
Once the “write enable” latch is set, the user may
proceed by issuing the write instruction, followed by the
addressandthenthedatatobewritten.Thisisminimally
a twenty-four clock operation. CS must go LOW and
remain LOW for the duration of the operation. The host
may continue to write up to four bytes of data to the
X25C02. The only restriction is the four bytes must
reside on the same page. A page address begins with
address XXXX XX00 and ends with XXXX XX11. If the
byteaddresscounterreachesXXXXXX11andtheclock
continues the counter will “roll over” to the first address
of the page and overwrite any data that may have been
written.
Data input on the SI line is sampled and latched on the
rising edge of SCK. Data is output on the SO line by the
falling edge of SCK.
Read Sequence
The CS line is first pulled LOW to select the device. The
8-bit read opcode is transmitted to the X25C02, fol-
lowed by the 8-bit address. After the READ opcode and
byte address are sent, the data stored in the memory
at the selected address is shifted out on the SO line.
The data stored in memory at the next address can be
readsequentiallybycontinuingtoprovideclockpulses.
The byte address is automatically incremented to the
next higher address after each byte of data is shifted
out. When the highest address is reached ($FF) the
address counter rolls over to address $00 allowing the
read cycle to be continued indefinitely. The read opera-
tion is terminated by taking CS HIGH. Refer to the read
operation sequence illustrated in Figure 1.
For the write operation (byte or page write) to be
completed, CS can only be brought HIGH after the
twenty-fourth, thirty-second, fourtieth or fourty-eighth
clock. If it is brought HIGH at any other time, the write
operation will not be completed. Refer to Figure 4 for a
detailed illustration of the page write sequence and time
frames in which CS going HIGH are valid.
Hold Operation
Write Sequence
The HOLD input should be HIGH (at VIH) under normal
operation. If a data transfer is to be interrupted HOLD
canbepulledLOWtosuspendthetransferuntilitcanbe
resumed. The only restriction is the SCK input must be
LOW when HOLD is first pulled low and SCK must also
be LOW when HOLD is released.
Prior to any attempt to write data into the X25C02, the
“write enable” latch must first be set by issuing the
WREN instruction (See Fig. 2). CS is first taken LOW,
then the instruction is clocked into the X25C02. After all
eightbitsoftheinstructionaretransmitted,CSmustthen
be taken HIGH. If the user continues the write operation
without taking CS HIGH after issuing the WREN instruc-
tion, the write operation will be ignored.
The HOLD input may be tied HIGH either directly to VCC
or tied to VCC through a resistor.
4
X25C02
Operational Notes
Data Protection
The X25C02 powers-up in the following state:
• The device is in the low power standby state.
The following circuitry has been included to prevent
inadvertent writes:
• The “write enable” latch is reset upon power-up.
• A HIGH to LOW transition on CS is required to
enter an active state and receive an instruction.
• A WREN instruction must be issued to set the “write
enable” latch.
• SO pin is high impedance.
• CS must come HIGH at the proper clock count in
order to start a write cycle.
• The “write enable” latch is reset.
The “write enable” latch is reset when WP is brought LOW.
Figure 1. Read Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
SCK
SI
INSTRUCTION
BYTE ADDRESS
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
3843 FHD F04.1
Figure 2. Set Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
HIGH IMPEDANCE
3843 FHD F05.1
SO
5
X25C02
Figure 3. Byte Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
7
9
6
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
INSTRUCTION
BYTE ADDRESS
DATA BYTE
5
4
3
2
1
0
7
6
5
4
3
2
1
0
HIGH IMPEDANCE
SO
3843 FHD F06.2
Figure 4. Page Write Operation Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
SI
INSTRUCTION
BYTE ADDRESS
DATA BYTE 1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
CS
SCK
SI
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
DATA BYTE 2
DATA BYTE 3
DATA BYTE 4
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
3843 FHD F07.2
6
X25C02
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias .................. –65°C to +135°C
Storage Temperature ....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is
not implied. Exposure to absolute maximum rating con-
ditions for extended periods may affect device reliability.
Voltage on any Pin with Respect to V ......... –1V to +7V
SS
D.C. Output Current ............................................. 5mA
Lead Temperature
(Soldering, 10 seconds).............................. 300°C
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
Limits
Temp
Min.
0°C
Max.
+70°C
+85°C
X25C02
5V ±10%
Commercial
Industrial
Military
3843 PGM T04.1
–40°C
–55°C
+125°C
3843 PGM T03.1
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
SCK = V x 0.1/V x 0.9 @ 1MHz,
SO = Open
I
V
V
Supply Current (Active)
2
mA
CC
CC
CC
CC
I
I
I
Supply Current (Standby)
150
10
µA
µA
µA
V
CS = V , V = V or V
– 0.3V
CC
SB
CC
CC
IN
SS
Input Leakage Current
Output Leakage Current
Input LOW Voltage
V
V
= V to V
SS CC
LI
IN
10
= V to V
SS CC
LO
OUT
(1)
V
V
V
V
–1
V
x 0.3
IL
CC
(1)
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
V
x 0.7 V
+ 0.5
V
IH
CC
CC
0.4
V
I = 2mA
OL
OL
OH
V
–0.8
V
I = –1mA
OH
CC
3843 PGM T05.3
POWER-UP TIMING
Symbol
Parameter
Min.
Max.
Units
(1)
t
Power-up to Read Operation
Power-up to Write Operation
1
5
ms
PUR
(1)
t
ms
PUW
3843 PGM T09
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V.
A
CC
Symbol
Test
Max.
Units
Conditions
= 0V
(2)
C
C
Output Capacitance (SO)
8
6
pF
pF
V
OUT
OUT
(2)
IN
Input Capacitance (SCK, SI, CS, WP, HOLD)
V
= 0V
3843 PGM T06.1
IN
Notes: (1) VIL min. and VIH max. are for reference only and are not tested.
(2) This parameter is periodically sampled and not 100% tested.
7
X25C02
EQUIVALENT A.C. LOAD CIRCUIT
A.C. TEST CONDITIONS
InputPulseLevels
V
CC
x0.1toV x0.9
CC
5V
InputRiseandFallTimes
InputandOutputTimingLevel
10ns
2.16KΩ
V
x0.5
CC
3843 PGM T07
OUTPUT
3.07KΩ
100pF
3843 FHD F12.1
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data Input Timing
Symbol
Parameter
Clock Frequency
Cycle Time
Min.
0
Max.
Units
MHz
ns
f
t
t
t
t
t
t
t
t
t
t
t
t
t
1
SCK
CYC
LEAD
LAG
WH
WL
SU
1000
500
500
400
400
100
100
CS Lead Time
CS Lag Time
ns
ns
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Data In Rise Time
Data In Fall Time
HOLD Setup Time
HOLD Hold Time
CS Deselect Time
Write Cycle Time
ns
ns
ns
ns
H
2
2
µs
RI
µs
FI
200
200
500
ns
HD
CD
CS
ns
ns
(3)
10
ms
3843 PGM T08.2
WC
Data Output Timing
Symbol
Parameter
Min.
Max.
Units
f
t
t
t
t
t
t
t
Clock Frequency
0
1
MHz
ns
SCK
DIS
V
Output Disable Time
Output Valid from clock Low
Output Hold Time
500
400
ns
0
ns
HO
(1)
Output Rise Time
300
300
ns
RO
(1)
Output Fall Time
ns
FO
LZ
HOLD HIGH to Output in Low Z
HOLD LOW to Output in High Z
100
100
ns
ns
HZ
3843 PGM T09.1
Notes: (3) t
is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal
nonvolatile write cycle.
WC
8
X25C02
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tV
tHO
tWL
tDIS
SO
MSB OUT
MSB–1 OUT
LSB OUT
ADDR
LSB IN
SI
3843 FHD F09.1
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
tRI
tFI
SI
MSB IN
LSB IN
HIGH IMPEDANCE
SO
3843 FHD F10
9
X25C02
Hold Timing
CS
SCK
SO
tHD
tCD
tCD
tHD
tHZ
tLZ
SI
HOLD
3843 FHD F11
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
10
X25C02
PACKAGING INFORMATION
8-LEAD MINIATURE SMALL OUTLINE GULL WING PACKAGE TYPE M
0.118 ± 0.002
(3.00 ± 0.05)
0.012 + 0.006 / -0.002
(0.30 + 0.15 / -0.05)
0.0256 (0.65) TYP
R 0.014 (0.36)
0.118 ± 0.002
(3.00 ± 0.05)
0.030 (0.76)
0.0216 (0.55)
7° TYP
0.036 (0.91)
0.032 (0.81)
0.040 ± 0.002
(1.02 ± 0.05)
0.008 (0.20)
0.004 (0.10)
0.150 (3.81)
0.007 (0.18)
0.005 (0.13)
REF.
0.193 (4.90)
REF.
NOTE:
1. ALL DIMENSIONS IN INCHES AND (MILLIMETERS)
3926 ILL F49
11
X25C02
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.065 (1.65)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0.015 (0.38)
MAX.
0°
15°
TYP. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
12
X25C02
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.050" TYPICAL
X 45°
0.020 (0.50)
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
13
X25C02
ORDERING INFORMATION
X25C02
P
T
-V
V
CC
Limits
Device
Blank = 5V ±10%
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
M = 8-Lead MSOP
P = 8-Lead Plastic DIP
S = 8-Lead SOIC
Part Mark Convention
Blank = 8-Lead SOIC
P = 8-Lead Plastic DIP
X25C02
X
X
Blank = 5V ±10%, 0°C to +70°C
I = 5V ±10%, –40°C to +85°C
M = 5V ±10%, –55°C to +125°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
14
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