X25328S8I [XICOR]
V CC Supervisory Circuit w/Serial E 2 PROM; V CC监控电路W /串行ë 2 PROM
| 型号： | X25328S8I |
| 厂家： | 
XICOR INC. |
| 描述： | V CC Supervisory Circuit w/Serial E 2 PROM |
| 文件： | 总16页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
64K
32K
16K
X25648/49,
X25328/29,
X25168/69
8K x 8 Bit
4K x 8 Bit
2K x 8 Bit
V
Supervisory Circuit w/Serial E2PROM
CC
FEATURES
DESCRIPTION
• Low Vcc Detection and Reset Assertion
—Reset Signal Valid to Vcc=1V
• Save Critical Data With Block LockTM Protection
—Block LockTM Protect 0, 1/4, 1/2 or all of
Serial E2PROM Memory Array
• In Circuit Programmable ROM Mode
• Long Battery Life With Low Power Consumption
—<1µA Max Standby Current
—<5mA Max Active Current during Write
—<400µA Max Active Current during Read
• 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power
Supply Operation
• 2MHz Clock Rate
• Minimize Programming Time
—32 Byte Page Write Mode
—Self-Timed Write Cycle
—5ms Write Cycle Time (Typical)
• SPI Modes (0,0 & 1,1)
These devices combines two popular functions, Supply
Voltage Supervision and Serial E2PROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
The user’s system is protected from low voltage condi-
tions by the devices low Vcc detection circuitry. When
Vcc falls below the minimum Vcc trip point, the system is
reset. RESET/RESET is asserted until Vcc returns to
proper operating levels and stabilizes.
The memory portion of the device is a CMOS Serial
E2PROM array with Xicor’s Block LockTM Protection. The
array is internally organized as x 8.The device features a
Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct WriteTM cell,
providing a minimum endurance of 100,000 cycles per
sector and a minimum data retention of 100 years.
• Built-in Inadvertent Write Protection
—Power-Up/Power-Down Protection Circuitry
—Write Enable Latch
—Write Protect Pin
• High Reliability
• Available Packages
—14-Lead SOIC (X2564X)
—14-Lead TSSOP (X2532X, X2516X)
—8-Lead SOIC (X2532X, X2516X)
BLOCK DIAGRAM
SI
DATA
PAGE DECODE LOGIC
REGISTER
SO
32
8
COMMAND
DECODE &
CONTROL
LOGIC
X - DECODE
LOGIC
SCK
CS
SERIAL
E2PROM
ARRAY
STATUS
REGISTER
RESET
CONTROL
RESET/RESET
LOW
VOLTAGE
SENSE
V
CC
HIGH
VOLTAGE
CONTROL
PROGRAMMING,
BLOCK LOCK &
ICP ROM CONTROL
WP
7036 FRM 01
Xicor, Inc. 1994, 1995, 1996 Patents Pending
7032 -1.1 6/17/97 T1/C0/D0 SH
Characteristics subject to change without notice
1
X25648/49, X25328/29, X25168/69
PIN DESCRIPTIONS
Serial Output (SO)
PIN CONFIGURATION
14-LEAD SOIC
14
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out by
the falling edge of the serial clock.
NC
CS
CS
SO
WP
1
NC
V
2
3
4
5
6
7
13
12
11
10
9
CC
V
CC
X25648/49
Serial Input (SI)
RESET/RESET
SI is a serial data input pin. All opcodes, byte addresses,
and data to be written to the memory are input on this pin.
Data is latched by the rising edge of the serial clock.
SCK
SI
V
SS
NC
8
NC
Serial Clock (SCK)
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present on
the SI pin are latched on the rising edge of the clock input,
while data on the SO pin change after the falling edge of
the clock input.
8-LEAD SOIC
V
1
8
CS
SO
WP
CC
X25328/29
X25168/69
2
3
4
7
6
5
RESET/RESET
SCK
SI
Chip Select (CS)
V
SS
When CS is HIGH, the device is deselected and the SO
output pin is at high impedance and unless a nonvolatile
write cycle is underway, the device will be in the standby
power mode. CS LOW enables the device, placing it in
the active power mode. It should be noted that after
power-up, a HIGH to LOW transition on CS is required
prior to the start of any operation.
14-LEAD TSSOP
V
1
2
3
4
5
6
7
14
13
12
11
10
9
CS
SO
NC
CC
RESET/RESET
NC
NC
NC
SCK
SI
Write Protect (WP)
X25328/29
X25168/69
NC
NC
WP
When WP is low and the nonvolatile bit WPEN is “1”,
nonvolatile writes to the device Status Register are
disabled, but the part otherwise functions normally. When
WP is held high, all functions, including nonvolatile writes
to the Status Register operate normally. If an internal
Status Register Write Cycle has already been initiated,
WP going low while WPEN is a “1” will have no effect on
this write. Subsequent write attempts to the Status
Register under these conditions will be disabled.
V
SS
8
7036 FRM 02
PIN NAMES
The WP pin function is blocked when the WPEN bit in the
Status Register is “0”. This allows the user to install the
device in a system with WP pin grounded and still be able
to program the Status Register. The WP pin functions will
be enabled when the WPEN bit is set to a “1”.
Symbol
CS
Description
Chip Select Input
Serial Output
SO
SI
Serial Input
Reset (RESET/RESET)
SCK
WP
Serial Clock Input
Program Protect Input
Ground
RESET/RESET is an active LOW/HIGH, open drain out-
put which goes active whenever Vcc falls below the mini-
mum Vcc sense level. It will remain active until Vcc rises
above the minimum Vcc sense level for 200ms.
V
SS
CC
V
Supply Voltage
RESET/RESET Reset Output
7036 FRM T01
2
X25648/49, X25328/29, X25168/69
PRINCIPLES OF OPERATION
The Write-In-Progress (WIP) bit is a volatile, read only bit
and indicates whether the device is busy with an internal
nonvolatile write operation. The WIP bit is read using the
RDSR instruction. When set to a “1”, a nonvolatile write
operation is in progress. When set to a “0”, no write is in
progress.
The device is designed to interface directly with the syn-
chronous Serial Peripheral Interface (SPI) of many popu-
lar microcontroller families.
The device monitors V
and asserts RESET/RESET
CC
output if the supply voltage falls below a preset minimum
. The device contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in on
the rising edge of SCK. CS must be LOW during the
entire operation.
The Write Enable Latch (WEL) bit indicates the Status of
the Write Enable Latch. When WEL=1, the latch is set
HIGH and when WEL=0 the latch is reset LOW. The WEL
bit is a volatile, read only bit. It can be set by the WREN
instruction and can be reset by the WRDS instruction.
V
trip
All instructions (Table 1), addresses and data are trans-
ferred MSB first. Data input on the SI line is latched on the
first rising edge of SCK after CS goes LOW. Data is out-
put on the SO line by the falling edge of SCK. SCK is
static, allowing the user to stop the clock and then start it
again to resume operations where left off.
The Block Lock bits, BL0 and BL1, set the level of Block
LockTM Protection. These nonvolatile bits are pro-
grammed using the WRSR instruction and allow the user
to protect one quarter, one half, all or none of the
E2PROM array. Any portion of the array that is Block Lock
Protected can be read but not written. It will remain pro-
tected until the BL bits are altered to disable Block Lock
Protection of that portion of memory.
Write Enable Latch
The device contains a Write Enable Latch.This latch must
be SET before a Write Operation is initiated. The WREN
instruction will set the latch and the WRDI instruction will
reset the latch (Figure 3). This latch is automatically reset
upon a power-up condition and after the completion of a
valid Write Cycle.
Status
Register
Bits
Array Addresses Protected
BL1 BL0
X2564X
X2532X
X2516X
0
0
1
1
0
1
0
1
None
None
None
Status Register
$1800–$1FFF $0C00–$0FFF $0600–$07FF
$1000–$1FFF $0800–$0FFF $0400–$07FF
The RDSR instruction provides access to the Status Reg-
ister. The Status Register may be read at any time, even
during a Write Cycle. The Status Register is formatted as
follows:
$0000–$1FFF $0000–$0FFF $0000–$07FF
7036 FRM T03
Bits 4 and 5 of the Status Register will be read as “1’s”
and must be written as “1’s” on all Status Register writes.
7
6
5
1
4
1
3
2
1
0
WPEN FLB
BL1 BL0 WEL WIP
7036 FRM T02
Table 1. Instruction Set
Instruction Name Instruction Format*
Operation
WREN
SFLB
0000 0110
0000 0000
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Set the Write Enable Latch (Enable Write Operations)
Set Flag Bit
WRDI/RFLB
RSDR
Reset the Write Enable Latch/Reset Flag Bit
Read Status Register
WRSR
Write Status Register (BlockLock,WPEN & Flag Bits)
Read Data from Memory Array Beginning at Selected Address
Write Data to Memory Array Beginning at Selected Address
READ
WRITE
*Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.
7036 FRM T04
3
X25648/49, X25328/29, X25168/69
The read only FLAG bit shows the status of a volatile latch
that can be set and reset by the system using the SFLB
and RFLB instructions. The Flag bit is automatically reset
upon power up.
To read the Status Register, the CS line is first pulled low
to select the device followed by the 8-bit RDSR instruc-
tion. After the RDSR opcode is sent, the contents of the
Status Register are shifted out on the SO line. Refer to
the Read Status Register Sequence (Figure 2).
The nonvolatile WPEN bit is programmed using the
WRSR instruction. This bit works in conjunction with the
WP pin to provide Programmable Hardware Write Protec-
tion (Table 2). When WP is LOW and the WPEN bit is pro-
grammed HIGH, all Status Register Write Operations are
disabled.
Write Sequence
Prior to any attempt to write data into the device, the
“Write Enable” Latch (WEL) must first be set by issuing
the WREN instruction (Figure 3). CS is first taken LOW,
then the WREN instruction is clocked into the device.
After all eight bits of the instruction are transmitted, CS
must then be taken HIGH. If the user continues the Write
Operation without taking CS HIGH after issuing the
WREN instruction, the Write Operation will be ignored.
In Circuit Programmable ROM Mode
This mechanism protects the Block Lock and Watchdog
bits from inadvertant corruption. It may be used to per-
form an In Circuit Programmable ROM function by hard-
wiring the WP pin to ground, writing and Block Locking
the desired portion of the array to be ROM, and then pro-
gramming the WPEN bit HIGH.
To write data to the E2PROM memory array, the user then
issues the WRITE instruction followed by the 16 bit
address and then the data to be written. Any unused bits
are specified to be “0’s”. The WRITE operation minimally
takes 32 clocks. CS must go low and remain low for the
duration of the operation. If the address counter reaches
the end of a page and the clock continues, the counter will
roll back to the first address of the page and overwrite any
data that may have been previously written.
Read Sequence
When reading from the E2PROM memory array, CS is
first pulled low to select the device. The 8-bit READ
instruction is transmitted to the device, followed by the 16-
bit address. After the READ opcode and address are
sent, the data stored in the memory at the selected
address is shifted out on the SO line. The data stored in
memory at the next address can be read sequentially by
continuing to provide clock pulses. The address is auto-
matically incremented to the next higher address after
each byte of data is shifted out.When the highest address
is reached, the address counter rolls over to address
$0000 allowing the read cycle to be continued indefinitely.
The read operation is terminated by taking CS high. Refer
to the Read E2PROM Array Sequence (Figure 1).
For the Page Write Operation (byte or page write) to be
completed, CS can only be brought HIGH after bit 0 of the
last data byte to be written is clocked in. If it is brought
HIGH at any other time, the write operation will not be
completed (Figure 4).
To write to the Status Register, the WRSR instruction is
followed by the data to be written (Figure 5). Data bits 0
and 1 must be “0”. Data bits 4 and 5 must be “1”.
Table 2.
STATUS
REGISTER
STATUS
REGISTER
DEVICE
PIN
STATUS
REGISTER
BLOCK
BLOCK
PROTECTED
BLOCK
UNPROTECTED
BLOCK
WPEN, BL0,
BL1 BITS
WEL
WPEN
WP#
0
1
1
1
X
1
0
X
X
0
X
1
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
Protected
Protected
Writable
Writable
7036 FRM T06
4
X25648/49, X25328/29, X25168/69
While the write is in progress following a Status Register
or E2PROM Sequence, the Status Register may be read
to check the WIP bit. During this time the WIP bit will be
high.
Operational Notes
The device powers-up in the following state:
• The device is in the low power standby state.
• A HIGH to LOW transition on CS is required to enter an
active state and receive an instruction.
• SO pin is high impedance.
RESET/RESET Operation
The RESET (X25XX3) output is designed to go LOW
whenever V has dropped below the minimum trip point,
• The Write Enable Latch is reset.
CC
V
.
• The Flag Bit is reset.
trip
• Reset Signal is active for t
.
PURST
The RESET (X25XX5) output is designed to go HIGH
whenever V has dropped below the minimum trip point,
Data Protection
CC
V
.
trip
The following circuitry has been included to prevent inad-
vertent writes:
The RESET/RESET output is an open drain output and
requires a pull up resistor.
• A WREN instruction must be issued to set the Write
Enable Latch.
• CS must come HIGH at the proper clock count in order
to start a nonvolatile write cycle.
Figure 1. Read E2PROM Array Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
SI
INSTRUCTION
16 BIT ADDRESS
15 14 13
3
2
1
0
DATA OUT
HIGH IMPEDANCE
7
6
5
4
3
2
1
0
SO
MSB
7036 FRM 03
5
X25648/49, X25328/29, X25168/69
Figure 2. Read Status Register Sequence
CS
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
SCK
INSTRUCTION
SI
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
7036 FRM 04
Figure 3. Write Enable Latch Sequence
CS
0
1
2
3
4
5
6
7
SCK
SI
HIGH IMPEDANCE
SO
7036 FRM 05
6
X25648/49, X25328/29, X25168/69
Figure 4. Write Sequence
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30 31
SCK
INSTRUCTION
16 BIT ADDRESS
15 14 13
DATA BYTE 1
3
2
1
0
7
6
5
4
3
2
1
0
SI
CS
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
SCK
SI
DATA BYTE 2
DATA BYTE 3
DATA BYTE N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
6
5
4
3
2
1
0
7036 FRM 06
Figure 5. Status Register Write Sequence
CS
0
1
2
3
4
5
6
7
8
7
9
10 11 12 13 14 15
SCK
INSTRUCTION
DATA BYTE
6
5
4
3
2
1
0
SI
HIGH IMPEDANCE
SO
7036 FRM 07
Symbol Table
WAVEFORM
INPUTS
OUTPUTS
Must be
steady
Will be
steady
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
N/A
Center Line
is High
Impedance
7
X25648/49, X25328/29, X25168/69
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias ........................–65°Cto+135°C
Storage Temperature .............................–65°Cto+150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
listed in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Voltage on any Pin with Respect to V ....... –1.0V to +7V
SS
D.C. Output Current ....................................................5mA
Lead Temperature (Soldering, 10 seconds)............300°C
RECOMMENDED OPERATING CONDITIONS
Temp
Min.
0°C
Max.
70°C
Supply Voltage
X25XXX–1.8
X25XXX–2.7
X25XXX
Limits
1.8V-3.6V
2.7V to 5.5V
4.5V-5.5V
Commercial
Industrial
–40°C
+85°C
7036 FRM T07
7036 FRM T08
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Limits
Symbol
Parameter
Min. Typ. Max. Units
Test Conditions
SCK = V x 0.1/V x 0.9 @ 2MHz,
SO = Open
CC
CC
I
V
V
Write Current (Active)
5
mA
mA
CC1
CC
SCK = V x 0.1/V x 0.9 @ 2MHz,
CC
CC
I
Read Current (Active)
0.4
CC2
CC
SO = Open
I
I
I
I
I
V
V
V
Standby Current WDT=OFF
Standby Current WDT=ON
Standby Current WDT=ON
1
µA CS = V , V = V or V , V = 5.5V
CC IN SS CC CC
SB1
SB2
SB3
LI
CC
CC
CC
50
20
10
10
µA CS = V , V = V or V , V = 5.5V
CC IN SS CC CC
µA CS = V , V = V or V , V =3.6V
CC IN
SS
CC CC
Input Leakage Current
Output Leakage Current
Input LOW Voltage
0.1
0.1
µA
µA
V
V
V
= V to V
SS CC
IN
= V to V
CC
LO
OUT
SS
(1)
IL
–0.5
V
x0.3
CC
V
(1)
Input HIGH Voltage
V
x0.7
V
+0.5
CC
V
V
V
V
V
CC
IH
Output LOW Voltage
Output LOW Voltage
Output LOW Voltage
Output HIGH Voltage
Output HIGH Voltage
Output HIGH Voltage
Reset Output LOW Voltage
0.4
V
V
> 3.3V, I = 2.1mA
OL1
CC OL
0.4
0.4
V
2V < V ≤ 3.3V, I = 1mA
CC OL
OL2
V
V
V
≤ 2V, I = 0.5mA
OL
OL3
CC
CC
V
V
V
V
V
V
V
–0.8
–0.4
–0.2
V
> 3.3V, I
= –1.0mA
OH1
OH2
OH3
OLRS
CC
CC
CC
OH
V
2V < V ≤ 3.3V, I
= –0.4mA
CC
OH
V
V
≤ 2V, I
= –0.25mA
CC
OH
0.4
V
I
= 1mA
OL
7036 FRM T09
POWER-UP TIMING
Symbol
Parameter
Min.
Max.
Units
(2)
1
5
ms
ms
Power-up to Read Operation
Power-up to Write Operation
t
PUR
(2)
PUW
t
7036 FRM T10
CAPACITANCE T = +25°C, f = 1MHz, V
= 5V.
A
CC
Symbol
Test
Max.
Units
pF
Conditions
= 0V
(2)
OUT
8
6
V
OUT
Output Capacitance (SO, RESET, RESET)
Input Capacitance (SCK, SI, CS, WP)
C
(2)
IN
pF
V
= 0V
C
IN
Notes: (1) V min. and V max. are for reference only and are not tested.
7036 FRM T11
IL
IH
(2) This parameter is periodically sampled and not 100% tested.
8
X25648/49, X25328/29, X25168/69
EQUIVALENT A.C. LOAD CIRCUIT AT 5V V
A.C. TEST CONDITIONS
CC
V
x 0.1 to V x 0.9
Input Pulse Levels
CC
CC
5V
5V
Input Rise and Fall Times
Input and Output Timing Level
10ns
3.3KΩ
1.64KΩ
V
x0.5
CC
7036 FRM T12
OUTPUT
1.64KΩ
RESET/RESET
30pF
100pF
A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)
Data Input Timing
Symbol
Parameter
Voltage Range
Min.
Max.
Units
2.7V–5.5V
1.8V–3.6V
2
1
f
t
t
t
t
t
t
t
t
t
t
t
Clock Frequency
0
MHz
SCK
2.7V–5.5V
1.8V–3.6V
500
1000
Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
CYC
LEAD
LAG
WH
WL
2.7V–5.5V
1.8V–3.6V
250
500
CS Lead Time
CS Lag Time
2.7V–5.5V
1.8V–3.6V
250
500
2.7V–5.5V
1.8V–3.6V
200
400
Clock HIGH Time
Clock LOW Time
Data Setup Time
Data Hold Time
Input Rise Time
Input Fall Time
CS Deselect Time
Write Cycle Time
2.7V–5.5V
1.8V–3.6V
200
400
2.7V–5.5V
1.8V–3.6V
50
50
SU
2.7V–5.5V
1.8V–3.6V
H
2.7V–5.5V
1.8V–3.6V
(3)
RI
100
100
2.7V–5.5V
1.8V–3.6V
(3)
FI
2.7V–5.5V
1.8V–3.6V
500
CS
2.7V–5.5V
1.8V–3.6V
(4)
WC
10
7036 FRM T13
9
X25648/49, X25328/29, X25168/69
Data Output Timing
Symbol
Parameter
Clock Frequency
Part Number
Min.
Max.
Units
2.7V–5.5V
1.8V–3.6V
2
1
f
t
t
t
t
t
0
MHz
SCK
2.7V–5.5V
1.8V–3.6V
Output Disable Time
Output Valid from Clock Low
Output Hold Time
250
ns
ns
ns
ns
DIS
V
2.7V–5.5V
1.8V–3.6V
200
400
2.7V–5.5V
1.8V–3.6V
0
HO
2.7V–5.5V
1.8V–3.6V
(3)
RO
Output Rise Time
100
100
2.7V–5.5V
1.8V–3.6V
(3)
FO
Output Fall Time
ns
7036 FRM T14
Notes: (3) This parameter is periodically sampled and not 100% tested.
(4) t is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal
WC
nonvolatile write cycle.
10
X25648/49, X25328/29, X25168/69
Serial Output Timing
CS
tCYC
tWH
tLAG
SCK
tV
tHO
tWL
tDIS
SO
SI
MSB OUT
MSB–1 OUT
LSB OUT
ADDR
LSB IN
Serial Input Timing
tCS
CS
tLEAD
tLAG
SCK
tSU
tH
tRI
tFI
SI
MSB IN
LSB IN
HIGH IMPEDANCE
SO
11
X25648/49, X25328/29, X25168/69
Power-Up and Power-Down Timing
VTRIP
0 Volts
VTRIP
VCC
tPURST
tPURST
tF
tRPD
tR
RESET (X25643)
RESET (X25645)
RESET Output Timing
Symbol
Parameter
Min.
Typ.
Max.
Units
Reset Trip Point Voltage, 5V Device
Reset Trip Point Voltage, 2.7V Device
Reset Trip Point Voltage, 1.8V Device
4.25
2.55
1.7
4.5
2.7
1.8
V
V
V
V
t
TRIP
Power-up Reset Timeout
100
200
280
500
ms
ns
ns
ns
PURST
(5)
V
V
V
Detect to Reset/Output
Fall Time
t
t
t
CC
CC
CC
RPD
(5)
F
0.1
0.1
1
(5)
R
Rise Time
V
Reset Valid V
CC
V
RVALID
7036 FRM T15
Notes: (5) This parameter is periodically sampled and not 100% tested.
12
X25648/49, X25328/29, X25168/69
PACKAGING INFORMATION
14-LEAD PLASTIC SMALL OUTLINE GULLWING PACKAGETYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.51)
0.336 (8.55)
0.345 (8.75)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.10)
0.010 (0.25)
0.050 (1.27)
0.050" Typical
0.010 (0.25)
X 45°
0.020 (0.50)
0.050" Typical
0° – 8°
0.250"
0.0075 (0.19)
0.010 (0.25)
0.016 (0.410)
0.037 (0.937)
0.030"Typical
14 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
13
X25648/49, X25328/29, X25168/69
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
0.050" TYPICAL
X 45°
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
14
X25648/49, X25328/29, X25168/69
14-LEAD PLASTIC, TSSOP, PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.177 (4.5)
.252 (6.4) BSC
.193 (4.9)
.200 (5.1)
.047 (1.20)
.0075 (.19)
.0118 (.30)
.002 (.05)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
DetailA (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
15
X25648/49, X25328/29, X25168/69
ORDERING INFORMATION
X25648/49
X25328/29
X25168/69
P
T
-V
V
Limits
CC
Device
Blank = 5V ±10%
2.7 = 2.7V to 5.5V
1.8 = 1.8V to 3.6V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
Package
S14 = 14-Lead SOIC
S8 = 8-Lead SOIC
V14 = 14-Lead TSSOP
Part Mark Convention
X25648/49
X
X
X25328/29
X25168/69
X
X
Blank = 14-Lead SOIC
Blank = 8-Lead SOIC
V = 14 Lead TSSOP
Blank = 5V ±10%, 0°C to +70°C
I = 5V ±10%, –40°C to +85°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, –40°C to +85°C
AG = 1.8V to 3.6V, 0°C to +70°C
Blank = 5V ±10%, 0°C to +70°C
I = 5V ±10%, –40°C to +85°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, –40°C to +85°C
AG = 1.8V to 3.6V, 0°C to +70°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
16
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