X24F032VI [XICOR]

SerialFlash TM Memory with Block Lock TM Protection; SerialFlash TM记忆带座锁TM保护


型号：	X24F032VI
厂家：	XICOR INC.
描述：	SerialFlash TM Memory with Block Lock TM Protection SerialFlash TM记忆带座锁TM保护
文件：	总18页 (文件大小：87K)
中文：	中文翻译
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APPLICATION

NOTE

A V A I L A B L E

AN76 • AN78 • AN81 • AN87

64K/32K/16K

8K/4K/2K x 8 Bit

X24F064/032/016

SerialFlash^TMMemory with Block Lock^TMProtection

FEATURES

DESCRIPTION

• 1.8V to 3.6V or 5V “Univolt” Read and

Program Power Supply Versions

• Low Power CMOS

The X24F064/032/016 is

CMOS SerialFlash

Memory Family, internally organized 8K/4K/2K x 8.

The family features a serial interface and software

protocol allowing operation on a simple two wire bus.

—Active Read Current Less Than 1mA

—Active Program Current Less Than 3mA

—Standby Current Less Than 1µA

• Internally Organized 8K/4K/2K x 8

• New Programmable Block Lock Protection

—Software Write Protection

—Programmable hardware Write Protect

• Block Lock (0, 1/4, 1/2, or all of the Flash

Memory array)

Device select inputs (S , S , S ) allow up to eight

devices to share a common two wire bus.

A Program Protect Register accessed at the highest

address location, provides three new programming

protection features: Software Programming Protection,

Block Lock Protection, and Hardware Programming

Protection. The Software Programming Protection

feature prevents any nonvolatile writes to the device

until the WEL bit in the program protect register is set.

The Block Lock^TMProtection feature allows the user to

individually protect four blocks of the array by program-

ming two bits in the programming protect register. The

Programmable Hardware Program Protect feature

allows the user to install each device with PP tied to

• 2 Wire Serial Interface

• Bidirectional Data Transfer Protocol

• 32 Byte Sector Programming

• Self Timed Program Cycle

—Typical Programming Time of 5ms

Per Sector

• High Reliability

—Endurance: 100,000 cycles per byte

—Data Retention: 100 Years

• Available Packages

, program the entire memory array in place, and

then enable the hardware programming protection by

programming a PPEN bit in the program protect

including the program protect register itself, are

permanently protected from being programmed.

—8-Lead PDIP

—8-Lead SOIC (JEDEC)

—14-Lead TSSOP (X24F032/016)

—20-Lead TSSOP (X24F064)

FUNCTIONAL DIAGRAM

DATA REGISTER

SDA

SECTOR DECODE LOGIC

SCL

DECODE

LOGIC

COMMAND

DECODE

AND CONTROL

LOGIC

SECTORED

MEMORY

ARRAY

S₀/S₀

S₁/S₁

S₂/S₂

PROGRAM

PROTECT

HIGH VOLTAGE

CONTROL

PROGRAMMING

CONTROL LOGIC

SerialFlash Memory and Block Lock

Protection are trademarks of Xicor, Inc.

6686 ILL F01.5

Xicor, 1995, 1996 Patents Pending

6686-3.8 8/29/96 T3/C0/D0 SH

Characteristics subject to change without notice

X24F064/032/016

Xicor SerialFlash Memories are designed and tested for

applications requiring extended endurance. Inherent

data retention is greater than 100 years.

PIN CONFIGURATION

14-LEAD TSSOP

X24F016

PIN DESCRIPTIONS

Serial Clock (SCL)

8-LEAD DIP & SOIC

The SCL input is used to clock all data into and out of

the device.

SCL

SDA

SCL

SDA

Serial Data (SDA)

SDA is a bidirectional pin used to transfer data into

and out of the device. It is an open drain output and

may be wire-ORed with any number of open drain or

open collector outputs.

14-LEAD TSSOP

X24F032

8-LEAD DIP & SOIC

An open drain output requires the use of a pull-up

resistor. For selecting typical values, refer to the pull-

up resistor selection graph at the end of this data

sheet.

SCL

SDA

SCL

SDA

Device Select (S , S , S , S , S , S )

20-LEAD TSSOP

The device select inputs are used to set the device

select bits of the 8-bit slave address. This allows

multiple devices to share a common bus. These inputs

can be static or actively driven. If used statically they

X24F064

8-LEAD DIP & SOIC

SCL

SDA

must be tied to V or V

as appropriate. If actively

driven, they must be driven with CMOS levels (driven

to V or V ).

SCL

SDA

Program Protect (PP)

The program protect input controls the hardware

program protect feature. When held LOW, hardware

program protection is disabled and the X24F064/

032/016 can be programmed normally. When this

input is held HIGH, and the PPEN bit in the

program protect register is set HIGH, program

protection is enabled, and nonvolatile writes are

disabled to the selected blocks as well as the

program protect register itself.

6686 ILL F02.4

PIN NAMES

Symbol

Description

Device Select Inputs

S₀, S₀, S₁, S₁, S₂, S₂

SDA

SCL

Serial Data

Serial Clock

Program Protect

Ground

V_SS

V_CC

Supply Voltage

No Connect

6686 FRM T01.1

X24F064/032/016

DEVICE OPERATION

Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are

reserved for indicating start and stop conditions. Refer

to Figures 1 and 2.

The X24F064/032/016 supports a bidirectional bus ori-

ented protocol. The protocol defines any device that

sends data onto the bus as a transmitter, and the re-

ceiving device as the receiver. The device controlling

the transfer is a master and the device being controlled

is the slave. The master will always initiate data trans-

fers, and provide the clock for both transmit and receive

operations. Therefore, the X24F064/032/016 will be

considered a slave in all applications.

Start Condition

All commands are preceded by the start condition,

which is a HIGH to LOW transition of SDA when SCL is

HIGH. The X24F064/032/016 continuously monitors

the SDA and SCL lines for the start condition and will

not respond to any command until this condition has

been met.

Figure 1. Data Validity

SCL

SDA

DATA STABLE

DATA

CHANGE

6686 ILL F04

Notes: (5) Typical values are for T = 25°C and nominal supply voltage (2.7V)

(6) t is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the

device requires to perform the internal program operation.

Figure 2. Definition of Start and Stop

SCL

SDA

START BIT

STOP BIT

6686 ILL F05

X24F064/032/016

Stop Condition

The X24F064/032/016 will respond with an acknowl-

edge after recognition of a start condition and its slave

address. If both the device and a write operation have

been selected, the X24F064/032/016 will respond with

an acknowledge after the receipt of each subsequent

eight-bit word.

All communications must be terminated by a stop

condition, which is a LOW to HIGH transition of SDA

when SCL is HIGH. The stop condition is also used to

place the device into the standby power mode after a

read sequence. A stop condition can only be issued

after the transmitting device has released the bus.

In the read mode the X24F064/032/016 will transmit

eight bits of data, release the SDA line and monitor

the line for an acknowledge. If an acknowledge is

detected and no stop condition is generated by the

master, the X24F064/032/016 will continue to

transmit data. If an acknowledge is not detected, the

device will terminate further data transmissions. The

master must then issue a stop condition to return the

X24F064/032/016 to the standby power mode and

place the device into a known state.

Acknowledge

Acknowledge is a software convention used to indicate

successful data transfer. The transmitting device,

either master or slave, will release the bus after trans-

mitting eight bits. During the ninth clock cycle the

receiver will pull the SDA line LOW to acknowledge

that it received the eight bits of data. Refer to Figure 3.

Figure 3. Acknowledge Response From Receiver

SCL FROM

MASTER

DATA OUTPUT

FROM

TRANSMITTER

DATA

OUTPUT

FROM

RECEIVER

START

ACKNOWLEDGE

6686 ILL F06

X24F064/032/016

Also included in the slave address is an extension of

the array’s address which is concatenated with the

eight bits of address in the sector address ﬁeld,

providing direct access to the entire SerialFlash

Memory array.

DEVICE ADDRESSING

Following a start condition the master must output the

address of the slave it is accessing (see Figure 4). The

next two bits are the device select bits. A system could

have up to eight X24F032/016’s on the bus or up to

four 24F064’s on the bus. The device addresses are

deﬁned by the state of the S , S₁, and S₂inputs. Note

some of the slave addresses must be the inverse of

the corresponding input pin.

The last bit of the slave address deﬁnes the operation

to be performed. When set HIGH a read operation is

selected, when set LOW a program operation is

selected.

Figure 4. Slave Address

Following the start condition, the X24F064/032/016

monitors the SDA bus comparing the slave address

being transmitted with its slave address device type

identiﬁer. Upon a correct comparison of the device

select inputs, the X24F064/032/016 outputs an

acknowledge on the SDA line. Depending on the state

of the R/W bit, the X24F064/032/016 will execute a

read or program operation.

X24F064

DEVICE

SELECT

HIGH ORDER

SECTOR ADDRESS

A11

A10

A12

R/W

X24F032

DEVICE

SELECT

HIGH ORDER

SECTOR ADDRESS

PROGRAMMING OPERATIONS

The X24F064/032/016 offers a 32-byte sector pro-

gramming operation. For a program operation, the

X24F064/032/016 requires a second address field.

This field contains the address of the first byte in the

sector. Upon receipt of the address, comprised of

eight bits, the X24F064/032/016 responds with an ac-

knowledge and awaits the next eight bits of data,

again responding with an acknowledge. The master

then transmits 31 more bytes. After the receipt of

each byte, the X24F064/032/016 will respond with an

acknowledge.

A10

R/W

X24F016

DEVICE

TYPE

IDENTIFIER

DEVICE

SELECT

HIGH ORDER

SECTOR ADDRESS

A10

R/W

6686 ILL F07.4

Figure 5. Sector Programming

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SECTOR ADDRESS

DATA n

DATA n+1

DATA n+31

SDA LINE

BUS ACTIVITY:

X24F016/032/064

6686 ILL F10.3

X24F064/032/016

Flow 1. ACK Polling Sequence

After the receipt of each byte, the five low order ad-

dress bits are internally incremented by one. The high

order bits of the sector address remain constant. If the

master should transmit more or less than 32 bytes prior

to generating the stop condition, the contents of the

sector cannot be guaranteed. All inputs are disabled

until completion of the internal program cycle. Refer to

Figure 5 for the address, acknowledge and data trans-

fer sequence.

PROGRAM OPERATION

COMPLETED

ENTER ACK POLLING

ISSUE

START

Acknowledge Polling

The Max Write Cycle Time can be significantly reduced

using Acknowledge Polling. To initiate Acknowledge

Polling, the master issues a start condition followed by

the Slave Address Byte for a write or read operation. If

the device is still busy with the high voltage cycle, then

no ACK will be returned. If the device has completed

the write operation, an ACK will be returned and the

host can then proceed with the read or write operation.

Refer to Flow 1.

ISSUE SLAVE

ADDRESS AND R/W = 0

ISSUE STOP

ACK

RETURNED?

YES

READ OPERATIONS

Read operations are initiated in the same manner as

program operations with the exception that the R/W bit

of the slave address is set HIGH. There are three basic

read operations: current address read, random read

and sequential read.

OPERATION

A WRITE?

YES

ISSUE SECTOR

ADDRESS

It should be noted that the ninth clock cycle of the read

operation is not a “don’t care.” To terminate a read op-

eration, the master must either issue a stop condition

during the ninth cycle or hold SDA HIGH during the

ninth clock cycle and then issue a stop condition.

ISSUE STOP

PROCEED

6686 ILL F09.1

X24F064/032/016

Current Address Read

Random Read

Internally, the X24F064/032/016 contains an ad-

dress counter that maintains the address of the last

byte read, incremented by one byte. Therefore, if the

last read was from address n, the next read opera-

tion accesses data from address n + 1. Upon receipt

of the slave address with the R/W set HIGH, the

X24F064/032/016 issues an acknowledge and trans-

mits the eight-bit word. The read operation is termi-

nated by the master; by not responding with an

acknowledge and by issuing a stop condition. Refer

to Figure 6 for the sequence of address, acknowl-

edge and data transfer.

Random read operations allow the master to access

any memory location in a random manner. Prior to is-

suing the slave address with the R/W bit set HIGH, the

master must first perform a “dummy” write operation.

The master issues the start condition, and the slave ad-

dress with the R/W bit set LOW, followed by the byte

address it is to read. After the byte address acknowl-

edge, the master immediately reissues the start condi-

tion and the slave address with the R/W bit set HIGH.

This will be followed by an acknowledge from the

X24F064/032/016 and then by the eight-bit byte. The

read operation is terminated by the master; by not re-

sponding with an acknowledge and by issuing a stop

condition. Refer to Figure 7 for the address, acknowl-

edge and data transfer sequence.

Figure 6. Current Address Read

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY:

X24F016/032/064

DATA

6686 ILL F11.1

Figure 7. Random Read

SLAVE

ADDRESS

BYTE

ADDRESS n

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY:

X24F016/032/064

DATA n

6686 ILL F12.3

X24F064/032/016

Sequential Read

The data output is sequential, with the data from

address n followed by the data from n + 1. The

address counter for read operations increments all

address bits, allowing the entire memory contents to

be serially read during one operation. At the end of the

address space, the counter “rolls over” to 0 and the

X24F064/032/016 continues to output data for each

acknowledge received. Refer to Figure 8 for the

address, acknowledge and data transfer sequence.

Sequential reads can be initiated as either a current

address read or random access read. The first byte is

transmitted as with the other modes, however, the

master now responds with an acknowledge, indicating

it requires additional data. The X24F064/032/016

continues to output data for each acknowledge

received. The read operation is terminated by the

master; by not responding with an acknowledge and

then issuing a stop condition.

Figure 8. Sequential Read

SLAVE

ADDRESS

BUS ACTIVITY:

MASTER

SDA LINE

BUS ACTIVITY:

X24F016/032/064

DATA n

DATA n+1

DATA n+2

DATA n+x

6686 ILL F13.1

Figure 9. Typical System Configuration

PULL-UP

RESISTORS

SDA

SCL

MASTER

SLAVE

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER/

RECEIVER

MASTER

TRANSMITTER

TRANSMITTER/

RECEIVER

6686 ILL F14

X24F064/032/016

other address than the highest address location is

performed, the contents of the byte in the array at the

highest address location is read out instead of the

Program Protect Register.

PROGRAM PROTECT REGISTER

The Program Protect Register (PPR) is accessed at the

highest address of each device:

X24F064 = 1FFF

X24F032 = 0FFF

X24F016 = 07FF

WEL and RWEL are volatile latches that power-up in

the LOW (disabled) state. A write to any address other

than the highest address location, where the Program

Protect Register is located, will be ignored (no ACK)

until the WEL bit is set HIGH. The WEL bit is set by

writing 0000001x to the highest address location.

Once set, WEL remains HIGH until either reset (by

writing 00000000 to the highest address location) or

until the part powers-up again. The RWEL bit controls

writes to the Block Lock bits. RWEL is set by ﬁrst

setting WEL = 1 and then writing 0000011x to the

highest address location. RWEL must be set in order

to change the Block Lock bits (BL0 and BL1) or the

PPEN bit. RWEL is reset when the Block Lock or

PPEN bits are changed, or when the part powers-up

again.

Figure 10. Program Protect Register

PPEN

BL1

BL0

WEL

RWEL

6686 ILL F15

PPR.1 = WEL

– Write Enable Latch (Volatile)

0 = Write enable latch reset, programming disabled

1 = Write enable latch set, programming enabled

Programming the BL or PPEN Bits

If WEL = 0 then “no ACK” after ﬁrst byte of input data.

A three step sequence is required to change the

nonvolatile Block Lock or Program Protect Enable:

PPR.2 = RWEL

– Register Write Enable Latch (Volatile)

0 = Register write enable latch reset, programming

disabled

1) Set WEL = 1 (write 00000010 to the highest

address location, volatile write cycle)

1 = Register write enable latch set, programming

enabled

(Start)

2) Set RWEL = 1 (write 00000110 to the highest

address location, volatile write cycle)

PPR.3, PPR.4 = BL0, BL1

– Block Lock Bits (Nonvolatile)

(See Block Lock Bits section for definition)

(Start)

PPR.7 = PPEN

3) Set BL1, BL0, and/or PPEN bits (Write w00yz010 to

the highest address location)

– Programming Protect Enable Bit (Nonvolatile)

(See Programmable Hardware Program Protect sec-

tion for definition)

w = PPEN, y = BL1, Z = BL0,

(Stop)

Writing to the Program Protect Register

The Program Protect Register is written by performing

a write of one byte directly to the highest address loca-

tion. During normal Sector Programming, the byte in

the array at the highest address will be written instead

of the Program Protect Register (assuming program-

ming is not disabled by the Block Lock register).

Step 3 is a nonvolatile program cycle, requiring 10ms

to complete. RWEL is reset (0) by this program cycle,

requiring another program cycle to set RWEL again

before the Block Lock bits can be changed. RWEL

must be 0 in step 3; if w00yz110 is written to the

highest address location, RWEL is set but PPEN,

BL1 and BL0 are not changed (the device remains at

step 2).

The state of the Program Protect Register can be read

by performing a random read at the highest address

location at any time. If a sequential read starting at any

X24F064/032/016

Block Lock Bits

Programmable Hardware Program Protect

The Block Lock Bits BL0 and BL1 determine which

blocks of the memory are write-protected:

The Program Protect (PP) pin and the Program Protect

Enable (PPEN) bit in the Program Protect Register

control the programmable hardware program protect

feature. Hardware program protection is enabled when

the PP pin and the PPEN bit are both HIGH, and

disabled when either the PP pin is LOW or the PPEN

bit is LOW. When the chip is hardware program-

protected, nonvolatile programming is disabled,

including the Program Protect Register, the BL bits and

the PPEN bit itself, as well as to Block Locked sections

in the memory array. Only the sections of the memory

array that are not Block Locked can be written. Note

that since the PPEN bit is program-protected, it cannot

be changed back to a LOW state, and program protec-

tion is disabled as long as the PP pin is held HIGH.

Table 2 deﬁnes the program protection status for each

state of PPEN and PP.

Table 1. Block Lock Bits

BL1

BL0

Array Locked

None

Upper 1/4

Upper 1/2

Full Array (WPR not included)

6686 FRM T02

Table 2. Program Protect Status Table

Memory Array

PPEN

(Not Block Locked)

(Block Locked)

BL Bits

Programmable

Locked

PPEN Bit

Programmable

Locked

Programmable

Locked

Programmable

Locked

Programmable

Locked

6686 FRM T03

X24F064/032/016

ABSOLUTE MAXIMUM RATINGS*

*COMMENT

Temperature Under Bias

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only and the functional operation

of the device at these or any other conditions above

those indicated in the operational sections of this

speciﬁcation is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect device reliability.

X24F064/032/016 ......................–65°C to +135°C

Storage Temperature........................–65°C to +150°C

Voltage on any Pin with

Respect to V .................................... –1V to +7V

D.C. Output Current..............................................5mA

Lead Temperature (Soldering, 10 Seconds)...... 300°C

RECOMMENDED OPERATING CONDITIONS

Supply Voltage

X24F064/032/016

X24F064/032/016–5

Limits

Temperature

Commercial

Extended

Min.

0°C

Max.

+70°C

+85°C

1.8V to 3.6V

4.5V to 5.5V

–20°C

–40°C

6686 FRM T05.2

Industrial

6686 FRM T04.2

D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)

Limits

Symbol

Parameter

Min.

Max.

Units

Test Conditions

I_CC1

V_CCSupply Current (Read)

mA SCL = V_CCX 0.1/V_CCX 0.9 Levels

@ 100KHz, SDA = Open, All Other

I_CC2

V_CCSupply Current (Write)

Inputs = V or V_CC– 0.3V

(1)

V_CCStandby Current

µA

SCL = SDA = V_CC, All Other

I_SB1

Inputs = V or V_CC– 0.3V,

_CC= 3.6V

SCL = SDA = V_CC, All Other

Inputs = V or V_CC– 0.3V,

(1)

V_CCStandby Current

I_SB2

_CC= 5V ±10%

I_LI

Input Leakage Current

Output Leakage Current

Input LOW Voltage

µA

_IN= V to V_CC

I_LO

_OUT= V to V_CC

(2)

–1

V_CCx 0.3

V_lL

(2)

Input HIGH Voltage

Output LOW Voltage

V_CCx 0.7 V_CC+ 0.5

0.4

V_IH

V_OL

I_OL= 3mA

6686 FRM T06.4

CAPACITANCE T = +25°C, f = 1MHz, V = 2.7V

Symbol

Parameter

Max.

Units

Test Conditions

(3)

Input/Output Capacitance (SDA)

V_I/O= 0V

C_I/O

(3)

V_IN= 0V

Input Capacitance (S₁, S₂, SCL)

C_IN

6686 FRM T07

Notes: (1) Must perform a stop command prior to measurement.

(2) V min. and V max. are for reference only and are not 100% tested.

(3) This parameter is periodically sampled and not 100% tested.

X24F064/032/016

A.C. CONDITIONS OF TEST

EQUIVALENT A.C. LOAD CIRCUIT

Input Pulse Levels

V_CCx 0.1 to V_CCx 0.9

2.7V

Input Rise and

Fall Times

1533Ω

10ns

Input and Output

Timing Levels

OUTPUT

V_CCX 0.5

6686 FRM T08

100pF

6686 ILL F16.1

A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)

Read & Write Cycle Limits

Symbol

Parameter

SCL Clock Frequency

Min.

Max.

Units

f_SCL

100

KHz

T_I

Noise Suppression Time

100

Constant at SCL, SDA Inputs

t_AA

SCL LOW to SDA Data Out Valid

0.3

4.7

3.5

µs

t_BUF

Time the Bus Must Be Free Before a

New Transmission Can Start

t_HD:STA

t_LOW

Start Condition Hold Time

Clock LOW Period

µs

4.7

t_HIGH

Clock HIGH Period

t_SU:STA

Start Condition Setup Time

4.7

(for a Repeated Start Condition)

t_HD:DAT

t_SU:DAT

t_R

Data In Hold Time

µs

Data In Setup Time

250

SDA and SCL Rise Time

SDA and SCL Fall Time

Stop Condition Setup Time

Data Out Hold Time

t_F

300

t_SU:STO

t_DH

4.7

300

6686 FRM T09.1

(4)

POWER-UP TIMING

Symbol

Parameter

Max.

Units

t_PUR

Power-up to Read Operation

t_PUW

Power-up to Write Operation

6686 FRM T10

Notes: (4) t

and t

are the delays required from the time V is stable until the speciﬁed operation can be initiated.These parameters

PUW CC

PUR

are periodically sampled and not 100% tested.

X24F064/032/016

Bus Timing

HIGH

LOW

SCL

SU:STO

SU:STA

HD:STA

HD:DAT

SU:DAT

SDA IN

BUF

SDA OUT

6686 ILL F17

Program Cycle Limits

(5)

Symbol

Parameter

Min.

Typ.

Max.

Units

(6)

t_PR

Program Cycle Time

6686 FRM T11.1

The program cycle time is the time from a valid stop

condition of a write sequence to the end of the internal

erase/program cycle. During the program cycle, the

X24F064/032/016 bus interface circuits are disabled,

SDA is allowed to remain HIGH, and the device does

not respond to its slave address.

Bus Timing

SCL

ACK

SDA

8th BIT

WORD n

6686 ILL F18

STOP

CONDITION

START

CONDITION

Notes: (5) Typical values are for T = 25°C and nominal supply voltage (2.7V).

(6) t

is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum

time the device requires to automatically complete the internal program operation.

Guidelines for Calculating Typical Values of

Bus Pull-Up Resistors

SYMBOL TABLE

WAVEFORM

INPUTS

OUTPUTS

120

CC MAX

Must be

steady

Will be

steady

=1.2KΩ

MIN

100

OL MIN

May change

from LOW

to HIGH

Will change

from LOW

to HIGH

MAX

BUS

MAX.

RESISTANCE

May change

from HIGH

to LOW

Will change

from HIGH

to LOW

MIN.

Don’t Care:

Changes

Allowed

Changing:

State Not

Known

RESISTANCE

20 40 60 80

120

100

N/A

Center Line

is High

Impedance

BUS CAPACITANCE (pF)

6686 ILL F19.1

X24F064/032/016

PACKAGING INFORMATION

8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P

0.430 (10.92)

0.360 (9.14)

0.260 (6.60)

0.240 (6.10)

PIN 1 INDEX

PIN 1

0.060 (1.52)

0.020 (0.51)

0.300

(7.62) REF.

HALF SHOULDER WIDTH ON

ALL END PINS OPTIONAL

0.145 (3.68)

0.128 (3.25)

SEATING

PLANE

0.025 (0.64)

0.015 (0.38)

0.150 (3.81)

0.125 (3.18)

0.065 (1.65)

0.045 (1.14)

0.110 (2.79)

0.090 (2.29)

0.020 (0.51)

0.016 (0.41)

0.325 (8.25)

0.300 (7.62)

0.015 (0.38)

MAX.

0°

15°

TYP. 0.010 (0.25)

NOTE:

1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH

3926 FHD F01

X24F064/032/016

PACKAGING INFORMATION

8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S

0.150 (3.80)

0.158 (4.00)

0.228 (5.80)

0.244 (6.20)

PIN 1 INDEX

PIN 1

0.014 (0.35)

0.019 (0.49)

0.188 (4.78)

0.197 (5.00)

(4X) 7°

0.053 (1.35)

0.069 (1.75)

0.004 (0.19)

0.010 (0.25)

0.050 (1.27)

0.010 (0.25)

0.050" TYPICAL

X 45°

0.020 (0.50)

0.050"

TYPICAL

0° – 8°

0.0075 (0.19)

0.010 (0.25)

0.250"

0.016 (0.410)

0.037 (0.937)

0.030"

TYPICAL

8 PLACES

FOOTPRINT

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

3926 FHD F22.1

X24F064/032/016

PACKAGING INFORMATION

14-LEAD PLASTIC, TSSOP PACKAGE TYPE V

.025 (.65) BSC

.169 (4.3)

.252 (6.4) BSC

.177 (4.5)

.193 (4.9)

.200 (5.1)

.047 (1.20)

.0075 (.19)

.002 (.05)

.0118 (.30)

.006 (.15)

.010 (.25)

Gage Plane

0° – 8°

Seating Plane

.019 (.50)

.029 (.75)

Detail A (20X)

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

3926 FHD F32

X24F064/032/016

PACKAGING INFORMATION

20-LEAD PLASTIC, TSSOP PACKAGE TYPE V

.025 (.65) BSC

.169 (4.3)

.252 (6.4) BSC

.177 (4.5)

.252 (6.4)

.300 (6.6)

.047 (1.20)

.0075 (.19)

.002 (.05)

.0118 (.30)

.006 (.15)

.010 (.25)

Gage Plane

0° – 8°

Seating Plane

.019 (.50)

.029 (.75)

Detail A (20X)

.031 (.80)

.041 (1.05)

See Detail “A”

NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)

3926 FHD F45

X24F064/032/016

ORDERING INFORMATION

X24FXXX

–X

Range

Device

X24F064

X24F032

X24F016

Blank = 1.8V to 3.6V

5 = 4.5V to 5.5V

Temperature Range

Blank = Commercial = 0°C to +70°C

E = Extended = –20°C to +85°C

I = Industrial = –40°C to +85°C

Package

X24F032

X24F064

P = 8-Lead Plastic DIP

S = 8-Lead SOIC (JEDEC)

X24F016

P = 8-Lead Plastic DIP

S = 8-Lead SOIC (JEDEC)

V = 20-Lead TSSOP

V = 14-Lead TSSOP

Part Mark Convention

X24FXXX

P = 8-Lead Plastic DIP

Blank = 8-Lead SOIC (JEDEC)

V = 14/20-Lead TSSOP

X24F064

X24F032

X24F016

Blank = 1.8V to 3.6V, 0°C to +70°C

E = 1.8V to 3.6V, –20°C to +85°C

5 = 4.5V to 5.5V, 0°C to +70°C

I5 = 4.5V to 5.5V, –40°C to +85°C

LIMITED WARRANTY

Devices sold by Xicor, Inc. are covered by the warranty and patent indemniﬁcation provisions appearing in its Terms of Sale only. Xicor, Inc.

makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the

described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or ﬁtness for any purpose. Xicor, Inc. reserves the

right to discontinue production and change speciﬁcations and prices at any time and without notice.

Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,

licenses are implied.

U.S. PATENTS

Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;

4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;

4,883, 976. Foreign patents and additional patents pending.

LIFE RELATED POLICY

In situations where semiconductor component failure may endanger life, system designers using this product should design the system with

appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence.

Xicor's products are not authorized for use in critical components in life support devices or systems.

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain

life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably

expected to result in a signiﬁcant injury to the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the

failure of the life support device or system, or to affect its safety or effectiveness.

X24F032VI [XICOR]

相关型号：

X24F032VI-5

X24F032VIT1

X24F032VT1

X24F064

X24F064P

X24F064P-5

X24F064PE

X24F064PE-5

X24F064PI

X24F064PI-5

X24F064S

X24F064S-5