X24C08S14M-2.7 [XICOR]
Serial E2PROM; 串行E2PROM
| 型号： | X24C08S14M-2.7 |
| 厂家： | 
XICOR INC. |
| 描述： | Serial E2PROM |
| 文件： | 总16页 (文件大小：64K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
8K
X24C08
1024 x 8 Bit
Serial E2PROM
TYPICAL FEATURES
DESCRIPTION
2
The X24C08 is a CMOS 8,192 bit serial E PROM,
internally organized 1024 x 8. The X24C08 features a
serialinterfaceandsoftwareprotocolallowingoperation
on a simple two wire bus.
• 2.7V to 5.5V Power Supply
• Low Power CMOS
—Active Read Current Less Than 1 mA
—Active Write Current Less Than 3 mA
—Standby Current Less Than 50 µA
• Internally Organized 1024 x 8
• 2 Wire Serial Interface
—Bidirectional Data Transfer Protocol
• Sixteen Byte Page Write Mode
—Minimizes Total Write Time Per Byte
• Self Timed Write Cycle
—Typical Write Cycle Time of 5 ms
• High Reliability
The X24C08 is fabricated with Xicor’s advanced CMOS
Textured Poly Floating Gate Technology.
The X24C08 utilizes Xicor’s proprietary Direct Write™
cell providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
• 8 Pin Mini-DlP, 8 Pin SOIC and 14 Pin
SOIC Packages
FUNCTIONAL DIAGRAM
(8) V
CC
(4) V
SS
(7) TEST
H.V. GENERATION
START CYCLE
TIMING
& CONTROL
START
STOP
(5) SDA
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER
+COMPARATOR
2
E PROM
XDEC
64 X 128
LOAD
INC
(6) SCL
(3) A
2
WORD
ADDRESS
COUNTER
(2) A
(1) A
1
0
R/W
YDEC
8
CK
D
OUT
PIN
DATA REGISTER
D
OUT
ACK
3842 FHD F01
© Xicor, 1991 Patents Pending
3842-1
Characteristics subject to change without notice
1
X24C08
PIN DESCRIPTIONS
Serial Clock (SCL)
PIN CONFIGURATION
SOIC
The SCL input is used to clock all data into and out of the
device.
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
NC
V
A
0
A
1
Serial Data (SDA)
CC
TEST
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open
collector outputs.
NC
NC
X24C08
A
2
SCL
SDA
NC
V
SS
NC
8
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-Up
Resistor selection graph at the end of this data sheet.
3842 FHD F03
DIP/SOIC
Address (A , A )
0
1
A and A are unused by the X24C08; however, they
0
1
A
0
A
1
A
2
1
2
3
4
8
7
6
5
V
must be tied to V to insure proper device operation.
CC
SS
TEST
X24C08
Address (A )
2
SCL
The A input is used to set the appropriate bit of the
2
V
SDA
SS
seven bit slave address. This input can be used static or
3842 FHD F02
actively driven. If used statically, it must be tied to V or
SS
V
CC
as appropriate. If actively driven, it must be driven
to V or to V
.
SS
CC
PIN NAMES
Symbol
Description
A –A
Address Inputs
Serial Data
0
2
SDA
SCL
Serial Clock
TEST
Hold at V
Ground
SS
V
SS
V
CC
Supply Voltage
No Connect
NC
3842 PGM T01
2
X24C08
DEVICE OPERATION
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24C08 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
The X24C08 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave. The
master will always initiate data transfers, and provide
the clock for both transmit and receive operations.
Therefore, the X24C08 will be considered a slave in all
applications.
Stop Condition
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used by the
X24C08 to place the device into the standby power
mode after a read sequence. A stop condition can only
be issued after the transmitting device has released the
bus.
Clock and Data Conventions
DatastatesontheSDAlinecanchangeonlyduringSCL
LOW. SDA state changes during SCL HIGH are re-
served for indicating start and stop conditions. Refer to
Figures 1 and 2.
Figure 1. Data Validity
SCL
SDA
DATA STABLE
DATA
CHANGE
3842 FHD F06
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
3842 FHD F07
3
X24C08
Acknowledge
lected, the X24C08 will respond with an acknowledge
after the receipt of each subsequent eight bit word.
Acknowledge is a software convention used to indicate
successful data transfers. The transmitting device will
release the bus after transmitting eight bits. During the
ninth clock cycle the receiver will pull the SDA line LOW
to acknowledge that it received the eight bits of data.
Refer to Figure 3.
In the read mode the X24C08 will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the X24C08
will continue to transmit data. If an acknowledge is not
detected, the X24C08 will terminate further data trans-
missions. The master must then issue a stop condition
to return the X24C08 to the standby power mode and
place the device into a known state.
The X24C08 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write operation have been se-
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
1
8
9
DATA
OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
3842 FHD F08
4
X24C08
DEVICE ADDRESSING
The last bit of the slave address defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following a start condition the master must output the
address of the slave it is accessing. The most significant
four bits of the slave address are the device type
identifier (see Figure 4). For the X24C08 this is fixed as
1010[B].
Following the start condition, the X24C08 monitors the
SDA bus comparing the slave address being transmit-
ted with its slave address (device type and state of A
2
input.) Upon a correct compare the X24C08 outputs an
acknowledge on the SDA line. Depending on the state
of the R/W bit, the X24C08 will execute a read or write
operation.
Figure 4. Slave Address
HIGH
ORDER
DEVICE TYPE
IDENTIFIER
WORD
ADDRESS
WRITE OPERATIONS
Byte Write
1
0
1
0
A2
A1
A0 R/W
For a write operation, the X24C08 requires a second
address field. This address field is the word address,
comprised of eight bits, providing access to any one of
1024 words in the array. Upon receipt of the word
address the X24C08 responds with an acknowledge,
and awaits the next eight bits of data, again responding
with an acknowledge. The master then terminates the
transferbygeneratingastopcondition,atwhichtimethe
X24C08beginstheinternalwritecycletothenonvolatile
memory. While the internal write cycle is in progress the
X24C08 inputs are disabled, and the device will not
respond to any requests from the master. Refer to
Figure5fortheaddress, acknowledgeanddatatransfer
sequence.
DEVICE
ADDRESS
3842 FHD F09
The next bit addresses a particular device. A system
could have up to two X24C08 devices on the bus (see
Figure 10). The two addresses are defined by the state
of the A2 input.
The next two bits of the slave address field are an
extension of the array’s address and are concatenated
with the eight bits of address in the word address field,
providing direct access to the whole 1024 x 8 array.
Figure 5. Byte Write
S
T
S
SLAVE
ADDRESS
WORD
ADDRESS
A
R
T
T
BUS ACTIVITY:
MASTER
DATA
O
P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
X24C08
3842 FHD F10
5
X24C08
Page Write
Flow 1. ACK Polling Sequence
The X24C08 is capable of a sixteen byte page write
operation. It is initiated in the same manner as the byte
writeoperation,butinsteadofterminatingthewritecycle
after the first data word is transferred, the master can
transmit up to fifteen more words. After the receipt of
each word, the X24C08 will respond with an acknowl-
edge.
WRITE OPERATION
COMPLETED
ENTER ACK POLLING
ISSUE
START
Afterthereceiptofeachword,thefourloworderaddress
bitsareinternallyincrementedbyone.Thehighordersix
bits of the word address remain constant. If the master
should transmit more than sixteen words prior to gener-
ating the stop condition, the address counter will “roll
over” and the previously written data will be overwritten.
As with the byte write operation, all inputs are disabled
until completion of the internal write cycle. Refer to
Figure6fortheaddress, acknowledgeanddatatransfer
sequence.
ISSUE SLAVE
ADDRESS AND R/W = 0
ISSUE STOP
ACK
NO
RETURNED?
YES
Acknowledge Polling
NEXT
NO
The disabling of the inputs can be used to take advan-
tage of the typical 5 ms write cycle time. Once the stop
condition is issued to indicate the end of the host’s write
operation the X24C08 initiates the internal write cycle.
ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the X24C08 is still busy with the
write operation no ACK will be returned. If the X24C08
has completed the write operation an ACK will be
returned and the host can then proceed with the next
read or write operation. Refer to Flow 1.
OPERATION
A WRITE?
YES
ISSUE STOP
PROCEED
ISSUE BYTE
ADDRESS
PROCEED
3842 FHD F11
Figure 6. Page Write
S
T
S
T
O
P
SLAVE
ADDRESS
A
R
T
BUS ACTIVITY:
MASTER
WORD ADDRESS n
DATA n
DATA n+1
DATA n+15
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
X24C08
3842 FHD F12
NOTE: In this example n = xxxx 000 (B); x = 1 or 0
6
X24C08
READ OPERATIONS
The read operation is terminated by the master; by not
responding with an acknowledge and by issuing a stop
condition. RefertoFigure7forthesequenceofaddress,
acknowledge and data transfer.
Read operations are initiated in the same manner as
writeoperationswiththeexceptionthattheR/Wbitofthe
slave address is set to a one. There are three basic read
operations: current address read, random read and
sequential read.
Random Read
Randomreadoperationsallowthemastertoaccessany
memory location in a random manner. Prior to issuing
the slave address with the R/W bit set to one, the master
must first perform a “dummy” write operation. The mas-
ter issues the start condition, and the slave address
followed by the word address it is to read. After the word
addressacknowledge,themasterimmediatelyreissues
thestartconditionandtheslaveaddresswiththeR/Wbit
set to one. This will be followed by an acknowledge from
the X24C08 and then by the eight bit word. The read
operationisterminatedbythemaster;bynotresponding
with an acknowledge and by issuing a stop condition.
RefertoFigure8fortheaddress, acknowledgeanddata
transfer sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condition
duringtheninthcycleorholdSDAHIGHduringtheninth
clock cycle and then issue a stop condition.
Current Address Read
Internally the X24C08 contains an address counter that
maintains the address of the last word accessed,
incremented by one. Therefore, if the last access (either
areadorwrite)wastoaddressn,thenextreadoperation
would access data from address n + 1. Upon receipt of
the slave address with R/W set to one, the X24C08
issues an acknowledge and transmits the eight bit word.
Figure 7. Current Address Read
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
BUS ACTIVITY:
MASTER
SDA LINE
S
P
A
C
BUS ACTIVITY:
X24C08
DATA
K
3842 FHD F13
Figure 8. Random Read
S
T
A
R
T
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
WORD
ADDRESS n
SLAVE
ADDRESS
BUS ACTIVITY:
MASTER
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
X24C08
DATA n
3842 FHD F14
7
X24C08
Sequential Read
Thedataoutputissequential,withthedatafromaddress
n followed by the data from n + 1. The address counter
for read operations increments all address bits, allowing
the entire memory contents to be serially read during
oneoperation. Attheendoftheaddressspace(address
1023) the counter “rolls over” to address 0 and the
X24C08 continues to output data for each acknowledge
received. Refer to Figure 9 for the address, acknowl-
edge and data transfer sequence.
Sequential reads can be initiated as either a current
address read or random access read. The first word is
transmitted as with the other read modes; however, the
master now responds with an acknowledge, indicating it
requires additional data. The X24C08 continues to out-
put data for each acknowledge received. The read
operationisterminatedbythemaster;bynotresponding
with an acknowledge and by issuing a stop condition.
Figure 9. Sequential Read
S
SLAVE
ADDRESS
T
O
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
P
A
C
K
BUS ACTIVITY:
X24C08
DATA n
DATA n+1
DATA n+2
DATA n+x
3842 FHD F15
Figure 10. Typical System Configuration
V
CC
PULL-UP
RESISTORS
SDA
SCL
MASTER
SLAVE
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
TRANSMITTER/
RECEIVER
RECEIVER
3842 FHD F16
8
X24C08
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias................. –65°C to +135°C
Storage Temperature ...................... –65°C to +150°C
Voltage on any Pin with
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation of
the device at these or any other conditions above those
indicatedintheoperationalsectionsofthisspecificationis
not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
Respect to V
.................................–1.0V to +7V
SS
D.C. Output Current ........................................... 5 mA
Lead Temperature
(Soldering, 10 Seconds) .............................. 300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Min.
Max.
Supply Voltage
Limits
Commercial
Industrial
Military
0°C
–40°C
–55°C
70°C
+85°C
X24C08
4.5V to 5.5V
3.5V to 5.5V
3V to 5.5V
X24C08-3.5
X24C08-3
X24C08-2.7
+125°C
2.7V to 5.5V
D.C. OPERATING CHARACTERISTICS (Over recommneded operating conditions, unless otherwise specified.)
Limits
Symbol
Parameter
Min.
Max.
Units
Test Conditions
SCL = V x 0.1/V x 0.9 Levels @ 100
l
V
CC
Supply Current (Read)
1
CC1
CC
CC
KHz, SDA = Open,
l
V
V
Supply Current (Write)
Standby Current
3
mA
All Other Inputs = GND or V – 0.3V
CC2
CC
CC
(1)
(1)
I
I
150
µA
SCL = SDA = V – 0.3V, All Other
CC
SB1
CC
Inputs = GND or V , V = 5.5V
CC
CC
V
CC
Standby Current
50
µA
SCL = SDA = V – 0.3V, All Other
CC
SB2
Inputs = GND or V , V = 3V
CC
CC
I
I
Input Leakage Current
Output Leakage Current
Input Low Voltage
10
10
µA
µA
V
V
V
= GND to V
CC
LI
IN
= GND to V
CC
LO
OUT
(2)
V
V
V
–1.0
V
x 0.3
lL
CC
(2)
Input High Voltage
V
x 0.7 V + 0.5
V
IH
CC
CC
Output Low Voltage
0.4
V
I
OL
= 3 mA
OL
3842 PGM T02
CAPACITANCE T = 25°C, F = 1.0MHZ, V = 5V
A
CC
Symbol
Test
Input/Output Capacitance (SDA)
Input Capacitance (A , A , A , SCL)
Max.
Units
Conditions
(3)
C
C
8
6
pF
pF
V
V
= 0V
= 0V
I/O
I/O
(3)
IN
0
1
2
IN
3842 PGM T04
Notes: (1) Must perform a stop command prior to measurement.
(2) V min and V max. are for reference only and are not 100% tested.
IL
IH
(3) This parameter is periodically sampled and not 100% tested.
9
X24C08
A.C. CONDITIONS OF TEST
EQUIVALENT A.C. LOAD CIRCUIT
5.0V
Input Pulse Levels
V
x 0.1 to V x 0.9
CC
CC
Input Rise and
Fall Times
1533Ω
10ns
Output
100pF
I/O Timing Levels
V
x 0.5
CC
3842 PGM T05
3842 FHD F18
A.C. CHARACTERISTICS LIMITS (Over recommended operating conditions, unless otherwise specified.)
Read & Write Cycle Limits
Symbol
Parameter
Min.
Max.
Units
t
t
t
t
SCL Clock Frequency
0
100
100
3.5
KHz
ns
SCL
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out Valid
I
0.3
4.7
µs
AA
BUF
Time the Bus Must Be Free Before a
New Transmission Can Start
µs
t
t
t
t
t
t
t
t
t
t
Start Condition Hold Time
Clock Low Period
4.0
4.7
4.0
4.7
0
µs
µs
µs
µs
µs
ns
µs
ns
µs
HD:STA
LOW
Clock High Period
HIGH
SU:STA
HD:DAT
SU:DAT
R
Start Condition Setup Time
Data In Hold Time
Data In Setup Time
250
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
300
F
4.7
SU:STO
DH
300
ns
3842 PGM T06
POWER-UP TIMING
Symbol
Parameter
Max.
Units
(4)
t
t
Power-Up to Read Operation
Power-Up to Write Operation
1
5
ms
ms
PUR
(4)
PUW
3842 PGM T07
Bus Timing
t
t
t
R
t
HIGH
LOW
F
SCL
t
t
t
t
t
SU:STO
SU:STA
HD:STA
HD:DAT
SU:DAT
SDA IN
t
t
t
BUF
AA
DH
SDA OUT
3842 FHD F04
Note: (4) t
PUR
and t
are the delays required from the time V is stable until the specified operation can be initiated. These param-
CC
PUW
eters are periodically sampled and not 100% tested.
10
X24C08
WRITE CYCLE LIMITS
(5)
Typ.
Symbol
Parameter
Min.
Max.
Units
(6)
t
Write Cycle Time
5
10
ms
WR
3842 PGM T08
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
erase/programcycle.Duringthewritecycle,theX24C08
bus interface circuits are disabled, SDA is allowed to
remainhigh,andthedevicedoesnotrespondtoitsslave
address.
Write Cycle Timing
SCL
ACK
SDA
8th BIT
WORD n
t
WR
STOP
CONDITION
START
CONDITION
X24C08
ADDRESS
3842 FHD F05
Notes: (5) Typical values are for T = 25°C and nominal supply voltage (5V).
A
(6) t
is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the
WR
device requires to perform the internal write operation.
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
120
V
Must be
steady
Will be
steady
CC MAX
R
=
=1.8KΩ
MIN
I
100
80
OL MIN
MAX
t
R
May change
from Low to
High
Will change
from Low to
High
R
=
MAX
C
BUS
MAX.
60
40
20
0
RESISTANCE
May change
from High to
Low
Will change
from High to
Low
MIN.
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
RESISTANCE
20 40 60 80
120
100
0
Center Line
is High
Impedance
BUS CAPACITANCE (pF)
N/A
3842 FHD F17
11
X24C08
NOTES
12
X24C08
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.020 (0.50)
X 45°
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.027 (0.683)
0.037 (0.937)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESIS IN MILLIMETERS)
3926 FHD F22
13
X24C08
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.092 (2.34)
DIA. NOM.
0.255 (6.47)
0.245 (6.22)
PIN 1 INDEX
PIN 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.140 (3.56)
0.130 (3.30)
SEATING
PLANE
0.020 (0.51)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.062 (1.57)
0.058 (1.47)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0.015 (0.38)
MAX.
0°
15°
TYP. 0.010 (0.25)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F01
14
X24C08
PACKAGING INFORMATION
14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.336 (8.55)
0.345 (8.75)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
X 45°
0.020 (0.50)
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.027 (0.683)
0.037 (0.937)
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F10
15
X24C08
ORDERING INFORMATION
X24C08
P
T
-V
V
CC
Limits
Device
Blank = 4.5V to 5.5V
3.5 = 3.5V to 5.5V
3 = 3.0V to 5.5V
2.7 = 2.7V to 5.5V
Temperature Range
Blank = Commercial = 0°C to +70°C
I = Industrial = –40°C to +85°C
M = Military = –55°C to +125°C
Package
P = 8-Lead Plastic DIP
S8 = 8-Lead SOIC
S14 = 14-Lead SOIC
Part Mark Convention
P = 8-Lead Plastic DIP
S8 = 8-Lead SOIC
S = 14-Lead SOIC
X24C08
X
X
Blank = 4.5V to 5.5V, 0°C to +70°C
I = 4.5V to 5.5V, –40°C to +85°C
B = 3.5V to 5.5V, 0°C to +70°C
C = 3.5V to 5.5V, –40°C to +85°C
D = 3.0V to 5.5V, 0°C to +70°C
E = 3.0V to 5.5V, –40°C to +85°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, –40°C to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty,
express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement.
Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and
prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are
implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;
4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreign patents and
additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error
detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant
injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or effectiveness.
16
相关型号：
©2020 ICPDF网 联系我们和版权申明