X24645PI-2.7 [XICOR]
Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection; 先进的2线串行é 2 PROM带座锁TM保护
| 型号： | X24645PI-2.7 |
| 厂家： | 
XICOR INC. |
| 描述： | Advanced 2-Wire Serial E 2 PROM with Block Lock TM Protection |
| 文件： | 总18页 (文件大小：86K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
64K
8192 x 8 Bit
X24645
2
Advanced 2-Wire Serial E PROM with Block LockTM Protection
FEATURES
DESCRIPTION
2
• 2.7V to 5.5V Power Supply
The X24645 is a CMOS 65,536-bit serial E PROM,
internally organized 8192 x 8. The X24645 features a
serial interface and software protocol allowing opera-
tion on a simple two wire bus.
• Low Power CMOS
—Active Read Current Less Than 1mA
—Active Write Current Less Than 3mA
—Standby Current Less Than 1µA
• Internally Organized 8192 x 8
• New Programmable Block Lock Protection
—Software Write Protection
Two device select inputs (S , S ) allow up to four
1
2
devices to share a common two wire bus.
A Write Protect Register at the highest address loca-
tion, 1FFFh, provides three new write protection
features: Software Write Protect, Block Write Protect,
and Hardware Write Protect. The Software Write
Protect feature prevents any nonvolatile writes to the
X24645 until the WEL bit in the write protect register is
set. The Block Write Protection feature allows the user
to individually write protect four blocks of the array by
programming two bits in the write protect register. The
Programmable Hardware Write Protect feature allows
—Programmable hardware Write Protect
2
• Block Lock (0, 1/4, 1/2, or all of the E PROM
array)
• 2 Wire Serial Interface
• Bidirectional Data Transfer Protocol
• 32 Byte Page Write Mode
—Minimizes Total Write Time Per Byte
• Self Timed Write Cycle
—Typical Write Cycle Time of 5ms
• High Reliability
the user to install the X24645 with WP tied to V
,
CC
—Endurance: 100,000 Cycles
—Data Retention: 100 Years
• Available Packages
program the entire memory array in place, and then
enable the hardware write protection by programming
a WPEN bit in the write protect register. After this,
selected blocks of the array, including the write protect
register itself, are permanently write protected, as long
as WP remains HIGH.
—8-Lead PDIP
—8-Lead SOIC (JEDEC)
—14-Lead SOIC (JEDEC)
—20-Lead TSSOP
FUNCTIONAL DIAGRAM
WP
H.V. GENERATION
START CYCLE
TIMING &
CONTROL
V
V
CC
SS
WRITE PROTECT
REGISTER AND
LOGIC
START
STOP
SDA
LOGIC
CONTROL
LOGIC
SLAVE ADDRESS
REGISTER
+COMPARATOR
2
E PROM
256 X 256
XDEC
LOAD
WORD
INC
SCL
ADDRESS
COUNTER
S
S
2
1
R/W
YDEC
8
CK
D
OUT
PIN
DATA REGISTER
D
OUT
ACK
2783 ILL F01
Xicor, 1995, 1996 Patents Pending
2783-3.5 5/13/96 T1/C0/D0 NS
Characteristics subject to change without notice
1
X24645
2
Xicor E PROMs are designed and tested for applica-
PIN CONFIGURATIONS
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
8-LEAD DIP & SOIC
NC
1
2
3
4
8
7
6
5
V
CC
PIN DESCRIPTIONS
Serial Clock (SCL)
S
1
S
2
WP
X24645
SCL
SDA
The SCL input is used to clock all data into and out of
the device.
V
SS
Serial Data (SDA)
14-LEAD SOIC
SDA is a bidirectional pin used to transfer data into
and out of the device. It is an open drain output and
may be wire-ORed with any number of open drain or
open collector outputs.
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
V
CC
WP
SCL
SDA
NC
S
1
S
2
X24645
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
up resistor selection graph at the end of this data
sheet.
V
SS
NC
8
Device Select (S , S )
1
2
20-LEAD TSSOP
The device select inputs (S , S ) are used to set the
1
2
first and second bits of the 8-bit slave address. This
allows up to four X24645 devices to share a common
bus. These inputs can be static or actively driven. If
NC
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
V
CC
S
1
WP
used statically they must be tied to V
or V
as
SS
CC
NC
NC
NC
NC
appropriate. If actively driven, they must be driven with
CMOS levels (driven to V or V ).
NC
X24645
CC
SS
NC
Write Protect (WP)
SCL
SDA
NC
S
2
The write protect input controls the hardware write
protect feature. When held LOW, hardware write
protection is disabled and the X24645 can be written
normally. When this input is held HIGH, and the WPEN
bit in the write protect register is set HIGH, write
protection is enabled, and nonvolatile writes are
disabled to the selected blocks as well as the write
protect register itself.
V
SS
NC
NC
NC
2783 ILL F02.4
PIN NAMES
Symbol
Description
Device Select Inputs
S1, S2
SDA
SCL
WP
Serial Data
Serial Clock
Write Protect
Ground
VSS
VCC
NC
Supply Voltage
No Connect
2783 FRM T01.1
2
X24645
DEVICE OPERATION
Clock and Data Conventions
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
The X24645 supports a bidirectional bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the X24645 will be considered a slave in all
applications.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The X24645 continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
Figure 1. Data Validity
SCL
SDA
DATA STABLE
DATA
CHANGE
2783 ILL F04
Notes: (5) Typical values are for T = 25°C and nominal supply voltage (5V)
A
(6) t
is the minimum cycle time from the system perspective when polling techniques are not used. It is the maximum time the
WR
device requires to perform the internal write operation.
Figure 2. Definition of Start and Stop
SCL
SDA
START BIT
STOP BIT
2783 ILL F05
3
X24645
Stop Condition
The X24645 will respond with an acknowledge after
recognition of a start condition and its slave address. If
both the device and a write operation have been
selected, the X24645 will respond with an acknowl-
edge after the receipt of each subsequent 8-bit word.
All communications must be terminated by a stop
condition, which is a LOW to HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the device into the standby power mode after a
read sequence. A stop condition can only be issued
after the transmitting device has released the bus.
In the read mode the X24645 will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the X24645
will continue to transmit data. If an acknowledge is not
detected, the X24645 will terminate further data trans-
missions. The master must then issue a stop condition
to return the X24645 to the standby power mode and
place the device into a known state.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data. Refer to Figure 3.
Figure 3. Acknowledge Response From Receiver
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM
TRANSMITTER
DATA
OUTPUT
FROM
RECEIVER
START
ACKNOWLEDGE
2783 ILL F06
4
X24645
DEVICE ADDRESSING
The last bit of the slave address defines the operation to
be performed. When set HIGH a read operation is
selected, when set LOW, a write operation is selected.
Following a start condition the master must output the
address of the slave it is accessing (see Figure 4). The
next two bits are the device select bits. A system could
have up to four X24645’s on the bus. The four
addresses are defined by the state of the S1 and S2
inputs. S2 of the slave address must be the inverse of
the S2 input pin.
Following the start condition, the X24645 monitors the
SDA bus comparing the slave address being transmitted
with its slave address device type identifier. Upon a
correct compare the X24645 outputs an acknowledge on
the SDA line. Depending on the state of the R/W bit, the
X24645 will execute a read or write operation.
Figure 4. Slave Address
WRITE OPERATIONS
Byte Write
HIGH ORDER
ADDRESS
BITS
DEVICE
SELECT
For a write operation, the X24645 requires a second ad-
dress field. This address field is the byte address, com-
prised of eight bits, providing access to any one of 8192
words in the array. Upon receipt of the byte address, the
X24645 responds with an acknowledge and awaits the
next eight bits of data, again responding with an acknowl-
edge. The master then terminates the transfer by gener-
ating a stop condition, at which time the X24645 begins
the internal write cycle to the nonvolatile memory. While
the internal write cycle is in progress the X24645 inputs
are disabled, and the device will not respond to any re-
quests from the master. Refer to Figure 5 for the address,
acknowledge and data transfer sequence.
A10
A11
S
S
A12
A9
A8 R/W
2
1
2783 ILL F07.1
The next five bits of the slave address are an exten-
sion of the array’s address and are concatenated with
the eight bits of address in the byte address field,
providing direct access to the whole 8192 x 8 array.
Figure 5. Byte Write
S
T
S
SLAVE
ADDRESS
BYTE
ADDRESS
A
R
T
T
BUS ACTIVITY:
MASTER
DATA
O
P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
X24645
2783 ILL F08.1
5
X24645
Page Write
Flow 1. ACK Polling Sequence
The X24645 is capable of a 32-byte page write opera-
tion. It is initiated in the same manner as the byte write
operation, but instead of terminating the write cycle af-
ter the first data word is transferred, the master can
transmit up to thirty-one more bytes. After the receipt of
each byte, the X24645 will respond with an acknowl-
edge.
WRITE OPERATION
COMPLETED
ENTER ACK POLLING
ISSUE
START
After the receipt of each byte, the five low order ad-
dress bits are internally incremented by one. The high
order eight bits of the address remain constant. If the
master should transmit more than 32 bytes prior to gen-
erating the stop condition, the address counter will “roll
over” and the previously written data will be overwrit-
ten. As with the byte write operation, all inputs are dis-
abled until completion of the internal write cycle. Refer
to Figure 6 for the address, acknowledge, and data
transfer sequence.
ISSUE SLAVE
ADDRESS AND R/W = 0
ISSUE STOP
ACK
NO
RETURNED?
YES
Acknowledge Polling
NEXT
NO
The Max Write Cycle Time can be significantly reduced
using Acknowledge Polling. To initiate Acknowledge
Polling, the master issues a start condition followed by
the Slave Address Byte for a write or read operation. If
the device is still busy with the high voltage cycle, then
no ACK will be returned. If the device has completed
the write operation, an ACK will be returned and the
host can then proceed with the read or write operation.
Refer to Flow 1.
OPERATION
A WRITE?
YES
ISSUE BYTE
ADDRESS
ISSUE STOP
PROCEED
PROCEED
2783 ILL F09
Figure 6. Page Write
S
T
S
T
O
P
SLAVE
ADDRESS
A
R
T
BUS ACTIVITY:
MASTER
BYTE ADDRESS (n)
DATA n
DATA n+1
DATA n+31
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
X24645
2783 ILL F10.2
6
X24645
transmits the byte. The read operation is terminated by
the master; by not responding with an acknowledge
and by issuing a stop condition. Refer to Figure 7 for the
sequence of address, acknowledge and data transfer.
READ OPERATIONS
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the slave address is set HIGH. There are three basic
read operations: current address read, random read
and sequential read.
Random Read
Random read operations allow the master to access
any memory location in a random manner. Prior to issu-
ing the slave address with the R/W bit set HIGH, the
master must first perform a “dummy” write operation.
The master issues the start condition, and the slave ad-
dress with the R/W bit set LOW, followed by the byte
address it is to read. After the word address acknowl-
edge, the master immediately reissues the start condi-
tion and the slave address with the R/W bit set HIGH.
This will be followed by an acknowledge from the
X24645 and then by the data byte. The read operation
is terminated by the master; by not responding with an
acknowledge and by issuing a stop condition. Refer to
Figure 8 for the address, acknowledge and data trans-
fer sequence.
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read op-
eration, the master must either issue a stop condition
during the ninth cycle or hold SDA HIGH during the
ninth clock cycle and then issue a stop condition.
Current Address Read
Internally the X24645 contains an address counter that
maintains the address of the last byte read, increment-
ed by one or the exact address of the last byte written.
Therefore, if the last access read was to address n, the
next read operation would access data from address
n + 1. Upon receipt of the slave address with the R/W
set HIGH, the X24645 issues an acknowledge and
Figure 7. Current Address Read
S
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
BUS ACTIVITY:
MASTER
SDA LINE
S
P
A
C
BUS ACTIVITY:
X24645
DATA
K
2783 ILL F11
Figure 8. Random Read
S
S
T
T
A
R
T
S
T
O
P
SLAVE
ADDRESS
BYTE
ADDRESS n
SLAVE
ADDRESS
A
R
T
BUS ACTIVITY:
MASTER
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
X24645
DATA n
2783 ILL F12.1
7
X24645
Sequential Read
The data output is sequential, with the data from
address n followed by the data from n + 1. The address
counter for read operations increments all address bits,
allowing the entire memory contents to be serially read
during one operation. At the end of the address space
(address 8191), the counter “rolls over” to 0 and the
X24645 continues to output data for each acknowledge
Sequential reads can be initiated as either a current
address read or random access read. The first byte is
transmitted as with the other modes, however, the
master now responds with an acknowledge, indicating
it requires additional data. The X24645 continues to
output data for each acknowledge received. The read
operation is terminated by the master; by not
responding with an acknowledge and then issuing a
stop condition.
received. Refer to Figure
9 for the address,
acknowledge and data transfer sequence.
Figure 9. Sequential Read
S
T
O
P
SLAVE
ADDRESS
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
MASTER
SDA LINE
P
A
C
K
BUS ACTIVITY:
X24645
DATA n
DATA n+1
DATA n+2
DATA n+x
2783 ILL F13
Figure 10. Typical System Configuration
V
CC
PULL-UP
RESISTORS
SDA
SCL
MASTER
SLAVE
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
TRANSMITTER/
RECEIVER
RECEIVER
2783 ILL F14
8
X24645
WEL and RWEL are volatile latches that power-up in
the LOW (disabled) state. A write to any address other
than 1FFFh, where the Write Protect Register is
located, will be ignored (no ack) until the WEL bit is set
HIGH. The WEL bit is set by writing 0000001x to
address 1FFFh. Once set, WEL remains HIGH until
either reset (by writing 00000000 to 1FFFh) or until the
part powers-up again. The RWEL bit controls writes to
the block protect bits. RWEL is set by first setting WEL
to “1” and then writing 0000011x to address 1FFFh.
RWEL must be set in order to change the block protect
bits, BP0 and BP1, or the WPEN bit. RWEL is reset
when the block protect or WPEN bits are changed, or
when the part powers-up again.
WRITE PROTECT REGISTER
The Write Protect Register (WPR) is located at the
highest address, 1FFFh.
Figure 11. Write Protect Register
WPR (ADDR = 1FFFh)
7
6
5
4
3
1
0
2
WPEN
0
0
BP1
BP0
WEL
0
RWEL
2783 ILL F15.1
WPR.1 = WEL
– “Write Enable” Latch (Volatile)
0 = Write enable latch reset, writes disabled
1 = Write enable latch set, writes enabled
Programming the BP or WPEN Bits
A three step sequence is required to change the
nonvolatile Block Protect or Write Protect Enable:
If WEL = “0” then “no ACK” after first byte of input data.
WPR.2 = RWEL
1) Set WEL = 1 (write 00000010 to address 1FFFh,
volatile write cycle)
– “Register Write Enable” Latch (Volatile)
0 = Register write enable latch reset, writes dis-
abled
(Start)
1 = Register write enable latch set, writes enabled
2) Set RWEL = 1 (write 00000110 to address 1FFFh,
volatile write cycle)
WPR.3, WPR.4 = BP0, BP1
– Block Protect Bits (Nonvolatile)
(See Block Protect section for definition)
(Start)
WPR.7 = WPEN
– Write Protect Enable Bit (Nonvolatile)
(See Hardware Write Protect section for definition)
3) Set BP1, BP0, and/or WPEN bits (Write w00yz010
to address 1FFFh)
w = WPEN, y = BP1, Z = BP0,
(Stop)
Writing to the Write Protect Register
The Write Protect Register is written by performing a
random write of one byte directly to address, 1FFFh. If
a page write is performed starting with any address
other than 1FFF, the byte in the array at address
1FFFh will be written instead of the Write Protect
Register (assuming writes are not disabled by the
block protect register).
Step 3 is a nonvolatile write cycle, requiring 10ms to
complete. RWEL is reset to “0” by this write cycle,
requiring another write cycle to set RWEL again before
the block protect bits can be changed. RWEL must be
“0” in step 3; if w00yz110 is written to address 1FFFh,
RWEL is set but WPEN, BP1 and BP0 are not
changed (the device remains at step 2).
The state of the Write Protect Register can be read by
performing a random read at address 1FFFh at any
time. If a sequential read starting at any other address
than 1FFFh is performed, the contents of the byte in
the array at 1FFFh is read out instead of the Write
Protect Register.
9
X24645
Block Protect Bits
Programmable Hardware Write Protect
The Block Protect Bits BP0 and BP1 determine which
blocks of the memory are write-protected:
The Write Protect (WP) pin and the Write Protect
Enable (WPEN) bit in the Write Protect Register
control the programmable hardware write protect
feature. Hardware write protection is enabled when the
WP pin is HIGH and the WPEN bit is “1”, and disabled
when either the WP pin is LOW or the WPEN bit is “0”.
When the chip is hardware write-protected, nonvolatile
writes are disabled to the Write Protect Register,
including the BP bits and the WPEN bit itself, as well
as to block-protected sections in the memory array.
Only the sections of the memory array that are not
block-protected can be written. Note that since the
WPEN bit is write-protected, it cannot be changed
back to a LOW state, and write protection is disabled
as long as the the WP pin is held HIGH. Table 2
defines the write protection status for each state of
WPEN and WP.
Table 1. Block Protect Bits
Protected
BP1 BP0 Addresses
0
0
1
0
1
0
None
1800h–1FFFh
1000h–1FFFh
Upper 1/4
Upper 1/2
Full Array (WPR
not included)
1
1
0000h–1FFFh
2783 FRM T02
Table 2. Write Protect Status Table
Memory Array
(Not Block
Protected)
Memory Array
(Block Protected)
WP
L
WPEN
BP Bits
Writable
Writable
Protected
WPEN Bit
Writable
X
0
1
Writable
Writable
Writable
Protected
X
Protected
Writable
H
Protected
Protected
2783 FRM T03.1
10
X24645
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature under Bias
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
X24645.......................................–65°C to +135°C
Storage Temperature........................–65°C to +150°C
Voltage on any Pin with
Respect to V ....................................–1V to +7V
SS
D.C. Output Current ..............................................5mA
Lead Temperature
(Soldering, 10 seconds) ..............................300°C
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
X24645
Limits
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
+125°C
4.5V to 5.5V
2.7V to 5.5V
X24645-2.7
–40°C
–55°C
2783 FRM T05
Military
2783 FRM T04
D.C. OPERATING CHARACTERISTICS
Limits
Max.
Symbol
Parameter
Min.
Units
Test Conditions
ICC1
VCC Supply Current (Read)
1
3
mA SCL = VCC X 0.1/VCC X 0.9 Levels
@ 100KHz, SDA = Open, All Other
ICC2
VCC Supply Current (Write)
VCC Standby Current
mA
Inputs = V or VCC – 0.3V
SS
(1)
50
µA
µA
SCL = SDA = VCC, All Other
ISB1
Inputs = V or VCC – 0.3V,
SS
VCC = 5V ± 10%
(1)
VCC Standby Current
1
SCL = SDA = VCC, All Other
ISB2
Inputs = V or VCC – 0.3V,
SS
VCC = 2.7V
ILI
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
V
IN = V to VCC
SS
ILO
VOUT = V to VCC
SS
(2)
–1
VCC x 0.3
VlL
(2)
Input HIGH Voltage
Output LOW Voltage
VCC x 0.7 VCC + 0.5
0.4
V
V
VIH
VOL
IOL = 3mA, VCC = 4.5V
2783 FRM T06.2
CAPACITANCE T = +25°C, f = 1MHz, V = 5V
A
CC
Symbol
Parameter
Max.
Units
Test Conditions
VI/O = 0V
VIN = 0V
(3)
Input/Output Capacitance (SDA)
8
pF
CI/O
(3)
6
pF
Input Capacitance (S1, S2, SCL)
CIN
2783 FRM T07.1
Notes: (1) Must perform a stop command prior to measurement.
(2) V min. and V max. are for reference only and are not 100% tested.
IL
IH
(3) This parameter is periodically sampled and not 100% tested.
11
X24645
EQUIVALENT A.C. LOAD CIRCUIT
A.C. CONDITIONS OF TEST
Input Pulse Levels
VCC x 0.1 to VCC x 0.9
5V
Input Rise and
Fall Times
10ns
1.53KΩ
Input and Output
Timing Levels
OUTPUT
VCC X 0.5
2783 FRM T08
100pF
2783 ILL F16.1
A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read & Write Cycle Limits
Symbol
Parameter
SCL Clock Frequency
Min.
Max.
Units
fSCL
0
100
KHz
TI
Noise Suppression Time
100
ns
Constant at SCL, SDA Inputs
tAA
SCL LOW to SDA Data Out Valid
0.3
4.7
3.5
µs
µs
tBUF
Time the Bus Must Be Free Before a
New Transmission Can Start
tHD:STA
tLOW
Start Condition Hold Time
Clock LOW Period
4
µs
µs
µs
µs
4.7
4
tHIGH
Clock HIGH Period
tSU:STA
Start Condition Setup Time
4.7
(for a Repeated Start Condition)
tHD:DAT
tSU:DAT
tR
Data In Hold Time
0
µs
ns
µs
ns
µs
Data In Setup Time
250
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
tF
300
tSU:STO
tDH
4.7
300
ns
2783 FRM T09.2
(4)
POWER-UP TIMING
Symbol
Parameter
Max.
Units
tPUR
Power-up to Read Operation
1
5
ms
tPUW
Power-up to Write Operation
ms
2783 FRM T10
Notes: (4) t
and t
are the delays required from the time V is stable until the specified operation can be initiated.These parameters
PUW CC
PUR
are periodically sampled and not 100% tested.
12
X24645
Bus Timing
t
t
t
t
HIGH
LOW
R
F
SCL
t
t
t
t
t
SU:STA
HD:STA
HD:DAT
SU:DAT
SU:STO
SDA IN
t
t
t
AA
DH
BUF
SDA OUT
2783 ILL F17
Write Cycle Limits
Symbol
(5)
Parameter
Min.
Typ.
Max.
Units
(6)
TWR
Write Cycle Time
5
10
ms
2783 FRM T11
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
erase/program cycle. During the write cycle, the
X24645 bus interface circuits are disabled, SDA is
allowed to remain HIGH, and the device does not
respond to its slave address.
Bus Timing
SCL
ACK
SDA
8th BIT
WORD n
t
WR
2783 ILL F18
STOP
CONDITION
START
CONDITION
Notes: (5) Typical values are for T = 25°C and nominal supply voltage (5V).
A
(6) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
WR
time the device requires to automatically complete the internal write operation.
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
120
V
CC MAX
Must be
steady
Will be
steady
R
=
=1.8KΩ
MIN
I
100
80
OL MIN
t
R
May change
from LOW
to HIGH
Will change
from LOW
to HIGH
R
=
MAX
C
BUS
MAX.
60
40
20
0
RESISTANCE
May change
from HIGH
to LOW
Will change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
MIN.
RESISTANCE
20 40 60 80
120
100
0
N/A
Center Line
is High
Impedance
BUS CAPACITANCE (pF)
2783 ILL F19
13
X24645
PACKAGING INFORMATION
8-LEAD PLASTIC DUAL IN-LINE PACKAGE TYPE P
0.430 (10.92)
0.360 (9.14)
0.260 (6.60)
0.240 (6.10)
PIN 1 INDEX
PIN 1
0.060 (1.52)
0.020 (0.51)
0.300
(7.62) REF.
HALF SHOULDER WIDTH ON
ALL END PINS OPTIONAL
0.145 (3.68)
0.128 (3.25)
SEATING
PLANE
0.025 (0.64)
0.015 (0.38)
0.150 (3.81)
0.125 (3.18)
0.065 (1.65)
0.045 (1.14)
0.110 (2.79)
0.090 (2.29)
0.020 (0.51)
0.016 (0.41)
0.325 (8.25)
0.300 (7.62)
0.015 (0.38)
MAX.
0°
15°
TYP. 0.010 (0.25)
NOTE:
1. ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
2. PACKAGE DIMENSIONS EXCLUDE MOLDING FLASH
3926 FHD F01
14
X24645
PACKAGING INFORMATION
8-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.050" TYPICAL
X 45°
0.020 (0.50)
0.050"
TYPICAL
0° – 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
TYPICAL
8 PLACES
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F22.1
15
X24645
PACKAGING INFORMATION
14-LEAD PLASTIC SMALL OUTLINE GULL WING PACKAGE TYPE S
0.150 (3.80)
0.158 (4.00)
0.228 (5.80)
0.244 (6.20)
PIN 1 INDEX
PIN 1
0.014 (0.35)
0.020 (0.51)
0.336 (8.55)
0.345 (8.75)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.10)
0.010 (0.25)
0.050 (1.27)
0.050" Typical
0.010 (0.25)
0.020 (0.50)
X 45°
0° – 8°
0.050" Typical
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.41)
0.037 (0.937)
0.030" Typical
14 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F10.1
16
X24645
PACKAGING INFORMATION
20-LEAD PLASTIC, TSSOP PACKAGE TYPE V
.025 (.65) BSC
.169 (4.3)
.252 (6.4) BSC
.177 (4.5)
.252 (6.4)
.300 (6.6)
.047 (1.20)
.0075 (.19)
.002 (.05)
.0118 (.30)
.006 (.15)
.010 (.25)
Gage Plane
0° – 8°
Seating Plane
.019 (.50)
.029 (.75)
Detail A (20X)
.031 (.80)
.041 (1.05)
See Detail “A”
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
3926 FHD F45
17
X24645
ORDERING INFORMATION
X24645
X
X
-X
V
Range
CC
Device
Blank = 5V ±10%
2.7 = 2.7V to 5.5V
Temperature Range
Blank = 0°C to +70°C
I = –40°C to +85°C
M = –55°C to +125°C
Package
P = 8-Lead Plastic DIP
S8 = 8-Lead SOIC (JEDEC)
S = 14-Lead SOIC
V = 20-Lead TSSOP
Part Mark Convention
X24645
X
X
P = 8-Lead Plastic DIP
S = 14-Lead SOIC
Blank = 8-Lead SOIC (JEDEC)
V = 20-Lead TSSOP
Blank = 4.5V to 5.5V, 0°C to +70°C
I = 4.5V to 5.5V, –40°C to +85°C
F = 2.7V to 5.5V, 0°C to +70°C
G = 2.7V to 5.5V, –40°C to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.
makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the
right to discontinue production and change specifications and prices at any time and without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,
licenses are implied.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;
4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;
4,883, 976. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with
appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.
Xicor's products are not authorized for use in critical components in life support devices or systems.
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain
life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably
expected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
18
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