5962-8852512XX [XICOR]
EEPROM, 32KX8, 200ns, Parallel, CMOS, CDIP28, CERAMIC, DIP-28;
| 型号： | 5962-8852512XX |
| 厂家： | 
XICOR INC. |
| 描述： | EEPROM, 32KX8, 200ns, Parallel, CMOS, CDIP28, CERAMIC, DIP-28 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 CD 内存集成电路 |
| 文件： | 总28页 (文件大小：238K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
REVISIONS
LTR
A
DESCRIPTION
DATE (YR-MO-DA)
92-01-27
APPROVED
M. A. Frye
M. A. Frye
Add "Changes in accordance with NOR 5962-R115-92."
B
Add software data protection. Increase data retention to 20 years,
93-07-21
minimum. Add device types 08 through 16. Remove tests tDHWL
WHDX, and ESDS requirements from drawing.
,
t
C
D
Add "Changes in accordance with NOR 5962-R071-95."
Updated boilerplate paragraphs. ksr
95-02-14
05-04-15
M. A. Frye
Raymond Monnin
The original first page has been replaced.
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PMIC N/A
PREPARED BY
Kenneth Rice
CHECKED BY
DEFENSE SUPPLY CENTER COLUMBUS
STANDARD
MICROCIRCUIT
DRAWING
COLUMBUS, OHIO 43218-3990
http://www.dscc.dla.mil
Raymond Monnin
APPROVED BY
Michael A. Frye
THIS DRAWING IS
AVAILABLE
MICROCIRCUIT, MEMORY,
DIGITAL, CMOS 32K X 8
EEPROM, MONOLITHIC
SILICON
FOR USE BY ALL
DEPARTMENTS
DRAWING APPROVAL DATE
88-08-29
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE
AMSC N/A
REVISION LEVEL
D
SIZE
A
CAGE CODE
5962-88525
67268
SHEET
1 OF 23
DSCC FORM 2233
APR 97
.
5962-E286-05
1. SCOPE
1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in
accordance with MIL-PRF-38535, appendix A.
1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:
5962-88525
01
X
A
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
⏐
Drawing number
Device type
(see 1.2.1)
Case outline
(see 1.2.2)
Lead finish
(see 1.2.3)
1.2.1 Device type(s). The device type(s) identify the circuit function as follows:
Access Write
time speed
Write
mode
End of Write
Indicator
Software data
Endurance protect
Device type Generic number
See 6.6
Circuit function
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
(32K X 8 EEPROM) 350 ns 10 ms byte/page DATA polling 10,000 cycles
No
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
300 ns 10 ms byte/page
250 ns 10 ms byte/page
200 ns 10 ms byte/page
250 ns 10 ms byte/page
150 ns 10 ms byte/page
150 ns 3 ms byte/page
150 ns 10 ms byte/page
350 ns 10 ms byte/page
300 ns 10 ms byte/page
250 ns 10 ms byte/page
200 ns 10 ms byte/page
250 ns 10 ms byte/page
150 ns 10 ms byte/page
150 ns 3 ms byte/page
150 ns 10 ms byte/page
polling 10,000 cycles
polling 10,000 cycles
polling 10,000 cycles
polling 100,000 cycles
polling 10,000 cycles
polling 10,000 cycles
polling 100,000 cycles
polling 10,000 cycles
polling 10,000 cycles
polling 10,000 cycles
polling 10,000 cycles
polling 100,000 cycles
polling 10,000 cycles
polling 10,000 cycles
polling 100,000 cycles
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter
Descriptive designator
Terminals
Package style
U
X
Y
Z
See figure 1
GDIPI-T28 or CDIP2-T28
CQCC1-N32
128
28
32
Grid array
Dual-in-line
Rectangular leadless chip carrier
Flat package
CDFP4-F28
28
1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.
SIZE
STANDARD
MICROCIRCUIT DRAWING
5962-88525
A
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
SHEET
D
2
DSCC FORM 2234
APR 97
1.3 Absolute maximum ratings. 1/
Supply voltage range (VCC) ............................................................................
Storage temperature range ............................................................................
Maximum power dissipation (PD)....................................................................
Lead temperature (soldering, 10 seconds).....................................................
Junction temperature (TJ) 2/...........................................................................
Thermal resistance, junction-to-case (ΘJC).....................................................
Input voltage range (VIL, VIH)..........................................................................
Data retention.................................................................................................
Endurance:
-0.3 V dc to +6.25 V dc
-65°C to +150°C
1.0 W
+300°C
+175°C
See MIL-STD-1835
-0.3 V dc to +6.25 V dc
10 years (minimum)
Types 01-04, 06, 07, 09-12, 14, 15 ..............................................................
Types 05, 08, 13 ,16.....................................................................................
Chip clear voltage (VH) ...................................................................................
10,000 cycles/byte (minimum)
100,000 cycles/byte (minimum)
15.0 V dc
1.4 Recommended operating conditions. 1/
Supply voltage range (VCC) ............................................................................
Case operating temperature range (TC) .........................................................
Input voltage, low range (VIL)..........................................................................
Input voltage, high range (VIH)........................................................................
+4.5 V dc to +5.5 V dc
-55°C to +125°C
-0.1 V dc to +0.8 V dc
+2.0 V dc to VCC +0.3 V dc
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883
-
Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from
the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-
JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer
Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-
PRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying
activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan
may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device.
These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-
PRF-38535 is required to identify when the QML flow option is used.
1/ All voltages are referenced to VSS (ground).
2/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in
accordance with method 5004 of MIL-STD-883.
SIZE
STANDARD
5962-88525
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
SHEET
D
3
DSCC FORM 2234
APR 97
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535, appendix A and herein.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein and on figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Truth table(s). See 3.2.3.1 and 3.2.3.2
3.2.3.1 Unprogrammed or erased devices. The truth table for unprogrammed devices shall be as specified on figure 3.
3.2.3.2 Programmed devices. The requirements for supplying programmed devices are not part of this drawing.
3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are
as specified in table I and shall apply over the full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are described in table I.
3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed
in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN
number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device.
3.5.1 Certification/compliance mark. A compliance indicator “C” shall be marked on all non-JAN devices built in compliance
to MIL-PRF-38535, appendix A. The compliance indicator “C” shall be replaced with a "Q" or "QML" certification mark in
accordance with MIL-PRF-38535 to identify when the QML flow option is used.
3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an
approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to
listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535,
appendix A and the requirements herein.
3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided
with each lot of microcircuits delivered to this drawing.
3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing.
3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's
facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the
reviewer.
3.10 Processing EEPROMS. All testing requirements and quality assurance provisions herein shall be satisfied by the
manufacturer prior to delivery.
3.10.1 Erasure of EEPROMS. When specified, devices shall be erased in accordance with the procedures and
characteristics specified in 4.4.3.
3.10.2 Programmability of EEPROMS. When specified, devices shall be programmed to the specified pattern using the
procedures and characteristics specified in 4.4.2. Software data protect procedures shall be as specified in 4.4.5.
3.10.3 Verification of erasure or programmability of EPROMS. When specified, devices shall be verified as either programmed
to the specified pattern or erased. As a minimum, verification shall consist of reading the device per the procedures and
characteristics specified in 4.4.4. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall
be removed from the lot.
SIZE
STANDARD
5962-88525
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
SHEET
D
4
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics.
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Test
│Symbol
│
│
│
│
│
│
Conditions
-55°C ≤ TC ≤+125°C
VSS = 0 V,
│Group A │Device│ Limits
│subgroups │types
│
│
│
│
│
Unit
│
│
│
│
4.5 V ≤ VCC ≤ 5.5 V
│
│
│
│
│ Min
│ Max
│unless otherwise specified 1/
│
│
│
│
│
│
│
│
Supply current
(active)
│ICC1
│ CE = OE = VIL, WE = VIH
│ all I/O's = 0 mA,
│Inputs = VCC = 5.5 V,
│f = 1/tAVAV (minimum)
│
│
│ 1,2,3
│ All
│
│ 80
│ mA
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Supply current
(TTL standby)
│ICC2
│ CE = VIH, OE = VIL
│ all I/O's = 0 mA
│Inputs = VCC -0.3 V
│
│
│ 1,2,3
│ All
│
│ 3
│ mA
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Supply current
│ICC3
│ CE = VCC -0.3 V
│ 1,2,3
│ All
│
│ 350 │ µA
(CMOS standby)
│
│ all I/O's = 0 mA,
│
│
│
│
│
│
│Inputs = VIL to VCC -0.3 V
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Input leakage (high)
Input leakage (low)
│IIH
│
│VIN = 5.5 V
│ 1,2,3
│ All
│ -10
│ 10
│ µA
│
│
│
│
│
│
│
│
│
│
│ All
│
│
│
│ -10
│
│
│
│ 10
│
│
│
│IIL
│
│
│VIN = 0.1 V
│
│
│ 1,2,3
│
│
│ µA
│
│
Output leakage (high) │IOHZ 2/ │VOUT = 5.5 V, CE = VIH
│ 1,2,3
│
│
│ All
│
│
│ -10
│
│
│ 10
│
│
│ µA
│
│
│
│
│
│
Output leakage (low)
Input voltage low
Input voltage high
Output voltage low
│IOLZ 2/ │VOUT = 0.1 V, CE = VIH
│ 1,2,3
│
│
│ 1,2,3
│
│
│ 1,2,3
│
│
│ All
│
│
│ All
│
│
│ All
│
│
│ -10
│
│
│-0.1
│
│
│ 2.0
│
│
│ 10
│
│ µA
│
│
│
│
│
│
│
│VIL
│
│ 0.8
│
│
│VCC
│+ 0.3V │
│
│ V
│
│
│
│
│
│
│VIH
│
│ V
│
│
│
│
│
│VOL
│IOL = 2.1 mA, VIH = 2.0 V
│ 1,2,3
│ All
│
│ 0.45 │ V
│
│VCC = 4.5 V, VIL = 0.8 V
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│VOH
│
│
│
│
│
│
│ All
│
│
│
│
│ 2.4
│
│
│
│
│ V
│
│
│
Output voltage high
│IOH = -400 µA, VIH = 2.0 V
│VCC = 4.5 V, VIL = 0.8 V
│
│
│ 1,2,3
│
│
│
OE high leakage
(chip erase)
│IOE
│
│VH = 13 V
│
│ 1,2,3
│
│ All
│
│ -10
│
│ 100 │ µA
│
│
See footnotes at end of table.
SIZE
STANDARD
5962-88525
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
SHEET
D
5
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│ pF
│
│
│
Test
│Symbol
│
│
│
│
│
│
Conditions
-55°C ≤ TC ≤+125°C
VSS = 0 V,
│Group A
│subgroups │ types
│
│
│ Device
Limits
Unit
│
│
4.5 V ≤ VCC ≤ 5.5 V
│
│
│
│
│
│
│
│
│
│ Min
│ Max
│unless otherwise specified 1/
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Input capacitance
Output capacitance
Read cycle time
│CI 3/ 4/ │VIN = 0 V, VCC = 5.0 V
│ 4
All
All
│ 10
│
│
│
│
│
│
│TA = +25°C, f = 1 MHz
│See 4.3.1c
│
│
│
│
│CO 3/ 4/ │VOUT = 0 V, VCC = 5.0 V
│
4
│ 10
│ pF
│
│
│
│TA = +25°C, f = 1 MHz
│See 4.3.1c
│
│
│
│
│
│
│
│
│350
│300
│
│
│
│
│
│
│
│ ns
│ 01,09
│ 02,10
│tAVAV 5/ │See figure 4
│ 9,10,11
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│03,05,11,13 │250
│ 04,12 │200
│06-08,14-16 │150
│
│
│
│
│
│
│
│ 01,09
│ 02,10
│
│
│ 350
│ 300 │ ns
│ 250
│ 200
│ 150
│ 350
Address access time │tAVQV 5/
│ 9,10,11
│
│
│
│
│
│
│
│03,05,11,13 │
│ 04,12
│06-08,14-16 │
│
│
│
│
│
│
│ 01,09
│ 02,10
│
│
Chip enable access
time
│tELQV 5/
│ 9,10,11
│
│
│
│ 300 │ ns
│
│
│
│
│03,05,11,13 │
│ 04,12
│06-08,14-16 │
│ 250
│ 200
│ 150
│
│ 100 │ ns
│
│ 80
│
│
│
│
│
│
│
│
│01-03,05
│09-11,13
│
│
Output enable access │tOLQV 5/
│ 9,10,11
│
│
│
time
│
│
│
│04,06,07,08 │
│12,14,15,16 │
│
│
│
│
│
Chip enable to output │tELQX 4/
│ 9,10,11
│ All
│ 10
│
│ ns
in low Z
│
│
│
5/
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Chip disable to
output in high Z
│tEHQZ 4/
│ 9,10,11
│
│
│
│01,02,09,10 │
│ 80
│
│ 60
│
│ ns
│
│
│
│
│
│
5/
│
│
│03-08,11-16 │
│
│
Output enable to
output in low Z
│tOLQX 4/
│ 9,10,11
│ All
│ 10
│
│
│ ns
│
│
│
5/
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Output disable to
output in high Z
│tOHQZ 4/
│ 9,10,11
│
│
│
│ 9,10,11
│
│
│01,02,09,10 │
│ 80
│
│ 60
│
│
│
│
│ ns
│
│
│
│ ns
│
│
│
│
│
5/
│
│
│03-08,11-16 │
│
│
Output hold from
address change
│tAXQX 4/
│
│
│ All
│
│
│ 0
│
│
5/
See footnotes at end of table.
SIZE
STANDARD
5962-88525
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
SHEET
D
6
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
│
│
│
│
│
│
│
│
│
│
│
│
│
Test
│Symbol
│
│
│
│
│
│
Conditions
-55°C ≤ TC ≤+125°C
VSS = 0 V,
│Group A
│subgroups │ types
│
│
│ Device
Limits
│ Unit
│
│
│
│
│
│
│
│
│
│
4.5 V ≤ VCC ≤ 5.5 V
│ Min
│
│
│ Max
│
│
│unless otherwise specified 1/ │
│
│
│
│
│ 01-06,
│
│
│
Write cycle time
│tWHWL1 │See figure 5 or 7
│ 9,10,11
│
│ 08-14,
│ 16
│
│
│ 10
│
│ ms
│
│tEHEL1
│ as applicable
│
│
5/
│
│
│
│
│
│
│
│ 20
│
│ 3
│
│
│
│ ns
│ 07,15
│ All
Address set-up time
Address hold time
│tAVEL 5/ │See figures 5, 6, or 7
│ 9,10,11
│tAVWL
│ as applicable
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│tELAX 5/
│tWLAX
│
│
│tWLEL 5/
│tELWL
│
│
│tEHWH 5/ │
│tWHEH
│
│
│ 9,10,11
│ All
│ 150
│
│ ns
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Write set-up time
Write hold time
│ 9,10,11
│ All
│ 0
│
│
│
│ 0
│
│
│
│
│ ns
│
│
│
│
│
│
│
│
│
│
│
│
│ 9,10,11
│ All
│
│ ns
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
OE set-up time
OE hold time
│tOHEL
│tOHWL 5/ │
│
│
│
│ 9,10,11
│ All
│ 20
│
│ ns
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│tEHOL
│
│ 9,10,11
│ All
│ 20
│
│ ns
│tWHOL 5/ │
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
WE pulse width
│tELEH
│tWLWH
│ 5/ 6/
│
│
│
│
│
│
│
│ 9,10,11
│
│ All
│
│ .150
│
│ 1
│
│ µs
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Data set-up time
Delay to next write
Data hold time
│tDVEH
│tDVWH 5/ │
│
│
│ 9,10,11
│ All
│ 50
│
│ ns
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│tDVWL 4/
│tDVEL 5/
│
│ 9,10,11
│ All
│
│ 10 │ µs
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│tEHDX
│tWHDX 5/ │
│
│
│ 9,10,11
│ All
│ 10
│ ns
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Byte load cycle
│tWHWL2 │See figure 5 or 7
│ 5/ 6/ │ as applicable
│ 9,10,11
│
│
│ All
│
│
│ .20
│
│
│ 149 │ µs
│
│
│
│
│
│
See footnotes at end of table.
SIZE
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7
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
│
│
│
│
│
│
│
│
│
│
│
│
│
Test
│Symbol
│
│
Conditions
-55°C ≤ TC ≤+125°C
VSS = 0 V,
│Group A
│subgroups │ types
│
│
│ Device
Limits
│ Unit
│
│
│
│
│
│
│
│
│
│
4.5 V ≤ VCC ≤ 5.5 V
│ Min
│ Max
│
│unless otherwise specified 1/
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
Last byte loaded to
data polling
│tWHEL
│See figure 5 or 6
│ 9,10,11
│ All
│ 650 │ µs
│tEHEL 5/ │ as applicable
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
│
CE setup time
│tELWL 5/ │See figure 8
│ 9,10,11
│
│
│ 9,10,11
│
│
│ All
│
│
│ All
│
│
│ 5
│
│
│ 5
│
│
│
│
│
│
│
│
│ µs
│
│
│ µs
│
│
│
│
│
│
│
│
│
5/
Output set-up time
│tOVHWL
│
│
CE hold time
│tWHEH 5/ │
│ 9,10,11
│
│
│ All
│
│
│ 5
│
│
│
│
│
│ µs
│
│
│
│
│
5/
│
OE hold time
High voltage
Chip erase
│tWHOH
│
│
│VH 5/
│
│
│
│
│
│
│
│
│
│
│ 9,10,11
│
│
│ 9,10,11
│
│
│ 9,10,11
│
│
│ All
│
│
│ All
│
│
│ All
│
│
│ 5
│
│
│
│
│ µs
│
│
│ V
│
│
│
│ 12
│
│
│ 13
│
│
│210 │ ms
│
│
│
5/
│tWLWH2
│
│
│
│
│
│
│
WE pulse width for │tWLWH15/ │
chip erase
│ 9,10,11
│
│ All
│
│ 10
│
│
│
│ ms
│
│
│
1/ DC and read mode.
2/ Connect all address inputs and OE to VIH and measure IOLZ and IOHZ with the output under test connected to VOUT
3/ All pins not being tested are to be open.
.
4/ Tested initially and after any design or process changes that affect that parameter, and therefore shall be guaranteed to the
limits specified in table I.
5/ Tested by application of specified timing signals and conditions, including:
Equivalent ac test conditions:
Devices: All.
Output load: 1 TTL gate and CL = 100 pF (minimum) or equivalent circuit.
Input rise and fall times ≤ 10 ns.
Input pulse levels: 0.4 V and 2.4 V.
Timing measurements reference levels:
Inputs: 1 V and 2 V.
Outputs: 0.8 V and 2 V.
6/ During a page write operation the cycle time defined by tWLWH and tWHWL2 shall not be less than 1 µs.
SIZE
STANDARD
5962-88525
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
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REVISION LEVEL
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8
DSCC FORM 2234
APR 97
NOTES:
1. Dimensions are in inches.
2. Metric equivalents are given for general information only.
Inches
.002
.005
.008
.010
.012
.050
.067
.075
.100
.180
.551
.650
mm
0.05
0.13
0.20
0.25
0.30
1.27
1.70
1.90
2.54
4.57
14.00
16.51
FIGURE 1. Case outline.
SIZE
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MICROCIRCUIT DRAWING
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DSCC FORM 2234
APR 97
Device types
All
Case outlines
U, X,
Z
Y
Terminal numbers
Terminal symbols
1
2
A14
A12
A7
NC
A14
A12
A7
3
4
A6
5
A5
A6
6
A4
A5
7
A3
A4
8
A2
A3
9
A1
A2
10
11
12
13
14
15
16
17
18
19
A0
A1
I/O0
I/O1
I/O2
VSS
I/O3
I/O4
I/O5
I/O6
I/O7
A0
NC
I/O0
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
I/O6
CE
20
21
A10
I/O7
OE
A11
A9
22
23
24
CE
A10
A8
25
26
OE
NC
A11
A9
A13
WE
27
28
29
30
31
32
VCC
---
A8
---
A13
---
WE
---
VCC
FIGURE 2. Terminal connections.
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Mode
I/O
Device type
All
CE
VIL
VIH
VIL
VIL
X
OE
VIL
X
WE
VIH
X
Read
DOUT
High Z
Standby
Chip clear
Byte write
Write inhibit
Write inhibit
VH
VIH
VIL
X
VIL
VIL
X
DIN = VIH
Data in
High Z/D out
High Z/D out
X
VIH
X = Don't care state.
FIGURE3. Truth table for unprogrammed devices.
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FIGURE 4. Timing waveforms.
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CE
FIGURE 5.
controlled byte write programming waveform.
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WE
FIGURE 6.
controlled byte write programming waveform.
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Note: The page write operation of the device allows 2 to 64 bytes of data to be loaded into the device and then simultaneously
written during the internal programming period.
FIGURE 7. Page write programming waveform.
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FIGURE 8. Timer chip clear waveform.
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NOTES:
1. Software chip clear timings are referenced to WE or CE inputs, whichever is last to go low, and the WE or CE
inputs, whichever is first to go high.
2. The command sequence must conform to the page write timing.
FIGURE 9. Software chip clear algorithm (device types 09-16).
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NOTES:
1. Software data protection timings are referenced to the WE or CE inputs, whichever is last to go low, and the
WE or CE inputs, whichever is first to go high.
2. The command sequence and subsequent data must conform to page write timing.
FIGURE 10. Set software data protect algorithm (device types 09-16).
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NOTES:
1. Reset software data protection timings are referenced to the WE or CE inputs, whichever is last to go low,
and the WE or CE inputs, whichever is first to go high.
2. The command sequence and subsequent data must conform to page write timing.
FIGURE 11. Reset software data protect algorithm(device types 09-16).
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4. VERIFICATION
4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535,
appendix A.
4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices
prior to quality conformance inspection. The following additional criteria shall apply:
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition D or F. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1015 of MIL-STD-883.
(2) TA = +125°C, minimum.
(3) Devices shall be burned-in containing a checkerboard pattern or equivalent.
b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter
tests prior to burn-in are optional at the discretion of the manufacturer.
c. An endurance/data retention test prior to burn-in, in accordance with method 1033 of MIL-STD-883, shall be included
as part of the screening procedure with the following conditions:
(1) Cycling may be block, byte, or page at equipment room ambient temperature and shall cycle all bytes for a minimum
of 10,000 cycles for devices 01-04, 06,07, 09-12, 14,15 and a minimum of 50,000 cycles for device 05,08,13, and
16.
(2) After cycling, perform a high temperature unbiased bake for 72 hours at +150°C (minimum). The storage time may
be accelerated by using higher temperature in accordance with the Arrhenius Relationship:
A = acceleration factor (unitless quantity) = t / t
2
F
1
T = temperature in Kelvin (i.e., t + 273)
1
t1 = time (hrs) at temperature T1
t2 = time (hrs) at temperature T2
K = Boltzmanns constant = 8.62 x 10-5eV/°K using an apparent activation energy (E ) of 0.6 eV.
A
The maximum storage temperature shall not exceed +200°C for packaged devices or +300°C for unassembled devices.
(3) Read the data retention pattern and test using subgroups 1, 7, and 9 (minimum, e.g., high temperature equivalent
subgroups 2, 8A, and 10 may be used) after cycling and bake, prior to burn-in. Devices having bits not in the proper
state after storage shall constitute a device failure.
4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of
MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply.
4.3.1 Group A inspection.
a. Tests shall be as specified in table II herein.
b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted.
c. Subgroup 4 (CI and CO measurement) shall be measured only for the initial test and after process or design changes
which may affect input or output capacitance.
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DSCC FORM 2234
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d. Subgroups 7 and 8 shall include verification of the truth table.
4.3.2 Group C inspections.
a. End-point electrical parameters shall be as specified in table II herein.
b. All devices requiring end-point electrical testing shall be programmed with a checkerboard or equivalent alternating bit
pattern.
c. Steady-state life test conditions, method 1005 of MIL-STD-883.
(1) Test condition D or F. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1005 of MIL-STD-883.
(2) TA = +125°C, minimum.
(3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
d. An endurance test, in accordance with method 1033 of MIL-STD-883, shall be added to group C inspection prior to
performing the steady-state life test (see 4.3.2c) and extended data retention (see 4.3.2e).
Cycling may be block, byte, or page from devices passing group A after the completion of the requirements of 4.2
herein. Initially, two groups of devices shall be formed, cell 1 and cell 2.
The following conditions shall be met:
(1) Cell 1 shall be cycled at -55°C and cell 2 shall be cycled at +125°C for a minimum of 10,000 cycles for device
types 01-04,06,07,09-12,14,15 and 100,000 cycles for device types 05,08,13, and 16.
(2) Perform group A subgroups 1, 7, and 9 after cycling. Form two new cells (cells 3 and 4) for steady-state life and
extended data retention. Cell 3 for steady-state life test consists of one-half of the devices from cell 1 and one-
half of the devices from cell 2. Cell 4 for extended data retention consists of the remaining devices from cells 1
and 2.
(3) The sample plans for cell 1, cell 2, cell 3, and cell 4 shall individually be the same as for group C, as specified in
method 5005 of MIL-STD-883.
e. Extended data retention shall consist of:
(1) All devices shall be programmed with a charge on all memory cells in each device, such that the cell will read
opposite the state that the cell would read in its equilibrium state (e.g., worst case pattern, see 4.2a(3)).
(2) Unbiased bake for 1000 hours (minimum) at +150°C (minimum). The unbiased bake time may be accelerated by
using higher temperature in accordance with the Arrhenius Relationship:
A = acceleration factor (unitless quantity) = t / t
F
1
2
T = temperature in Kelvin (i.e., t1+ 273)
t1 = time (hrs) at temperature T1
t2 = time (hrs) at temperature T2
K = Boltzmanns constant = 8.62 x 10-5eV/°K using an apparent activation energy (EA) of 0.6 eV.
The maximum storage temperature shall not exceed +200°C for packaged devices or +300°C for unassembled devices.
SIZE
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(3) Read the pattern after bake and perform endpoint electrical tests for table II herein for group C.
4.3.3 Groups D inspections. Group D inspection shall be in accordance with table IV of method 5005 of MIL-STD-883 and as
follows:
a. End-point electrical parameters shall be as specified in table II herein.
b. All devices requiring end-point electrical testing shall be programmed with a checkerboard or equivalent alternating bit
pattern.
TABLE II. Electrical test requirements. 1/ 2/ 3/ 4/ 5/
MIL-STD-883 test requirements
Subgroups
(in accordance with
MIL-STD-883, method 5005,
table I)
Interim electrical parameters
(method 5004)
1, 7, 9 or 2, 8A, 10
1*, 2, 3, 7*, 8, 9, 10, 11
1, 2, 3, 4**, 7, 8, 9, 10, 11
1, 2, 3, 7, 8, 9, 10 ,11
Final electrical test parameters
(method 5004)
Group A test requirements
(method 5005)
Groups C and D end-point
electrical parameters
(method 5005)
1/ (*) Indicates PDA applies to subgroups 1 and 7.
2/ Any or all subgroups may be combined when using multifunction testers.
3/ Subgroup 7 and 8 shall consist of writing and reading the data pattern specified
in accordance with the limits of table I subgroups 9, 10, and 11.
4/ For all electrical tests, the device shall be programmed to the data pattern specified.
5/ (**) Indicates that subgroup 4 will only be performed during initial qualification and after
design or process changes (see 4.3.1c).
4.4 Methods of inspection. Methods of inspection shall be as specified in the appropriate tables of method 5005 of
MIL-STD-883 and as follows.
4.4.1 Voltage and current. All voltages given are referenced to the microcircuit VSS terminal. Currents given are conventional
current and positive when flowing into the referenced terminal.
4.4.2 Programming procedure. The following procedure shall be followed when programming (Write) is performed. The
waveforms and timing relationships shown on figure 5 (in accordance with appropriate device type) and the conditions specified
in table I shall be adhered to. Information is introduced by selectively programming a TTL low or TTL high on each I/O of the
address desired. Functionality shall be verified at all temperatures (group A subgroups 7 and 8) by programming all bytes of
each device and verifying the pattern used.
4.4.3 Erasing procedure. There are two forms of erasure, chip and byte, whereby all bits or the address selected will be
erased to a TTL high.
a. Chip erase is performed in accordance with the waveforms and timing relationships shown on figure 8 (in accordance
with appropriate device type) and the conditions specified in table I.
SIZE
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b. Byte erase is performed in accordance with the waveforms and timing relationships shown on figures 5, 6, and 7 (in
accordance with appropriate device type) and the conditions specified in table I.
4.4.4 Read mode operation. The waveforms and timing relationships shown on figure 4 and the conditions specified in table I
shall be applied when reading the device. Pattern verification utilizes the read mode.
4.4.5 Software data protection. Device types 09-16 software data protection offers a method of preventing inadvertent writes
(see figure 9). The instructions, waveforms, and timing relationships shown on figures 4, 5, 6, 7, 10, and 11, and the conditions
specified in table I shall apply (see 3.10.2).
4.4.5.1 Set software data protection. Device types 09-16 are placed in protected state by writing a series of instructions (see
figure 10) to the device. Once protected, writing to the device may only be performed by executing the same sequence of
instructions appended with either a byte write operation or page write operation. The waveforms and timing relationships shown
on figures 5, 6, and 7 and the test conditions and limits specified in table I shall apply.
4.4.5.2 Reset software data protection. Device types 09-16 protection feature is reset by writing a series of instructions (see
figure 11) to the device. The waveforms and timing relationships shown on figures 5, 6, and 7 and the test conditions and limits
specified in table I shall apply.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A.
6. NOTES
6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a
contractor-prepared specification or drawing.
6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be
used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC
5962) should contact DSCC-VA, telephone (614) 692-0544.
6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MIL-
HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by
DSCC-VA.
SIZE
STANDARD
5962-88525
A
MICROCIRCUIT DRAWING
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
REVISION LEVEL
SHEET
D
23
DSCC FORM 2234
APR 97
STANDARD MICROCIRCUIT DRAWING BULLETIN
DATE: 05-04-15
Approved sources of supply for SMD 5962-88525 are listed below for immediate acquisition only and shall be added
to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to
include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of
compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next
dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of
supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-8852501XA
5962-8852501YA
5962-8852501ZA
5962-8852501UA
5962-8852502XA
5962-8852502YA
5962-8852502ZA
5962-8852502UA
5962-8852503XA
1FN41
AT28C256-35DM/883
DM28C256-350/B
X28C256DMB-35
3/
3/
1FN41
AT28C256-35LM/883
LM28C256-350/B
X28C256EMB-35
3/
3/
1FN41
AT28C256-35FM/883
FM28C256-350/B
X28C256FMB-35
3/
3/
1FN41
AT28C256-35UM/883
TM28C256-350/B
X28C256KMB-35
3/
3/
1FN41
AT28C256-30DM/883
DM28C256-300/B
X28C256DMB-30
3/
3/
1FN41
AT28C256-30LM/883
LM28C256-300/B
X28C256EMB-30
3/
3/
1FN41
AT28C256-30FM/883
FM28C256-300/B
X28C256FMB-30
3/
3/
1FN41
AT28C256-30UM/883
TM28C256-300/B
X28C256KMB-30
3/
3/
1FN41
AT28C256-25DM/883
DM28C256-250/B
X28C256DMB-25
3/
3/
See notes at end of table.
Page 1 of 5
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-8852503YA
5962-8852503ZA
5962-8852503UA
5962-8852504XA
5962-8852504YA
5962-8852504ZA
5962-8852504UA
5962-8852505XA
5962-8852505YA
5962-8852505ZA
1FN41
AT28C256-25LM/883
LM28C256-250/B
X28C256EMB-25
3/
3/
1FN41
AT28C256-25FM/883
FM28C256-250/B
X28C256FMB-25
3/
3/
1FN41
AT28C256-25UM/883
TM28C256-250/B
X28C256KMB-25
3/
3/
1FN41
AT28C256-20DM/883
DM28C256-200/B
X28C256DMB-20
3/
3/
1FN41
AT28C256-20LM/883
LM28C256-200/B
X28C256EMB-20
3/
3/
1FN41
AT28C256-20FM/883
FM28C256-200/B
X28C256FMB-20
3/
3/
1FN41
AT28C256-20UM/883
TM28C256-200/B
X28C256KMB-20
3/
3/
1FN41
AT28C256E-25DM/883
DM28C256-250/B
X28C256DMB-25
3/
3/
1FN41
AT28C256E-25LM/883
LM28C256-250/B
X28C256EMB-25
3/
3/
1FN41
AT28C256E-25FM/883
FM28C256-250/B
X28C256FMB-25
3/
3/
5962-8852505UA
5962-8852506XA
1FN41
AT28C256E-25UM/883
1FN41
AT28C256-15DM/883
DM28C256A-150/B
X28C256DMB-15
3/
3/
See notes at end of table.
Page 2 of 5
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-8852506YA
5962-8852506ZA
5962-8852506UA
1FN41
AT28C256-15LM/883
LM28C256A-150/B
X28C256EMB-15
3/
3/
1FN41
AT28C256-15FM/883
FM28C256A-150/B
X28C256FMB-15
3/
3/
1FN41
AT28C256-15UM/883
TM28C256A-150/B
X28C256KMB-15
3/
3/
5962-8852507XA
5962-8852507YA
1FN41
3/
AT28C256F-15DM/883
DM28C256AH-150/B
AT28C256F-15LM/883
LM28C256AH-150/B
1FN41
3/
5962-8852507ZA
5962-8852507UA
5962-8852508XA
1FN41
3/
AT28C256F-15FM/883
FM28C256AH-150/B
1FN41
3/
AT28C256F-15UM/883
TM28C256AH-150/B
1FN41
AT28C256E-15DM/883
DM55C256A-150/B
X28C256DMB-15
3/
3/
5962-8852508YA
5962-8852508ZA
1FN41
AT28C256E-15LM/883
LM55C256A-150/B
X28C256EMB-15
3/
3/
1FN41
AT28C256E-15FM/883
FM55C256A-150/B
X28C256FMB-15
3/
3/
5962-8852508UA
5962-8852509XA
1FN41
1FN41
3/
AT28C256E-15UM/883
AT28C256-35DM/883
X28C256DMB-35
5962-8852509YA
5962-8852509ZA
1FN41
3/
AT28C256F-35LM/883
X28C256EMB-35
1FN41
3/
AT28C256F-35FM/883
X28C256FMB-35
See notes at end of table.
Page 3 of 5
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-8852509UA
5962-8852510XA
5962-8852510YA
5962-8852510ZA
5962-8852510UA
5962-8852511XA
5962-8852511YA
5962-8852511ZA
5962-8852511UA
5962-8852512XA
5962-8852512YA
5962-8852512ZA
5962-8852512UA
5962-8852513XA
5962-8852513YA
5962-8852513ZA
1FN41
3/
AT28C256F-35UM/883
X28C256KMB-35
1FN41
3/
AT28C256-30DM/883
X28C256DMB-30
1FN41
3/
AT28C256-30LM/883
X28C256EMB-30
1FN41
3/
AT28C256-30FM/883
X28C256FMB-30
1FN41
3/
AT28C256-30UM/883
X28C256KMB-30
1FN41
3/
AT28C256-25DM/883
X28C256DMB-25
1FN41
3/
AT28C256-25LM/883
X28C256EMB-25
1FN41
3/
AT28C256-25FM/883
X28C256FMB-25
1FN41
3/
AT28C256-25UM/883
X28C256KMB-25
1FN41
3/
AT28C256-20DM/883
X28C256DMB-20
1FN41
3/
AT28C256-20LM/883
X28C256EMB-20
1FN41
3/
AT28C256-20FM/883
X28C256FMB-20
1FN41
3/
AT28C256-20UM/883
X28C256KMB-20
1FN41
3/
AT28C256E-25DM/883
X28C256DMB-25
1FN41
3/
AT28C256E-25LM/883
X28C256EMB-25
1FN41
3/
AT28C256E-25FM/883
X28C256FMB-25
See notes at end of table.
Page 4 of 5
Standard
microcircuit drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
5962-8852513UA
5962-8852514XA
5962-8852514YA
5962-8852514ZA
5962-8852514UA
1FN41
3/
AT28C256E-25UM/883
X28C256KMB-25
1FN41
3/
AT28C256-15DM/883
X28C256DMB-15
1FN41
3/
AT28C256-15LM/883
X28C256EMB-15
1FN41
3/
AT28C256-15FM/883
X28C256FMB-15
1FN41
3/
AT28C256-15UM/883
X28C256KMB-15
5962-8852515XA
5962-8852515YA
5962-8852515ZA
5962-8852515UA
5962-8852516XA
1FN41
1FN41
1FN41
1FN41
AT28C256F-15DM/883
AT28C256F-15LM/883
AT28C256F-15FM/883
AT28C256-15UM/883
1FN41
3/
AT28C256E-15DM/883
X28C256DMB-15
5962-8852516YA
5962-8852516ZA
5962-8852516UA
1FN41
3/
AT28C256E-15LM/883
X28C256EMB-15
1FN41
3/
AT28C256E-15FM/883
X28C256FMB-15
1FN41
AT28C256E-15UM/883
1/
The lead finish shown for each PIN representing a hermetic package is the most readily
available from the manufacturer listed for that part. If the desired lead finish is not listed
contact the vendor to determine its availability.
2/
3/
Caution. Do not use this number for item acquisition. Items acquired to this number
may not satisfy the performance requirements of this drawing.
Not available from an approved source.
Vendor CAGE
number
Vendor name
and address
1FN41
ATMEL Corporation
2325 Orchard Parkway
San Jose, CA 95131
The information contained herein is disseminated for convenience only and the
Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
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