W78IE52_06 [WINBOND]
8-BIT MICROCONTROLLER; 8位微控制器
| 型号： | W78IE52_06 |
| 厂家： | 
WINBOND |
| 描述： | 8-BIT MICROCONTROLLER |
| 文件： | 总26页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W78IE52/W78I052A
8-BIT MICROCONTROLLER
Table of Contents -
1.
2.
3.
4.
5.
GENERAL DESCRIPTION ......................................................................................................... 3
FEATURES................................................................................................................................. 3
PIN CONFIGURATIONS ............................................................................................................ 4
PIN DESCRIPTION..................................................................................................................... 5
FUNCTIONAL DESCRIPTION ................................................................................................... 6
5.1
5.2
Timers 0, 1, and 2........................................................................................................... 6
New Defined Peripheral.................................................................................................. 6
5.2.1
5.2.2
5.2.3
5.2.4
INT2 / INT3 ................................................................................................................6
PORT4 .........................................................................................................................7
Reduce EMI Emission ..................................................................................................7
Power-off Flag ..............................................................................................................8
5.3
Watchdog Timer ............................................................................................................. 8
5.3.1
Watchdog Timer Control Register ................................................................................8
5.4
5.5
Clock............................................................................................................................. 10
Power Management...................................................................................................... 10
5.5.1
5.5.2
Idle Mode....................................................................................................................10
Power-down Mode......................................................................................................10
5.6
Reset............................................................................................................................. 10
6.
ON-CHIP FLASH EPROM CHARACTERISTICS..................................................................... 11
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Read Operation ............................................................................................................ 11
Output Disable Condition.............................................................................................. 11
Program Operation ....................................................................................................... 11
Program Verify Operation............................................................................................. 11
Erase Operation............................................................................................................ 11
Erase Verify Operation ................................................................................................. 11
Program/Erase Inhibit Operation.................................................................................. 12
7.
SECURITY BITS....................................................................................................................... 13
7.1
7.2
7.3
Lock bit.......................................................................................................................... 13
MOVC Inhibit................................................................................................................. 14
Encryption..................................................................................................................... 14
8.
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 14
DC CHARACTERISTICS.......................................................................................................... 15
AC CHARACTERISTICS.......................................................................................................... 16
9.
10.
Publication Release Date: October 2, 2006
- 1 -
Revision A4
W78IE52/W78I052A
10.1 Program Fetch Cycle.................................................................................................... 16
10.2 Data Read Cycle........................................................................................................... 17
10.3 Data Write Cycle........................................................................................................... 17
10.4 Port Access Cycle......................................................................................................... 17
10.5 Program Operation ....................................................................................................... 18
TIMING WAVEFORMS............................................................................................................. 19
11.1 Program Fetch Cycle.................................................................................................... 19
11.2 Data Read Cycle........................................................................................................... 19
11.3 Data Write Cycle........................................................................................................... 20
11.4 Port Access Cycle......................................................................................................... 20
11.5 Program Operation ....................................................................................................... 21
TYPICAL APPLICATION CIRCUITS ........................................................................................ 22
12.1 Expanded External Program Memory and Crystal....................................................... 22
12.2 Expanded External Data Memory and Oscillator ......................................................... 23
PACKAGE DIMENSIONS......................................................................................................... 24
13.1 40-pin DIP..................................................................................................................... 24
13.2 44-pin PLCC ................................................................................................................. 25
REVISION HISTORY................................................................................................................ 26
11.
12.
13.
14.
- 2 -
W78IE52/W78I052A
1. GENERAL DESCRIPTION
The W78IE52 is an 8-bit microcontroller which can accommodate a wider frequency range with low
power consumption. The instruction set for the W78IE52 is fully compatible with the standard 8051.
The W78IE52 contains an 8K bytes Flash EPROM; a 256 bytes RAM; four 8-bit bi-directional and bit-
addressable I/O ports; an additional 4-bit I/O port P4; three 16-bit timer/counters; a hardware
watchdog timer and a serial port. These peripherals are supported by eight sources two-level interrupt
capability. To facilitate programming and verification, the Flash EPROM inside the W78IE52 allows
the program memory to be programmed and read electronically. Once the code is confirmed, the user
can protect the code for security.
The W78IE52 microcontroller has two power reduction modes, idle mode and power-down mode, both
of which are software selectable. The idle mode turns off the processor clock but allows for continued
peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
2. FEATURES
y
y
y
y
y
y
y
y
y
Fully static design 8-bit CMOS microcontroller
Wide supply voltage of 2.4V to 5.5V
Industrial temperature grade -40ºC − 85ºC
256 bytes of on-chip scratchpad RAM
8 KB electrically erasable/programmable Flash EPROM
64 KB program memory address space
64 KB data memory address space
Four 8-bit bi-directional ports
One extra 4-bit bit-addressable I/O port, additional INT2 / INT3
(available on 44-pin PLCC package)
y
y
y
y
y
y
y
y
Three 16-bit timer/counters
One full duplex serial port (UART)
Watchdog Timer
Eight sources, two-level interrupt capability
EMI reduction mode
Built-in power management
Code protection mechanism
Packages:
− DIP 40:
W78IE52
− PLCC 44: W78IE52P
− Lead Free (RoHS) DIP 40: W78I052A24DL
− Lead Free (RoHS) PLCC 44: W78I052A24PL
Publication Release Date: October 2, 2006
Revision A4
- 3 -
W78IE52/W78I052A
3. PIN CONFIGURATIONS
40-Pin DIP (W78IE52)
1
VDD
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
T2, P1.0
T2EX, P1.1
2
P0.0, AD0
P0.1, AD1
P0.2, AD2
P0.3, AD3
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
3
P1.2
P1.3
4
5
P1.4
6
P1.5
7
P1.6
8
P1.7
9
RST
10
11
12
13
14
15
16
17
18
19
20
RXD, P3.0
TXD, P3.1
EA
ALE
INT0, P3.2
PSEN
P2.7, A15
INT1, P3.3
T0, P3.4
T1, P3.5
P2.6, A14
P2.5, A13
P2.4, A12
P2.3, A11
P2.2, A10
P2.1, A9
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
P2.0, A8
44-Pin PLCC (W78IE52P)
/
T
2
E
X
,
I
A
D
1
,
A
D
2
,
A
D
3
,
N
T
3
,
A
D
0
,
T
2
,
P
P
1
.
P
1
.
P
1
.
P
1
.
P
0
.
P
0
.
P
0
.
P
4
.
P
0
.
1
.
V
D
D
4
3
2
1
0
1
2
3
2
0
40
39
6
5
4
3
2
1
44 43 42
41
7
8
9
P0.4, AD4
P0.5, AD5
P0.6, AD6
P0.7, AD7
P1.5
P1.6
P1.7
RST
38
37
36
35
34
33
32
31
10
11
12
13
14
15
RXD, P3.0
INT2, P4.3
TXD, P3.1
EA
P4.1
ALE
INT0, P3.2
PSEN
P2.7, A15
INT1, P3.3
T0, P3.4
T1, P3.5
16
17
30
29
P2.6, A14
P2.5, A13
18 19 20 21 22 23 24 25 26 27 28
P
3
.
P
3
.
X
T
A
L
2
X
T
A
L
1
V
S
S
P
2
.
P
2
.
P
2
.
P
2
.
P
2
.
P
4
.
6
,
7
,
0
,
1
,
3
,
4
,
2
,
0
/
W
R
/
R
D
A
8
A
9
A
1
1
A
1
2
A
1
0
- 4 -
W78IE52/W78I052A
4. PIN DESCRIPTION
SYMBOL
DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute out of
external ROM. It should be kept high to access internal ROM. The ROM address and
EA
data will not be presented on the bus if EA pin is high and the program counter is
within on-chip ROM area.
PROGRAM STORE ENABLE: PSEN enables the external ROM data onto the Port 0
address/ data bus during fetch and MOVC operations. When internal ROM access is
PSEN
performed, no PSEN strobe signal outputs from this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that separates
the address from the data on Port 0.
ALE
RESET: A high on this pin for two machine cycles while the oscillator is running resets
the device.
RST
CRYSTAL1: This is the crystal oscillator input. This pin may be driven by an external
clock.
XTAL1
XTAL2
VSS
CRYSTAL2: This is the crystal oscillator output. It is the inversion of XTAL1.
GROUND: Ground potential
VDD
POWER SUPPLY: Supply voltage for operation.
PORT 0: Port 0 is a bi-directional I/O port which also provides a multiplexed low order
address/data bus during accesses to external memory. The Port 0 is also an open-drain
port and external pull-ups need to be connected while in programming.
P0.0 − P0.7
PORT 1: Port 1 is a bi-directional I/O port with internal pull-ups. The bits have alternate
functions which are described below:
P1.0 − P1.7
P2.0 − P2.7
T2(P1.0): Timer/Counter 2 external count input
T2EX(P1.1): Timer/Counter 2 Reload/Capture control
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also provides
the upper address bits for accesses to external memory.
PORT 3: Port 3 is a bi-directional I/O port with internal pull-ups. All bits have alternate
functions, which are described below:
RXD(P3.0) : Serial Port receiver input
TXD(P3.1) : Serial Port transmitter output
INT0 (P3.2): External Interrupt 0
P3.0 − P3.7
INT1(P3.3): External Interrupt 1
T0(P3.4) : Timer 0 External Input
T1(P3.5) : Timer 1 External Input
WR(P3.6) : External Data Memory Write Strobe
RD(P3.7) : External Data Memory Read Strobe
PORT 4: Another bit-addressable bidirectional I/O port P4. P4.3 and P4.2 are alternative
function pins. It can be used as general I/O port or external interrupt input sources
P4.0 − P4.3
(INT2 /INT3 ).
Publication Release Date: October 2, 2006
- 5 -
Revision A4
W78IE52/W78I052A
5. FUNCTIONAL DESCRIPTION
The W78IE52 architecture consists of a core controller surrounded by various registers, five general
purpose I/O ports, 256 bytes of RAM, three timer/counters, and a serial port. The processor supports
111 different opcodes and references both a 64K program address space and a 64K data storage
space.
5.1 Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0 and 1. The T2CON register provides control functions for Timer 2.
RCAP2H and RCAP2L are used as reload/capture registers for Timer 2.
The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a special feature
of the W78IE52: it is a 16-bit timer/counter that is configured and controlled by the T2CON register.
Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer,
depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-
reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that
of Timers 0 and 1.
5.2 New Defined Peripheral
In order to be more suitable for I/O, an extra 4-bit bit-addressable port P4 and two external interrupt
INT2 , INT3 has been added to either the PLCC or QFP 44 pin package. And description follows:
5.2.1 INT2 / INT3
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is
bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (/CLR) bit" instruction. For example,
"SETB 0C2H" sets the EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3
EX3
IE3
IT3
PX2
EX2
IE2
IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
- 6 -
W78IE52/W78I052A
POLLING
SEQUENCE WITHIN
PRIORITY LEVEL
ENABLE
REQUIRED
SETTINGS
INTERRUPT
TYPE
EDGE/LEVEL
VECTOR
ADDRESS
INTERRUPT SOURCE
External Interrupt 0
Timer/Counter 0
External Interrupt 1
Timer/Counter 1
Serial Port
03H
0BH
13H
1BH
23H
2BH
33H
3BH
0 (highest)
IE.0
IE.1
TCON.0
1
-
2
IE.2
TCON.2
3
IE.3
-
4
IE.4
-
Timer/Counter 2
External Interrupt 2
External Interrupt 3
5
6
IE.5
-
XICON.2
XICON.6
XICON.0
XICON.3
7 (lowest)
5.2.2 PORT4
Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port
address is located at 0D8H with the same function as that of port P1, except the P4.3 and P4.2 are
alternative function pins. It can be used as general I/O pins or external interrupt input sources (INT2 ,
INT3 ).
Example:
P4
REG 0D8H
P4, #0AH
A, P4
P4, #00000001B
P4, #11111110B
MOV
MOV
ORL
ANL
; Output data "A" through P4.0 − P4.3.
; Read P4 status to Accumulator.
5.2.3 Reduce EMI Emission
Because of on-chip Flash EPROM, when a program is running in internal ROM space, the ALE will be
unused. The transition of ALE will cause noise, so it can be turned off to reduce the EMI emission if it
is useless. Turning off the ALE signal transition only requires setting the bit 0 of the AUXR SFR, which
is located at 08Eh. When ALE is turned off, it will be reactivated when the program accesses external
ROM/RAM data or jumps to execute an external ROM code. The ALE signal will turn off again after it
has been completely accessed or the program returns to internal ROM code space. The AO bit in the
AUXR register, when set, disables the ALE output. In order to reduce EMI emission from oscillation
circuitry, W78IE52 allows user to diminish the gain of on-chip oscillator amplifiers by using
programmer to clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be
decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a
half of gain may affect the external crystal operating improperly at high frequency above 20 MHz. The
value of R and C1, C2 may need some adjustment while running at lower gain.
***AUXR - Auxiliary register (8EH)
-
-
-
-
-
-
-
AO
AO: Turn off ALE output.
Publication Release Date: October 2, 2006
Revision A4
- 7 -
W78IE52/W78I052A
5.2.4 Power-off Flag
***PCON - Power control (87H)
-
GF1
GF0
PD
IDL
-
-
POF
POF:
Power off flag. Bit is set by hardware when power on reset. It can be cleared by software
to determine chip reset is a warm boot or cold boot.
GF1, GF0: These two bits are general-purpose flag bits for the user.
PD:
IDL:
Power down mode bit. Set it to enter power down mode.
Idle mode bit. Set it to enter idle mode.
The power-off flag is located at PCON.4. This bit is set when VDD has been applied to the part. It can
be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software.
5.3 Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a
system monitor. This is important in real-time control applications. In case of power glitches or electro-
magnetic interference, the processor may begin to execute errant code. If this is left unchecked the
entire system may crash. The watchdog time-out selection will result in different time-out values
depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software
should restart the Watchdog timer to put it into a known state. The control bits that support the
Watchdog timer are discussed below.
5.3.1 Watchdog Timer Control Register
Bit:
7
6
5
4
-
3
-
2
1
0
ENW CLRW WIDL
Mnemonic: WDTC
PS2
PS1
PS0
Address: 8FH
ENW : Enable watch-dog if set.
CLRW: Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.
PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2 − 0 as follows:
- 8 -
W78IE52/W78I052A
PS2 PS1 PS0
PRESCALER SELECT
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
2
4
8
16
32
64
128
256
The time-out period is obtained using the following equation:
1
× 214 ×PRESCALER×1000×12 mS
OSC
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
ENW
WIDL
IDLE
EXTERNAL
RESET
INTERNAL
14-BIT TIMER
RESET
PRESCALER
OSC
1/12
CLEAR
CLRW
Watchdog Timer Block Diagram
Typical Watch-Dog time-out period when OSC = 20 MHz
PS2 PS1 PS0
WATCHDOG TIME-OUT PERIOD
19.66 mS
0
0
0
0
1
1
1
1
0
1
0
1
0
0
1
1
0
0
1
1
0
1
0
1
39.32 mS
78.64 mS
157.28 mS
314.57 mS
629.14 mS
1.25 S
2.50 S
Publication Release Date: October 2, 2006
Revision A4
- 9 -
W78IE52/W78I052A
5.4 Clock
The W78IE52 is designed to be used with either a crystal oscillator or an external clock. Internally, the
clock is divided by two before it is used. This makes the W78IE52 relatively insensitive to duty cycle
variations in the clock. The W78IE52 incorporates a built-in crystal oscillator. To make the oscillator
work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must
be connected from each pin to ground. An external clock source should be connected to pin XTAL1.
Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the
crystal oscillator.
5.5 Power Management
5.5.1 Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
5.5.2 Power-down Mode
When the PD bit of the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. The only way to exit power-down mode is
by a reset.
5.6 Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78IE52 is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line.
During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit
4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset.
- 10 -
W78IE52/W78I052A
6. ON-CHIP FLASH EPROM CHARACTERISTICS
The W78IE52 has several modes to program the on-chip Flash EPROM. All these operations are
configured by the pins RST, ALE, PSEN , A9CTRL (P3.0), A13CTRL (P3.1), A14CTRL (P3.2),
OECTRL (P3.3), CE (P3.6), OE (P3.7), A0 (P1.0) and VPP (EA ). Moreover, the A15 − A0 (P2.7 −
P2.0, P1.7 − P1.0) and the D7 − D0 (P0.7 − P0.0) serve as the address and data bus respectively for
these operations.
6.1 Read Operation
This operation is supported for customer to read their code and the Security bits. The data will not be
valid if the Lock bit is programmed to low.
6.2 Output Disable Condition
When the OE is set to high, no data output appears on the D7..D0.
6.3 Program Operation
This operation is used to program the data to Flash EPROM and the security bits. Program operation
is done when the VPP is reach to VCP (12.5V) level, CE set to low, and OE set to high.
6.4 Program Verify Operation
All the programming data must be checked after program operations. This operation should be
performed after each byte is programmed; it will ensure a substantial program margin.
6.5 Erase Operation
An erase operation is the only way to change data from 0 to 1. This operation will erase all the Flash
EPROM cells and the security bits from 0 to 1. This erase operation is done when the VPP is reach to
VEP level, CE set to low, and OE set to high.
6.6 Erase Verify Operation
After an erase operation, all of the bytes in the chip must be verified to check whether they have been
successfully erased to 1 or not. The erase verify operation automatically ensures a substantial erase
margin. This operation will be done after the erase operation if VPP = VEP (14.5V), CE is high and
OE is low.
Publication Release Date: October 2, 2006
- 11 -
Revision A4
W78IE52/W78I052A
6.7 Program/Erase Inhibit Operation
This operation allows parallel erasing or programming of multiple chips with different data. When P3.6
(CE) = VIH, P3.7 (OE ) = VIH, erasing or programming of non-targeted chips is inhibited. So, except
for the P3.6 and P3.7 pins, the individual chips may have common inputs.
P3.0
(A9
P3.1
(A13
P3.2
(A14
P3.3
(OE
P3.7
P3.6
P2, P1
P0
EA
(VPP)
OPERATIONS
NOTES
(A15…A0) (D7…D0)
( OE )
( CE )
CTRL) CTRL) CTRL) CTRL)
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
Address Data Out
Output Disable
Program
1
X
Hi-Z
VCP
VCP
Address
Data In
Program Verify
Address Data Out
3
4
5
A0: 0,
others: X
Data In
0FFH
Erase
1
1
X
0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
VEP
VEP
Erase Verify
Address Data Out
Program/Eras
e Inhibit
VCP/
VEP
X
X
Notes:
1. All these operations happen in RST = VIH, ALE = VIL and PSEN = VIH.
2. VCP = 12.5V, VEP = 14.5V, VIH = VDD, VIL = VSS.
3. The program verify operation follows behind the program operation.
4. This erase operation will erase all the on-chip Flash EPROM cells and the Security bits.
5. The erase verify operation follows behind the erase operation.
- 12 -
W78IE52/W78I052A
7. SECURITY BITS
During the on-chip Flash EPROM operation mode, the Flash EPROM can be programmed and
verified repeatedly. Until the code inside the Flash EPROM is confirmed OK, the code can be
protected. The protection of Flash EPROM and those operations on it are described below.
The W78IE52 has a Special Setting Register, the Security Register, which can not be accessed in
normal mode. The Security register can only be accessed from the Flash EPROM operation mode.
Those bits of the Security Registers can not be changed once they have been programmed from high
to low. They can only be reset through erase-all operation. The Security Register is addressed in the
Flash EPROM operation mode by address #0FFFFh.
D7 D6 D5 D4 D3 D2 D1 D0
Security Bits
0000h
1FFFh
B2 B1
B0
B7
Reserved
8KB Flash EPROM
Program Memory
B0 : Lock bit, logic 0: active
B1 : MOVC inhibit,
logic 0: the MOVC instruction in external memory
cannot access the code in internal memory.
logic 1: no restriction.
Reserved
B2 : Encryption
logic 0: the encryption logic enable
logic 1: the encryption logic disable
B7 : Osillator Control
logic 0: 1/2 gain
logic 1: Full gain
Default 1 for all security bits.
Reserved bits must be kept in logic 1.
0FFFFh
Security Register
Special Setting Register
7.1 Lock bit
This bit is used to protect the customer's program code in the W78IE52. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
Flash EPROM data and Special Setting Registers can not be accessed again.
Publication Release Date: October 2, 2006
- 13 -
Revision A4
W78IE52/W78I052A
7.2 MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.
7.3 Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.
+5V
+5V
V
DD
V
DD
PGM DATA
PGM DATA
A0 to A7
P1
P0
A0 to A7
P1
P0
EA/Vpp
V
IL
V
IL
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
EA/Vpp
ALE
P3.0
P3.1
P3.2
P3.3
P3.6
P3.7
V
V
CP
CP
V
IL
V
IL
V
IL
ALE
RST
V
IL
V
IL
V
IL
V
IL
V
IL
RST
V
IH
V
IH
V
IL
V
IH
V
IH
V
IH
PSEN
V
IH
PSEN
V
IL
X'tal1
X'tal2
Vss
X'tal1
X'tal2
Vss
A8 to A15
A8 to A15
P2
P2
Programming Configuration
Programming Verification
8. ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC Power Supply
SYMBOL
MIN.
MAX.
UNIT
V
-0.3
+7.0
VDD − VSS
VIN
Input Voltage
VSS -0.3
-40
VDD +0.3
85
V
Operating Temperature
Storage Temperature
TA
°C
°C
TST
-55
+150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
- 14 -
W78IE52/W78I052A
9. DC CHARACTERISTICS
VSS = 0V, TA = 25° C, unless otherwise specified.
SPECIFICATION
PARAMETER
Operating Voltage
Operating Current
SYM.
VDD
IDD
UNIT
TEST CONDITIONS
MIN.
MAX.
5.5
20
3
2.4
V
-
-
-
-
-
-
mA
mA
mA
mA
μA
No load VDD = 5.5V
No load VDD = 2.4V
6
VDD = 5.5V, FOSC = 20 MHz
VDD = 2.4V, FOSC = 12 MHz
VDD = 5.5V, FOSC = 20 MHz
Idle Current
IIDLE
1.5
50
20
Power Down Current
IPWDN
VDD = 2.4V, FOSC = 12 MHz
VDD = 5.5V
μA
Input Current
P1, P2, P3, P4
Input Current
RST
IIN1
IIN2
-50
-10
+10
μA
μA
VIN = 0V or VDD
VDD = 5.5V
+300
0 < VIN < VDD
Input High Voltage
RST[*1]
3.5
1.7
3.5
1.6
-
VDD +0.2
VDD +0.2
VDD +0.2
VDD +0.2
0.45
V
V
V
V
V
V
V
VDD = 5.5V
VIH2
VIH3
VOL1
VDD = 2.4V
Input High Voltage
XTAL1 [*3]
VDD = 5.5V
VDD = 2.4V
Output Low Voltage
P1, P2, P3, P4
Output Low Voltage
VDD = 4.5V, IOL = +2 mA
VDD = 2.4V, IOL = +1 mA
VDD = 4.5V, IOL = +4 mA
-
0.25
-
0.45
VOL2
ISK1
-
0.25
V
VDD = 2.4V, IOL = +2 mA
P0, ALE, PSEN [*2]
Sink Current
4
1.8
8
12
5.4
16
mA
mA
mA
VDD = 4.5V, Vin = 0.45V
VDD = 2.4V, Vin = 0.45V
VDD = 4.5V, Vin = 0.45V
P1, P2, P3, P4
Sink Current
ISK2
4.0
2.4
1.4
2.4
1.4
9
-
mA
V
VDD = 2.4V, Vin = 0.45V
P0, ALE, PSEN
Output High Voltage
P1, P2, P3, P4
VDD = 4.5V, IOH = -100 μA
VDD = 2.4V, IOH = -8 μA
VDD = 4.5V, IOH = -400 μA
VOH1
VOH2
ISR1
ISR2
-
V
Output High Voltage
-
V
-
V
VDD = 2.4V, IOH = -200 μA
VDD = 4.5V, Vin = 2.4V
VDD = 2.4V, Vin = 1.4V
VDD = 4.5V, Vin = 2.4V
VDD = 2.4V, Vin = 1.4V
P0, ALE, PSEN [*2]
Source Current
P1, P2, P3, P4
-100
-10
-8
-250
-30
μA
μA
mA
Source Current
-14
-1.0
-2.4
mA
P0, ALE, PSEN
Notes:
*1. RST pin is a Schmitt trigger input.
*2. P0, ALE and /PSEN are tested in the external access mode.
*3. XTAL1 is a CMOS input.
*4. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0.
Publication Release Date: October 2, 2006
Revision A4
- 15 -
W78IE52/W78I052A
10. AC CHARACTERISTICS
The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually
experience less than a ±20 nS variation. The numbers below represent the performance expected
from a 0.6micron CMOS process when using 2 and 4 mA output buffers.
Clock Input Waveform
XTAL1
TCH
TCL
FOP,
TCP
PARAMETER
Operating Speed
SYMBOL
FOP
MIN.
0
TYP.
MAX.
UNIT
MHz
nS
NOTES
-
-
-
-
20
-
1
2
3
3
Clock Period
Clock High
Clock Low
Notes:
TCP
41.7
20
TCH
-
nS
TCL
20
-
nS
1. The clock may be stopped indefinitely in either state.
2. The TCP specification is used as a reference in other specifications.
3. There are no duty cycle requirements on the XTAL1 input.
10.1 Program Fetch Cycle
PARAMETER
SYMBOL
TAAS
MIN.
1 TCP -Δ
1 TCP -Δ
1 TCP -Δ
-
TYP.
MAX.
UNIT
nS
nS
nS
nS
nS
nS
nS
nS
NOTES
Address Valid to ALE Low
Address Hold from ALE Low
-
-
4
1, 4
4
TAAH
-
-
TAPL
-
-
ALE Low to PSEN Low
TPDA
TPDH
TPDZ
TALW
TPSW
-
2 TCP
1 TCP
1 TCP
-
2
PSEN Low to Data Valid
Data Hold after PSEN High
Data Float after PSEN High
ALE Pulse Width
0
-
3
0
-
2 TCP
3 TCP
4
4
2 TCP -Δ
3 TCP -Δ
-
PSEN Pulse Width
Notes:
1. P0.0 − P0.7, P2.0 − P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 TCP.
3. Data have been latched internally prior to PSEN going high.
4. "Δ" (due to buffer driving delay and wire loading) is 20 nS.
- 16 -
W78IE52/W78I052A
10.2 Data Read Cycle
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
3 TCP +Δ
4 TCP
2 TCP
2 TCP
-
UNIT
nS
NOTES
1, 2
1
TDAR
-
3 TCP -Δ
ALE Low to RD Low
RD Low to Data Valid
Data Hold from RD High
Data Float from RD High
RD Pulse Width
TDDA
TDDH
TDDZ
TDRD
-
-
nS
0
0
-
-
nS
nS
6 TCP
nS
2
6 TCP -Δ
Notes:
1. Data memory access time is 8 TCP.
2. "Δ" (due to buffer driving delay and wire loading) is 20 nS.
10.3 Data Write Cycle
PARAMETER
ALE Low to WR Low
SYMBOL
MIN.
TYP.
MAX.
UNIT
nS
TDAW
TDAD
TDWD
TDWR
-
3 TCP -Δ
1 TCP -Δ
1 TCP -Δ
6 TCP -Δ
3 TCP +Δ
-
-
-
-
-
nS
Data Valid to WR Low
Data Hold from WR High
WR Pulse Width
nS
6 TCP
nS
Note: "Δ" (due to buffer driving delay and wire loading) is 20 nS.
10.4 Port Access Cycle
PARAMETER
Port Input Setup to ALE Low
Port Input Hold from ALE Low
Port Output to ALE
SYMBOL
TPDS
MIN.
1 TCP
0
TYP.
MAX.
UNIT
nS
-
-
-
-
-
-
TPDH
nS
TPDA
1 TCP
nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
Publication Release Date: October 2, 2006
- 17 -
Revision A4
W78IE52/W78I052A
10.5 Program Operation
PARAMETER
VPP Setup Time
SYMBOL
TVPS
TDS
MIN.
2.0
2.0
2.0
2.0
0
TYP.
MAX.
UNIT
μS
-
-
-
-
-
-
-
-
-
-
Data Setup Time
μS
Data Hold Time
TDH
μS
Address Setup Time
Address Hold Time
TAS
μS
TAH
μS
CE Program Pulse Width for
Program Operation
TPWP
290
300
310
μS
OECTRL Setup Time
OECTRL Hold Time
TOCS
TOCH
TOES
2.0
2.0
2.0
-
-
-
-
-
-
μS
μS
μS
nS
OE Setup Time
TDFP
TOEV
0
-
-
-
130
150
OE High to Output Float
Data Valid from OE
nS
Note: Flash data can be accessed only in flash mode. The RST pin must pull in VIH status, the ALE pin must pull in VIL status,
and the PSEN pin must pull in VIH status.
- 18 -
W78IE52/W78I052A
11. TIMING WAVEFORMS
11.1 Program Fetch Cycle
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
XTAL1
ALE
TALW
TAPL
PSEN
TPSW
TAAS
PORT 2
PORT 0
TPDA
TAAH
TPDH, TPDZ
A0-A7
A0-A7
Code
A0-A7
Code
Data
Data
A0-A7
11.2 Data Read Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
PORT 2
A8-A15
DATA
A0-A7
PORT 0
RD
T
T
DDA
DAR
T
T
DDH, DDZ
T
DRD
Publication Release Date: October 2, 2006
Revision A4
- 19 -
W78IE52/W78I052A
Timing Waveforms, continued
11.3 Data Write Cycle
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
XTAL1
ALE
PSEN
A8-A15
PORT 2
PORT 0
WR
A0-A7
DATA OUT
TDWD
TDAD
TDWR
TDAW
11.4 Port Access Cycle
S5
S6
S1
XTAL1
ALE
T
T
T
PDA
PDS
PDH
PORT
DATA OUT
INPUT
SAMPLE
- 20 -
W78IE52/W78I052A
Timing Waveforms, continued
11.5 Program Operation
Program
Program
Verify
Read Verify
V
IH
P2, P1
(A15... A0)
Address Stable
Address Valid
V
IL
TAS
V
P3.6
(CE)
IH
T
PWP
V
IL
TAH
V
P3.3
(OECTRL)
IH
T
OCS
V
IL
TOCH
P3.7
(OE)
V
IH
T
OES
V
IL
TDFP
TDH
V
IH
P0
(A7... A0)
OUT
D
Data In
Data Out
V
IL
TDS
Vcp
TOEV
Vpp
V
IH
T
VPS
Publication Release Date: October 2, 2006
Revision A4
- 21 -
W78IE52/W78I052A
12. TYPICAL APPLICATION CIRCUITS
12.1 Expanded External Program Memory and Crystal
V
DD
V
DD
31
19
AD0
38 AD1
39
3
4
7
11
12
13
AD0
AD1
AD2
AD0
AD1
AD2
A0
A1
A2
A3
A4
A5
A6
A7
A8 25
A9 24
A1021
A11
A12
A1326
2 A0
5 A1
10
9
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
A0
O0
O1
O2
O3
O4
O5
O6
O7
EA
A1
AD2
AD3
AD4
AD5
AD6
AD7
A2
6
37
36
35
34
33
32
8
A2
XTAL1
AD38
9 A3
12A4
15 AD3
10 u
C1
7
A3
13
16
17
18
AD4
14
6
AD4
AD5
AD6
A4
R
18
9
A5
A6
A7
15
16
19
AD5
17
5
XTAL2
RST
A5
CRYSTAL
C2
AD6
4
A6
3
AD718
19 AD7
A7
8.2 K
A8
1
GND
A8
A9
A10
A11
A12
A13
A14
21
22
23
24
25
26
27
OC
G
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
A9
11
A10
A11
A12
A13
A14
A15
INT0
23
2
12
13
14
15
INT1
T0
T1
74373
A14
A15
27
1
1
2
3
4
5
6
7
8
28 A15
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
GND
20
CE
OE
RD
17
16
29
30
11
10
22
WR
27512
PSEN
ALE
TXD
RXD
W78IE52
Figure A
CRYSTAL
16 MHz
20 MHz
C1
C2
R
30P
15P
30P
15P
-
-
Above table shows the reference values for crystal applications (full gain).
Note: C1, C2, R components refer to Figure A.
- 22 -
W78IE52/W78I052A
Typical Application Circuits, continued
12.2 Expanded External Data Memory and Oscillator
V
DD
V
DD
31
19
AD0
A0
A1
A2
3
2
5
6
9
10
9
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
A0
A1
11 AD0
12 AD1
13 AD2
15 AD3
16 AD4
17 AD5
18 AD6
19 AD7
39AD0
38
37AD2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
D0
D1
D2
D3
D4
D5
D6
D7
D0 Q0
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
D7 Q7
EA
AD14
AD1
AD2
AD3
7
8
A2 8
XTAL1
A3 A3
7
6
5
4
3
OSCILLATOR
10 u
AD3
AD4
AD5
AD6
36
35
34
33
AD413
AD514
17
AD6
AD718
12A4
15A5
A4
A5
A6
A7
18
XTAL2
A6
16
19A7
8.2 K
32AD7
9
A8 25
A9
RST
INT0
GND
1
P2.0 21
24
21
A8
A9
OC
G
A10
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
11
22
23
24
25
26
27
28
A10
A11
A12
A13
12
13
14
15
A11
23
A10
A11
A12
A13
A14
A122
74373
INT1
T0
T1
26
A13
1
A14
A14
GND20
22
CE
OE
1
2
3
4
5
6
7
8
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RD
27
17
16
29
30
11
10
WR
WR
20256
PSEN
ALE
TXD
RXD
W78IE52
Figure B
Publication Release Date: October 2, 2006
Revision A4
- 23 -
W78IE52/W78I052A
13. PACKAGE DIMENSIONS
13.1 40-pin DIP
Dimension in inchDimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
5.334
0.210
A
0.010
0.150 0.155 0.160 3.81 3.937 4.064
0.254
A1
2
A
B
0.016 0.018
0.406 0.457 0.559
1.219 1.27 1.372
0.022
0.054
0.050
0.048
0.008
1
B
c
0.010 0.014 0.203 0.254 0.356
2.055 2.070
D
52.20 52.58
D
E
E1
40
21
15.494
13.97
0.610
15.24
0.590 0.600
14.986
13.72 13.84
0.540
0.545 0.550
0.110
0.090 0.100
2.286 2.54 2.794
e
L
a
1
3.048
0
0.120 0.130 0.140
15
3.302 3.556
15
1
E
0
17.01
2.286
0.630 0.650 0.670 16.00 16.51
0.090
A
e
S
20
1
Notes:
E
1. Dimension D Max. & S include mold flash or
tie bar burrs.
S
c
2. Dimension E1 does not include interlead flash
3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.
A2
A
L
Base Plane
1
A
.
Seating Plane
4. Dimension B1 does not include dambar
protrusion/intrusion.
B
e1
eA
5. Controlling dimension: Inches.
6. General appearance spec. should be based o
final visual inspection spec.
a
B1
- 24 -
W78IE52/W78I052A
Package Dimensions, continued
13.2 44-pin PLCC
H D
D
6
1
44
40
Dimension in inch Dimension in mm
Symbol
Min. Nom. Max. Min. Nom. Max.
7
39
0.185
4.699
A
A
A2
b 1
b
0.020
0.508
1
0.145 0.150 0.155 3.683 3.81 3.937
0.026 0.028
0.016 0.018
0.032 0.66
0.406
0.813
0.559
0.356
0.711
0.457
0.022
HE
GE
E
0.008 0.010 0.014 0.203 0.254
c
16.46 16.59 16.71
16.46 16.59 16.71
1.27 BSC
0.648 0.653 0.658
D
E
e
0.648 0.653
0.658
0.050 BSC
0.590
0.590
0.680
0.680
14.99 15.49 16.00
14.99 15.49 16.00
17.27 17.53 17.78
17.27 17.53 17.78
17
29
0.610
0.630
GD
0.610 0.630
0.690 0.700
0.690 0.700
G
E
D
E
18
28
H
c
H
L
y
0.090 0.100
2.54 2.794
0.10
0.110 2.296
0.004
L
Notes:
A2
A1
A
1. Dimension D & E do not include interlead
flash.
2. Dimension b1 does not include dambar
protrusion/intrusion.
θ
e
b
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
b 1
Seating Plane
y
GD
Publication Release Date: October 2, 2006
Revision A4
- 25 -
W78IE52/W78I052A
14. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
A1
A2
A3
September 14, 2001
April 20, 2005
-
Initial Issued
22
3
Add Important Notice
December 13, 2005
Add lead-free(RoHS) parts
Remove block diagram
A4
October 2, 2006
Change operating frequency into 20MHz
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
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Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
2727 North First Street, San Jose,
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
200336 China
CA 95134, U.S.A.
TEL: 86-21-62365999
FAX: 86-21-62365998
TEL: 1-408-9436666
FAX: 1-408-5441798
http://www.winbond.com.tw/
Taipei Office
Winbond Electronics Corporation Japan
Winbond Electronics (H.K.) Ltd.
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
TEL: 81-45-4781881
FAX: 81-45-4781800
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
Please note that all data and specifications are subject to change without notice.
All the trademarks of products and companies mentioned in this datasheet belong to their respective owners.
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相关型号：
W78IRD2A40DL
Microcontroller, 8-Bit, FLASH, 8051 CPU, 25MHz, CMOS, PDIP40, ROHS COMPLIANT, DIP-40
WINBOND
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