W78C378ED_技术文档

Preliminary W78E378/W78C378/W78C374

MONITOR CONTROLLER

GENERAL DESCRIPTION

The W78E378, W78C378 and W78C374B are ASIC which is a stand-alone high-performance

microcontroller specially designed for monitor control applications. The device integrates the

embedded 80C31 microcontroller core, on-chip MTP or Mask ROM, 576 bytes of RAM, and a number

of dedicated hardware monitor functions. Additional special function registers are incorporated to

control the on-chip peripheral hardware. The chip is used to control the interface signal of other

devices in the monitor and to process the video sync signals. Because of the highly integration and

Flash cell for program memory, the device can offer users the competitive advantages of low cost

and reduced development time.

FEATURES

· 80C31 MCU Core Embedded

· 32K Bytes MTP-ROM (W78E378)

· 32K Bytes Mask-ROM (W78C378)

· 16K Bytes Mask-ROM (W78C374B)

· Total 576 Bytes of On-chip Data RAM

- 256 bytes accessed as in the 80C32

-

320 bytes accessed as external data memory via "MOVX @Ri"

· PWM DACs

-

Eight 8-bit Static PWM DACs: DAC0 DAC8

- Three 8-bit Dynamic PWM DACs: DAC9- DAC10

· Sync Processor

-

Horizontal & Vertical Polarity Detector

Sync Separator for Composite Sync

- 12-bit Horizontal & Vertical Frequency Counter

-

Programmable Dummy Frequency Generator

- Programmable H-clamp Pulse Output

-

SOA Interrupt

Hsync/2 Output

· Serial Ports:

- DDC1 Port- support DDC1

-

SIO1 & SIO2 Ports - each can support DDC2B/2B+/2Bi/2AB (each has 2 slave addresses)

· Two 16-bit Timer/Counters (8031's Timer0 & Timer1)

INT0

· One External Interrupt Input (8031's

· One Parabola Interrupt Generator

)

· One ADC with 7 Multiplexed Analog Inputs

· Two 12 mA(min) Output Pins for Driving LEDs

· Watchdog Timer (2²²/Fosc = 0.42s @Fosc = 10 MHz)

· Power Low Reset

· Frequency: 10 MHz max. (with the same performance as a normal 8051 that uses 20 MHz)

· Packaged in 40/32-pin 600 mil DIP & 44-pin PLCC

Publication Release Date: December 1999

- 1 -

Revision A1

Preliminary W78E378/W78C378/W78C374

PIN CONFIGURATIONS

40-pin DIP

1

W78E378E

40-pin DIP:

P4.1

40 P4.2

W78C378E

P4.0 (HFI)

2

3

39 P4.3

32-pin DIP

1

W78C374E

P3.5 (ADC4, T0)*

32

38 P3.6 (ADC5, T1)*

P1.1 (DAC1)*

P1.0 (DAC0)*

4

5

2

3

31

30

37 P1.2 (DAC2)*

36 P1.3 (DAC3)*

W78E378

32-pin DIP:

P3.4 (VOUT)

P3.3 (HOUT)

HIN

6

7

4

5

6

7

8

29

28

27

26

25

35 P1.4 (DAC4)*

34 P1.5 (DAC5)*

33 P1.6 (DAC6)*

32 P1.7 (DAC7)*

31 P2.0 (DAC8)

W78C378

W78C374

8

VIN

9

10

RESET

VDD

11

12

13

14

15

9

24

23

22

21

20

30 P2.1 (DAC9)

29 P2.2 (DAC10)

28 P2.3 (Hclamp)

27 P2.4 (ADC0)

26 P2.5 (ADC1)

VSSA

OSCOUT

OSCIN

10

11

12

13

P3.2 (

)

INT0

P3.1 (SCL)* 16

P3.0 (SDA)* 17

14

15

16

19

18

17

25 P2.6 (ADC2)

24 P2.7 (ADC3)

23 P3.7 (ADC6)*

VSS

18

P4.7 (HFO) 19

P4.6 20

22 P4.4 (SCL2)*

21 P4.5 (SDA2)*

44-pin PLCC

P P P P P P P P P P P

3 1 1 3 4 4 4 4 3 1 1

.

. . . . . . . . . .

4 0 1 5 0 1 2 3 6 2 3

6 5 4 3 2 1 4 4 4 4 4

4 3 2 1 0

P3.3

HIN

7

8

9

10

11

P1.4

NC

39

38

37

36

35

34

33

32

31

30

29

IN

V

P1.5

P1.6

P1.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

RESET

V_DD

W78E378P

W78C378P

W78C374P

VDDA 12

VDD

VSSA 14

15

13

OSCOUT

OSCIN 16

P3.2 17

1 1 2 2 2 2 2 2 2 2 2

8 9 0 1 2 3 4 5 6 7 8

P P V V P P P P P P P

3 3 S S 4 4 4 4 3 2 2

.

S S .

. . . . . .

1 0

7 6 5 4 7 7 6

- 2 -

Preliminary W78E378/W78C378/W78C374

PIN DESCRIPTION

PIN NAME

I/O

DESCRIPTION

I/O Chip reset input (active low) input &

RESET

Internal reset output (generated by WDT or power low)

TTL Schmitt trigger input, internal pull-up ~30 K

W

OL

= +12 mA @V = 0.45V

I

DD

V

-

Positive power supply

SS

V

Ground

SS

V

-

Ground

OUT

OSC

O

I

Output from the inverting oscillator amplifier

IN

OSC

Input to the inverting oscillator amplifier, 10 MHz max.

Hsync input

IN

H

I

TTL Schmitt trigger input , w/o PMOS

IH IL

V /V = 2.0V/0.8V, V+/ V- = ~1.6V/ 1.1V

IN

V

I

Vsync input

TTL Schmitt trigger input, w/o PMOS

IH IL

V /V = 2.0V/0.8V, V+/ V- = ~1.6V/ 1.1V

P1.0 (DAC0)

P1.1 (DAC1)

P1.2 (DAC2)

P1.3 (DAC3)

P1.4 (DAC4)

P1.5 (DAC5)

P1.6 (DAC6)

P1.7 (DAC7)

I/O General purpose I/O, DAC0 special function output

Open-drain output

, sink current: 15 mA

I/O General purpose I/O, DAC1 special function output

Open-drain output

, sink current: 15 mA

I/O General purpose I/O, DAC2 special function output

Open-drain output

, sink current: 4 mA

I/O General purpose I/O, DAC3 special function output

Open-drain output

, sink current: 4 mA

I/O General purpose I/O, DAC4 special function output

Open-drain output

, sink current: 4 mA

I/O General purpose I/O, DAC5 special function output

Open-drain output

, sink current: 4 mA

I/O General purpose I/O, DAC6 special function output

Open-drain output

, sink current: 4 mA

I/O General purpose I/O, DAC7 special function output

Open-drain output

, sink current: 4 mA

Publication Release Date: December 1999

Revision A1

- 3 -

Preliminary W78E378/W78C378/W78C374

Pin Description, Continued

PIN NAME

I/O

DESCRIPTION

P2.0 (DAC8)

I/O General purpose I/O, DAC8 Special Function output

m

Sink/Source current: 4 mA/-100 A (-4 mA for SF output)

P2.1 (DAC9)

P2.2 (DAC10)

P2.3 (Hclamp)

P2.4 (ADC0)

P2.5 (ADC1)

P2.6 (ADC2)

P2.7 (ADC3)

P3.0 (SDA)

I/O General purpose I/O, DAC9 Special Function output

Sink/Source current: 4 mA/-100 mA (-4 mA for SF output)

I/O General purpose I/O, DAC10 Special Function output

m

Sink/Source current: 4 mA/-100 A (-4 mA for SF output)

I/O General purpose I/O, Hclamp Special Function output

m

Sink/Source current: 4 mA/-100 A (-4 mA for SF output)

I/O General purpose I/O, ADC input channel 0

Sink/Source current: 4 mA/-100 mA

I/O General purpose I/O, ADC input channel 1

m

Sink/Source current: 4 mA/-100 A

I/O General purpose I/O, ADC input channel 2

m

Sink/Source current: 4 mA/-100 A

I/O General purpose I/O, ADC input channel 3

m

Sink/Source current: 4 mA/-100 A

I/O General purpose I/O, DDC port serial data I/O

Schmitt trigger input

IH IL

DD

V /V = 0.7 V /0.3 V , V+/V- = ~0.6 V / 0.4 V

Open-drain output

, sink current: 8 mA

P3.1 (SCL)

I/O General purpose I/O, DDC port serial clock I/O

Schmitt trigger input

IH IL

DD

V /V = 0.7 V /0.3 V , V+/V- = ~0.6 V / 0.4 V

Open-drain output

, sink current: 8 mA

I/O

INT0

input

P3.2 (

)

General purpose I/O,

Sink/Source current: 1 mA/ -100 mA

OUT

special function output

P3.3 (H

P3.4 (V

I/O General purpose I/O, H

m

Sink/Source current: 4 mA/-100 A (-4 mA for SF output)

OUT

I/O General purpose I/O, V

special function output

m

Sink/Source current: 4 mA/-100 A (-4 mA for SF output)

P3.5 (ADC4, T0) I/O General purpose I/O, ADC input channel 4

Open-drain output

, sink current: 4 mA

P3.6 (ADC5, T1) I/O General purpose I/O, ADC input channel 5

Open-drain output

, sink current: 4 mA

I/O General purpose I/O, ADC input channel 6

P3.7 (ADC6)

Open-drain output

, sink current: 4 mA

- 4 -

Preliminary W78E378/W78C378/W78C374

Pin Description, Continued

PIN NAME

I/O

DESCRIPTION

P4.0 (HFI)

I/O P4.0 Output, HFI Input

Sink/Source current: 4 mA/-4 mA

P4.1

P4.2

O

P4.1 Output

Sink/Source current: 4 mA/-4 mA

P4.2 Output

Sink/Source current: 4 mA/-4 mA

P4.3 Output

P4.3

Sink/Source current: 4 mA/-4 mA

P4.4 (SCL2)

I/O P4.4 Output, SIO2 port serial clock I/O

Schmitt trigger input

IH IL

DD

V /V = 0.7 V /0.3 V , V+/V- = ~0.6 V /0.4 V

Open-drain output

, sink current: 8 mA

P4.5 (SDA2)

I/O P4.5 Output, SIO2 port serial data I/O

Schmitt trigger input

IH IL

DD

V /V = 0.7 V /0.3 V , V+/V- = ~0.6 V /0.4 V

Open-drain output

, sink current: 8 mA

P4.6

O

P4.6 Output

Sink/Source current: 4 mA/-4 mA

P4.7 Output, HFO Output

P4.7 (HFO)

Sink/Source current: 4 mA/-4 mA

Publication Release Date: December 1999

Revision A1

- 5 -

Preliminary W78E378/W78C378/W78C374

BLOCK DIAGRAM

V_DD

VSS

80C31 Core excluding internal RAM

freq2

Note:

freq1 = freq2

CPU

freq1

OSCIN

Osc.

Circuit

Interrupt

Processor

INT0 (P3.2)

OSCOUT

T0 (P3.5)

T1 (P3.6)

Timer 0

Timer 1

RESET

Reset

Circuit

P1, P2, P3

P4

I/O Port

Power Low

Detection

Note:

P1, P4.4~P4.5

P3.0~P3.1 & P3.5~P3.7

are open-drain.

Watch Dog

Timer

SCL (P3.1)

SDA (P3.0)

VPP (P3.2)

Program Memory

SIO1

SIO2

Data Memory

RAM: 576 Bytes

SCL2 (P4.4)

SDA2 (P4.5)

HIN, VIN

HFI (P4.0)

Sync.

Processor

VOUT (P3.4)

HOUT (P3.3)

Hclamp (P2.3)

HFO (P4.7)

DAC0~7 (P1.0~P1.7)

DAC8~10 (P2.0~P2.2)

Static DACs

ADC0 (P2.4)

ADC1 (P2.5)

ADC2 (P2.6)

ADC3 (P2.7)

ADC4 (P3.5)

ADC5 (P3.6)

ADC6 (P3.7)

Dynamic DACs

ADC

8-bit Internal Bus

- 6 -

Preliminary W78E378/W78C378/W78C374

FUNCTIONAL DESCRIPTION

Address Space

7FFFh

(3FFFh)

Internal

Program Memory

FFh

Internal RAM

256 Bytes

8051SFRs &

Serial Ports SFRs

On-Chip Data Memory

64 Bytes

External Access

"MOVX @Ri"

new SFRs

C0h

BFh

Indirect Addressing Direct Addressing

"MOV"

"MOV @Ri"

External Access

"MOVX @Ri"

80h

7Fh

80h

7Fh

00h

On-Chip Data Memory

128 Bytes

On-Chip Data Memory

128 Bytes

Direct or Indirect

Addressing

"MOV" or "MOV @Ri"

External Access

"MOVX @Ri"

External Access

"MOVX @Ri"

0000h

00h

BANK0

BANK1

Program/Data/SFRs Address Space

SFRs accessed using 'Direct Addressing'

REGISTER

ADDRESS

BITS

POWER

RESET

R/W

ON RESET

1

2

8

00h

x0h

R/W

A*

B*

E0h

F0h

D0h

81h

82h

83h

A8h

B8h

88h

89h

8Ah

8Ch

8Bh

8Dh

87h

3

PSW*

SP

4

DPL

DPH

IE*

5

6

7

8

IP*

9

TCON*

TMOD

TL0

10

11

12

13

14

15

TH0

TL1

TH1

PCON

Publication Release Date: December 1999

Revision A1

- 7 -

Preliminary W78E378/W78C378/W78C374

SFRs accessed using 'Direct Addressing', continued

REGISTER

ADDRESS

BITS

POWER

RESET

R/W

ON RESET

R/W

R

16

17

18

19

20

21

22

23

24

25

26

27

28

P1*

90h

A0h

B0h

C0h

D8h

D9h

DAh

DBh

DCh

E8h

E9h

EAh

EBh

ECh

8

3

8

00h

FFh

1Fh

00h

F8h

FFh

00h

F8h

FFh

00h

FFh

1Fh

xxh

00h

F8h

FFh

00h

F8h

FFh

00h

P2*

P3*

TMREG*

S1CON*

S1STA

S1DAT

S1ADR1

S1ADR2

S2CON*

S2STA

S2DAT

S2ADR1

S2ADR2

R/W

R

R/W

Notes:

1. The SFRs marked with an asterisk (*) are both bit- and byte-addressable.

2. Port 1 and P3.5 P3.7 outputs low during & after reset.

-

3. "x" means no reset action.

4. The SFRs in the shaded region are new-defined.

* Modified PCON

BIT

0

NAME

ADCS2

PD

FUNCTION

ADC channel Select bit 2

Power Down bit

1

2

GF0

General purpose flag bit

Test purpose flag bit

3

GF1

4

TEST0

TEST1

ADCcal

CPUhalt

5

6

Set 0/1 to select 1.0V/3.0V for ADC calibration

Set to let CPU halt when the chip runs internally

7

* TMREG: Test Mode Register

BIT

0

NAME

TM1

FUNCTION

Test Mode1

Test Mode2

Test Mode3

1

TM2

2

TM3

- 8 -

Preliminary W78E378/W78C378/W78C374

SFRs accessed using 'MOVX @Ri'

REGISTER

ADDRESS

BITS

POWER

RESET

R/W

ON RESET

TYPE

1

CTRL1

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

92h

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

9Dh

9Eh

9Fh

A0h

8

5

8

-

00h

x

00h

xxh

00h

x

W

2

CTRL2

P1SF

3

W

4

P2SF

W

5

P3SF

W

6

PARAL

PARAH

HFCOUNTL

HFCOUNTH

VFCOUNTL

VFCOUNTH

WDTCLR

SOARL

SOARH

SOACLR

INTMSK

INTVECT

INTCLR

DDC1

R/W

R

7

8

9

x

R

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

x

R

x

R

x

W

8/6

-

x

R/W

W

x

6

8

0

00h

x

00h

x

R/W

R

W

x

W

ADC

x

R

DAC0

00h

FFh

00h

x

R/W

W

DAC1

x

DAC2

x

DAC3

x

DAC4

x

DAC5

x

DAC6

x

DAC7

x

DAC8

x

DAC9

x

DAC10

P4

x

FFh

00h

CTRL3

W

Note: "x" means no reset action.

Publication Release Date: December 1999

Revision A1

- 9 -

Preliminary W78E378/W78C378/W78C374

* CTRL1: Control Register 1 (Write Only)

BIT

NAME

FUNCTION

A-to-D Conversion START control

0

ADCSTRT

Set by S/W to start conversion.

Cleared by H/W while conversion completed (read SOARH.6 to check).

ADC channel Select bit 0

1

2

3

4

ADCS0

ADCS1

ENDDC1

HCES

ADC channel Select bit 1

Enable DDC1

H-Clamp Edge Select

0: Select leading edge of restored Hsync

1: Select trailing edge of restored Hsync

H-Clamp Width Select bit

5

6

7

HCWS

DUMMYEN

VSDIS

Dummy signal Enable

Vsync Separator Disable, 0: Enable, 1: Disable

* CTRL2: Control Register 2 (Write Only)

BIT

NAME

HSPS

FUNCTION

0

HSync Polarity Select

0: Positive, 1: Negative

VSync Polarity Select

0: Positive, 1: Negative

1

VSPS

2

3

4

5

6

7

HDUMS0

VDUMS

DDC1B9

WDTEN

SOAHDIS

OSCHI

H Dummy frequency Select 0

V Dummy frequency Select

Bit 9 in DDC1 mode

Enable Watch Dog Timer

Disable SOA low to high detection

OSC freq. Higher than 10 MHz

* CTRL3: Control Register 3 (Write Only)

BIT

NAME

ENHFO

FUNCTION

Enable HF input/output for P4.0/P4.7, respectively

0: Disable, 1: Enable

0

1

2

HDUMS1

H Dummy frequency Select 1

Select HFO polarity

HFO_POL

0: Positive, 1: Negative

3

4

HFO_HALF

Select HFO output freq.

0: the same as HFI, 1: half of the HFI

Select on-chip ext. RAM bank

0: Bank 0, 1: Bank 1

ENBNK1

-

5 7

- 10 -

Preliminary W78E378/W78C378/W78C374

*P1SF: Port1 special function output enable register (Write Only)

BIT

0

NAME

P10SF

P11SF

P12SF

P13SF

P14SF

P15SF

P16SF

P17SF

FUNCTION

Port 1.0 Special Function enable (DAC0 output)

Port 1.1 Special Function enable (DAC1 output)

Port 1.2 Special Function enable (DAC2 output)

Port 1.3 Special Function enable (DAC3 output)

Port 1.4 Special Function enable (DAC4 output)

Port 1.5 Special Function enable (DAC5 output)

Port 1.6 Special Function enable (DAC6 output)

Port 1.7 Special Function enable (DAC7 output)

1

2

3

4

5

6

7

*P2SF: Port2 special function output enable register (Write Only)

BIT

0

NAME

P20SF

P21SF

P22SF

P23SF

P24SF

P25SF

P26SF

P27SF

FUNCTION

Port 2.0 Special Function enable (DAC8 output)

Port 2.1 Special Function enable (DAC9 output)

Port 2.2 Special Function enable (DAC10 output)

Port 2.3 Special Function enable (Hclamp output)

Port 2.4 Special Function enable (ADC0 input)

Port 2.5 Special Function enable (ADC1 input)

Port 2.6 Special Function enable (ADC2 input)

Port 2.7 Special Function enable (ADC3 input)

1

2

3

4

5

6

7

*P3SF: Port3 special function output enable register (Write Only)

BIT

NAME

FUNCTION

-

0 2

OUT

3

4

P33SF

P34SF

-

Port 3.3 Special Function enable (H

)

Port 3.4 Special Function enable (V

-

)

5- 7

*HFCOUNTL: Horizontal frequency counter register, low byte (Read Only)

BIT

0

NAME

HF0

HF1

HF2

HF3

HF4

HF5

HF6

HF7

FUNCTION

H frequency count bit 0

H frequency count bit 1

H frequency count bit 2

H frequency count bit 3

H frequency count bit 4

H frequency count bit 5

H frequency count bit 6

H frequency count bit 7

1

2

3

4

5

6

7

Publication Release Date: December 1999

Revision A1

- 11 -

Preliminary W78E378/W78C378/W78C374

*HFCOUNTH: Horizontal frequency counter register, high byte (Read Only)

BIT

0

NAME

HF8

FUNCTION

H frequency count bit 8

H frequency count bit 9

1

HF9

2

HF10

HF11

-

H frequency count bit 10

H frequency count bit 11

-

3

-

4 5

6

7

NOH

HPOL

Set by hardware if no Hin signal

Hin polarity. 0: Positive, 1: Negative

*VFCOUNTL: Vertical frequency counter register, low byte (Read Only)

BIT

0

NAME

VF0

VF1

VF2

VF3

VF4

VF5

VF6

VF7

FUNCTION

V frequency count bit 0

V frequency count bit 1

V frequency count bit 2

V frequency count bit 3

V frequency count bit 4

V frequency count bit 5

V frequency count bit 6

V frequency count bit 7

1

2

3

4

5

6

7

*VFCOUNTH: Vertical frequency counter register, high byte (Read Only)

BIT

0

NAME

VF8

FUNCTION

V frequency count bit 8

V frequency count bit 9

1

VF9

2

VF10

VF11

-

V frequency count bit 10

3

V frequency count bit 11

-

4 5

IN

6

7

NOV

VPOL

Set by hardware if no V signal

IN

V

polarity. 0: Positive, 1: Negative

* INTVECT: Interrupt Vector Register (Read Only)

BIT

0

NAME

SCLINT

ADCINT

DDC1INT

SOAINT

VEVENT

FUNCTION

SCL pin pulled low detected

1

ADC conversion completed

2

DDC1 port buffer empty

3

SOA condition happen

4

Vsync pulse detected or NOV = 1 (V counter overflow)

(The VEVENT is designed to be generated only 'one' time

if no Vsync input.)

5

PARAINT

Parabola Interrupt generated

- 12 -

Preliminary W78E378/W78C378/W78C374

* INTMSK: Interrupt Mask Register (Read/Write)

BIT

0

NAME

FUNCTION

Set/clear to enable/disable SCLINT

Set/clear to enable/disable ADCINT

MSCLINT

MADCINT

1

2

MDDC1INT Set/clear to enable/disable DDC1INT

MSOAINT Set/clear to enable/disable SOAINT

3

4

MVEVENT Set/clear to enable/disable VEVENT

MPARAINT Set/clear to enable/disable PARAINT

5

* INTCLR (Write Only)

BIT

0

NAME

FUNCTION

CSCLINT

CADCINT

Write 1 to this bit to clear SCLINT in INTVECT

Write 1 to this bit to clear ADCINT in INTVECT

1

2

CDDC1INT Write 1 to this bit to clear DDC1INT in INTVECT

CSOAINT Write 1 to this bit to clear SOAINT in INTVECT

3

4

CVEVENT Write 1 to this bit to clear VEVENT in INTVECT

CPARAINT Write 1 to this bit to clear PARAINT in INTVECT

5

*PARAL: Parabola interrupt generator register, low byte (Read/Write)

BIT

0

NAME

PARA0

PARA1

PARA2

PARA3

PARA4

PARA5

PARA6

PARA7

FUNCTION

PARAINT period register bit 0

1

PARAINT period register bit 1

PARAINT period register bit 2

PARAINT period register bit 3

PARAINT period register bit 4

PARAINT period register bit 5

PARAINT period register bit 6

PARAINT period register bit 7

2

3

4

5

6

7

*PARAH: Parabola interrupt generator register, high byte (Read/Write)

BIT

0

NAME

PARA8

PARA9

PARA10

PARA11

PARA12

FUNCTION

PARAINT period register bit 8

1

PARAINT period register bit 9

PARAINT period register bit 10

PARAINT period register bit 11

PARAINT period register bit 12

2

3

4

Publication Release Date: December 1999

Revision A1

- 13 -

Preliminary W78E378/W78C378/W78C374

*SOARL: SOA register, low byte (Read/Write)

BIT

0

NAME

SL0

FUNCTION

SOA Low register bit 0

SOA Low register bit 1

SOA Low register bit 2

SOA Low register bit 3

SOA Low register bit 4

SOA Low register bit 5

1

SL1

2

SL2

3

SL3

4

SL4

5

SL5

6

(OVL)

(OVH)

OVL = 1: current H count larger than SOARL, for test

OVH = 1: current H count smaller than SOARH, for test

7

*SOARH: SOA register, high byte (Read/Write)

BIT

0

NAME

SH0

SH1

SH2

SH3

SH4

SH5

FUNCTION

SOA High register bit 0

SOA High register bit 1

SOA High register bit 2

SOA High register bit 3

SOA High register bit 4

SOA High register bit 5

1

2

3

4

5

6

(ADCSTRT) ADCSTRT bit status, for test

(WDTQ10) Watch Dog Timer, bit 10, for test

7

* ADC

Result of the A-to-D conversion.

* DAC0~DAC8

* DAC9~DAC10

* WDTCLR

8-bit PWM static DAC register.

8-bit PWM dynamic DAC register.

Watchdog-timer-clear register, without real hardware but an address.

Writing any value to WDTCLR will clear the watchdog timer.

Safe-Operation-Area Clear register, without real hardware but an address.

Writing any value to SOACLR will clear the SOAINT.

DDC1 latch buffer.

* SOACLR

* DDC1

* S1CON

* S1STA

* S1DAT

SIO1 control register.

SIO1 status register.

SIO1 data register.

* S1ADR1, S1ADR2 SIO1 address registers.

* S2CON

* S2STA

* S2DAT

SIO2 control register.

SIO2 status register.

SIO2 data register.

* S2ADR1, S2ADR2 SIO2 address registers.

- 14 -

Preliminary W78E378/W78C378/W78C374

Modified Timer 0 & Timer 1

Modified point in Timer 0

(Not divided by 12)

.

OSC

6

.

C/T = 0

C/T = 1

To TL0

T0 pin

(P3.5)

TR0

GATE

INT0 pin

(P3.2)

Modified point in Timer 1

(Not divided by 12)

.

6

.

OSC

C/T = 0

C/T = 1

To TL1

T1 pin

(P3.6)

TR1

GATE

Modified point in Timer 1

(No INT1 pin)

DD

V

Publication Release Date: December 1999

Revision A1

- 15 -

Preliminary W78E378/W78C378/W78C374

DDC1/SIO1 and SIO2 Ports

1. DDC1/SIO1 port

DDC Port

IN

SIO1

SCL

SDA

SCL

OUT

IN

SDA

OUT

0

1

Support DDC2B/2B+

DDC1

OUT

SDA

SCL

Vsync

Support DDC1

ENDDC1

· ENDDC1 = 1, used as DDC1 (Display Data Channel) port:

To support DDC1, use Vsync signal for shift clock and P3.0 (SDA) for data output.

·

ENDDC1 = 0, used as SIO1 port:

To support DDC2B/2B+/2Bi/2AB, use P3.1 (SCL) for serial clock and P3.0 (SDA) for serial data.

SCLINT interrupt is generated when SCL (P3.1) has a high-to-low transition and then keeps at low for

16 ´ 1/Fosc.

Fosc

8 MHz

10 MHz

SCL low

m

2 S

m

1.6 S

2. SIO2 port:

·

To support DDC2B/2B+/2Bi/2AB, use P4.4 (SCL) for serial clock and P4.5 (SDA) for serial data.

DDC1 Port

The DDC1 is a serial output port that supports DDC1 communication. To enable the DDC1 port,

ENDDC1 (bit 3 of CTRL1) should be set to '1'. Once previous eight data bits in the shift register and

IN

one null bit (the 9th bit) are shifted out to the SDA sequentially on each rising edge of the V signal,

the DDC1 control circuit loads the next data byte from the latch buffer (the DDC1 register) to the shift

register and generates a DDC1INT signal to the CPU. In the interrupt service routine, the S/W should

fetch the next byte of EDID data and write it to the DDC1 register. If ENDDC1 is cleared, the shift

register is stopped, and the SDA output is kept high. The bit DDC1B9 (bit 4 of CTRL2) decides the 9th

bit in a DDC transmission. If DDC1B9 is set, the 9th bit will be '1', otherwise '0'.

- 16 -

Preliminary W78E378/W78C378/W78C374

To use DDC1 port, a user should pay attention to the following items:

(1) When the chip is powered-on or after reset , the 8-bit shift register in DDC1 H/W contains all 0s. If

you write a data to the latch buffer (the DDC1 register), it will be loaded to the shift register at the

IN

9th clock (on V ), so from the 10th clock, the real data bit begins to shift out.

(2) Because there is no reset signal to the latch buffer, it contains a random data after power-on. If

you enable DDC1 without writing data to the latch buffer, SDA will have the random data shifted

out after 9 clocks. The shift register is reset to 00H during CPU reset.

(3) The DDC1 H/W has a counter that counts how many bits shifted out. This counter is initialized to 0

when power-up or reset. When you firstly enable DDC1 after power-on, the first bit is already

shifted out without clock, so the first clock triggers the second data bit (D6) to shift out and "0000

0001 1" will be got. After the first 9 clocks that shift out an invalid byte, the counter counts from 1

IN

to 9 cyclically according to the clock pulse on V -pin. See the following illustration.

0 1 2 3 4 5 6 7 8 9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

...

After power on, the

counter count:

0 0 0 0 0 0 0 0 1 1 D7 D6 D5 D4 D3 D2 D1 D0 ack D7 D6 D5 D4 D3 D2 D1 D0 ack

…

shifted-out data bit:

1 2 3 4 5 6 7 8 9

|--> invalid data

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

...

IN

V

clock pulse:

|--> normal data

(4) The interrupt happens on the failing edge of the following first clock. The next data, which is about

to be shifted out, in the latch buffer is loaded into the shift register at the rising edge of the

following first clock. At the same time, data bit D7 is shifted out and the counter value is "1".

SIO1 Port (with two slave addresses)

The SIO1 port is a serial I/O port, which supports all transfer modes from and to the I²C bus. The

SIO1 port handles byte transfers autonomously. To enable this port, the bit ENDDC1 in CTRL1

should be cleared to '0'. The CPU interfaces to the SIO1 port through the following five special

S1CON

S1ADR1 S1ADR2

S1STA

S1DAT

function registers:

register, DAh) and

(control register, D8h),

(status register, D9h), (data

/

(address registers, DBh/DCh). The SIO1 H/W interfaces to the

I²C bus via two pins: SDA (P3.0, serial clock line) and SCL (P3.1, serial data line). The output latches

of P3.0 and P3.1 must be set to "1" before using this port.

SIO2 Port (with two slave addresses)

The function of this port is the same as SIO1 port. The CPU interfaces to the SIO2 port through the

S2CON

S2STA

following five special function registers:

(control register, E8h),

(status register, E9h),

S2DAT

S2ADR1 S2ADR2

(data register, EAh) and

/ (address registers, EBh/ECh). The SIO2 H/W

interfaces to the I²C bus via two pins: SDA2 (P4.5, serial clock line) and SCL2 (P4.4, serial data line).

The output latches of P4.5 and P4.4 must be set to "1" before using this port.

Operation of SIO1 Port:

(SIO2 has the same function except their addresses of control registers)

Publication Release Date: December 1999

- 17 -

Revision A1

Preliminary W78E378/W78C378/W78C374

a) Control Registers

a-1) The Address Registers, S1ADR1, S1ADR2

The SIO1 is equipped with two address registers: S1ADR1 & S1ADR2. The CPU can read from and

write to these two 8-bit, directly addressable SFRs. The content of these registers are irrelevant when

SIO1 is in master modes. In the slave modes, the seven most significant bits must be loaded with the

MCU's own address. The SIO1 hardware will react if either of the addresses is matched.

7

6

5

4

3

2

1

0

-

X

|------------------------ Own Slave Address -----------------------|

a-2) The Data Register, S1DAT

This register contains a byte of serial data to be transmitted or a byte which has just been received.

The CPU can read from or write to this 8-bit directly addressable SFR while it is not in the process of

shifting a byte. This occurs when SIO1 is in a defined state and the serial interrupt flag (SI) is set.

Data in S1DAT remains stable as long as SI is set. While data is being shifted out, data on the bus is

simultaneously being shifted in; S1DAT always contains the last data byte present on the bus. Thus,

in the event of lost arbitration, the transition from master transmitter to slave receiver is made with

the correct data in S1DAT.

7

6

5

4

3

2

1

0

SD7

SD6

SD5

SD4

SD3

SD2

SD1

SD0

|<---------------------------- Shift direction -----------------------------

S1DAT and the acknowledge bit form a 9-bit shift register, the acknowledge bit is controlled by the

SIO1 hardware and cannot be accessed by the CPU. Serial data is shifted through the acknowledge

bit into S1DAT on the rising edges of serial clock pulses on the SCL line. When a byte has been

shifted into S1DAT, the serial data is available in S1DAT, and the acknowledge bit (ACK or NACK) is

returned by the control logic during the ninth clock pulse. Serial data is shifted out from S1DAT on the

falling edges of SCL clock pulses, and is shifted into S1DAT on the rising edges of SCL clock pulses.

a-3) The Control Register, S1CON

The CPU can read from and write to this 8-bit, directly addressable SFR. Two bits are affected by the

SIO1 hardware: the SI bit is set when a serial interrupt is requested, and the STO bit is cleared when

a STOP condition is present on the bus. The STO bit is also cleared when ENS1 = "0".

7

6

5

4

3

2

1

0

CR2

ENS1

STA

STO

SI

AA

CR1

CR0

ENS1, the SIO1 Enable Bit

ENS1 = "0": When ENS1 is "0", the SDA and SCL outputs are in a high impedance state. SDA and

SCL input signals are ignored, SIO1 is in the not addressed slave state, and STO bit in S1CON is

forced to "0". No other bits are affected. P3.0 (SDA) and P3.1 (SCL) may be used as open drain I/O

ports.

ENS1 = "1": When ENS1 is "1", SIO1 is enabled. The P3.0 and P3.1 port latches must be set to logic

1.

- 18 -

Preliminary W78E378/W78C378/W78C374

STA, the START Flag

STA = "1": When the STA bit is set to enter a master mode, the SIO1 hardware checks the status of

I2C bus and generates a START condition if the bus is free. If the bus is not free, then SIO1 waits for

a STOP condition and generates a START condition after a delay. If STA is set while SIO1 is already

in a master mode and one or more bytes are transmitted or received, SIO1 transmits a repeated

START condition. STA may be set at any time. STA may also be set when SIO1 is an addressed

slave.

STA = "0": When the STA bit is reset, no START condition or repeated START condition will be

generated.

STO, the STOP Flag

STO = "0": When the STO bit is set while SIO1 is in a master mode, a STOP condition is transmitted

to the I2C bus. When the STOP condition is detected on the bus, the SIO1 hardware clears the STO

flag. In a slave mode, the STO flag may be set to recover from an bus error condition. In this case, no

STOP condition is transmitted to the I2C bus. However, the SIO1 hardware behaves as if a STOP

condition has been received and switches to the defined not addressed slave receiver mode. The

STO flag is automatically cleared by hardware. If the STA and STO bits are both set, then a STOP

condition is transmitted to the I2C bus if SIO1 is in a master mode (in a slave mode, SIO1 generates

an internal STOP condition which is not transmitted). SIO1 then transmits a START condition.

SI, the Serial Interrupt Flag

SI = "1": When a new SIO1 state is present in the S1STA register, the SI flag is set by hardware, and,

if the EA and ES bits (in IE register) are both set, a serial interrupt is requested. The only state that

does not cause SI to be set is state F8H, which indicates that no relevant state information is

available. When SI is set, the low period of the serial clock on the SCL line is stretched, and the serial

transfer is suspended. A high level on the SCL line is unaffected by the serial interrupt flag. SI must

be cleared by software.

SI = "0": When the SI flag is reset, no serial interrupt is requested, and there is no stretching on the

serial clock on the SCL line.

AA, the Assert Acknowledge Flag

AA = "1": If the AA flag is set, an acknowledge (low level to SDA) will be returned during the

acknowledge clock pulse on the SCL line when: 1) The own slave address has been received. 2) A

data byte has been received while SIO1 is in the master receiver mode. 3) A data byte has been

received while SIO1 is in the addressed slave receiver mode.

AA = "0": If the AA flag is reset, a not acknowledge (high level to SDA) will be returned during the

acknowledge clock pulse on SCL when: 1) A data has been received while SIO1 is in the master

receiver mode. 2) A data byte has been received while SIO1 is in the addressed slave receiver mode.

CR0, CR1 and CR2, the Clock Rate Bits

These three bits determine the serial clock frequency when SIO1 is in a master mode. It is not

important when SIO1 is in a slave mode. In the slave modes, SIO1 will automatically synchronize

with any clock frequency up to 100 KHz.

Publication Release Date: December 1999

- 19 -

Revision A1

Preliminary W78E378/W78C378/W78C374

Bit Freq. (KHz) @Fosc

CR2

CR1

CR0

8 MHz

10 MHz

Fosc Divided

By

0

1

0

1

0

1

0

1

0

1

0

1

0

31.25

35.7

41.7

50.0

8.3

39.1

44.6

52.1

62.5

10.4

83.3

166.7

256

224

192

160

960

120

60

66.7

133.3

a-4) The Status Register, S1STA

S1STA is an 8-bit read-only register. The three least significant bits are always 0. The five most

significant bits contain the status code. There are 23 possible status codes. When S1STA contains

F8H, no serial interrupt is requested. All other S1STA values correspond to defined SIO1 states.

When each of these states is entered, a status interrupt is requested (SI = 1). A valid status code is

present in S1STA one machine cycle after SI is set by hardware and is still present one machine

cycle after SI has been reset by software.

In addition, state 00H stands for a Bus Error. A Bus Error occurs when a START or STOP condition is

present at an illegal position in the format frame. Examples of illegal positions are during the serial

transfer of an address byte, a data byte or an acknowledge bit.

b) Operating Modes

The four operating modes are: Master/Transmitter, Master/Receiver, Slave/Transmitter and

Slave/Receiver. Bits STA, STO and AA in S1CON decide the next action the SIO1 hardware will take

after SI is cleared. When the next action is completed, a new status code in S1STA will be updated

and SI will be set by hardware in the same time. Now, the interrupt service routine is entered (if the

SI_interrupt is enabled), the new status code can be used to decide which appropriate service routine

the software is to branch. Data transfers in each mode are shown in the following figures.

*** Legend for the following four figures:

Software's access to S1DAT with respect to "Expected next action":

Last state

08H

1) "Data byte will be transmitted":

A START has been

transmitted.

Last action is done

Software should load the data byte (to be transmitted) into S1DAT

before new S1CON setting is done.

2) "SLA+W (R) will be transmitted":

Next setting in S1CON

(STA,STO,SI,AA)=(0,0,0,X)

SLA+W will be transmitted;

ACK bit will be received.

Software should load the SLA+W/R (to be transmitted) into S1DAT

before new S1CON setting is done.

Expected next action

3) "Data byte will be received":

Software can read the received data byte from S1DAT

while a new state is entered.

New state

18H

SLA+W has been transmitted;

ACK has been received.

Next action is done

- 20 -

Preliminary W78E378/W78C378/W78C374

Master/Transmitter Mode

Set STA to generate

a START.

From Slave Mode (C)

08H

A START has been

transmitted.

(STA,STO,SI,AA)=(0,0,0,X)

SLA+W will be transmitted;

ACK bit will be received.

From Master/Receiver (B)

18H

SLA+W has been transmitted;

ACK has been received.

or

20H

SLA+W has been transmitted;

NOT ACK has been received.

(STA,STO,SI,AA)=(0,1,0,X)

A STOP will be transmitted;

STO flag will be reset.

(STA,STO,SI,AA)=(0,0,0,X)

Data byte will be transmitted;

ACK will be received.

(STA,STO,SI,AA)=(1,0,0,X)

A repeated START will be transmitted.

(STA,STO,SI,AA)=(1,1,0,X)

A STOP followed by a START will be

transmitted;

STO flag will be reset.

28H

10H

Send a STOP

followed by a START

Data byte in S1DAT has been transmitted;

ACK has been received.

A repeated START has been

transmitted.

or

30H

Data byte in S1DAT has been transmitted;

NOT ACK has been received.

(STA,STO,SI,AA)=(0,0,0,X)

SLA+R will be transmitted;

38H

ACK bit will be received;

SIO1 will be switched to MST/REC mode.

Arbitration lost in SLA+R/W

or Data bytes.

To Master/Receiver (A)

(STA,STO,SI,AA)=(0,0,0,X)

(STA,STO,SI,AA)=(1,0,0,X)

A START will be transmitted when

the bus becomes free.

I2C bus will be released;

Not addressed SLV mode will be entered.

Enter NAslave

Send a START

when bus becomes free

Publication Release Date: December 1999

Revision A1

- 21 -

Preliminary W78E378/W78C378/W78C374

Master/Receiver Mode

Set STA to generate

a START.

From Slave Mode (C)

08H

A START has been

transmitted.

(STA,STO,SI,AA)=(0,0,0,X)

SLA+R will be transmitted;

ACK will be received.

From Master/Transmitter (A)

48H

40H

SLA+R has been transmitted;

NOT ACK has been received.

SLA+R has been transmitted;

ACK has been received.

(STA,STO,SI,AA)=(0,0,0,0)

Data byte will be received;

NOT ACK will be returned.

(STA,STO,SI,AA)=(0,0,0,1)

Data byte will be received;

ACK will be returned.

58H

50H

Data byte has been received;

NOT ACK has been returned.

Data byte has been received;

ACK has been returned.

(STA,STO,SI,AA)=(1,1,0,X)

(STA,STO,SI,AA)=(0,1,0,X)

A STOP will be transmitted;

STO flag will be reset.

(STA,STO,SI,AA)=(1,0,0,X)

A repeated START will be transmitted.

A STOP followed by a START will

be transmitted;

STO flag will be reset.

Send a STOP

10H

Send a STOP

followed by a START

A repeated START has been

transmitted.

(STA,STO,SI,AA)=(0,0,0,X)

SLA+W will be transmitted;

ACK will be received;

38H

Arbitration lost in NOT ACK bit.

SIO1 will be switched to MST/TRX mode.

To Master/Transmitter (B)

(STA,STO,SI,AA)=(1,0,0,X)

A START will be transmitted

when the bus becomes free.

(STA,STO,SI,AA)=(0,0,0,X)

I2C bus will be released;

Not addressed SLV mode will be entered.

Send a START

when bus becomes free

Enter NAslave

- 22 -

Preliminary W78E378/W78C378/W78C374

Slave/Transmitter Mode

Set AA

A8H

Own SLA+R has been received;

ACK has been returned.

or

B0H

Arbitration lost in SLA+R/W as master;

Own SLA+R has been received;

ACK has been returned.

(STA,STO,SI,AA)=(0,0,0,0)

Last data byte will be transmitted;

ACK will be received.

(STA,STO,SI,AA)=(0,0,0,1)

Data byte will be transmitted;

ACK will be received.

C8H

C0H

B8H

Last data byte in S1DAT has been transmitted;

ACK has been received.

Data byte or Last data byte in S1DAT has

Data byte in S1DAT has been transmitted;

ACK has been received.

been transmitted;

NOT ACK has been received.

(STA,STO,SI,AA)=(0,0,0,0)

Last data byte will be transmitted;

ACK will be received.

(STA,STO,SI,AA)=(0,0,0,1)

Data byte will be transmitted;

ACK will be received.

(STA,STO,SI,AA)=(1,0,0,1)

Switch to not addressed SLV mode;

Own SLA will be recognized;

A START will be transmitted when

the bus becomes free.

(STA,STO,SI,AA)=(1,0,0,0)

(STA,STO,SI,AA)=(0,0,0,1)

Switch to not addressed SLV mode;

Own SLA will be recognized.

(STA,STO,SI,AA)=(0,0,0,0)

Switch to not addressed SLV mode;

No recognition of own SLA.

Switch to not addressed SLV mode;

No recognition of own SLA;

A START will be transmitted when

the bus becomes free.

Enter NAslave

`

Send a START

when bus becomes free

To Master Mode (C)

Publication Release Date: December 1999

Revision A1

- 23 -

Preliminary W78E378/W78C378/W78C374

Slave/Receiver Mode

Set AA

60H

Own SLA+W has been received;

ACK has been returned.

or

68H

Arbitration lost in SLA+R/W as master;

Own SLA+W has been received;

ACK has been returned.

(STA,STO,SI,AA)=(0,0,0,0)

Data byte will be received;

NOT ACK will be returned.

(STA,STO,SI,AA)=(0,0,0,1)

Data byte will be received;

ACK will be returned.

88H

80H

Previously addressed with own SLA address;

Data has been received;

NOT ACK has been returned.

Previously addressed with own SLA address;

Data has been received;

ACK has been returned.

(STA,STO,SI,AA)=(0,0,0,0)

(STA,STO,SI,AA)=(0,0,0,1)

Data will be received;

ACK will be returned.

A0H

Data will be received;

A STOP or repeated START has been

received while still addressed as SLV/REC.

NOT ACK will be returned.

(STA,STO,SI,AA)=(1,0,0,1)

Switch to not addressed SLV mode;

Own SLA will be recognized;

A START will be transmitted when

the bus becomes free.

(STA,STO,SI,AA)=(1,0,0,0)

Switch to not addressed SLV mode;

No recognition of own SLA;

A START will be transmitted when

the bus becomes free.

(STA,STO,SI,AA)=(0,0,0,1)

Switch to not addressed SLV mode;

Own SLA will be recognized.

(STA,STO,SI,AA)=(0,0,0,0)

Switch to not addressed SLV mode;

No recognition of own SLA.

Enter NAslave

`

Send a START

when bus becomes free

To Master Mode (C)

- 24 -

Preliminary W78E378/W78C378/W78C374

Parabola Interrupt Generator

The parabola interrupt generator is a 13-bit auto-reload timer, which generates an interrupt to the

CPU periodically for software to load the parabola waveform data to the dynamic DACs

-

(DAC8 DAC10). The software should calculate the value of the PARAH and PARAL registers by:

´

¸

segment number. The segment number is the number of integration segments

(Vcount

16)

between two Vsync pulses. The interrupt interval is programmable:

·

Time base = 1/Fosc

Programmable interrupt period = Time base (PARAH 256 + PARAL + 1)

´

Maximum period = Time base 8192

Note: Zero value in [PARAH, PARAL] is inhibited.

A-to-D Converter

(ref. Application Note in Appendix A.)

One 4-bit Analog-to-Digital Converter.

· Conversion time = (6/Fosc) ´ 128 sec.

· 7 channels selected by an analog multiplexer

(ADCS2, ADCS1, ADCS0) (0, 0, 0) (0, 0, 1) (0, 1, 0) (0, 1, 1) (1, 0, 0) (1, 0, 1) (1, 1, 0)

Selected Channel

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

The conversion of the ADC is started by setting bit ADCSTRT in CTRL1 by software. When the

conversion is completed, the ADCSTRT bit is cleared by hardware automatically, and the ADCINT bit

in INTVECT is set by hardware at the same time if MADCINT in INTMSK is set.

PWM DACs

Eight 8-bit Static DACs: DAC0-DAC7

PWM

·

The PWM frequency F

= Fosc ÷ 255

The duty cycle of the PWM output = Register value ÷ 255

CC

´

The DC voltage after the low pass filter = V

duty cycle

Static DAC application circuit:

Low-pass filter

V_OUTPUT

Static DAC

R

C

T = RC

¡ Ñ

V_OUTPUT= V_CCn/255, if T >> T _PWM

Publication Release Date: December 1999

Revision A1

- 25 -

Preliminary W78E378/W78C378/W78C374

Three 8-bit Dynamic DACs: DAC8-DAC10

The dynamic DACs are especially used to generate parabola waveform for geometric compensation,

or to be used as static DACs. Dynamic DAC application circuit:

470

+Vsync

470

0.022u

100K

10u/50V

Dynamic DAC

V_output

VDD

10K

4.7u/16V

10K

The following types of distoration can be compensated:

1. H size distortion:

a. PinCushion Correction (Amplitude)

b. Trapezoid (Keystone)

25%

c. CBOW (Quarter Width)

d. PinCushion Correction (Corner)

e. S Curve

The PCC amplitude can be compensated against V size adjustment automatically.

The Trapzoid can be compensated against V center adjustment automatically.

2. H center distortion:

a. Pin balance (Bow)

b. Key balance (Tilt)

c. Corner balance

- 26 -

Preliminary W78E378/W78C378/W78C374

Sync Processor

Polarity Detector

The H/V polarity is detected automatically and can be known from HPOL bit (HFCOUNTH.7) and

VPOL bit (VFCOUNTH.7).

Fosc

10 MHz

(64/Fosc) 62 (counter overflow) = 396.8 S

Max. H+V width

Max. V width

´

m

´

m

(2048/Fosc) 2 = 409.6 S

Sync Separator

The Vsync is separated from the composite sync automatically, without any software effort.

Fosc

10 MHz

Min. V width & Max. H width

´

m

(1/Fosc) 64 = 6.4 S

Horizontal & Vertical Frequency Counter

There are two 12-bit counters which can count H and V frequency automatically. When VEVENT

(Vsync frequency counter timeout) interrupt happens, the count value values are latched into the

counter registers (HFCOUNTH, HFCOUNTL, VFCOUNTH and VFCOUNTL). And then the S/W may

read the count value (H_COUNTand V_COUNT) from the counter registers to calculate the H and V

frequency by the formulas listed below.

V frequency:

RESOL

´

The resolution of V frequency counter: V

= (1/Fosc) 64.

FREQ

COUNT

´

= 1/(V

The V frequency: V

V

).

The lowest V frequency can be detected: Fosc ÷ 262144. (38.1Hz @Fosc =10 MHz)

H frequency:

RESOL

The resolution of H frequency counter: H

= (1/Fosc) ¸ 8.

FREQ

The H frequency: H

COUNT

= 1/(H

RESOL

H ).

´

¸

The lowest H frequency can be detected: Fosc 512. (19.5 KHz @Fosc = 10 MHz)

Dummy Frequency Generator

The Dummy H and V frequencies are generated for factory burn-in or showing warning message

while there are no input frequency.

(HDUMS1, HDUMS0)

(0, 0)

(0, 1)

(1, 0)

(1, 1)

dummyH

F

´

5

Fosc/(8

4

8) Fosc/(8

2

8)

Fosc/(8

3

8)

Fosc/(8

8)

Hsync width

´

(8 4)/Fosc

(8 2)/Fosc

(8 3)/Fosc

(8 5)/Fosc

VDUMS

0

1

dummyV

F

dummyH

F /1024

F

/ 512

dummyH

8/ F

dummyH

Vsync width

16/ F

Publication Release Date: December 1999

Revision A1

- 27 -

Preliminary W78E378/W78C378/W78C374

1/FdummyH

Hsync width

Hdummy

Vdummy

.....

Vsync width

1/FdummyV

For Fosc = 10 MHz:

(HDUMS1,

HDUMS0)

(0, 1)

(1, 0)

52.083 KHz

(0, 0)

(1, 1)

dummyH

F

78.125 KHz

39.063 KHz

31.250 KHz

Hsync width

VDUMS

m

1.6 S

m

2.4 S

m

3.2 S

m

4.0 S

0

1

0

1

0

1

0

1

152.6 Hz

76.3 Hz 101.7 Hz 50.9 Hz 76.3 Hz 38.1 Hz 61.0 Hz 30.5 Hz

dummyV

F

H-clamp Pulse Generator

1. Leading edge/Trailing edge selectable.

* HCES = 0: select leading edge

* HCES = 1: select trailing edge

Negative polarity Hsync

Hsync

Postive polarity Hsync

Hsync

Hclamp

(Leading-edge)

Hclamp

(Trailing-edge)

Hclamp

(Trailing-edge)

- 28 -

Preliminary W78E378/W78C378/W78C374

2. Pulse width selectable.

For Fosc = 10 MHz:

HCWS = 0

HCWS = 1

Pulse Width

-

500 600 nS

900 1000 nS

Safe Operation Area (SOA) Interrupt

´

Upper boundary frequency = F_OSC/ [8 SOARH]

Lower boundary frequency = F_OSC/ [8 ´ (SOARL + 1)]

Function description:

·

If the condition, H_FREQlower than the lower boundary freq. or higher than the upper boundary freq.,

happens twice continuously, the SOAINT will be activated.

·

If the HIN is stopped for a certain period, the SOAINT will also be generated.

The no Hsync response time is 512/F_OSC. (e.x., 51.2us for 10 MHz)

·

If SOAHDIS = 1, then no upper boundary frequency.

Half Hsync Output

When ENHFO (bit 0 of CTRL3) is set, P4.7 (HFO) will output the same or half frequency from P4.0

(HFI). The divide-by-two operation is done at the falling edge of HFI signal when HFO_HALF (bit 3 of

CTRL3) is set. The polarity of HFO is specified by HF_POL (bit 2 of CTRL3).

HFI

HFO

(HFO_HALF=0)

(HF_POL=1)

HFO

(HFO_HALF=0)

(HF_POL=0)

HFO

(HFO_HALF=1)

Publication Release Date: December 1999

- 29 -

Revision A1

Preliminary W78E378/W78C378/W78C374

Interrupts

The five interrupt sources are listed as below.

SOURCE VECTOR ADDRESS

DESCRIPTON

PRIORITY WITHIN A LEVEL

1

2

3

4

5

IE0

TF0

0003H

000BH

0013H

001BH

002BH

Interrupt 0 edge detected

Timer 0 overflow

Miscellaneous interrupts^*1

Highest

IE1

TF1

Timer 1 overflow

SI1+SI2

SIO1 or SIO2 interrupt

Lowest

Note: *1: SCLINT + ADCINT + DDC1INT + SOAINT + VEVENT + PARAINT.

The miscellaneous interrupts at vector address 0013H is driven by the following six sources, which

are:

(1) SCLINT: when high-to-low transition on SCL-pin,

(2) ADCINT: when A-to-D conversion completion,

IN

(3) DDC1INT: when DDC1 data byte transmitted (after 9 clock pulses from V ) in the DDC port,

(4) SOAINT: when SOA activated,

(5) VEVENT: on every Vsync pulse or vertical frequency counter overflow,

(6) PARAINT: when parabola timer timeout.

If IE1 interrupt occurs, it is necessary for the programmer to read the INTVECT register to tell where

the interrupt request comes. These sources can be masked individually by clearing their

corresponding bits in the INTMSK register. To clear any of these interrupt flags, just write a '1' to the

corresponding bit in the INTCLR.

The interrupt enable bits and priority control bits for these five main sources are listed as below.

INTERRUPT FLAG

ENABLE BIT

IE.0 & IE.7

IE.1 & IE.7

IE.2 & IE.7

IE.3 & IE.7

IE.5 & IE.7

PRIORITY CONTROL BIT

1

2

3

4

5

IE0

TF0

IP.0

IP.1

IP.2

IP.3

IP.5

IE1

TF1

SI+SI2

- 30 -

Preliminary W78E378/W78C378/W78C374

Vector Address

IE

IP

High Priority

Low Priority

0003H

000BH

IE0

IE.0

IP.0

IP.1

TF0

IE.1

Interrupt Polling

Sequence

0013H

IE1

IP.2

IE.2

001BH

002BH

TF1

IE.3

IE.5

IP.3

IP.5

SI1+SI2

IE.7

INTMSK

Bit 0

INTVECT

SCL Interrupt

SCLINT

0

1

2

3

4

5

Bit 1

ADC Interrupt

DDC1 Interrupt

SOA Interrupt

ADCINT

DDC1INT

SOAINT

VEVENT

PARAINT

Bit 2

0

Bit 3

IE1

IT1

1

Bit 4

VEVENT Interrupt

PARA Interrupt

Bit 5

Publication Release Date: December 1999

Revision A1

- 31 -

Preliminary W78E378/W78C378/W78C374

Reset Circuit- Power-low Detector & Watchdog Timer

The reset signals come from the following three sources:

1. External reset input (active low)

2. Power low detect

3. Hardware Watchdog Timer

CC

3.5V

The power-low detection circuit generates a reset signal once the V falls below

for above 10

CC

m

1.8V

4.3V

S or falls below

, and the reset signal is released after V goes up to .

4.3V

3.8V

1.8V

VCC

10uS

Power-low Reset

The purpose of a watchdog timer is to reset the CPU if the user program fails to reload the watchdog

timer within a reasonable period of time known as the "watchdog interval". The clock source of the

watchdog timer comes from the internal system clock. It can be enabled/disabled by set/clear

RESET

WDTEN (bit 5 of CTRL2). For debug purpose, if the WDT reset or power low reset occur, the

pin will be pulled low internally. The pulled-low duration due to WDT reset is about 60/Fosc sec. The

block diagram of the reset circuitry is shown as below.

R:100K

C:0.01u

/RESET

Watchdog

Timer

Reset Logic

EN

WDTEN

External Reset

Power-low

Supervisor

Iol=12mA @Vol=0.45V

- 32 -

Preliminary W78E378/W78C378/W78C374

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings

PARAMETER

DC Power Supply

Input Voltage

SYMBOL

MIN.

-0.3

SS

MAX.

+7.0

DD

UNIT

V

DD

V

IN

V

-0.3

V

+0.3

V

IN

Input Current

I

-100

0

+100

70

mA

A

T

Operating Temperature

°C

TST

Storage Temperature

-55

150

°

C

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the

device.

D.C. Characteristics

VDD-VSS= 5V 10%, TA = 25 C, Fosc = 10 MHz, unless otherwise specified.

±

°

PARAMETER

SYM.

SPECIFICATION

MIN. TYP. MAX.

UNIT

TEST CONDITIONS

DD

Operating Voltage

Operating Current

Power-down Current

Input

V

4.5

5

-

5.5

30

V

All function must pass!

DD

I

-

mA

No load, V = 5.5V

PD

DD

I

-

100

No load, V = 5.5V

m

A

IN1

DD

IN

Input Current

I

-75

-10

-

-10

+10

-100

+10

V

= 5.5V, V = 0V

m

A

IN

-

= 5.5V, V = 5.5V

-

P2, P3.2 P3.4, P4.0

IN2

DD

IN

I

-300

-10

= 5.5V, V = 0V

m

A

RESET

Input Current

IN

= 5.5V, V = 5.5V

LK

IN

Input Leakage Current

I

-10

V

= 5.5V, 0V<V <

mA

DD

S.F. enabled)

-

P1, P2.4 P2.7(

-

P3.0, P3.1, P3.5 P3.7,

IN

P4.4, P4.5 H , V

TL

DD

IN

Logical 1-to-0 Transition

Current

I

-650

0

-

-100

0.8

V

= 5.5V, V = 2.0V

m

A

-

P2, P3.2 P3.4

IL1

V

DD

Input Low Voltage

-

V

= 4.5V

P1, P2, P3 (except P3.0 &

IN

P3.1), P4.0, H , V ,

RESET

, OSCIN

Publication Release Date: December 1999

Revision A1

- 33 -

Preliminary W78E378/W78C378/W78C374

D.C. Characteristics, continued

PARAMETER

SYM.

SPECIFICATION

MIN. TYP. MAX.

UNIT

TEST CONDITIONS

IL2

DD

Input Low Voltage

V

0

-

0.3

V

= 4.5V

DD

P3.0, P3.1, P4.4, P4.5

Input High Voltage

IH1

DD

V

2.0

-

V

= 5.5V

P1, P2, P3 (except P3.0 &

+0.2

IN

RESET

P3.1), P4.0, H , V ,

IH2

DD

Input High Voltage

V

0.7

-

V

= 5.5V

DD

V

P3.0, P3.1, P4.4, P4.5

Input High Voltage

OSCIN

+0.2

IH3

DD

V

3.5

V

= 5.5V

+0.2

Output

DD

V

Output Low Voltage

V_OL1

-

0.45

V

= 4.5V

OL

I

= +12 mA

RESET

P1.0, P1.1,

DD

Output Low Voltage

P3.0, P3.1, P4.4, P4.5

Output Low Voltage

P1 (except P1.0 & P1.1)

V_OL2

-

0.45

V

= 4.5V

OL

I

= +8 mA

DD

V

V_OL3

= 4.5V

OL

I

= +4 mA

-

P2, P3 (except P3.0 P3.2)

P4 (except P4.4 & P4.5)

Output Low Voltage

P3.2, OSCOUT

DD

V_OL4

V_OH1

V_OH2

V_OH3

-

0.45

V

= 4.5V

OL

I

= +0.8 mA

DD

V = 4.5V

Output High Voltage

2.4

-

OH

-

m

= -100 A

P2, P3.2 P3.4

I

DD

V

Output High Voltage

= 4.5V

OH

P4 (except P4.4 & P4.5)

I

= -4 mA

DD

V

Special Function Output

High Voltage

= 4.5V

OH

I

= -4 mA

-

P2.0 P2.3, P3.3, P3.4

DD

Output High Voltage

OSCOUT

V_OH4

2.4

-

V

= 4.5V

OH

I

= -3 mA

Notes:

*1.

has an internal pull-up resistor of about 30 K

.

RESET

W

*2. P2 and P3.2 P3.4 can source a transition current when they are being externally driven from 1 to 0. The transition current

-

reaches its maximum value when VIN is approximately 2V.

*3. P3.0, P3.1, P4.4, P4.5, HIN, VIN and

are Schmitt trigger inputs.

RESET

- 34 -

Preliminary W78E378/W78C378/W78C374

Appendix A. Application Note for Usage of ADC

To use the ADC, users should pay attention to the following points:

DD

(1) According to the absolute maximum ratings, the input voltage should not exceed V

+0.3V,

DD

-

especially for the ADC channel pins (P2.4 P2.7 & P3.5 P3.7). If a voltage over V +0.3V exists

on any of these ADC channel pins, the AD conversion will fail.

(2) Owing to the CMOS process, the ADC curve of some chip might differ from those of the others.

So, before using the ADC, the S/W should do the ADC calibration described below.

Step 1. Set (ADCS2, ADCS1, ADCS0, ADCcal) = (1, 1, 1, 0) and then do AD coversion to get

0.948V

A

the ADC value for the on-chip

Step 2. Set (ADCS2, ADCS1, ADCS0, ADCcal) = (1, 1, 1, 1) and then do AD coversion to get

2.924V

input. Suppose it is

.

B

input. Suppose it is .

the ADC value for the on-chip

Step 3. Because the ADC curve in the usable range is linear, any V and X should meet the

formula:

(X-A)/(V-0.948) = (B-A)/(2.924-0.948),

where V is the key voltage (designed by users and thus known) and X is its predicted

ADC value. Then, we can get X = A + (V-0.948)(B-A)/(2.924-0.948), regardless of V >

Of course, some effort should be paid in S/W to find .)

0.948V or < 0.948V. (

X

Step 4. Suppose there are N keys used, the N predicted ADC values for these keys can be

found.

ADC value

B

X

Usable range

(is linear)

A

ADC input voltage

1.0

2.0

3.0

4.0

5.0

V

After finding these N predicted ADC values, the S/W can recognize which key is pressed by

comparing the ADC value of this key with the set of predicted values (found previously).

** Note: To get the exact on-chip calibration voltages (0.948V and 2.924V), the V_DDshould be 5.0V as close as possible.

Publication Release Date: December 1999

- 35 -

Revision A1

Preliminary W78E378/W78C378/W78C374

Test strategy before shipping:

(1) Vi = 0V => ADC < 20

(2) Vi = 0.8V => ADC > 25

(3) Vi = 3.2V => ADC < 248

(4) Vi = 4.4V => ADC = 255

(5) 0.8V < Vi < 3.2V, 25 points (step 0.1V) will be tested. All test points should be recognized

correctly.

Comment:

a. (1) guarantees 0V input can be recognized (ADC value < 20).

b. (4) guarantees 5V input can be recognized (ADC value = 255).

c. (2), (3) and (5) guarantee linear (with 4 bits at least) within the usable range (0.8V to 3.2V).

25

20

ADC value

0.8

Usable range

248

3.2

4.4

Analog voltage (V)

- 36 -

Preliminary W78E378/W78C378/W78C374

PACKAGE DIMENSIONS

32-pin P-DIP

Dimension in inches

Dimension in mm

Symbol

A

Nom.

Min.

Max. Min.

0.210

Max.

5.33

0.010

0.25

A

B

1

0.150 0.155 0.160 3.81

3.94

0.46

1.27

0.25

4.06

0.56

1.37

0.36

2

0.016 0.018

0.41

1.22

0.20

0.022

0.054

0.050

0.048

0.008

B₁

c

D

E

0.010 0.014

1.650 1.660

D

17

32

41.91 42.16

15.49

14.10

2.79

0.590 0.600 0.610 14.99 15.24

13.84

2.29

3.05

0

13.97

2.54

3.30

0.545 0.550 0.555

E

1

0.110

0.140

15

0.090 0.100

0.120 0.130

0

e

L

a

1

E₁

3.56

15

0.630 0.650 0.670 16.00 16.51 17.02

0.085

e_A

S

2.16

16

1

Notes:

E

S

1. Dimensions D Max. & S include mold flash or

tie bar burrs.

c

2. Dimension E1 does not include interlead flash.

3. Dimensions D & E1 include mold mismatch and

are determined at the mold parting line.

4. Dimension B1 does not include dambar

protrusion/intrusion.

2

A

L

A1

Base Plane

Seating Plane

5. Controlling dimension: Inches

B

e1

e_A

a

6. General appearance spec. should be based on

B1

final visual inspection spec.

40-pin DIP

Dimension in inch

Dimension in mm

Symbol

A

Min. Nom. Max. Min. Nom. Max.

5.334

0.210

0.010

0.150 0.155 0.160

0.254

3.81

1

A

3.937 4.064

A

B

2

0.016 0.018

0.406 0.457 0.559

0.022

0.054

0.050

1.219 1.27

1.372

0.356

0.048

0.008

1

B

c

0.203

0.010 0.014

2.055 2.070

0.254

52.20

15.24

D

52.58

D

E

e

L

a

40

21

15.494

0.610

0.590 0.600

14.986

13.72

0.540

13.84 13.97

2.54 2.794

0.545

0.550

0.110

1

0.090 0.100

2.286

3.048

0

0.120 0.130 0.140

3.302 3.556

15

1

E

0

15

0.630

0.670 16.00

0.090

17.01

2.286

0.650

16.51

e

S

A

20

1

Notes:

E

1. Dimension D Max. & S include mold flash or

tie bar burrs.

S

c

2. Dimension E1 does not include interlead flash.

3. Dimension D & E1 include mold mismatch and

are determined at the mold parting line.

4. Dimension B1 does not include dambar

protrusion/intrusion.

5. Controlling dimension: Inches.

A2

A

L

Base Plane

1

A

.

Seating Plane

B

e₁

eA

a

B ₁

6. General appearance spec. should be based on

final visual inspection spec.

Publication Release Date: December 1999

Revision A1

- 37 -

Preliminary W78E378/W78C378/W78C374

Package Dimensions, continued

44-pin PLCC

D

H

D

6

1

44

40

Dimension in inches

Dimension in mm

Symbol

Max. Min. Nom.

Min. Nom.

Max.

4.70

0.185

0.51

7

39

A

0.020

1

A

0.145 0.150

0.026 0.028

0.016 0.018

3.68 3.81 3.94

0.155

A

b

c

2

1

0.032 0.66

0.81

0.56

0.36

0.71

0.022

0.41 0.46

E

H

E

0.008 0.010 0.014 0.20 0.25

G

16.46 16.59 16.71

0.648 0.653 0.658

D

E

e

BSC

1.27 BSC

0.050

0.590

0.680

0.090

14.99 15.49 16.00

D

E

D

E

0.610 0.630

G

H

L

17

29

17.27

0.700

17.53 17.78

0.690

0.100

18

28

c

2.54

0.110 2.29

0.004

2.79

0.10

y

Notes:

L

2

1. Dimension D & E do not include interlead flash.

A

2. Dimension b1 does not include dambar

protrusion/intrusion.

3. Controlling dimension: Inches

4. General appearance spec. should be based

on final visual inspection spec.

q

e

b

b₁

1

A

Seating Plane

y

G D

Winbond Electronics (H.K.) Ltd.

Winbond Electronics North America Corp.

Headquarters

Rm. 803, World Trade Square, Tower II, Winbond Memory Lab.

123 Hoi Bun Rd., Kwun Tong,

No. 4, Creation Rd. III,

Science-Based Industrial Park,

Hsinchu, Taiwan

TEL: 886-3-5770066

FAX: 886-3-5792766

Winbond Microelectronics Corp.

Kowloon, Hong Kong

TEL: 852-27513100

FAX: 852-27552064

Winbond Systems Lab.

2727 N. First Street, San Jose,

CA 95134, U.S.A.

http://www.winbond.com.tw/

TEL: 408-9436666

FAX: 408-5441798

Voice & Fax-on-demand: 886-2-27197006

Taipei Office

11F, No. 115, Sec. 3, Min-Sheng East Rd.,

Taipei, Taiwan

TEL: 886-2-27190505

FAX: 886-2-27197502

Note: All data and specifications are subject to change without notice.

- 38 -


型号：	W78C378ED
厂家：	WINBOND
描述：	Microcontroller, 8-Bit, MROM, 10MHz, CMOS, PDIP40, 0.600 INCH, DIP-40 时钟微控制器光电二极管外围集成电路
文件：	总38页 (文件大小：396K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W78C378ED [WINBOND]

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