W25X20CVSNBG_技术文档

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

3.3 V

2M-BIT

SERIAL FLASH MEMORY WITH

4KB SECTORS AND DUAL I/O SPI

For Automotive Applications

Publication Release Date: September 10, 2012

Revision A

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FOR AUTOMOTIVE APPLICATIONS

W25X20CV

Table of Contents

1.

2.

3.

4.

5.

GENERAL DESCRIPTION ......................................................................................................... 4

FEATURES................................................................................................................................. 4

PIN CONFIGURATION SOIC 150 / 208-MIL.............................................................................. 5

PAD CONFIGURATION WSON 6X5-MM AND USON 2X3-MM................................................ 5

PIN DESCRIPTION SOIC, WSON 6X5-MM AND USON 2X3-MM............................................ 5

5.1

5.2

5.3

5.4

5.5

5.6

Package Types............................................................................................................... 6

Chip Select (/CS)............................................................................................................ 6

Serial Data Input, Output and IOs (DIO, DO, IO0 and IO1) ........................................... 6

Write Protect (/WP)......................................................................................................... 6

HOLD (/HOLD)................................................................................................................ 6

Serial Clock (CLK) .......................................................................................................... 6

6.

7.

BLOCK DIAGRAM ...................................................................................................................... 7

6.1

SPI OPERATIONS.......................................................................................................... 8

6.1.1 Standard SPI Instructions .................................................................................................8

6.1.2 Dual SPI Instructions ........................................................................................................8

6.1.3 Hold Function....................................................................................................................8

WRITE PROTECTION.................................................................................................... 9

6.2.1 Write Protect Features......................................................................................................9

6.2

CONTROL AND STATUS REGISTERS................................................................................... 10

7.1

STATUS REGISTER .................................................................................................... 10

7.1.1 BUSY..............................................................................................................................10

7.1.2 Write Enable Latch (WEL) ..............................................................................................10

7.1.3 Block Protect Bits (BP1, BP0).........................................................................................10

7.1.4 Top/Bottom Block Protect (TB) .......................................................................................10

7.1.5 Reserved Bits .................................................................................................................11

7.1.6 Status Register Protect (SRP) ........................................................................................11

7.1.7 Status Register Memory Protection ................................................................................12

INSTRUCTIONS........................................................................................................... 13

7.2.1 Manufacturer and Device Identification...........................................................................13

7.2.2 Instruction Set ...............................................................................................................14

7.2.3 Write Enable (06h)..........................................................................................................15

7.2.4 Write Enable for Volatile Status Register (50h)...............................................................15

7.2.5 Write Disable (04h) .........................................................................................................16

7.2.6 Read Status Register (05h) ............................................................................................16

7.2.7 Write Status Register (01h).............................................................................................17

7.2.8 Read Data (03h) .............................................................................................................18

7.2.9 Fast Read (0Bh)..............................................................................................................19

7.2.10 Fast Read Dual Output (3Bh) .......................................................................................20

7.2.11 Fast Read Dual I/O (BBh).............................................................................................21

7.2.12 Continuous Read Mode Bits (M7-0)..............................................................................23

7.2.13 Continuous Read Mode Reset (FFFFh)........................................................................23

7.2.14 Page Program (02h) .....................................................................................................24

7.2.15 Sector Erase (20h)........................................................................................................25

7.2

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W25X20CV

7.2.16 32KB Block Erase (52h)................................................................................................26

7.2.17 Block Erase (D8h).........................................................................................................27

7.2.18 Chip Erase (C7h or 60h)...............................................................................................28

7.2.19 Power-down (B9h) ........................................................................................................29

7.2.20 Release Power-down / Device ID (ABh) .......................................................................30

7.2.21 Read Manufacturer / Device ID (90h) ...........................................................................32

7.2.22 Read Manufacturer / Device ID Dual I/O (92h) .............................................................33

7.2.23 Read Unique ID Number (4Bh).....................................................................................34

7.2.24 JEDEC ID (9Fh)............................................................................................................35

ELECTRICAL CHARACTERISTICS......................................................................................... 36

8.

8.1

8.2

8.3

8.4

8.5

8.6

Absolute Maximum Rating............................................................................................ 36

Operating Ranges......................................................................................................... 36

Power-up Timing and Write Inhibit Threshold .............................................................. 37

DC Electrical Characteristics ........................................................................................ 38

AC Measurement Conditions........................................................................................ 39

AC Electrical Characteristics ........................................................................................ 40

AC Electrical Characteristics (cont’d)........................................................................................ 41

8.7

8.8

8.9

Serial Output Timing..................................................................................................... 42

Serial Input Timing........................................................................................................ 42

HOLD Timing ................................................................................................................ 42

8.10 WP Timing .................................................................................................................... 42

PACKAGE SPECIFICATION.................................................................................................... 43

9.

9.1

9.2

9.3

9.4

8-Pin SOIC 150-mil (Package Code SN)...................................................................... 43

8-Pin SOIC 208-mil (Package Code SS)...................................................................... 44

8-Pad WSON 6x5-mm (Package Code ZP) ................................................................. 45

8-Pad USON 2x3-mm (Package Code UX).................................................................. 47

10.

11.

ORDERING INFORMATION..................................................................................................... 48

10.1 Valid Part Numbers and Top Side Marking .................................................................. 49

REVISION HISTORY................................................................................................................ 50

Publication Release Date: September 10, 2012

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W25X20CV

1. GENERAL DESCRIPTION

The W25X20CV (2M-bit) Serial Flash memories provide a storage solution for systems with limited

space, pins and power. The 25X series offers flexibility and performance well beyond ordinary Serial

Flash devices. They are ideal for code download applications as well as storing voice, text and data.

The devices operate on a single 2.6V to 3.6V power supply with current consumption as low as 1mA

active and 1µA for power-down. All devices are offered in space-saving packages.

The W25X20CV arrays are organized into 1,024 programmable pages of 256-bytes each. Up to 256

bytes can be programmed at a time. The W25X20CV have 64 erasable sectors, 8 erasable 32KB

blocks and 4 erasable 64KB blocks respectively. The small 4KB sectors allow for greater flexibility in

applications that require data and parameter storage. (See figure 2.)

The W25X20CV support the standard Serial Peripheral Interface (SPI), and a high performance dual

output as well as Dual I/O SPI: Serial Clock, Chip Select, Serial Data DIO (I/O0), DO (I/O1). SPI

clock frequencies up to 80MHz are supported allowing equivalent clock rates of 160MHz when using

the Fast Read Dual Output instruction. These transfer rates are comparable to those of 8 and 16-bit

Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few

as 16-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place)

operation.

A Hold pin, Write Protect pin and programmable write protect, with top or bottom array control

features, provide further control flexibility. Additionally, the device supports JEDEC standard

manufacturer and device identification with a 64-bit Unique Serial Number.

2. FEATURES

 Family of Serial Flash Memories

– W25X20CV: 2M-bit/256K-byte (262,144)

– 256-bytes per programmable page

 Software and Hardware Write Protection

– Write-Protect all or portion of memory

– Enable/Disable protection with /WP pin

– Top or bottom array protection

– Uniform erasable 4KB, 32KB & 64KB regions.

 SPI with Single / Dual Outputs / I/O

– Standard SPI: CLK, /CS, DI, DO, /WP, /Hold

– Dual SPI: CLK, /CS, IO0, IO1, /WP, /Hold

 Flexible Architecture with 4KB sectors

– Uniform Sector/Block Erase (4/32/64-kbytes)

– Page program up to 256 bytes <1ms

– More than 100,000 erase/write cycles⁽¹⁾

– More than 20-year data retention

 Data Transfer up to 160M-bits / second

– Clock operation to 80MHz

– 160MHz equivalent Dual I/O SPI

– Auto-increment Read capability

 Low Power, Wide Temperature Range

– Single 2.6V to 3.6V supply

– 1mA active current, <1µA Power-down(typ.)

– -40°C to +80/105°C operating range

 Efficient “Continuous Read Mode”

– Low Instruction overhead

– Continuous Read

– As few as 16 clocks to address memory

– Allows true XIP (execute in place) operation

 Space Efficient Packaging

– 8-pin SOIC 150/208-mil

– 8-pad WSON 6x5-mm

– 8-pad USON 2x3-mm

Note: 1. More than 100,000 Block Erase/Program cycles for Industrial and Automotive temperature; more than

10,000 full chip Erase/Program cycles tested in compliance with AEC-Q100.

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W25X20CV

3. PIN CONFIGURATION SOIC 150 / 208-MIL

Figure 1a. W25X20CV Pin Assignments, 8-pin SOIC 150 / 208-mil (Package Code SN, SS)

4. PAD CONFIGURATION WSON 6X5-MM AND USON 2X3-MM

Figure 1b. W25X20CV Pad Assignments, 8-pad WSON 6x8-mm and USON 2x3-mm (Package Code ZP, UX)

5. PIN DESCRIPTION SOIC, WSON 6X5-MM AND USON 2X3-MM

PIN NO.

PIN NAME

/CS

I/O

FUNCTION

1

2

3

4

5

6

7

8

I

I/O

I

Chip Select Input

Data Input / Output⁽¹⁾

Write Protect Input

Ground

Data Input / Output⁽¹⁾

Serial Clock Input

Hold Input

DO (IO1)

/WP

GND

DI (IO0)

CLK

I/O

I

/HOLD

VCC

Power Supply

Note:

1 IO0 and IO1 are used for Standard and Dual SPI instructions

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W25X20CV

5.1

Package Types

W25X20CV is offered in 8-pin plastic 150/208-mil width SOIC (package code SN, SS), 8-pad 6x5-mm

WSON (package code ZP) and 2x3-mm USON (package code UX). Refer to see figures 1a and 1b,

respectively.

5.2 Chip Select (/CS)

The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is

deselected and the Serial Data Output (DO, or IO0, IO1) pins are at high impedance. When

deselected, the devices power consumption will be at standby levels unless an internal erase,

program or write status register cycle is in progress. When /CS is brought low the device will be

selected, power consumption will increase to active levels and instructions can be written to and data

read from the device. After power-up, /CS must transition from high to low before a new instruction will

be accepted. The /CS input must track the VCC supply level at power-up (see “Power-up Timing and

Write inhibit threshold” and Figure 26). If needed, a pull-up resister on /CS can be used to accomplish

this.

5.3 Serial Data Input, Output and IOs (DIO, DO, IO0 and IO1)

The W25X20CV support standard SPI and Dual SPI operation. Standard SPI instructions use the

unidirectional DI (input) pin to serially write instructions, addresses or data to the device on the rising

edge of the Serial Clock (CLK) input pin. Standard SPI also uses the unidirectional DO (output) to read

data or status from the device on the falling edge of CLK.

Dual SPI instructions use the bidirectional IO pins to serially write instructions, addresses or data to the

device on the rising edge of CLK and read data or status from the device on the falling edge of CLK.

5.4 Write Protect (/WP)

The Write Protect (/WP) pin can be used to prevent the Status Register from being written. Used in

conjunction with the Status Register’s Block Protect (TB, BP1 and BP0) bits and Status Register

Protect (SRP) bit, a portion or the entire memory array can be hardware protected. The /WP pin is

active low.

5.5 HOLD (/HOLD)

The Hold (/HOLD) pin allows the device to be paused while it is actively selected. When /HOLD is

brought low, while /CS is low, the DO pin will be at high impedance and signals on the DIO and CLK

pins will be ignored (don’t care). When /HOLD is brought high, device operation can resume. The

/HOLD function can be useful when multiple devices are sharing the same SPI signals.

5.6 Serial Clock (CLK)

The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations.

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W25X20CV

6. BLOCK DIAGRAM

Figure 2. W25X20CV Serial Flash Memory Block Diagram

Publication Release Date: September 10, 2012

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W25X20CV

6.1 SPI OPERATIONS

6.1.1 Standard SPI Instructions

The W25X20CV are accessed through an SPI compatible bus consisting of four signals: Serial Clock

(CLK), Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI

instructions use the DI input pin to serially write instructions, addresses or data to the device on the

rising edge of CLK. The DO output pin is used to read data or status from the device on the falling

edge CLK.

SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0

and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and

data is not being transferred to the Serial Flash. For Mode 0 the CLK signal is normally low on the

falling and rising edges of /CS. For Mode 3 the CLK signal is normally high on the falling and rising

edges of /CS.

6.1.2 Dual SPI Instructions

The W25X20CV support Dual SPI operation when using the “Fast Read Dual Output (3Bh)” and “Fast

Read Dual I/O (BBh)” instructions. These instructions allow data to be transferred to or from the device

at two to three times the rate of ordinary Serial Flash devices. The Dual SPI Read instructions are

ideal for quickly downloading code to RAM upon power-up (code-shadowing) or for executing non-

speed-critical code directly from the SPI bus (XIP). When using Dual SPI instructions, the DI and DO

pins become bidirectional I/O pins: IO0 and IO1.

6.1.3 Hold Function

The /HOLD signal allows the W25X20CV operation to be paused while it is actively selected (when

/CS is low). The /HOLD function may be useful in cases where the SPI data and clock signals are

shared with other devices. For example, consider if the page buffer was only partially written when a

priority interrupt requires use of the SPI bus. In this case the /HOLD function can save the state of the

instruction and the data in the buffer so programming can resume where it left off once the bus is

available again.

To initiate a /HOLD condition, the device must be selected with /CS low. A /HOLD condition will

activate on the falling edge of the /HOLD signal if the CLK signal is already low. If the CLK is not

already low the /HOLD condition will activate after the next falling edge of CLK. The /HOLD condition

will terminate on the rising edge of the /HOLD signal if the CLK signal is already low. If the CLK is not

already low the /HOLD condition will terminate after the next falling edge of CLK.

During a /HOLD condition, the Serial Data Output (DO) is high impedance, and Serial Data

Input/Output (DIO) and Serial Clock (CLK) are ignored. The Chip Select (/CS) signal should be kept

active (low) for the full duration of the /HOLD operation to avoid resetting the internal logic state of the

device.

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W25X20CV

6.2 WRITE PROTECTION

Applications that use non-volatile memory must take into consideration the possibility of noise and

other adverse system conditions that may compromise data integrity. To address this concern, the

W25X20CV provide several means to protect data from inadvertent writes.

6.2.1 Write Protect Features



Device resets when VCC is below threshold.

Time delay write disable after Power-up.

Write enable/disable instructions.

Automatic write disable after program and erase.

Software and Hardware (/WP pin) write protection using Status Register.

Write Protection using Power-down instruction.

Upon power-up or at power-down, the W25X20CV will maintain a reset condition while VCC is below

the threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 26). While reset, all

operations are disabled and no instructions are recognized. During power-up and after the VCC

voltage exceeds VWI, all program and erase related instructions are further disabled for a time delay of

tPUW. This includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the

Write Status Register instructions. Note that the chip select pin (/CS) must track the VCC supply level

at power-up until the VCC-min level and tVSL time delay is reached. If needed, a pull-up resister on

/CS can be used to accomplish this.

After power-up the device is automatically placed in a write-disabled state with the Status Register

Write Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page

Program, Sector Erase, Chip Erase or Write Status Register instruction will be accepted. After

completing a program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared

to a write-disabled state of 0.

Software controlled write protection is facilitated using the Write Status Register instruction and setting

the Status Register Protect (SRP) and Block Protect (TB, BP1 and BP0) bits. These allow a portion

small as 4KB sector or the entire memory array to be configured as read only. Used in conjunction

with the Write Protect (/WP) pin, changes to the Status Register can be enabled or disabled under

hardware control. See Status Register for further information. Additionally, the Power-down instruction

offers an extra level of write protection as all instructions are ignored except for the Release Power-

down instruction.

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W25X20CV

7.

CONTROL AND STATUS REGISTERS

The Read Status Register instruction can be used to provide status on the availability of the Flash

memory array, if the device is write enabled or disabled, and the state of write protection. The Write

Status Register instruction can be used to configure the device write protection features.

7.1 STATUS REGISTER

7.1.1 BUSY

BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing

a Page Program, Sector Erase, Block Erase, Chip Erase or Write Status Register instruction. During

this time the device will ignore further instructions except for the Read Status Register instruction (see

tW, tPP, tSE, tBE, and tCE in AC Characteristics). When the program, erase or write status register

instruction has completed, the BUSY bit will be cleared to a 0 state indicating the device is ready for

further instructions.

7.1.2 Write Enable Latch (WEL)

Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to a 1 after executing

a Write Enable Instruction. The WEL status bit is cleared to a 0 when the device is write disabled. A

write disable state occurs upon power-up or after any of the following instructions finished: Write

Disable, Page Program, Sector Erase, Block Erase, Chip Erase and Write Status Register.

7.1.3 Block Protect Bits (BP1, BP0)

The Block Protect Bits (BP1 and BP0) are non-volatile read/write bits in the status register (S3 and S2)

that provide Write Protection control and status. Block Protect bits can be set using the Write Status

Register Instruction (see tW in AC characteristics). All, none or a portion of the memory array can be

protected from Program and Erase instructions (see Status Register Memory Protection table). The

factory default setting for the Block Protection Bits is 0, none of the array protected. The Block Protect

bits cannot be written to if the Status Register Protect (SRP) bit is set to 1 and the Write Protect (/WP)

pin is low.

7.1.4 Top/Bottom Block Protect (TB)

The Top/Bottom bit (TB) controls if the Block Protect Bits (BP1, BP0) protect from the Top (TB=0) or

the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The TB bit is

non-volatile and the factory default setting is TB=0. The TB bit can be set with the Write Status

Register Instruction provided that the Write Enable instruction has been issued. The TB bit cannot be

written to if the Status Register Protect (SRP) bit is set to 1 and the Write Protect (/WP) pin is low.

Publication Release Date: September 10, 2012

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W25X20CV

7.1.5 Reserved Bits

Status register bit location S6 and S4 are reserved for future use. Current devices will read 0 for this

bit location. It is recommended to mask out the reserved bit when testing the Status Register. Doing

this will ensure compatibility with future devices.

7.1.6 Status Register Protect (SRP)

The Status Register Protect (SRP) bit is a non-volatile read/write bit in status register (S7) that can be

used in conjunction with the Write Protect (/WP) pin to disable writes to status register. When the SRP

bit is set to a 0 state (factory default) the /WP pin has no control over status register. When the SRP

pin is set to a 1, the Write Status Register instruction is locked out while the /WP pin is low. When the

/WP pin is high the Write Status Register instruction is allowed.

Status

Register

SRP

/WP

Description

Software

Protection

/WP pin has no control, The Status register can be written to

after a Write Enable instruction WEL = 1. [Factory Default]

0

1

X

0

1

Hardware

Protected

When /WP pin is low the Status Register locked and can’t be

written to.

Hardware

When /WP pin is high the status register is unlocked and can

Unprotected be written to after a Write Enable instruction WEL = 1.

S7

S6

(R)

S5

TB

S4

(R)

SS3

SS2

SS1

SS0

SRP

BP1

BP0

WEL

BUSY

STATUS REGISTER PROTECT

(Non-volatile)

RESERVED

TOP/BOTTOM PROTECT

(Non-volatile)

BLOCK PROTECT BITS

(Non-volatile)

WRITE ENABLE LATCH

(volatile)

ERASE/WRITE IN PROGRESS

(volatile)

Figure 3. Status Register Bit Locations

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W25X20CV

7.1.7 Status Register Memory Protection

STATUS REGISTER⁽¹⁾

W25X20CV (2M-BIT) MEMORY PROTECTION

TB

x

0

1

x

BP1

0

1

0

BP0

0

1

0

1

BLOCK(S)

NONE

3

2 and 3

0

ADDRESSES

NONE

DENSITY

NONE

64KB

128KB

64KB

PORTION

NONE

030000h - 03FFFFh

020000h - 03FFFFh

000000h - 00FFFFh

000000h - 01FFFFh

000000h - 03FFFFh

Upper 1/4

Upper 1/2

Lower 1/4

Lower 1/2

ALL

1

0

1

0 and 1

0 thru 3

128KB

256KB

Note:

1. x = don’t care

2. If any erase or program command specifies a memory region that contains protected data portion, this

command will be ignore.

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W25X20CV

7.2 INSTRUCTIONS

The instruction set of the W25X20CV consists of twenty basic instructions that are fully controlled

through the SPI bus (see Instruction Set table). Instructions are initiated with the falling edge of Chip

Select (/CS). The first byte of data clocked into the DIO input provides the instruction code. Data on

the DIO input is sampled on the rising edge of clock with most significant bit (MSB) first.

Instructions vary in length from a single byte to several bytes and may be followed by address bytes,

data bytes, dummy bytes (don’t care), and in some cases, a combination. Instructions are completed

with the rising edge of edge /CS. Clock relative timing diagrams for each instruction are included in

figures 4 through 25. All read instructions can be completed after any clocked bit. However, all

instructions that Write, Program or Erase must complete on a byte boundary (CS driven high after a

full 8-bits have been clocked) otherwise the instruction will be terminated. This feature further protects

the device from inadvertent writes. Additionally, while the memory is being programmed or erased, or

when the Status Register is being written, all instructions except for Read Status Register will be

ignored until the program or erase cycle has completed.

7.2.1 Manufacturer and Device Identification

MANUFACTURER ID

(M7-M0)

Winbond Serial Flash

EFh

(ID15-ID0)

9Fh

Device ID

(ID7-ID0)

ABh, 90h, 92h

11h

Instruction

W25X20CV

3012h

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W25X20CV

7.2.2 Instruction Set ⁽¹⁾

INSTRUCTION

NAME

BYTE 1 BYTE 2

(CODE)

BYTE 3

BYTE 4

BYTE 5

BYTE 6

N-BYTES

Write Enable

06h

Write Enable for

Volatile Status

Register

50h

Write Disable

04h

05h

01h

03h

(2)

Read Status Register

Write Status Register

Read Data

(S7–S0)⁽¹⁾

(S7–S0)

A23–A16

A15–A8

A7–A0

(D7–D0)

(Next byte)

continuous

(Next Byte)

continuous

(one byte per

4 clocks,

Fast Read

0Bh

A23–A16

dummy

(D7–D0)

Fast Read Dual

Output

3Bh

A23–A16

A15–A8

A7–A0

dummy

(D7-D0, …)⁽⁵⁾

continuous)

A7-A0, M7-

M0⁽⁶⁾

Fast Read Dual I/O

Page Program

BBh

02h

A23-A8⁽⁶⁾

(D7-D0, …)⁽⁵⁾

A7–A0

Up to 256

bytes

A23–A16

A15–A8

(D7–D0)

(Next byte)

Sector Erase (4KB)

Block Erase (32KB)

Block Erase (64KB)

Chip Erase

20h

52h

A23–A16

A15–A8

A7–A0

D8h

C7h/60h

B9h

Power-down

Release Power-down

/ Device ID

ABh

90h

dummy

00h

(ID7-ID0)⁽⁴⁾

(M7-M0)

Manufacturer/

Device ID ⁽³⁾

(ID7-ID0)

Manufacturer/Device

ID by Dual I/O

A7-A0,

M[7:0]

(MF[7:0],

ID[7:0])

92h

A23-A8

(ID15-ID8)

Memory

Type

(M7-M0)

(ID7-ID0)

Capacity

JEDEC ID

9Fh

4Bh

Manufacturer

Read Unique ID

dummy

(ID63-ID0)

Notes:

1

Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read from

the device on the DO pin.

2

3

4

5

The Status Register contents will repeat continuously until /CS terminates the instruction.

See Manufacturer and Device Identification table for Device ID information.

The Device ID will repeat continuously until /CS terminates the instruction.

Dual Output and Dual I/O data

IO0 = (D6, D4, D2, D0)

IO1 = (D7, D5, D3, D1)

6

Dual Input Address

IO0 = A22, A20, A18, A16, A14, A12, A10, A8 A6, A4, A2, A0, M6, M4, M2, M0

IO1 = A23, A21, A19, A17, A15, A13, A11, A9 A7, A5, A3, A1, M7, M5, M3, M1

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W25X20CV

7.2.3 Write Enable (06h)

The Write Enable instruction (Figure 4) sets the Write Enable Latch (WEL) bit in the Status Register to

a 1. The WEL bit must be set prior to every Page Program, Sector Erase, Block Erase, Chip Erase

and Write Status Register instruction. The Write Enable instruction is entered by driving /CS low,

shifting the instruction code “06h” into the Data Input (DI) pin on the rising edge of CLK, and then

driving /CS high.

/CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

Mode 3

Mode 0

CLK

Instruction (06h)

High Impedance

DI

(IO₀)

DO

(IO₁)

Figure 4. Write Enable Instruction Sequence Diagram

7.2.4 Write Enable for Volatile Status Register (50h)

The non-volatile Status Register bits described in section 8.1 can also be written to as volatile bits.

This gives more flexibility to change the system configuration and memory protection schemes quickly

without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status

Register non-volatile bits. To write the volatile values into the Status Register bits, the Write Enable for

Volatile Status Register (50h) instruction must be issued prior to a Write Status Register (01h)

instruction. Write Enable for Volatile Status Register instruction (Figure 5) will not set the Write Enable

Latch (WEL) bit, it is only valid for the Write Status Register instruction to change the volatile Status

Register bit values.

Instruction (50h)

Figure 5. Write Enable for Volatile Status Register Instruction Sequence Diagram

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7.2.5 Write Disable (04h)

The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register

to a 0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h”

into the DIO pin and then driving /CS high. WEL bit is automatically reset after Power-up and upon

completion of the Write Status Register, Page Program, Sector Erase, Block Erase and Chip Erase

instructions. Write Disable instruction can also be used to invalidate the Write Enable for Volatile

Status Register instruction

/CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

Mode 3

Mode 0

CLK

Instruction (04h)

High Impedance

DI

(IO₀)

DO

(IO₁)

Figure 6. Write Disable Instruction Sequence Diagram

7.2.6 Read Status Register (05h)

The Read Status Register instruction allows the 8-bit Status Register to be read. The instruction is

entered by driving /CS low and shifting the instruction code “05h” into the DIO pin on the rising edge of

CLK. The status register bits are then shifted out on the DO pin at the falling edge of CLK with most

significant bit (MSB) first as shown in figure 6. The Status Register bits are shown in figure 3 and

include the BUSY, WEL, BP1, BP0, TB and SRP bits (see description of the Status Register earlier in

this datasheet).

The Status Register instruction may be used at any time, even while a Program, Erase or Write Status

Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the

cycle is complete and if the device can accept another instruction. The Status Register can be read

continuously, as shown in Figure 7. The instruction is completed by driving /CS high.

Figure 7. Read Status Register Instruction Sequence Diagram

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7.2.7 Write Status Register (01h)

The Write Status Register instruction allows the Status Register to be written. A Write Enable

instruction must previously have been executed for the device to accept the Write Status Register

Instruction (Status Register bit WEL must equal 1). Once write enabled, the instruction is entered by

driving /CS low, sending the instruction code “01h”, and then writing the status register data byte as

illustrated in figure 8. The Status Register bits are shown in figure 3 and described earlier in this

datasheet.

Only non-volatile Status Register bits SRP, TB, BP1 and BP0 (bits 7, 5, 3 and 2) can be written to. All

other Status Register bit locations are read-only and will not be affected by the Write Status Register

instruction.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not

done the Write Status Register instruction will not be executed. After /CS is driven high, the self-timed

Write Status Register cycle will commence for a time duration of tW (See AC Characteristics). While

the Write Status Register cycle is in progress, the Read Status Register instruction may still accessed

to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle and a

0 when the cycle is finished and ready to accept other instructions again. After the Write Register

cycle has finished the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.

The Write Status Register instruction allows the Block Protect bits (TB, BP1 and BP0) to be set for

protecting all, a portion, or none of the memory from erase and program instructions. Protected areas

become read-only (see Status Register Memory Protection table). The Write Status Register

instruction also allows the Status Register Protect bit (SRP) to be set. This bit is used in conjunction

with the Write Protect (/WP) pin to disable writes to the status register. When the SRP bit is set to a 0

state (factory default) the /WP pin has no control over the status register. When the SRP pin is set to a

1, the Write Status Register instruction is locked out while the /WP pin is low. When the /WP pin is

high the Write Status Register instruction is allowed.

During volatile Status Register write operation (50h combined with 01h), after /CS is driven high, the

Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC

Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.

Figure 8. Write Status Register Instruction Sequence Diagram

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7.2.8 Read Data (03h)

The Read Data instruction allows one or more data bytes to be sequentially read from the memory.

The instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h”

followed by a 24-bit address (A23-A0) into the DI pin. The code and address bits are latched on the

rising edge of the CLK pin. After the address is received, the data byte of the addressed memory

location will be shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first.

The address is automatically incremented to the next higher address after each byte of data is shifted

out allowing for a continuous stream of data. This means that the entire memory can be accessed with

a single instruction as long as the clock continues. The instruction is completed by driving /CS high.

The Read Data instruction sequence is shown in figure 9. If a Read Data instruction is issued while an

Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any

effects on the current cycle. The Read Data instruction allows clock rates from D.C. to a maximum of

fR (see AC Electrical Characteristics).

/CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31 32 33 34 35 36 37 38 39

CLK

Instruction (03h)

24-Bit Address

DI

(IO₀)

23 22 21

3

2

1

0

*

Data Out 1

High Impedance

DO

(IO₁)

7

6

5

4

3

2

1

0

7

= MSB

*

Figure 9. Read Data Instruction Sequence Diagram

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7.2.9 Fast Read (0Bh)

The Fast Read instruction is similar to the Read Data instruction except that it can operate at the

highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding

eight “dummy” clocks after the 24-bit address as shown in figure 10. The dummy clocks allow the

devices internal circuits additional time for setting up the initial address. During the dummy clocks the

data value on the DIO pin is a “don’t care”.

/CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

CLK

Instruction (0Bh)

24-Bit Address

DI

(IO₀)

23 22 21

3

2

1

0

*

High Impedance

DO

(IO₁)

= MSB

*

/CS

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

CLK

Dummy Clocks

DI

(IO₀)

0

Data Out 1

Data Out 2

High Impedance

DO

(IO₁)

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

*

Figure 10. Fast Read Instruction Sequence Diagram

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7.2.10 Fast Read Dual Output (3Bh)

The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction

except that data is output on two pins, IO₀and IO₁. This allows data to be transferred from the

W25X20CV at twice the rate of standard SPI devices. The Fast Read Dual Output instruction is ideal

for quickly downloading code from Flash to RAM upon power-up or for applications that cache code-

segments to RAM for execution.

Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest

possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight

“dummy” clocks after the 24-bit address as shown in figure 11. The dummy clocks allow the device's

internal circuits additional time for setting up the initial address. The input data during the dummy

clocks is “don’t care”. However, the IO₀pin should be high-impedance prior to the falling edge of the

first data out clock.

/CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

CLK

Instruction (3Bh)

24-Bit Address

DI

(IO₀)

23 22 21

3

2

1

0

*

High Impedance

DO

(IO₁)

= MSB

*

/CS

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

CLK

IO₀switches from

Dummy Clocks

Input to Output

DI

(IO₀)

0

6

4

2

0

6

4

5

2

3

0

1

6

4

5

2

3

0

1

6

4

5

2

3

0

1

6

7

High Impedance

DO

(IO₁)

7

5

3

1

7

Data Out 1

Data Out 2

Data Out 3

Data Out 4

*

Figure 11. Fast Read Dual Output Instruction Sequence Diagram

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7.2.11 Fast Read Dual I/O (BBh)

The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO

pins, IO₀and IO₁. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to

input the Address bits (A23-0) two bits per clock. This reduced instruction overhead may allow for

code execution (XIP) directly from the Dual SPI in some applications.

Fast Read Dual I/O with “Continuous Read Mode”

The Fast Read Dual I/O instruction can further reduce instruction overhead through setting the

“Continuous Read Mode” bits (M7-0) after the input Address bits (A23-0), as shown in figure 12a. The

upper nibble of the (M7-4) controls the length of the next Fast Read Dual I/O instruction through the

inclusion or exclusion of the first byte instruction code. The lower nibble bits of the (M3-0) are don’t

care (“x”). However, the IO pins should be high-impedance prior to the falling edge of the first data out

clock.

If the “Continuous Read Mode” bits M5-4 = (1,0), then the next Fast Read Dual I/O instruction (after

/CS is raised and then lowered) does not require the BBh instruction code, as shown in figure 12b.

This reduces the instruction sequence by eight clocks and allows the Read address to be immediately

entered after /CS is asserted low. If the “Continuous Read Mode” bits M5-4 do not equal to (1,0), the

next instruction (after /CS is raised and then lowered) requires the first byte instruction code, thus

returning to normal operation. A “Continuous Read Mode” Reset instruction can also be used to reset

(M7-0) before issuing normal instructions (See 9.2.12 for detail descriptions).

/CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

Instruction (BBh)

A23-16

A15-8

A7-0

M7-0

DI

(IO₀)

22 20 18 16 14 12 10

8

9

6

7

4

2

0

1

6

4

2

0

1

DO

(IO₁)

23 21 19 17 15 13 11

5

3

7

5

3

*

= MSB

*

/CS

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

CLK

IOs switch from

Input to Output

DI

(IO₀)

0

1

6

4

5

2

0

6

4

5

2

0

1

6

4

5

2

0

1

6

4

5

2

0

1

6

7

DO

(IO₁)

7

3

1

7

3

7

3

7

3

*

Byte 1

Byte 2

Byte 3

Byte 4

Figure 12a. Fast Read Dual I/O Instruction Sequence (Initial instruction or previous M5-4  10)

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/CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

CLK

A23-16

A15-8

A7-0

M7-0

DI

(IO₀)

22 20 18 16 14 12 10

8

9

6

7

4

2

0

1

6

4

2

0

1

DO

(IO₁)

23 21 19 17 15 13 11

5

3

7

5

3

*

= MSB

*

/CS

15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

CLK

IOs switch from

Input to Output

DI

(IO₀)

0

1

6

4

5

2

0

6

4

5

2

0

1

6

4

5

2

0

1

6

4

5

2

0

1

6

7

DO

(IO₁)

7

3

1

7

3

7

3

7

3

*

Byte 1

Byte 2

Byte 3

Byte 4

Figure 12b. Fast Read Dual I/O Instruction Sequence (Previous instruction set M5-4 = 10)

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7.2.12 Continuous Read Mode Bits (M7-0)

The “Continuous Read Mode” bits are used in conjunction with the “Fast Read Dual I/O” instruction to

provide the highest random Flash memory access rate with minimum SPI instruction overhead, thus

allow true XIP (execute in place) to be performed on serial flash devices.

M7-0 need to be set by the Dual I/O Read instruction. M5-4 are used to control whether the 8-bit SPI

instruction code BBh is needed or not for the next command. When M5-4 = (1,0), the next command

will be treated same as the current Dual I/O Read command without needing the 8-bit instruction code;

when M5-4 do not equal to (1,0), the device returns to normal SPI mode, all commands can be

accepted. M7-6 and M3-0 are reserved bits for future use, either 0 or 1 values can be used.

7.2.13 Continuous Read Mode Reset (FFFFh)

Continuous Read Mode Reset instruction can be used to set M4 = 1, thus the device will release the

Continuous Read Mode and return to normal SPI operation, as shown in figure 13.

Mode Bit Reset

for Dual I/O

/CS

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Mode 3

Mode 0

Mode 3

Mode 0

CLK

IO₀

FFFFh

Don’t Care

IO₁

Figure 13. Continuous Read Mode Reset for Fast Read Dual I/O

Since W25X20CV does not have a hardware Reset pin, so if the controller resets while W25X20CV

are set to Continuous Mode Read, the W25X20CV will not recognize any initial standard SPI

instructions from the controller. To address this possibility, it is recommended to issue a Continuous

Read Mode Reset instruction as the first instruction after a system Reset. Doing so will release the

device from the Continuous Read Mode and allow Standard SPI instructions to be recognized.

To reset “Continuous Read Mode” during Dual I/O operation, sixteen clocks are needed to shift in

instruction “FFFFh”.

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7.2.14 Page Program (02h)

The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed

at previously erased (FFh) memory locations. A Write Enable instruction must be executed before the

device will accept the Page Program Instruction (Status Register bit WEL = 1). The instruction is

initiated by driving the /CS pin low then shifting the instruction code “02h” followed by a 24-bit address

(A23-A0) and at least one data byte, into the DIO pin. The /CS pin must be held low for the entire

length of the instruction while data is being sent to the device.

If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address

bits) should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the

remaining page length, the addressing will wrap to the beginning of the page. In some cases, less

than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the

same page. One condition to perform a partial page program is that the number of clocks cannot

exceed the remaining page length. If more than 256 bytes are sent to the device the addressing will

wrap to the beginning of the page and overwrite previously sent data.

As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last

byte has been latched. If this is not done the Page Program instruction will not be executed. After /CS

is driven high, the self-timed Page Program instruction will commence for a time duration of tpp (See

AC Characteristics). While the Page Program cycle is in progress, the Read Status Register

instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during

the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept

other instructions again. After the Page Program cycle has finished the Write Enable Latch (WEL) bit

in the Status Register is cleared to 0. The Page Program instruction will not be executed if the

addressed page is protected by the Block Protect (BP1, and BP0) bits (see Status Register Memory

Protection table).

Figure 14. Page Program Instruction Sequence Diagram

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7.2.15 Sector Erase (20h)

The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state

of all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector

Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS

pin low and shifting the instruction code “20h” followed a 24-bit sector address (A23-A0) (see Figure 2).

The Sector Erase instruction sequence is shown in figure 15.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not

done the Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector

Erase instruction will commence for a time duration of tSE (See AC Characteristics). While the Sector

Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the

status of the BUSY bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the

cycle is finished and the device is ready to accept other instructions again. After the Sector Erase

cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Sector

Erase instruction will not be executed if the addressed page is protected by the Block Protect (TB,

BP1, and BP0) bits (see Status Register Memory Protection table).

/CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

29 30 31

Mode 3

Mode 0

CLK

Instruction (20h)

24-Bit Address

DI

(IO₀)

23 22

2

1

0

*

High Impedance

DO

(IO₁)

= MSB

*

Figure 15. Sector Erase Instruction Sequence Diagram

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7.2.16

32KB Block Erase (52h)

The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of

all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block

Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS

pin low and shifting the instruction code “52h” followed a 24-bit block address (A23-A0) (see Figure 2).

The Block Erase instruction sequence is shown in figure 16.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not

done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block

Erase instruction will commence for a time duration of tBE1 (See AC Characteristics). While the Block

Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the

status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the

cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle

has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase

instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP1, and

BP0) bits (see Status Register Memory Protection table).

/CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

29 30 31

Mode 3

Mode 0

CLK

Instruction (52h)

24-Bit Address

DI

(IO₀)

23 22

2

1

0

*

High Impedance

DO

(IO₁)

= MSB

*

Figure 16. 32KB Block Erase Instruction Sequence Diagram

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7.2.17 Block Erase (D8h)

The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of

all 1s (FFh). A Write Enable instruction must be executed before the device will accept the Block

Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS

pin low and shifting the instruction code “D8h” followed a 24-bit block address (A23-A0) (see Figure 2).

The Block Erase instruction sequence is shown in figure 17.

The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not

done the Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block

Erase instruction will commence for a time duration of tBE (See AC Characteristics). While the Block

Erase cycle is in progress, the Read Status Register instruction may still be accessed for checking the

status of the BUSY bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the

cycle is finished and the device is ready to accept other instructions again. After the Block Erase cycle

has finished the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase

instruction will not be executed if the addressed page is protected by the Block Protect (TB, BP1, and

BP0) bits (see Status Register Memory Protection table).

/CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

29 30 31

Mode 3

Mode 0

CLK

Instruction (D8h)

24-Bit Address

DI

(IO₀)

23 22

2

1

0

*

High Impedance

DO

(IO₁)

= MSB

*

Figure 17. Block Erase Instruction Sequence Diagram

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7.2.18 Chip Erase (C7h or 60h)

The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). A

Write Enable instruction must be executed before the device will accept the Chip Erase Instruction

(Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low and

shifting the instruction code “C7h” or “60h”. The Chip Erase instruction sequence is shown in figure 18.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip

Erase instruction will not be executed. After /CS is driven high, the self-timed Chip Erase instruction

will commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in

progress, the Read Status Register instruction may still be accessed to check the status of the BUSY

bit. The BUSY bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is

ready to accept other instructions again. After the Chip Erase cycle has finished the Write Enable

Latch (WEL) bit in the Status Register is cleared to 0. The Chip Erase instruction will not be executed

if any page is protected by the Block Protect (TB, BP1 and BP0) bits (see Status Register Memory

Protection table).

/CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

Mode 3

Mode 0

CLK

Instruction (C7h/60h)

High Impedance

DI

(IO₀)

DO

(IO₁)

Figure 18. Chip Erase Instruction Sequence Diagram

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7.2.19 Power-down (B9h)

Although the standby current during normal operation is relatively low, standby current can be further

reduced with the Power-down instruction. The lower power consumption makes the Power-down

instruction especially useful for battery powered applications (See ICC1 and ICC2 in AC

Characteristics). The instruction is initiated by driving the /CS pin low and shifting the instruction code

“B9h” as shown in figure 19.

The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Power-

down instruction will not be executed. After /CS is driven high, the power-down state will entered

within the time duration of tDP (See AC Characteristics). While in the power-down state only the

Release from Power-down / Device ID instruction, which restores the device to normal operation, will

be recognized. All other instructions are ignored. This includes the Read Status Register instruction,

which is always available during normal operation. Ignoring all but one instruction makes the Power

Down state a useful condition for securing maximum write protection. The device always powers-up in

the normal operation with the standby current of ICC1.

/CS

tDP

Mode 3

Mode 0

0

1

2

3

4

5

6

7

Mode 3

Mode 0

CLK

Instruction (B9h)

DI

(IO₀)

Stand-by current

Power-down current

Figure 19. Deep Power-down Instruction Sequence Diagram

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7.2.20 Release Power-down / Device ID (ABh)

The Release from Power-down / Device ID instruction is a multi-purpose instruction. It can be used to

release the device from the power-down state, obtain the devices electronic identification (ID) number

or do both.

To release the device from the power-down state, the instruction is issued by driving the /CS pin low,

shifting the instruction code “ABh” and driving /CS high as shown in figure 20. Release from power-

down will take the time duration of tRES1 (See AC Characteristics) before the device will resume

normal operation and other instructions are accepted. The /CS pin must remain high during the tRES1

time duration.

When used only to obtain the Device ID while not in the power-down state, the instruction is initiated

by driving the /CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The

Device ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first as

shown in figure 20. The Device ID values for the W25X20CV are listed in Manufacturer and Device

Identification table. The Device ID can be read continuously. The instruction is completed by driving

/CS high.

When used to release the device from the power-down state and obtain the Device ID, the instruction

is the same as previously described, and shown in figure 21, except that after /CS is driven high it

must remain high for a time duration of tRES2 (See AC Characteristics). After this time duration the

device will resume normal operation and other instructions will be accepted.

If the Release from Power-down / Device ID instruction is issued while an Erase, Program or Write

cycle is in process (when BUSY equals 1) the instruction is ignored and will not have any effects on

the current cycle

/CS

tRES1

Mode 3

Mode 0

0

1

2

3

4

5

6

7

Mode 3

Mode 0

CLK

Instruction (ABh)

DI

(IO₀)

Power-down current

Stand-by current

Figure 20. Release Power-down Instruction Sequence

Publication Release Date: September 10, 2012

Revision A

- 30 -

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

/CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

29 30 31 32 33 34 35 36 37 38

Mode 3

Mode 0

tRES2

CLK

Instruction (ABh)

3 Dummy Bytes

DI

(IO₀)

23 22

2

1

0

Device ID

*

High Impedance

DO

(IO₁)

7

6

5

4

3

2

1

0

*

= MSB

Power-down current

Stand-by current

*

Figure 21. Release Power-down / Device ID Instruction Sequence Diagram

Publication Release Date: September 10, 2012

Revision A

- 31 -

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

7.2.21 Read Manufacturer / Device ID (90h)

The Read Manufacturer/Device ID instruction is an alternative to the Release from Power-down/

Device ID instruction that provides both JEDEC assigned manufacturer ID and the specific device ID.

The Read Manufacturer/Device ID instruction is very similar to the Release from Power-down / Device

ID instruction. The instruction is initiated by driving the /CS pin low and shifting the instruction code

“90h” followed by a 24-bit address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond

(EFh) and the Device ID are shifted out on the falling edge of CLK with most significant bit (MSB) first

as shown in figure 22. The Device ID values for the W25X20CV are listed in Manufacturer and Device

Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read first and

then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read continuously,

alternating from one to the other. The instruction is completed by driving /CS high.

/CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10

28 29 30 31

CLK

Instruction (90h)

Address (000000h)

DI

(IO₀)

23 22 21

3

2

1

0

*

High Impedance

DO

(IO₁)

= MSB

*

/CS

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Mode 3

Mode 0

CLK

DI

(IO₀)

0

DO

(IO₁)

7

6

5

4

3

2

1

0

Manufacturer ID (EFh)

Device ID

*

Figure 22. Read Manufacturer / Device ID Diagram

Publication Release Date: September 10, 2012

Revision A

- 32 -

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

7.2.22 Read Manufacturer / Device ID Dual I/O (92h)

The Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer/Device

ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 2x

speed.

The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction.

The instruction is initiated by driving the /CS pin low and shifting the instruction code “92h” followed by

a 24-bit address (A23-A0) of 000000h, 8-bit Continuous Read Mode Bits, with the capability to input

the Address bits two bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the

Device ID are shifted out 2 bits per clock on the falling edge of CLK with most significant bits (MSB)

first as shown in figure 28. The Device ID values for the W25X20CV are listed in Manufacturer and

Device Identification table. If the 24-bit address is initially set to 000001h the Device ID will be read

first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read

continuously, alternating from one to the other. The instruction is completed by driving /CS high.

/CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

A23-16

A15-8

A7-0 (00h)

M7-0

Instruction (92h)

High Impedance

DI

(IO₀)

6

4

2

0

1

6

4

2

0

1

6

4

2

0

1

6

4

2

0

1

DO

(IO₁)

7

5

3

7

5

3

7

5

3

7

5

3

= MSB

*

/CS

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Mode 3

Mode 0

CLK

IOs switch from

Input to Output

DI

(IO₀)

0

1

6

4

5

2

0

6

4

5

2

3

0

1

6

4

5

2

3

0

1

6

4

5

2

3

0

1

DO

(IO₁)

7

3

1

7

MFR ID

(repeat)

Device ID

(repeat)

*

MFR ID

Device ID

Figure 23. Read Manufacturer / Device ID Dual I/O Diagram

“Continuous Read Mode” bits M7-0 must be set to FXh to be compatible with Fast Read Dual I/O instruction.

Note:

1.

Publication Release Date: September 10, 2012

Revision A

- 33 -

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

7.2.23 Read Unique ID Number (4Bh)

The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique

to each W25X20CV device. The ID number can be used in conjunction with user software methods to

help prevent copying or cloning of a system. The Read Unique ID instruction is initiated by driving the

/CS pin low and shifting the instruction code “4Bh” followed by a four bytes of dummy clocks. After

which, the 64-bit ID is shifted out on the falling edge of CLK as shown in figure 24.

/CS

Mode 3

Mode 0

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

CLK

Instruction (4Bh)

Dummy Byte 1

Dummy Byte 2

DI

(IO₀)

High Impedance

DO

(IO₁)

/CS

23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Mode 3

Mode 0

CLK

Dummy Byte 3

Dummy Byte 4

DI

(IO₀)

High Impedance

DO

(IO₁)

63 62 61

2

1

0

= MSB

64-bit Unique Serial Number

*

Figure 24. Read Unique ID Number Instruction Sequence

Publication Release Date: September 10, 2012

Revision A

- 34 -

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

7.2.24 JEDEC ID (9Fh)

For compatibility reasons, the W25X20CV provide several instructions to electronically determine the

identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI

compatible serial memories that was adopted in 2003.

The instruction is initiated by driving the /CS pin low and shifting the instruction code “9Fh”. The

JEDEC assigned Manufacturer ID byte for Winbond (EFh) and two Device ID bytes, Memory Type

(ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling edge of CLK with most significant

bit (MSB) first as shown in figure 25. For memory type and capacity values refer to Manufacturer and

Device Identification table.

Figure 25. Read JEDEC ID

Publication Release Date: September 10, 2012

- 35 -

Revision A

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

8. ELECTRICAL CHARACTERISTICS

(1)

8.1 Absolute Maximum Rating

PARAMETERS

SYMBOL

VCC

CONDITIONS

RANGE

UNIT

Supply Voltage

–0.6 to +4.6

V

Voltage Applied to Any Pin

VIO

Relative to Ground

–0.6 to VCC +0.4

<20nS Transient

Relative to Ground

Transient Voltage on any Pin

VIOT

–2.0V to VCC+2.0V

V

Storage Temperature

Lead Temperature

Electrostatic Discharge Voltage

Notes:

TSTG

TLEAD

VESD

–65 to +150

°C

V

See Note ⁽²⁾

Human Body Model⁽³⁾–2000 to +2000

1. This device has been designed and tested for the specified operation ranges. Proper operation outside of these levels is not

guaranteed. Exposure to absolute maximum ratings may affect device reliability. Exposure beyond absolute maximum ratings

may cause permanent damage.

2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the European directive

on restrictions on hazardous substances (RoHS) 2002/95/EU.

3. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 ohms, R2=500 ohms).

8.2 Operating Ranges

SPEC

PARAMETER

SYMBOL CONDITIONS

UNIT

MIN

MAX

Supply Voltage

VCC

TA

F_R= 80MHz, fR = 33MHz

2.6

3.6

V

Industrial Grade Plus⁽¹⁾

Automotive Grade 3⁽¹⁾

Automotive Grade 2⁽¹⁾

-40

+105

+85

Ambient Temperature,

Operating

°C

+105

Note:

1. Please contact Winbond for more information and availability.

Publication Release Date: September 10, 2012

Revision A

- 36 -

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

8.3 Power-up Timing and Write Inhibit Threshold

SPEC

PARAMETER

SYMBOL

UNIT

MIN

10

5

MAX

VCC (min) to /CS Low

tVSL⁽¹⁾

tPUW⁽¹⁾

VWI⁽¹⁾

µs

ms

V

Time Delay Before Write Instruction

Write Inhibit Threshold Voltage

1.0

2.0

Note:

1. These parameters are characterized only.

Figure 26a. Power-up Timing and Voltage Levels

Figure 26b. /CS must track VCC

Publication Release Date: September 10, 2012

Revision A

- 37 -

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

8.4 DC Electrical Characteristics

SPEC

PARAMETER

SYMBOL CONDITIONS

CIN⁽¹⁾

VIN = 0V⁽²⁾

UNIT

MIN

TYP

MAX

6

Input Capacitance

Output Capacitance

Input Leakage

pF

µA

Cout⁽¹⁾VOUT = 0V⁽²⁾

8

ILI

±2

I/O Leakage

ILO

/CS = VCC,

VIN = GND or VCC

Standby Current

ICC1

10

1

50

5

µA

/CS = VCC,

VIN = GND or VCC

Power-down Current

ICC2

ICC3

Current Read Data /

Dual Output 1MHz⁽²⁾

C = 0.1 VCC / 0.9 VCC

DO = Open

1/3

4/5

5/6

6/7

4/8

mA

Current Read Data /

Dual Output 33MHz⁽²⁾

C = 0.1 VCC / 0.9 VCC

DO = Open

8/10

10/12

12/14

Current Read Data /

Dual Output 80MHz⁽²⁾

C = 0.1 VCC / 0.9 VCC

DO = Open

Current Read Data /

Dual Output 80MHz⁽²⁾

C = 0.1 VCC / 0.9 VCC

DO = Open

Current Write Status

Register

ICC4

ICC5

ICC6

/CS = VCC

8

12

15

mA

Current Page Program

10

Current Sector/Block

Erase

Current Chip Erase

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Notes:

ICC7

VIL

15

mA

V

–0.5

VCCx0.3

VIH

VCCx0.7

V

VOL

VOH

IOL = 100 µA

0.4

V

IOH = –100 µA

VCC–0.2

V

1. Tested on sample basis and specified through design and characterization data. TA=25°C, VCC=3.0V.

2. Checker Board Pattern.

Publication Release Date: September 10, 2012

Revision A

- 38 -

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

8.5 AC Measurement Conditions

SPEC

PARAMETER

SYMBOL

UNIT

MAX

MIN

Load Capacitance

CL

TR, TF

VIN

30

5

pF

ns

V

Input Rise and Fall Times

Input Pulse Voltages

0.1 VCC to 0.9 VCC

0.3 VCC to 0.7 VCC

0.5 VCC to 0.5 VCC

Input Timing Reference Voltages

Output Timing Reference Voltages

IN

V

OUT

V

Note:

1. Output Hi-Z is defined as the point where data out is no longer driven.

Input Levels

0.9 VCC

Input and Output Timing

Reference Levels

0.5 VCC

0.1 VCC

Figure 27. AC Measurement I/O Waveform

Publication Release Date: September 10, 2012

Revision A

- 39 -

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

8.6 AC Electrical Characteristics

SPEC

DESCRIPTION

SYMBOL ALT

UNIT

MIN

TYP

MAX

Clock frequency for all instructions,

except Read Data (03h)

2.6V-3.6V VCC

F_R

f_c

D.C.

80

MHz

Clock freq. Read Data instruction 03h

2.6V-3.6V VCC

f_R

D.C.

6

33

MHz

ns

Clock High, Low Time, for Fast Read (0Bh, 3Bh) /

other instructions except Read Data (03h)

tCLH,

tCLL

(1)

Clock High, Low Time for Read Data (03h)

instruction

tCRLH,

6

ns

(1)

tCRLL

tCLCH

tCHCL

(2)

Clock Rise Time peak to peak

Clock Fall Time peak to peak

/CS Active Setup Time relative to CLK

/CS Not Active Hold Time relative to CLK

Data In Setup Time

0.1

5

V/ns

ns

tSLCH

tCHSL

tDVCH

tCHDX

tCHSH

tSHCH

tSHSL1

tCSS

5

ns

tDSU

tDH

2

ns

Data In Hold Time

5

ns

/CS Active Hold Time relative to CLK

/CS Not Active Setup Time relative to CLK

5

ns

5

ns

/CS Deselect Time (for Array Read  Array

Read)

tCSH

50

ns

/CS Deselect Time (for Erase/Program  Read

SR) Volatile Status Register Write Time

tSHSL2

100

50

ns

(2)

Output Disable Time

tSHQZ

tDIS

tV1

tV2

7

8

ns

Clock Low to Output Valid

tCLQV1

tCLQV2

Clock Low to Output Valid (for Read ID instructions)

Continued – next page

Publication Release Date: September 10, 2012

Revision A

- 40 -

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

AC Electrical Characteristics (cont’d)

SPEC

DESCRIPTION

SYMBOL ALT

UNIT

MIN

0

TYP

MAX

Output Hold Time

tCLQX

tHLCH

tCHHH

tHHCH

tCHHL

tHO

ns

µs

/HOLD Active Setup Time relative to CLK

/HOLD Active Hold Time relative to CLK

/HOLD Not Active Setup Time relative to CLK

/HOLD Not Active Hold Time relative to CLK

/HOLD to Output Low-Z

5

(2)

tHHQX

tLZ

7

(2)

/HOLD to Output High-Z

tHLQZ

tWHSL

tSHWL

tHZ

12

(3)

Write Protect Setup Time Before /CS Low

Write Protect Hold Time After /CS High

/CS High to Power-down Mode

20

100

(2)

tDP

3

/CS High to Standby Mode without Electronic

Signature Read

tRES1⁽²⁾

tRES2⁽²⁾

/CS High to Standby Mode with Electronic

Signature Read

1.8

µs

Write Status Register Time

Byte Program Time (First Byte) ⁽⁴⁾

Additional Byte Program Time (After First Byte) ⁽⁴⁾

Page Program Time

tW

t_BP1

t_BP2

tPP

tSE

10

15

30

ms

µs

ms

s

2.5

0.4

30

5

3

Sector Erase Time (4KB)

300

800

1,000

2

Block Erase Time (32KB)

tBE

120

150

0.5

1

Block Erase Time (64KB)

tBE

2

Chip Erase Time

tCE

Notes:

1.

2.

3.

4.

Clock high + Clock low must be less than or equal to 1/fC.

Value guaranteed by design and/or characterization, not 100% tested in production.

Only applicable as a constraint for a Write Status Register instruction when SRP is set to 1.

For multiple bytes after first byte within a page, t_BPN= t_{BP1 +}t_{BP2 * N}(typical) and t_BPN= t_{BP1 +}t_{BP2 * N}(max), where N = number

of bytes programmed.

Publication Release Date: September 10, 2012

- 41 -

Revision A

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

8.7 Serial Output Timing

/CS

tCLH

CLK

tCLQV

tCLQX

tCLQV

tCLL

tSHQZ

tCLQX

IO

output

MSB OUT

LSB OUT

8.8 Serial Input Timing

/CS

tSHSL

tSHCH

tCHSL

tSLCH

tCHSH

CLK

tDVCH

tCHDX

tCLCH

tCHCL

IO

input

MSB IN

LSB IN

8.9 /HOLD Timing

/CS

tHLCH

tCHHL

tHHCH

CLK

tCHHH

/HOLD

tHLQZ

tHHQX

IO

output

IO

input

8.10 /WP Timing

/CS

tWHSL

/WP

tSHWL

CLK

IO

input

Write Status Register is allowed

Write Status Register is not allowed

Publication Release Date: September 10, 2012

Revision A

- 42 -

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

9. PACKAGE SPECIFICATION

9.1 8-Pin SOIC 150-mil (Package Code SN)

c

8

5

E

H

E

L

1

4

θ

0.25

D

A

Y

e

SEATING PLANE

GAUGE PLANE

A1

b

MILLIMETERS

INCHES

SYMBOL

Min

1.35

0.10

0.33

0.19

3.80

4.80

Max

1.75

0.25

0.51

0.25

4.00

5.00

Min

Max

0.069

0.010

0.020

0.010

0.157

0.196

A

A1

b

0.053

0.004

0.013

0.008

0.150

0.188

c

E⁽³⁾

D⁽³⁾

e⁽²⁾

1.27 BSC

0.050 BSC

5.80

-

6.20

0.10

1.27

10°

0.228

-

0.244

0.004

0.050

10°

H

Y⁽⁴⁾

E

L

0.40

0°

0.016

0°

∘

Notes:

1. Controlling dimensions: millimeters, unless otherwise specified.

2. BSC = Basic lead spacing between centers.

3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package.

4. Formed leads coplanarity with respect to seating plane shall be within 0.004 inches.

Publication Release Date: September 10, 2012

- 43 -

Revision A

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

9.2 8-Pin SOIC 208-mil (Package Code SS)

GAUGE PLANE

θ

MILLIMETERS

Nom

INCHES

Nom

SYMBOL

Min

Max

Min

Max

A

A1

A2

b

1.75

0.05

1.70

0.35

0.19

5.18

5.13

5.18

5.13

1.95

0.15

1.80

0.42

0.20

5.28

5.23

5.28

5.23

1.27 BSC.

7.90

0.65

---

2.16

0.25

1.91

0.48

0.25

5.38

5.33

5.38

5.33

0.069

0.002

0.067

0.014

0.007

0.204

0.202

0.204

0.202

0.077

0.006

0.071

0.017

0.008

0.208

0.206

0.208

0.206

0.050 BSC.

0.311

0.026

---

0.085

0.010

0.075

0.019

0.010

0.212

0.210

0.212

0.210

C

D

D1

E

E1

e⁽²⁾

H

7.70

0.50

---

8.10

0.80

0.10

8°

0.303

0.020

---

0.319

0.031

0.004

8°

L

y

0°

---

0°

---

θ

Notes:

1. Controlling dimensions: millimeters, unless otherwise specified.

2. BSC = Basic lead spacing between centers.

3. Dimensions D1 and E1 do not include mold flash protrusions and should be measured from the bottom of the package.

4. Formed leads coplanarity with respect to seating plane shall be within 0.004 inches.

Publication Release Date: September 10, 2012

- 44 -

Revision A

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

9.3 8-Pad WSON 6x5-mm (Package Code ZP)

MILLIMETERS

INCHES

SYMBOL

MIN

0.70

0.00

TYP.

0.75

0.02

MAX

0.80

0.05

MIN

0.028

0.000

TYP.

0.030

0.001

MAX

0.031

0.002

A

A1

b

C

0.35

-

0.40

0.20 REF.

6.00

0.48

-

0.014

-

0.016

0.008 REF.

0.236

0.019

-

D

5.90

3.35

4.90

4.25

6.10

3.45

5.10

4.35

0.232

0.132

0.193

0.167

0.240

0.136

0.201

0.171

D2

E

3.40

0.134

5.00

0.197

4.30

0.169

E2

e

1.27 BSC

0.050 BSC

L

y

0.55

0.00

0.60

-

0.65

0.022

0.000

0.024

-

0.026

0.003

0.075

Publication Release Date: September 10, 2012

Revision A

- 45 -

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

8-Pad WSON 6x5-mm Cont’d.

MILLIMETERS

TYP.

INCHES

TYP.

SYMBOL

MIN

MAX

MIN

MAX

SOLDER PATTERN

M

N

P

―

3.40

4.30

6.00

0.50

0.75

―

0.1338

0.1692

0.2360

0.0196

0.0255

―

Q

R

Notes:

1. Advanced Packaging Information; please contact Winbond for the latest minimum and maximum specifications.

2. BSC = Basic lead spacing between centers.

3. Dimensions D and E do not include mold flash protrusions and should be measured from the bottom of the package.

Publication Release Date: September 10, 2012

- 46 -

Revision A

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

9.4 8-Pad USON 2x3-mm (Package Code UX)

A

1

L1

A1

e

b

D2

D

L3

E

L

C

E

y

Note: Exposed pad dimension D2 & E2 may be different by die size.

MILLIMETER

INCHES

SYMBOL

MIN

0.50

0.00

0.20

―

TYP.

0.55

0.02

0.25

0.15 REF

2.00

1.60

3.00

0.20

0.50

0.45

0.10

0.35

―

MAX

0.60

0.05

0.30

―

MIN

0.020

0.000

0.008

―

TYP.

0.022

0.001

0.010

MAX

0.024

0.002

0.012

―

A

A1

b

C

0.006 REF

0.079

0.063

0.118

0.008

0.020

0.018

0.004

0.014

―

D

1.90

1.55

2.90

0.15

―

2.10

1.65

3.10

0.25

―

0.075

0.061

0.114

0.006

―

0.083

0.065

0.122

0.010

―

D2

E

E2

e

L

0.40

―

0.50

―

0.016

―

0.020

―

L1

L3

y

0.30

0.00

0.40

0.075

0.012

0.000

0.016

0.003

Publication Release Date: September 10, 2012

Revision A

- 47 -

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

10. ORDERING INFORMATION⁽¹⁾

W 25X xxC V xx⁽²⁾A

W

=

Winbond

25X

20C

=

SpiFlash Serial Flash Memory with 4KB sectors, Dual SPI

2M-bit

V

=

2.6V to 3.6V

SN

ZP

=

8-pin SOIC 150-mil

8-pad WSON 6x5-mm

SS

UX

=

8-pin SOIC 208-mil

8-pad USON 2x3-mm

J

A

B

=

Industrial Grade Pluse (-40°C to +105°C)

Automotive Grade 2 (-40°C to +105°C)

Automotive Grade 3 (-40°C to +85°C)

=

G

=

Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb₂O₃)

Notes:

1a. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and Reel

(shape T) or Tray (shape S), when placing orders.

1b. The “W” prefix is not included on the part marking.

2. Only the 2^ndletter is used for the part marking, package type ZP is not used for the part marking.

Publication Release Date: September 10, 2012

- 48 -

Revision A

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

10.1 Valid Part Numbers and Top Side Marking

The following table provides the valid part numbers for the W25X20CV SpiFlash Memories. Please

contact Winbond for specific availability by density and package type. Winbond SpiFlash memories

use a 12-digit Product Number for ordering. However, due to limited space, the Top Side Marking on

all packages uses an abbreviated number less than 10-digit.

Part Numbers for Industrial Plus Grade Temperature⁽³⁾:

PACKAGE TYPE

DENSITY

2M-bit

PRODUCT NUMBER

W25X20CVSNJG

W25X20CVSSJG

TOP SIDE MARKING

25X20CVNJG

SN

SOIC-8 150mil

SS

2M-bit

25X20CVSJG

SOIC-8 208mil

ZP⁽¹⁾⁽²⁾

2M-bit

W25X20CVZPJG

W25X20CVUXJG

25X20CVJG

WSON-8 6x5mm

UX⁽²⁾⁽⁴⁾

2Gxxx

0Gxxxx

USON-8 2X3mm

Part Numbers for Automotive Grade 3 Temperature⁽³⁾:

PACKAGE TYPE

DENSITY

2M-bit

PRODUCT NUMBER

W25X20CVSNBG

W25X20CVSSBG

TOP SIDE MARKING

25X20CVNBG

SN

SOIC-8 150mil

SS

2M-bit

25X20CVSBG

SOIC-8 208mil

ZP⁽¹⁾⁽²⁾

2M-bit

W25X20CVZPBG

W25X20CVUXBG

25X20CVBG

WSON-8 6x5mm

UX⁽²⁾⁽⁴⁾

2Gxxx

0Gxxxx

USON-8 2X3mm

Part Numbers for Automotive Grade 2 Temperature⁽³⁾:

PACKAGE TYPE

DENSITY

2M-bit

PRODUCT NUMBER

W25X20CVSNAG

W25X20CVSSAG

TOP SIDE MARKING

25X20CVNAG

SN

SOIC-8 150mil

SS

2M-bit

25X20CVSAG

SOIC-8 208mil

ZP⁽¹⁾⁽²⁾

2M-bit

W25X20CVZPAG

W25X20CVUXAG

25X20CVAG

WSON-8 6x5mm

UX⁽²⁾⁽⁴⁾

2Gxxx

0Gxxxx

USON-8 2X3mm

Notes:

1. WSON package type ZP is not used in the top side marking.

2. These Package types are Special Order only, please contact Winbond for more information.

3. For Industrial Plus, Automotive Grade 2 & Grade 3 Temperature parts, please contact Winbond for more information

and availability.

4. USON package type UX has special top marking due to size limitation.

2 = 2Mb; G = W25X C series; 3V; 0 = Standard part; G = Green.

Publication Release Date: September 10, 2012

- 49 -

Revision A

FOR AUTOMOTIVE APPLICATIONS

W25X20CV

11. REVISION HISTORY

VERSION

DATE

PAGE

DESCRIPTION

New Create

A

2012/09/10

All

Trademarks

Winbond and SpiFlash are trademarks of Winbond Electronics Corporation.

All other marks are the property of their respective owner.

Important Notice

Winbond products are not designed, intended, authorized or warranted for use as components in

systems or equipment intended for surgical implantation, atomic energy control instruments, airplane

or spaceship instruments, transportation instruments, traffic signal instruments, combustion control

instruments, or for other applications intended to support or sustain life. Further more, Winbond

products are not intended for applications wherein failure of Winbond products could result or lead to a

situation wherein personal injury, death or severe property or environmental damage could occur.

Winbond customers using or selling these products for use in such applications do so at their own risk

and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.

Information in this document is provided solely in connection with Winbond products. Winbond

reserves the right to make changes, corrections, modifications or improvements to this document and

the products and services described herein at any time, without notice.

Publication Release Date: September 10, 2012

- 50 -

Revision A


型号：	W25X20CVSNBG
厂家：	WINBOND
描述：	Flash, 256KX8, PDSO8, SOIC-8 时钟光电二极管内存集成电路
文件：	总50页 (文件大小：1226K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W25X20CVSNBG [WINBOND]

相关型号：

W25X20CVSNJG

W25X20CVUXAG

W25X20CVUXJG

W25X20CVZPAG

W25X20CVZPJG

W25X20L

W25X20LDAC

W25X20LDACG

W25X20LDACZ

W25X20LDAI

W25X20LDAIG

W25X20LDAIZ