PC87309-ICK/VLJ [WINBOND]
Multifunction Peripheral, CMOS, PQFP100, EIAJ, PLASTIC, QFP-100;
| 型号： | PC87309-ICK/VLJ |
| 厂家： | 
WINBOND |
| 描述： | Multifunction Peripheral, CMOS, PQFP100, EIAJ, PLASTIC, QFP-100 时钟 |
| 文件： | 总194页 (文件大小：1474K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
- March 1998
PRELIMINARY
April 1998
PC87309 SuperI/O Plug and Play Compatible Chip
in Compact 100-Pin VLJ Packaging
Highlights
For flexible UART and IR support, the PC87309 offers two
operation modes:
General Description
The PC87309 is a single-chip solution to the most common-
ly used ISA, EISA and MicroChannel® peripherals in a com-
pact, 100-pin VLJ packaging. This fully Plug and Play (PnP)
and PC97 compatible chip conforms to the Plug and Play
ISA Specification Version 1.0a, May 5, 1994, and meets
specifications defined in the PC97 Hardware Design Guide.
●
Mode 1: Full-IR Mode
UART1 works as UART; UART2 works as fully IR-
compliant device
●
Mode 2: Two-UART Mode
Either both UARTs work as UARTs, or UART1 works
as UART and UART2 works as partially IR-compliant
device, providing only IRRX and IRTX support
The PC87309 incorporates: a Floppy Disk Controller (FDC),
a Mouse and Keyboard Controller (KBC), two enhanced
UARTs, one of which is with Infrared (IR) support, a full
IEEE 1284 parallel port and support for Power Management
(PM). The chip also provides a separate configuration reg-
ister set for each module.
Outstanding Features
●
Full SuperI/O functionality in compact, cost-effective
100-pin VLJ packaging
●
The Infrared (IR) interface complies with the HP-SIR and
SHARP-IR standards, and supports all four basic protocols
for Consumer Remote Control circuitry (RC-5, RC-6, NEC,
RCA and RECS 80).
PC97 compliant
PC87309 Block Diagram
Floppy Drive
Interface
DMA
Channels
Data Handshake
High Current Driver
IRQ
Floppy Disk
Controller (FDC)
(Logical Device 0)
Plug and Play
(PnP)
IEEE 1284
Parallel Port
(Logical Device 1)
µP Address
Data and
Control
Power Management
(PM) Logic
(Logical Device 4)
Serial Port
with IR (UART2)
(Logical Devices 2)
Serial Port
(UART1)
(Logical Devices 3)
Mouse and Keyboard
Controller (KBC)
(Logical Devices 5 & 6)
Ports
Data and
Control
Infrared
Serial
Control
Serial
Interface
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
IBM®, MicroChannel®, PC-AT® and PS/2® are registered trademarks of International Business Machines Corporation.
Microsoft® and Windows® are registered trademarks of Microsoft Corporation.
© 1998 National Semiconductor Corporation
www.national.com
Highlights
●
Two UARTs that provide:
Features
— Software compatibility with the 16550A and the 16450
●
100% compatibility with PnP requirements specified in
— A relocatable address that is referenced by an 11-bit
the “Plug and Play ISA Specification”, PC97, ISA, EISA,
and MicroChannel architectures
programmable register
— 7 IRQ channel options
●
A special PnP module that includes:
— Shadow register support for write-only bit monitoring
— UART data rates up to 1.5 Mbaud
— Flexible IRQs, DMAs and base addresses that meet
the PnP requirements specified by Microsoft® in
●
®
An enhanced UART and Infrared (IR) interface on the
UART2 that supports:
their 1995 hardware design guide for Windows and
PnP ISA Revision 1.0A
— HP-SIR
— PnP ISA mode (with isolation mechanism – Wait for
— ASK-IR option of SHARP-IR
— DASK-IR option of SHARP-IR
— Consumer Remote Control circuitry
— A PnP compatible external transceiver
Key state Motherboard PnP mode
●
A Floppy Disk Controller (FDC) that provides:
— A relocatable address that is referenced by an 11-bit
programmable register
— Three 8-bit DMA options for the UART with Slow In-
— Software compatibility with the PC8477, which con-
tains a superset of the floppy disk controller func-
tions in the µDP8473, the NEC µPD765A and the
N82077
frared support (UART2)
●
A bidirectional parallel port that includes:
— A relocatable address that is referenced by an 11-bit
— 7 IRQ channel options
— Three 8-bit DMA channel options
— 16-byte FIFO
programmable register
— Software or hardware control
— 7 IRQ channel options
— Burst and non-burst modes
— Three 8-bit DMA channel options
— Demand mode DMA support
— A new high-performance, on-chip, digital data sepa-
rator that does not require any external filter compo-
nents
— An Enhanced Parallel Port (EPP) that is compatible
with the new version EPP 1.9, and is IEEE 1284
compliant
— Support for standard 5.25" and 3.5" floppy disk
drives
— An Enhanced Parallel Port (EPP) that also supports
— Perpendicular recording drive support
version EPP 1.7 of the Xircom specification.
— Three-mode Floppy Disk Drive (FDD) support
— Support for an Enhanced Parallel Port (EPP) as
— Full support for the IBM Tape Drive Register (TDR)
mode 4 of the Extended Capabilities Port (ECP)
implementation of AT and PS/2 drive types
— An Extended Capabilities Port (ECP) that is IEEE
●
1284 compliant, including level 2
A Keyboard and mouse Controller (KBC) with:
— Selection of internal pull-up or pull-down resistor for
— A relocatable address that is referenced by an 11-bit
programmable register, reported as a fixed address
in resource data
Paper End (PE) pin
— Reduction of PCI bus utilization by supporting a de-
mand DMA mode mechanism and a DMA fairness
mechanism
— 7 IRQ options for the keyboard controller
— 7 IRQ options for the mouse controller
— An 8-bit microcontroller
— A protection circuit that prevents damage to the par-
allel port when a printer connected to it powers up or
is operated at high voltages
— Software compatibility with the 8042AH and
PC87911 microcontrollers
— Output buffers that can sink and source 14 mA
— 2 KB of custom-designed program ROM
— 256 bytes of RAM for data
●
Enhanced Power Management (PM), including:
— Reduced current leakage from pins
— Low-power CMOS technology
— Three programmable dedicated open drain I/O lines
for keyboard controller applications
— Ability to shut off clocks to all modules
— Asynchronous access to two data registers and one
status register during normal operation
●
●
Clock source:
— Support for both interrupt and polling
— 93 instructions
— Source is a 48 MHz clock input signal.
General features include:
— An 8-bit timer/counter
— Access to all configuration registers is through an In-
dex and a Data register, which can be relocated
within the ISA I/O address space
— Support for binary and BCD arithmetic
— Operation at 8 MHz,12 MHz or 16 MHz (programma-
ble option)
— 100-pin Plastic Quad Flatpack (PQFP) package
— Customizing by using the PC87323VUL, which in-
cludes a RAM-based KBC, as a development plat-
form for keyboard controller code for the PC87309
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2
Highlights
Basic Configuration
P12
P21,20
Keyboard I/O
Interface
KBCLK
KBDAT
MDAT
48 MHz
Clock
CLKIN
MCLK
MR
AEN
SIN1
SOUT1
RTS1
A11-0
D7-0
RD
EIA
Drivers
DTR1/BOUT1
CTS1
WR
IOCHRDY
DSR1
DCD1
RI1
IRQ1
IRQ7-3
IRRX2,1
IRTX
IRSL2-0
IRQ12
DRQ3-1
DACK3-1
TC
Infrared (IR)
Interface
ID3-0
PC87309
SIN2
SOUT2
RTS2
PD7-0
EIA
Drivers
DTR2/BOUT2
CTS2
SLIN/ASTRB
STB/WRITE
AFD/DSTRB
INIT
DSR2
Parallel
Port
DCD2
RI2
Connector
ACK
ERR
SLCT
PE
BUSY/WAIT
RDATA
WDATA
WGATE
HDSEL
Floppy
Disk
DIR
STEP
Controller
TRK0
(FDC)
Connector
INDEX
DSKCHG
WP
BADDR1,0
CFG0
Configuration
Select Logic
MTR1,0
DR1,0
DENSEL
DRATE0
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Table of Contents
Table of Contents
Highlights.......................................................................................................................................................1
1.0 Signal/Pin Connection and Description
1.1
1.2
CONNECTION DIAGRAM .........................................................................................................12
SIGNAL/PIN DESCRIPTIONS ...................................................................................................13
2.0 Configuration
2.1
2.2
2.3
2.4
HARDWARE CONFIGURATION ...............................................................................................19
2.1.1
2.1.2
Wake Up Options ........................................................................................................19
The Index and Data Register Pair ...............................................................................19
SOFTWARE CONFIGURATION ...............................................................................................20
2.2.1
2.2.2
Accessing the Configuration Registers ........................................................................20
Address Decoding .......................................................................................................20
THE CONFIGURATION REGISTERS .......................................................................................21
2.3.1
2.3.2
Standard Plug and Play (PnP) Register Definitions ....................................................21
Configuration Register Summary ................................................................................25
CARD CONTROL REGISTERS ................................................................................................28
2.4.1
2.4.2
2.4.3
2.4.4
SID Register ................................................................................................................28
SuperI/O Configuration 1 Register (SIOCF1) ..............................................................28
SuperI/O Configuration 2 Register (SIOCF2) ..............................................................29
SRID Register ..............................................................................................................29
2.5
FDC CONFIGURATION REGISTERS (LOGICAL DEVICE 0) ..................................................30
2.5.1
2.5.2
SuperI/O FDC Configuration Register .........................................................................30
Drive ID Register .........................................................................................................30
2.6
2.7
2.8
2.9
SUPERI/O PARALLEL PORT CONFIGURATION REGISTER (LOGICAL DEVICE 1) .............30
SUPERI/O UART2 AND INFRARED CONFIGURATION REGISTER (LOGICAL DEVICE 2) ..31
SUPERI/O UART1 CONFIGURATION REGISTER (LOGICAL DEVICE 3) ..............................32
SUPERI/O KBC CONFIGURATION REGISTER (LOGICAL DEVICE 6) ..................................32
2.10 CONFIGURATION REGISTER BITMAPS ................................................................................32
3.0 The Floppy Disk Controller (FDC) (Logical Device 0)
3.1
3.2
FDC FUNCTIONS .....................................................................................................................34
3.1.1
3.1.2
Microprocessor Interface .............................................................................................34
System Operation Modes ............................................................................................34
DATA TRANSFER .....................................................................................................................35
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
Data Rates ...................................................................................................................35
The Data Separator .....................................................................................................35
Perpendicular Recording Mode Support .....................................................................36
Data Rate Selection .....................................................................................................36
Write Precompensation ...............................................................................................37
FDC Low-Power Mode Logic .......................................................................................37
Reset ...........................................................................................................................37
3.3
THE REGISTERS OF THE FDC ...............................................................................................37
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Table of Contents
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.3.6
3.3.7
3.3.8
3.3.9
Status Register A (SRA) ..............................................................................................38
Status Register B (SRB) ..............................................................................................39
Digital Output Register (DOR) .....................................................................................39
Tape Drive Register (TDR) ..........................................................................................41
Main Status Register (MSR) ........................................................................................42
Data Rate Select Register (DSR) ................................................................................43
Data Register (FIFO) ...................................................................................................43
Digital Input Register (DIR) ..........................................................................................44
Configuration Control Register (CCR) .........................................................................45
3.4
3.5
THE PHASES OF FDC COMMANDS .......................................................................................45
3.4.1
3.4.2
3.4.3
3.4.4
3.4.5
Command Phase .........................................................................................................45
Execution Phase ..........................................................................................................45
Result Phase ...............................................................................................................47
Idle Phase ....................................................................................................................47
Drive Polling Phase .....................................................................................................48
THE RESULT PHASE STATUS REGISTERS ..........................................................................48
3.5.1
3.5.2
3.5.3
3.5.4
Result Phase Status Register 0 (ST0) .........................................................................48
Result Phase Status Register 1 (ST1) .........................................................................49
Result Phase Status Register 2 (ST2) .........................................................................49
Result Phase Status Register 3 (ST3) .........................................................................50
3.6
3.7
FDC REGISTER BITMAPS .......................................................................................................51
3.6.1
3.6.2
Standard ......................................................................................................................51
Result Phase Status ....................................................................................................52
COMMAND SET .......................................................................................................................53
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
3.7.7
3.7.8
3.7.9
Abbreviations Used in FDC Commands ......................................................................54
The CONFIGURE Command ......................................................................................55
The DUMPREG Command .........................................................................................55
The FORMAT TRACK Command ...............................................................................56
The INVALID Command ..............................................................................................58
The LOCK Command ..................................................................................................60
The MODE Command .................................................................................................60
The NSC Command ....................................................................................................62
The PERPENDICULAR MODE Command .................................................................62
3.7.10 The READ DATA Command .......................................................................................64
3.7.11 The READ DELETED DATA Command ......................................................................66
3.7.12 The READ ID Command .............................................................................................67
3.7.13 The READ A TRACK Command .................................................................................68
3.7.14 The RECALIBRATE Command ...................................................................................68
3.7.15 The RELATIVE SEEK Command ................................................................................69
3.7.16 The SCAN EQUAL, the SCAN LOW OR EQUAL and the SCAN HIGH OR EQUAL
Commands ..................................................................................................................69
3.7.17 The SEEK Command ..................................................................................................70
3.7.18 The SENSE DRIVE STATUS Command ....................................................................71
3.7.19 The SENSE INTERRUPT Command ..........................................................................71
3.7.20 The SET TRACK Command ........................................................................................72
3.7.21 The SPECIFY Command ............................................................................................73
3.7.22 The VERIFY Command ...............................................................................................74
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Table of Contents
3.7.23 The VERSION Command ............................................................................................76
3.7.24 The WRITE DATA Command ......................................................................................76
3.7.25 The WRITE DELETED DATA Command ....................................................................77
3.8
EXAMPLE OF A FOUR-DRIVE CIRCUIT USING THE PC87309 .............................................78
4.0 Parallel Port (Logical Device 1)
4.1
PARALLEL PORT CONFIGURATION ......................................................................................79
4.1.1
4.1.2
4.1.3
Parallel Port Operation Modes ....................................................................................79
Configuring Operation Modes ......................................................................................79
Output Pin Protection ..................................................................................................79
4.2
STANDARD PARALLEL PORT (SPP) MODES ........................................................................79
4.2.1
4.2.2
4.2.3
4.2.4
SPP Modes Register Set .............................................................................................80
SPP Data Register (DTR) ............................................................................................80
Status Register (STR) .................................................................................................81
SPP Control Register (CTR) ........................................................................................81
4.3
ENHANCED PARALLEL PORT (EPP) MODES ........................................................................82
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
4.3.7
4.3.8
4.3.9
EPP Register Set .........................................................................................................82
SPP or EPP Data Register (DTR) ...............................................................................83
SPP or EPP Status Register (STR) .............................................................................83
SPP or EPP Control Register (CTR) ...........................................................................83
EPP Address Register (ADDR) ...................................................................................83
EPP Data Register 0 (DATA0) ....................................................................................84
EPP Data Register 1 (DATA1) ....................................................................................84
EPP Data Register 2 (DATA2) ....................................................................................84
EPP Data Register 3 (DATA3) ....................................................................................84
4.3.10 EPP Mode Transfer Operations ..................................................................................85
4.3.11 EPP 1.7 and 1.9 Data Write and Read Operations .....................................................85
4.4
4.5
EXTENDED CAPABILITIES PARALLEL PORT (ECP) .............................................................86
4.4.1
4.4.2
4.4.3
ECP Modes .................................................................................................................86
Software Operation ......................................................................................................86
Hardware Operation ....................................................................................................87
ECP MODE REGISTERS ..........................................................................................................87
4.5.1
4.5.2
4.5.3
4.5.4
4.5.5
4.5.6
4.5.7
4.5.8
4.5.9
Accessing the ECP Registers ......................................................................................87
Second Level Offsets ..................................................................................................88
ECP Data Register (DATAR) .......................................................................................88
ECP Address FIFO (AFIFO) Register .........................................................................88
ECP Status Register (DSR) .........................................................................................88
ECP Control Register (DCR) .......................................................................................89
Parallel Port Data FIFO (CFIFO) Register ...................................................................90
ECP Data FIFO (DFIFO) Register ...............................................................................90
Test FIFO (TFIFO) Register ........................................................................................90
4.5.10 Configuration Register A (CNFGA) .............................................................................90
4.5.11 Configuration Register B (CNFGB) .............................................................................91
4.5.12 Extended Control Register (ECR) ...............................................................................91
4.5.13 ECP Extended Index Register (EIR) ...........................................................................92
4.5.14 ECP Extended Data Register (EDR) ...........................................................................93
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Table of Contents
4.5.15 ECP Extended Auxiliary Status Register (EAR) ..........................................................93
4.5.16 Control0 Register .........................................................................................................93
4.5.17 Control2 Register .........................................................................................................93
4.5.18 Control4 Register .........................................................................................................94
4.5.19 PP Confg0 Register .....................................................................................................94
4.6
DETAILED ECP MODE DESCRIPTIONS .................................................................................95
4.6.1
4.6.2
4.6.3
4.6.4
4.6.5
4.6.6
Software Controlled Data Transfer (Modes 000 and 001) ...........................................95
Automatic Data Transfer (Modes 010 and 011) ..........................................................95
Automatic Address and Data Transfers (Mode 100) ...................................................97
FIFO Test Access (Mode 110) ....................................................................................97
Configuration Registers Access (Mode 111) ...............................................................97
Interrupt Generation ....................................................................................................97
4.7
4.8
PARALLEL PORT REGISTER BITMAPS .................................................................................98
4.7.1
4.7.2
EPP Modes ..................................................................................................................98
ECP Modes .................................................................................................................99
PARALLEL PORT PIN/SIGNAL LIST ......................................................................................101
5.0 Enhanced Serial Port with IR -UART2 (Logical Device 2)
5.1
5.2
FEATURES ..............................................................................................................................102
FUNCTIONAL MODES OVERVIEW .......................................................................................102
5.2.1
5.2.2
5.2.3
UART Modes: 16450 or 16550, and Extended ..........................................................102
Sharp-IR, IrDA SIR Infrared Modes ...........................................................................102
Consumer IR Mode ...................................................................................................102
5.3
5.4
REGISTER BANK OVERVIEW ...............................................................................................102
UART MODES – DETAILED DESCRIPTION ..........................................................................104
5.4.1
5.4.2
16450 or 16550 UART Mode .....................................................................................104
Extended UART Mode ...............................................................................................104
5.5
5.6
5.7
SHARP-IR MODE – DETAILED DESCRIPTION .....................................................................105
SIR MODE – DETAILED DESCRIPTION ................................................................................105
CONSUMER-IR MODE – DETAILED DESCRIPTION ............................................................105
5.7.1
5.7.2
Consumer-IR Transmission .......................................................................................105
Consumer-IR Reception ............................................................................................106
5.8
FIFO TIME-OUTS ....................................................................................................................106
5.8.1
5.8.2
5.8.3
UART, SIR or Sharp-IR Mode Time-Out Conditions .................................................106
Consumer-IR Mode Time-Out Conditions .................................................................106
Transmission Deferral ...............................................................................................107
5.9
AUTOMATIC FALLBACK TO A NON-EXTENDED UART MODE ..........................................107
5.11 BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS .................................................107
5.11.1 Receiver Data Port (RXD) or the Transmitter Data Port (TXD) .................................108
5.11.2 Interrupt Enable Register (IER) .................................................................................108
5.11.3 Event Identification Register (EIR) ............................................................................110
5.11.4 FIFO Control Register (FCR) .....................................................................................112
5.11.5 Link Control Register (LCR) and Bank Selection Register (BSR) .............................112
5.11.6 Bank Selection Register (BSR) .................................................................................113
5.11.7 Modem/Mode Control Register (MCR) ......................................................................114
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Table of Contents
5.11.8 Link Status Register (LSR) ........................................................................................115
5.11.9 Modem Status Register (MSR) ..................................................................................116
5.11.10 Scratchpad Register (SPR) .......................................................................................117
5.11.11 Auxiliary Status and Control Register (ASCR) ..........................................................117
5.12 BANK 1 – THE LEGACY BAUD GENERATOR DIVISOR PORTS .........................................117
5.12.1 Legacy Baud Generator Divisor Ports (LBGD(L) and LBGD(H)), ..............................118
5.12.2 Link Control Register (LCR) and Bank Select Register (BSR) ..................................118
5.13 BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS ............................................118
5.13.1 Baud Generator Divisor Ports, LSB (BGD(L)) and MSB (BGD(H)) ...........................119
5.13.2 Extended Control Register 1 (EXCR1) ......................................................................120
5.13.3 Link Control Register (LCR) and Bank Select Register (BSR) ..................................121
5.13.4 Extended Control and Status Register 2 (EXCR2) ....................................................121
5.13.5 Reserved Register .....................................................................................................121
5.13.6 TX_FIFO Current Level Register (TXFLV) ................................................................121
5.13.7 RX_FIFO Current Level Register (RXFLV) ...............................................................122
5.14 BANK 3 – MODULE REVISION ID AND SHADOW REGISTERS ..........................................122
5.14.1 Module Revision ID Register (MRID) ........................................................................122
5.14.2 Shadow of Link Control Register (SH_LCR) .............................................................122
5.14.3 Shadow of FIFO Control Register (SH_FCR) ............................................................123
5.14.4 Link Control Register (LCR) and Bank Select Register (BSR) ..................................123
5.15 BANK 4 – IR MODE SETUP REGISTER ................................................................................123
5.15.1 Reserved Registers ...................................................................................................123
5.15.2 Infrared Control Register 1 (IRCR1) ..........................................................................123
5.15.3 Link Control Register (LCR) and Bank Select Register (BSR) ..................................123
5.15.4 Reserved Registers ...................................................................................................123
5.16 BANK 5 – INFRARED CONTROL REGISTERS .....................................................................123
5.16.1 Reserved Registers ...................................................................................................124
5.16.2 (LCR/BSR) Register ..................................................................................................124
5.16.3 Infrared Control Register 2 (IRCR2) ..........................................................................124
5.16.4 Reserved Registers ...................................................................................................124
5.17 BANK 6 – INFRARED PHYSICAL LAYER CONFIGURATION REGISTERS .........................124
5.17.1 Infrared Control Register 3 (IRCR3) ..........................................................................124
5.17.2 Reserved Register .....................................................................................................124
5.17.3 SIR Pulse Width Register (SIR_PW) .........................................................................124
5.17.4 Link Control Register (LCR) and Bank Select Register (BSR) ..................................125
5.17.5 Reserved Registers ...................................................................................................125
5.18 BANK 7 – CONSUMER-IR AND OPTICAL TRANSCEIVER CONFIGURATION REGISTERS 125
5.18.1 Infrared Receiver Demodulator Control Register (IRRXDC) .....................................125
5.18.2 Infrared Transmitter Modulator Control Register (IRTXMC) ......................................126
5.18.3 Consumer-IR Configuration Register (RCCFG) ........................................................128
5.18.4 Link Control/Bank Select Registers (LCR/BSR) ........................................................129
5.18.5 Infrared Interface Configuration Register 1 (IRCFG1) ...............................................129
5.18.6 Reserved Register .....................................................................................................129
5.18.7 Infrared Interface Configuration 3 Register (IRCFG3) ...............................................129
5.18.8 Infrared Interface Configuration Register 4 (IRCFG4) ...............................................130
5.19 UART2 WITH IR REGISTER BITMAPS ..................................................................................131
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Table of Contents
6.0 Enhanced Serial Port - UART1 (Logical Device 3)
6.1
6.2
REGISTER BANK OVERVIEW ...............................................................................................136
DETAILED DESCRIPTION ......................................................................................................136
6.2.1
6.2.2
16450 or 16550 UART Mode .....................................................................................137
Extended UART Mode ...............................................................................................137
6.3
6.4
FIFO TIME-OUTS ....................................................................................................................137
AUTOMATIC FALLBACK TO A NON-EXTENDED UART MODE ..........................................138
6.4.1
Transmission Deferral ...............................................................................................138
6.5
BANK 0 – GLOBAL CONTROL AND STATUS REGISTERS .................................................138
6.5.1
6.5.2
6.5.3
6.5.4
6.5.5
6.5.6
6.5.7
6.5.8
6.5.9
Receiver Data Port (RXD) or the Transmitter Data Port (TXD) .................................138
Interrupt Enable Register (IER) .................................................................................139
Event Identification Register (EIR) ............................................................................140
FIFO Control Register (FCR) .....................................................................................142
Line Control Register (LCR) and Bank Selection Register (BSR) .............................142
Bank Selection Register (BSR) .................................................................................143
Modem/Mode Control Register (MCR) ......................................................................143
Line Status Register (LSR) ........................................................................................144
Modem Status Register (MSR) ..................................................................................145
6.5.10 Scratchpad Register (SPR) .......................................................................................146
6.5.11 Auxiliary Status and Control Register (ASCR) ..........................................................146
6.6
6.7
BANK 1 – THE LEGACY BAUD GENERATOR DIVISOR PORTS .........................................146
6.6.1
6.6.2
Legacy Baud Generator Divisor Ports (LBGD(L) and LBGD(H)), ..............................147
Line Control Register (LCR) and Bank Select Register (BSR) ..................................147
BANK 2 – EXTENDED CONTROL AND STATUS REGISTERS ............................................148
6.7.1
6.7.2
6.7.3
6.7.4
6.7.5
6.7.6
6.7.7
Baud Generator Divisor Ports, LSB (BGD(L)) and MSB (BGD(H)) ...........................148
Extended Control Register 1 (EXCR1) ......................................................................149
Line Control Register (LCR) and Bank Select Register (BSR) ..................................149
Extended Control and Status Register 2 (EXCR2) ....................................................149
Reserved Register .....................................................................................................150
TX_FIFO Current Level Register (TXFLV) ................................................................150
RX_FIFO Current Level Register (RXFLV) ...............................................................150
6.8
6.9
BANK 3 – MODULE REVISION ID AND SHADOW REGISTERS ..........................................150
6.8.1
6.8.2
6.8.3
6.8.4
Module Revision ID Register (MRID) ........................................................................151
Shadow of Line Control Register (SH_LCR) .............................................................151
Shadow of FIFO Control Register (SH_FCR) ............................................................151
Line Control Register (LCR) and Bank Select Register (BSR) ..................................151
UART1 REGISTER BITMAPS .................................................................................................151
7.0 Power Management (Logical Device 4)
7.1
7.2
POWER MANAGEMENT OPTIONS .......................................................................................155
THE POWER MANAGEMENT REGISTERS ..........................................................................155
7.2.1
7.2.2
7.2.3
7.2.4
Power Management Index Register ..........................................................................155
Power Management Data Register ...........................................................................155
Function Enable Register 1 (FER1) ...........................................................................155
Power Management Control Register (PMC1) ..........................................................156
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9
Table of Contents
7.2.5
Power Management Control 3 Register (PMC3) .......................................................156
7.3
POWER MANAGEMENT REGISTER BITMAPS ....................................................................157
8.0 Mouse and Keyboard Controller (KBC) (Logical Devices 5 and 6)
8.1
8.2
8.3
SYSTEM ARCHITECTURE .....................................................................................................158
FUNCTIONAL OVERVIEW .....................................................................................................159
DEVICE CONFIGURATION ....................................................................................................159
8.3.1
8.3.2
8.3.3
8.3.4
I/O Address Space ....................................................................................................159
Interrupt Request Signals ..........................................................................................159
KBC Clock .................................................................................................................161
Timer or Event Counter .............................................................................................161
8.4
8.5
EXTERNAL I/O INTERFACES ................................................................................................161
8.4.1
8.4.2
Keyboard and Mouse Interface .................................................................................161
General Purpose I/O Signals .....................................................................................162
INTERNAL KBC - PC87309 INTERFACE ...............................................................................163
8.5.1
8.5.2
8.5.3
The KBC DBBOUT Register, Offset 60h, Read Only ................................................163
The KBC DBBIN Register, Offset 60h (F1 Clear) or 64h (F1 Set), Write Only ..........163
The KBC STATUS Register ......................................................................................163
8.6
INSTRUCTION TIMING ...........................................................................................................163
9.0 Interrupt and DMA Mapping
9.1
9.2
IRQ MAPPING .........................................................................................................................164
DMA MAPPING .......................................................................................................................164
10.0 Device Specifications
10.1 GENERAL DC ELECTRICAL CHARACTERISTICS ...............................................................165
10.1.1 Recommended Operating Conditions .......................................................................165
10.1.2 Absolute Maximum Ratings .......................................................................................165
10.1.3 Capacitance ...............................................................................................................165
10.1.4 Power Consumption under Recommended Operating Conditions ............................165
10.2 DC CHARACTERISTICS OF PINS, BY GROUP ....................................................................166
10.2.1 Group 1 ......................................................................................................................166
10.2.2 Group 2 ......................................................................................................................166
10.2.3 Group 3 ......................................................................................................................166
10.2.4 Group 4 ......................................................................................................................167
10.2.5 Group 5 ......................................................................................................................167
10.2.6 Group 6 ......................................................................................................................167
10.2.7 Group 7 ......................................................................................................................168
10.2.8 Group 8 ......................................................................................................................168
10.2.9 Group 9 ......................................................................................................................169
10.2.10 Group 10 ....................................................................................................................169
10.2.11 Group 11 ....................................................................................................................169
10.2.12 Group 12 ....................................................................................................................169
10.2.13 Group 13 ....................................................................................................................170
10.2.14 Group 14 ....................................................................................................................170
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10
Table of Contents
10.2.15 Group 15 ....................................................................................................................170
10.2.16 Group 18 ....................................................................................................................170
10.3 AC ELECTRICAL CHARACTERISTICS ..................................................................................171
10.3.1 AC Test Conditions ....................................................................................................171
10.3.2 Clock Timing ..............................................................................................................171
10.3.3 Microprocessor Interface Timing ...............................................................................172
10.3.4 Baud Output Timing ...................................................................................................174
10.3.5 Transmitter Timing .....................................................................................................175
10.3.6 Receiver Timing .........................................................................................................176
10.3.7 UART, Sharp-IR, SIR and Consumer Remote Control Timing ..................................178
10.3.8 IRSLn Write Timing ...................................................................................................179
10.3.9 Modem Control Timing ..............................................................................................179
10.3.10 FDC DMA Timing ......................................................................................................180
10.3.11 ECP DMA Timing ......................................................................................................181
10.3.12 UART2 DMA Timing ..................................................................................................182
10.3.13 Reset Timing .............................................................................................................183
10.3.14 FDC - Write Data Timing ...........................................................................................183
10.3.15 FDC - Drive Control Timing .......................................................................................184
10.3.16 FDC - Read Data Timing ...........................................................................................184
10.3.17 Standard Parallel Port Timing ....................................................................................185
10.3.18 Enhanced Parallel Port 1.7 Timing ............................................................................186
10.3.19 Enhanced Parallel Port 1.9 Timing ............................................................................187
10.3.20 Extended Capabilities Port (ECP) Timing ..................................................................188
Glossary .....................................................................................................................................................189
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11
Signal/Pin Connection and Description
1.0 Signal/Pin Connection and Description
1.1 CONNECTION DIAGRAM
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PD6
PD7
CTS1
DCD1
DSR1
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DIR
WDATA
DR1/DENSEL
DR0
MTR1/P12
MTR0/DRATE0
IRTX/DENSEL
IRRX1/P12/DRATE0
DACK3
VDD
VSS
DACK2
DACK1
DRQ3
DRQ2
DRQ1
MR
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
BOUT1/DTR1/BADDR0
RI1
RTS1/BADDR1
SIN1
VDD
VSS
SOUT1/CGF0
CTS2/A11
PC87309VLJ
DCD2/P12
DSR2/DRATE0
BOUT2/DTR2/IRSL2/ID2
RI2/DENSEL
RTS2/IRSL1/ID1
SIN2/ID3
CLKIN
IRQ12
IRQ7
SOUT2/IRSL0/IRRX2/ID0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
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12
Signal/Pin Connection and Description
The Module column indicates the functional module that is
1.2 SIGNAL/PIN DESCRIPTIONS
associated with these pins. In this column, the System label
indicates internal functions that are common to more than
one module. The I/O and Group # column describes wheth-
er the pin is an input, output, or bidirectional pin (marked as
Input, Output or I/O, respectively).
TABLE 1-1 lists the signals of the PC87309 in alphabetical
order and shows the pin(s) associated with each. TABLE
1-2 on page 18 lists the signals that are multiplexed in Full-
IR and Two-UART modes. TABLE 1-3 on page 18 lists the
pins that have strap functions during reset.
TABLE 1-1. Signal/Pin Description Table
I/O and
Signal/Pin
Name
Pin
Number
Module
Function
Group #
A11-0
93, 20-16,
14-9
ISA-Bus
Input
ISA-Bus Address – A11-0 are used for address decoding on any
access except DMA accesses, on the condition that the AEN signal is
low.
Group 1
A11 is multiplexed with CTS2 on pin 93 and available in Full-IR mode
only. Since A11 is required to support full ISA PnP mode (for
decoding A79h), this mode is not available in Two-UART mode.
See Section 2.2.2.
ACK
AFD
68
74
Parallel Port
Parallel Port
Input
Acknowledge – This input signal is pulsed low by the printer to
indicate that it has received data from the parallel port. This pin is
internally connected to an internal weak pull-up.
Group 3
I/O
Automatic Feed – When this signal is low the printer should
automatically feed a line after printing each line. This pin is in TRI-
STATE after a 0 is loaded into the corresponding control register bit.
An external 4.7 KΩ pull-up resistor should be attached to this pin.
Group 8
This signal is multiplexed with DSTRB. See TABLE 4-12 on page 101
for more information.
AEN
21
73
ISA-Bus
Input
DMA Address Enable – This input signal disables function selection
via A11-0 when it is high. Access during DMA transfer is not affected
by this signal. This pin is used for external decoding of A11-15 in
Two-UART mode or A15-12 in Full-IR mode.
Group 1
ASTRB
Parallel Port
Output Address Strobe (EPP) – This signal is used in EPP mode as an
address strobe. It is active low.
Group 8
This signal is multiplexed with SLIN. See TABLE 4-12 on page 101 for
more information.
BADDR1,0 88,86
Configuration
Input
Base Address Strap Pins 0 and 1 – These pins determine the base
addresses of the Index and Data registers, the value of the Plug and
Play ISA Serial Identifier and the configuration state immediately after
reset. These pins are pulled down by internal 30 KΩ resistors.
External 10 KΩ pull-up resistors to VDD should be employed.
Group 4
BADDR1 is multiplexed with RTS1.
BADDR0 is multiplexed with DTR1 and BOUT1.
See TABLE 2-1 and Section 2.1.
BOUT2,1
96,86
UART1,
UART2
Output Baud Output – This multi-function pin provides the associated serial
channel Baud Rate generator output signal if test mode is selected,
Group 12
i.e., bit 7 of the EXCR1 register is set. See “Bit 7 - Baud Generator
Test (BTEST)” on page 121.
After Master Reset this pin provides the DTR function.
BOUT2 is multiplexed with DTR2, IRSL2 and ID2.
BOUT1 is multiplexed with DRT1 and BADDR0.
BUSY
66
Parallel Port
Input
Busy – This pin is set high by the printer when it cannot accept
another character. It is internally connected to a weak pull-down
resistor.
Group 2
This signal is multiplexed with WAIT. See TABLE 4-12 on page 101 for
more information.
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13
Signal/Pin Connection and Description
I/O and
Signal/Pin
Name
Pin
Number
Module
Function
Group #
CFG0
92
Configuration
Input
This pin selects between Full-IR and Two-UART mode as the default
configuration upon power up. It is pulled down by internal 30 KΩ
resistors. External 10 KΩ pull-up resistors to VDD should be
Group 4
employed.
This signal is multiplexed with SOUT1.
See TABLE 2-1 and Section 2.1.
CLKIN
33
Clock
Input
Clock In – A TTL or CMOS compatible 48 MHz clock.
Group 1
CTS2,1
93,83
UART1,
UART2
Input
UART1 and UART2 Clear to Send – When low, these signals indicate
that the modem or other data transfer device is ready to exchange data.
Group 1
CTS2 is multiplexed with A11, and available only in Two-UART mode.
D7-0
8-1
ISA-Bus
ISA-Bus
I/O
ISA-Bus Data – Bidirectional data lines to the microprocessor. D0 is
the LSB and D7 is the MSB. These signals have 24 mA (sink)
buffered outputs.
Group 5
DACK3
42
Input
DMA Acknowledge 1,2 and 3 – These active low input signals
acknowledge a request for DMA services and enable the IOWR and
IORD input signals during a DMA transfer. These DMA signals can be
mapped to the following logical devices: FDC, UART or Parallel Port.
DACK2,1
39,38
Group 1
DCD2,1
94,84
UART1,
UART2
Input
UART1 and UART2 Data Carrier Detected – When low, this signal
indicates that the modem or other data transfer device has detected
the data carrier.
Group 1
DCD2 is multiplexed with P12 and available only in Two-UART mode.
DENSEL
97, 48 or
44
FDC
Output Density Select – Indicates that a high FDC density data rate (500
Kbps or 1 Mbps) or a low density data rate (250 or 300 Kbps) is
Group 11
selected.
DENSEL polarity is controlled by bit 5 of the SuperI/O FDC
Configuration register as described in Section 2.5.1.
This signal is multiplexed with: IRTX, , DR1, or R12.
DIR
50
FDC
FDC
Output Direction – This output signal determines the direction of the Floppy
Disk Drive (FDD) head movement (active = step in, inactive = step
out) during a seek operation. During reads or writes, DIR is inactive.
Group 11
DR1,0
48, 47
Output Drive Select 0 and 1 – These active low output signals are the
decoded drive select output signals. DR0 and DR1 are controlled by
Group 11
Digital Output Register (DOR) bits 0 and 1. They are encoded with
information to control four FDDs when bit 7 of the SuperI/O FDC
Configuration register is 1, as described in Section 2.5.1.
DR0 can optionally become a logical OR of DR0 and MTR0 when
MTR0/DRATE0 is used as DRATE0.
DR1 is multiplexed with DENSEL and is available only in Two-UART
mode. Optionally, it can become a logical OR of DR1 and MTR1
when MTR1/P12 is used as P12.
See MTR0,1 for more information.
DRATE0
95, 45 or
43
FDC
Output Data Rate 0 – This output signal reflects the value of bit 0 of the
Configuration Control Register (CCR) or the Data Rate Select Register
Group 14
(DSR), whichever was written to last. Output from the pin is totem-pole
buffered (6 mA sink, 6 mA source).
This signal is multiplexed with IRRX1/P12, MTR0 or DSR2
DRQ3-1
37-35
58
ISA-Bus
FDC
Output DMA Request 1, 2 and 3 – These active high output signals inform
the DMA controller that a data transfer is needed. These DMA signals
can be mapped to the following logical devices: Floppy Disk Controller
(FDC), UART or parallel port.
Group 13
DSKCHG
Input
Disk Change – This input signal indicates whether or not the drive
door has been opened. The state of this pin is available from the
Digital Input Register (DIR). This pin can also be configured as the
RGATE data separator diagnostic input signal via the MODE
command. See the MODE command in Section 3.7.7.
Group 1
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14
Signal/Pin Connection and Description
I/O and
Signal/Pin
Name
Pin
Number
Module
Function
Group #
DSR2,1
95,85
UART1,
UART2
Input
Data Set Ready – When low, this signal indicates that the data
transfer device, e.g., modem, is ready to establish a communications
link.
Group 1
DSR2 is multiplexed with DRATE0 and available only in Two-UART
mode.
DSTRB
DTR2,1
74
Parallel Port
Output Data Strobe – This signal is used in EPP mode as a data strobe. It
is active low.
Group 8
DSTRB is multiplexed with AFD. See TABLE 4-12 on page 101 for
more information.
96,86
UART1,
UART2
Output Data Terminal Ready – When low, this output signal indicates to the
modem or other data transfer device that the UART1 or UART2 is
ready to establish a communications link.
Group 12
A Master Reset (MR) deactivates this signal high, and loopback
operation holds this signal inactive.
DTR1 is multiplexed with BADDR0 and with BOUT1.
DTR2 is multiplexed with IRSL2/ID2/BOUT2 and is available only in
Two-UART mode. (BOUT2 is multiplexed implicitly and controlled by
UART2.)
ERR
71
52
Parallel Port
Input
Error – This input signal is set active low by the printer when it has
detected an error. This pin is internally connected to an internal weak
pull-up.
Group 3
HDSEL
FDC
Output Head Select – This output signal determines which side of the FDD
is accessed. Active low selects side 1, inactive selects side 0.
Group 11
ID3
ID2
ID1
ID0
99
UART2
Input
Identification – These ID signals identify the infrared transceiver for
Plug and Play support. These pins are read after reset.
96
Group 1
ID0,1,2 are multiplexed implicitly with IRSL0,1,2 respectively by the
UART2 cell.
98
100
ID3 is multiplexed with SIN2.
ID2 is multiplexed with BOUT2, DTR2, IRSL2.
ID1 is multiplexed with RTS2, IRSL1
ID0 is multiplexed with SOUT2,IRSL0, IRRX2
INDEX
INIT
56
72
FDC
Input
Index – This input signal indicates the beginning of an FDD track.
Group 1
Parallel Port
I/O
Initialize – When this signal is active low, it causes the printer to be
initialized. This signal is in TRI-STATE after a 1 is loaded into the
corresponding control register bit.
Group 8
An external 4.7 KΩ pull-up resistor should be employed.
IOCHRDY
IORD
22
23
24
ISA-Bus
ISA-Bus
ISA-Bus
ISA-Bus
Output I/O Channel Ready – This is the I/O channel ready open drain output
signal. When IOCHRDY is driven low, the EPP extends the host cycle.
Group 15
Input
I/O Read – An active low RD input signal indicates that the
microprocessor has read data.
Group 1
IOWR
Input
I/O Write – WR is an active low input signal that indicates a write
operation from the microprocessor to the controller.
Group 1
IRQ1
26
I/O
Interrupt Requests 1, 3, 4, 5, 6, 7 and 12 – IRQ polarity and push-
pull or open-drain output selection is software configurable by the
logical device mapped to the IRQ line.
IRQ7-3
IRQ12
31-27
32
Group 10
Keyboard Controller (KBC) or Mouse interrupts can be configured by
the Interrupt Request Type Select 0 register (index 71h) as either
edge or level.
IRRX2,1
100,43
UART2
Input
Infrared Reception 1 and 2 – Infrared serial input data.
Group 18 IRRX1 is multiplexed with P12/DRATE0 and is available only in Two-
UART mode.
IRRX2 is multiplexed with SOUT2/IRSL0/ID0 and is available only in
Full-IR mode.
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15
Signal/Pin Connection and Description
I/O and
Signal/Pin
Name
Pin
Number
Module
Function
Group #
IRSL0
IRSL1
IRSL2
100
UART2
Output Infrared Control Signals 0, 1 and 2 – These signals control the
Infrared analog front end. The pins on which these signals are driven
98
96
Group 12
is determined by the SuperI/O Configuration 2 register (index 22h).
SeeTABLE 1-2 for more information.
IRSL0 is multiplexed on pin 100 with SOUT2, IRRX2 and ID0, and is
available only in Full-IR mode.
IRSL1 is multiplexed on pin 98 with RTS2 and ID1, and is available
only in Full-IR mode.
IRSL2 is multiplexed on pin 96 with DTR2, BOUT2 and ID2, and is
available only in Full-IR mode.
IRTX
44
59
UART2
KBC
Output Infrared Transmit – Infrared serial output data.
Group 12 This signal is multiplexed with DENSEL only in Two-UART mode.
KBCLK
I/O
Keyboard Clock – This I/O pin transfers the keyboard clock between
the SuperI/O chip and the external keyboard using the PS/2 protocol.
Group 6
This pin is connected internally to the internal TO signal of the KBC.
KBDAT
MCLK
MDAT
MR
60
61
62
34
KBC
KBC
I/O
Keyboard Data – This I/O pin transfers the keyboard data between
the SuperI/O chip and the external keyboard using the PS/2 protocol.
Group 6
This pin is connected internally to KBC’s P10.
I/O
Mouse Clock – This I/O pin transfers the mouse clock between the
SuperI/O chip and the external keyboard using the PS/2 protocol.
Group 6
This pin is connected internally to KBC’s T1.
KBC
I/O
Mouse Data – This I/O pin transfers the mouse data between the
SuperI/O chip and the external keyboard using the PS/2 protocol.
Group 6
This pin is connected internally to KBC’s P11.
ISA-Bus
Input
Master Reset – An active high MR input signal resets the controller
to the idle state, and resets all disk interface output signals to their
inactive states. MR also clears the DOR, DSR and CCR registers,
and resets the MODE command, CONFIGURE command, and LOCK
command parameters to their default values. MR does not affect the
SPECIFY command parameters. MR sets the configuration registers
to their selected default values.
Group 1
MTR1,0
46,45
FDC
Output Motor Select 1,0 – These motor enable lines for drives 0 and 1 are
controlled by bits D7-4 of the Digital Output Register (DOR). They are
Group 11
output signals that are active when they are low. They are encoded with
information to control four FDDs when bit 7 of the SuperI/O FDC
Configuration register is set See TABLE 1-2 for more information. See
DR1,0.
MTR0 is multiplexed with DRATE0 only in Two-UART mode.
MTR1 is multiplexed with P12 only in Two-UART mode.
P12
94, 46 or
43
KBC
I/O
I/O Port – KBC quasi-bidirectional port for general purpose input and
output.
P12 is multiplexed on pin 43 with IRRX1 and DRATE0, on pin 46 with
MTR1, and on pin 94 with DCD2.
Group 7
P21,P20
PD7-0
64,63
82-75
KBC
I/O
I/O Port – KBC open-drain signals for general purpose input and
output. These signals are controlled by KBC firmware.
Group 7
Parallel Port
I/O
Parallel Port Data – These bidirectional signals transfer data to and
from the peripheral data bus and the appropriate parallel port data
register. These signals have a high current drive capability. See
Section 10.1.
Group 9
PE
70
54
Parallel Port
FDC
Input
Paper End – This input signal is set high by the printer when it is out
of paper. This pin has an internal weak pull-up or pull-down resistor.
Group 2
Group 3
RDATA
Input
Read Data – This input signal holds raw serial data read from the
Floppy Disk Drive (FDD).
Group 1
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16
Signal/Pin Connection and Description
I/O and
Signal/Pin
Name
Pin
Number
Module
Function
Group #
RI2,1
97,87
UART1
Input
Ring Indicators (Modem) – When low, this signal indicates that a
telephone ring signal has been received by the modem.
Group 1
The RI1 and RI2 pins have schmitt-trigger input buffers.
RI2 is multiplexed with DENSEL and available only in Two-UART
mode.
RTS2,1
98,88
UART1,
UART2
Output Request to Send – When low, these output signals indicate to the
modem or other data transfer device that the corresponding UART1
Group 12
or UART2 is ready to exchange data.
A Master Reset (MR) sets RTS to inactive high. Loopback operation
holds it inactive.
RTS2 is multiplexed on pin 98 with IRSL1 and ID1, and available only
in Two-UART mode. RTS1 is multiplexed on pin 88 with BADDR1.
SIN2,1
99,89
UART1,
UART2
Input
Serial Input – This input signal receives composite serial data from
the communications link (peripheral device, modem or other data
transfer device).
Group 1
SIN2 is multiplexed on pin 99 with ID3 and available only in Two-
UART mode.
SLCT
SLIN
69
73
Parallel Port
Parallel Port
Input
Select – This input signal is set active high by the printer when the
printer is selected. This pin is internally connected to a nominal 25 KΩ
pull-down resistor.
Group 2
I/O
Select Input – When this signal is active low it selects the printer.
This signal is in TRI-STATE after a 0 is loaded into the corresponding
control register bit. Use an external 4.7 KΩ pull-up resistor.
Group 8
This signal is multiplexed with ASTRB.
SOUT2,1
100,92
UART1,
UART2
Output Serial Output – This output signal sends composite serial data to the
communications link (peripheral device, modem or other data transfer
Group 12
device).
The SOUT2,1 signals are set active high after a Master Reset (MR).
SOUT2 is multiplexed on pin 100 with IRRX2, IRSL0 and ID0, and is
available only in Two-UART mode.
SOUT1 is multiplexed on pin 92 with CFG0.
STB
67
Parallel Port
I/O
Data Strobe – This output signal indicates to the printer that valid
data is available at the printer port.
Group 8
This signal is in TRI-STATE after a 0 is loaded into the corresponding
control register bit.
An external 4.7 KΩ pull-up resistor should be employed.
For Input mode see bit 5, described in Section 4.5.16.
This signal is multiplexed with WRITE.
STEP
TC
51
25
FDC
Output Step – This output signal issues pulses to the disk drive at a software
programmable rate to move the head during a seek operation.
Group 11
ISA-Bus
Input
DMA Terminal Count – The DMA controller issues TC to indicate the
termination of a DMA transfer. TC is accepted only when a DACK
signal is active.
Group 1
TC is active high in PC-AT mode, and active low in PS/2 mode.
TRK0
VDD
55
FDC
Input
Track 0 – This input signal indicates to the controller that the head of
the selected floppy disk drive is at track 0.
Group 1
90,41
Power
Input
Main 5 V Power Supply – This signal is the 5 V supply voltage for
the digital circuitry.
Supply
VSS
91,65,40,
15
Power
Output Ground – This signal provides the ground for the digital circuitry.
Supply
WAIT
66
Parallel Port
Input
Wait – In EPP mode, the parallel port device uses this signal to
extend its access cycle. WAIT is active low. This signal is multiplexed
with BUSY. See TABLE 4-12 on page 101 for more information.
Group 2
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17
Signal/Pin Connection and Description
I/O and
Signal/Pin
Name
Pin
Number
Module
Function
Group #
WDATA
49
FDC
Output Write Data (FDC) – This output signal holds the write
precompensated serial data that is written to the selected floppy disk
Group 11
drive. Precompensation is software selectable.
WGATE
53
FDC
Output Write Gate (FDC) – This output signal enables the write circuitry of
the selected disk drive. WGATE is designed to prevent glitches during
Group 11
power up and power down. This prevents writing to the disk when
power is cycled.
WP
57
67
FDC
Input
Write Protected – This input signal indicates that the disk in the
selected drive is write protected.
Group 1
WRITE
Parallel Port
Output Write Strobe – In EPP mode, this active low signal is a write strobe.
Group 8 This signal is multiplexed with STB. See TABLE 4-12 on page 101 for
more information.
TABLE 1-2. Multiplexed Pins in Full-IR and Two-UART Modes
Full-IR Mode
CFG0 = 0
Two-UART Mode
CFG0 = 1
Pin
Signal/Pin Name
Direction
Signal/Pin Name
Direction
93
94
95
96
97
98
99
100
A11
P12
I
CTS2
DCD2
I
I
I/O
O
DRATE0
IRSL2/ID2
DENSEL
IRSL1/ID1
ID3
DSR2
I
I/O
I/O
I/O
I
DTR2/BOUT2
RI2
O
I
RTS2
O
I
SIN2
IRRX2/IRSL0/ID0
IRRX1
I/O
I
SOUT2
O
I/O
431
441
451
461
481
IRRX1/P12/DRATE0
IRTX
MTR0
MTR1
DR1
O
O
O
O
IRTX/DENSEL
MTR0/DRATE0
MTR1/P12
O
O
I/O
O
DR1/DENSEL
1. These pins have additional multiplexing options in Two-UART mode,
controlled by a configuration register. They do not automatically
change functions.
TABLE 1-3. Pins with a Strap Function During Reset
Function
Pin
Symbols
BADDR0
BADDR1
CFG0
86
88
92
DTR1/BOUT1/BADDR0
RTS1/BADDR1
SOUT1/CFG0
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18
Configuration
●
PnP Motherboard mode – system wakes up in Config
state.
2.0 Configuration
The PC87309VLJ is partially configured by hardware, dur-
ing reset. The configuration can also be changed by soft-
ware, by changing the values of the configuration registers.
The BIOS configures the PC87309VLJ. Index and Data
register addresses are different from the addresses of
the PnP Index and Data registers. Configuration regis-
ters can be accessed as if the serial isolation procedure
had already been done, and the PC87309VLJ is select-
ed.
The configuration registers are accessed using an Index
register and a Data register. During reset, hardware strap-
ping options define the addresses of the configuration reg-
isters. See Section 2.1.2 "The Index and Data Register
Pair".
The BIOS may switch the addresses of the Index and
Data registers to the PnP ISA addresses of the Index
and Data registers, by using software to modify the base
address bits, as shown in Section 2.4.3 on page 29.
After the Index and Data register pair have determined the
addresses of the configuration registers, the addresses of
the Index and Data registers can be changed within the ISA
I/O address space, and a 11-bit programmable register con-
trols references to their addresses and to the addresses of
the other registers.
CFG0 strap-pin selects between the following two modes:
●
Mode 1: Full-IR Mode
UART1 works as UART; UART2 works as fully IR-
compliant device
This chapter describes the hardware and software configu-
ration processes. For each, it describes configuration of the
Index and Data register pair first. See Sections 2.1 "HARD-
WARE CONFIGURATION" and 2.2 "SOFTWARE CON-
FIGURATION" on page 20.
●
Mode 2: Two-UART Mode
Either both UART1 and UART2 work as UARTs, or
UART 1 works as UART and UART2 works as partially
IR-compliant device, providing only IRRX and IRTX
support
Section 2.3 "THE CONFIGURATION REGISTERS" on
page 21 presents an overview of the configuration registers
of the PC87309VLJ and describes each in detail.
2.1.2
The Index and Data Register Pair
During reset, a hardware strapping option on the BADDR0
and BADDR1 pins defines an address for the Index and
Data Register pair.
2.1 HARDWARE CONFIGURATION
The PC87309VLJ Hardware Cofiguration is based on three
strap-pins: BADDR0, BADDR1 and CFG0.
TABLE 2-1 "Strap Pins and Base Addresses" shows the
base addresses for the Index and Data registers that hard-
ware sets for each combination of values of the Base Ad-
dress strap pins (BADDR0 and BADDR1). You can access
and change the content of the configuration registers at any
time, as long as the base addresses of the Index and Data
registers are defined.
The PC87309VLJ wakes up with the KBC active (enabled)
and all the other logical devices wake up inactive (disabled).
This is always true and is not affected by strapping.
Clock source is 48MHz, fed via CLKIN.
2.1.1
Wake Up Options
When BADDR1 is low (0), the PnP protocol defines the ad-
dresses of the Index and Data register, and the system
wakes up from reset in the Wait for Key state.
The PC87309VLJ supports three available Wake Up Op-
tions:
●
When BADDR1 is high (1), the addresses of the Index and
Data register are according to TABLE 2-1 "Strap Pins and
Base Addresses", and the system wakes up from reset in
the Config state.
Full PnP ISA with Full-IR mode.
●
PnP Motherboard with Full-IR mode.
●
PnP Motherboard with Two-UART mode.
This configures the PC87309VLJ with default values, auto-
matically, without software intervention. After reset, use
software as described in Section 2.2 "SOFTWARE CON-
FIGURATION" on page 20 to modify the selected base ad-
dress of the Index and Data register pair, and the defaults
for configuration registers.
TABLE 2-1 "Strap Pins and Base Addresses" on page 20
shows the strap pins and their applicable wake up options.
The three available wake up options are a combination of
the four basic modes which are determined by three strap-
pins during reset:
BADDR0 and BADDR1 strap-pins select one of two basic
modes.
The PnP soft reset has no effect on the logical devices, ex-
cept for the effect of the Activate registers (index 30h) in
each logical device.
●
Full PnP ISA mode – System wakes up in Wait for Key
state. (Not available when in Two-UART mode - see
CFG0 in TABLE 2-1).
Index and Data register addresses are as defined in the
“Plug and Play ISA Specification, Version 1.0a, May 5,
1994.”
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19
Configuration
TABLE 2-1. Strap Pins and Base Addresses
Address
CFG0
BADDR1
BADDR0
Configuration Type
Index Register
Data Register
0279h
Write: 0A79h
Full PnP ISA mode
Full-IR mode
0
0
0
1
1
0
1
1
x
x
x
0
1
0
1
Write Only
Read: RD_DATA Port
PnP Motherboard mode
Full-IR mode
015Ch Read/Write
002Eh Read/Write
015Ch Read/Write
002Eh Read/Write
015Dh Read/Write
002Fh Read/Write
015Dh Read/Write
002Fh Read/Write
PnP Motherboard mode
Full-IR mode
PnP Motherboard mode
Two-UART mode
PnP Motherboard mode
Two-UART mode
2.2 SOFTWARE CONFIGURATION
2.2.1 Accessing the Configuration Registers
2.2.2
Address Decoding
The address decoding of all logical devices, as well as the
configuration registers, consists of 11 non-zero address bits
(A10-0) and AEN. The supported I/O range is 0 to 3FFh.
The only non-zero A11 address decoding is the PnP
WRITEA_DATA port at ISA address A79h, when working in
full PnP mode.
Only two system I/O addresses are required to access any
of the configuration registers. The Index and Data register
pair is used to access registers for all read and write opera-
tions.
In a write operation, the target configuration register is iden-
tified, based on a value that is loaded into the Index register.
Then, the data to be written into the configuration register is
transferred via the Data register.
In full PnP mode, the addresses of the Index and Data reg-
isters that access the Configuration Registers are decoded
using pins A10-0, according to the ISA PnP specification.
In PnP Motherboard mode, the addresses of the Index and
Data registers that access the Configuration Registers are
decoded using pins A10-1. Pin A0 distinguishes between
these two registers.
Similarly, for a read operation, first the source configuration
register is identified, based on a value that is loaded into the
Index register. Then, the data to be read is transferred via
the Data register.
KBC and mouse register addresses are decoded using pins
A1,0 and A10-3. Pin A2 distinguishes between the device
registers.
Reading the Index register returns the last value loaded into
the Index register. Reading the Data register returns the
data in the configuration register pointed to by the Index
register.
Power Management (PM) register addresses are decoded
using pins A10-1.
If, during reset, the Base Address 1 (BADDR1) signal is low
(0), the Index and Data registers are not accessible imme-
diately after reset. As a result, all configuration registers of
the PC87309VLJ are also not accessible at this time. To ac-
cess these registers, you must apply the PnP ISA protocol.
FDC and UART register addresses are decoded using pins
A10-3.
Parallel Port (PP) modes determine which pins are used for
register addresses. TABLE 2-2 shows which address pins
are used to decode base address and which address pins
are used to distinguish between registers in each mode.
If during reset, the Base Address 1 (BADDR1) signal is high
(1), all configuration registers are accessible immediately
after reset.
TABLE 2-2. Address Pins Used for Parallel Port
It is up to the configuration software to guarantee no con-
flicts between the registers of the active (enabled) logical
devices, between IRQ signals and between DMA channels.
If conflicts of this type occur, the results are unpredictable.
Pins Used to
PP Mode Decode Base Distinguish between
Pins Used to
Address
Registers
To maintain compatibility with other SuperI/O‘s, the value of
reserved bits may not be altered. Use read-modify-write.
SPP
ECP
EPP
A10-2
A9-2
A1,0
A1,0 and A10
A2-0
A10-3
NOTE: When working with the Parallel Port in ECP mode
and enabling the registers at base (address)+403h,
base+404h, base+405h (the default state) both the
Parallel Port base address and the ECP registers
are 8 byte aligned and take 8 bytes of the I/O
space.
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20
Configuration
TABLE 2-3. Parallel Port Address Range Allocation
SuperI/O Parallel Port
a
Configuration Register Bits
Parallel Port Mode
Decoded Range
7
6
5
4
SPP
0
0
x
x
x
Three registers, from base (address) to base + 02h
Eight registers, from base to base + 07h
EPP (Non IEEE1284 Mode 4)
0
1
x
IEEE1284, No Mode 4,
No Internal Configuration
Six registers, from base to base + 02h and from
base + 400h to base + 402h
1
1
0
1
0
1
0
0
IEEE1284 with Mode 4,
No Internal Configuration
11 registers, from base to base + 07h and from
base + 400h to base + 402h
1
1
0
1
0
1
1
1
16 registers, from base to base + 07h and from
base + 400h to base + 407h
IEEE1284 with Mode 4,
Configuration within Parallel Port
or
a. The SuperI/O processor does not decode the Parallel Port outside this range.
●
A15-11 are read only 0 in all base address registers. To en-
sure full 16-bit decoding as required by PC95/PC97, you
must externally decode A15-11 (in Two-UART mode) or
A15-12 (in Full-IR mode), and drive them via AEN as shown
below:
FDC Configuration Registers (Logical Device 0)
— SuperI/O FDC Configuration Register
— Drive ID Register
●
●
SuperI/O Parallel Port Configuration Register (Logical
Device 1)
●
In Two-UART mode (A11 not available)
AEN<=(AEN|A11|A12|A13|A14|A15)
where | = logical OR
SuperI/O UART2 and Infrared Configuration Register
(Logical Device 2)
●
In Full-IR mode (A11 available on pin 93)
AEN<=(AEN|A12|A13|A14|A15)
where | = logical OR
●
●
SuperI/O UART1 Configuration Register (Logical De-
vice 3)
SuperI/O KBC Configuration Register (Logical Device 6)
2.3 THE CONFIGURATION REGISTERS
2.3.1
Standard Plug and Play (PnP) Register Definitions
The configuration registers control the setup of the
PC87309VLJ. Their major functions are to:
TABLES 2-4 through 2-9 describe the standard PnP regis-
ters. For more detailed information on these registers,
refer the “Plug and Play ISA Specification, Version 1.0a,
May 5, 1994”
●
Identify the chip
●
Enable major functions (such as, the Keyboard Control-
ler (KBC) for the keyboard and the mouse, the Floppy
Disc Controller (FDC), UARTs, parallel and general pur-
pose ports, power management and pin functionality)
●
Define the I/O addresses of these functions
●
Define the status of these functions upon reset
Section 2.3.2 "Configuration Register Summary" on page
25 summarizes information for each register of each func-
tion. In addition, the following non-standard, or card control,
registers are described in detail, in Section 2.4 "CARD
CONTROL REGISTERS" on page 28.
●
Card Control Registers
— SID Register
— SuperI/O Configuration 1 Register (SIOCF1)
— SuperI/O Configuration 2 Register (SIOCF2)
— SRID Register
— NSC-Test Register
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21
Configuration
TABLE 2-4. Plug and Play (PnP) Standard Control Registers
Name Description
Index
00h
Set RD_DATA Port Writing to this location modifies the address of the port used for reading from the
PnP ISA cards. Data bits 7-0 are loaded into I/O read port address bits 9-2.
Reads from this register are ignored. Bits1 and 0 are fixed at the value 11.
01h
02h
Serial Isolation Reading this register causes a PnP card in the Isolation state to compare one bit
of the ID of the board. This register is read only.
Config Control
This register is write-only. The values are not sticky, that is, hardware automatically
clears the bits and there is no need for software to do so.
Bit 0 - Reset
Writing this bit resets all logical devices (except the KBC, Logical Device 6) and
restores the contents of configuration registers to their power-up (default) values.
In addition, all the logical devices enter their default state and the CSN is
preserved.
Bit 1 - Return to the Wait for Key state.
Writing this bit puts the device in the Wait for Key state, with CSN preserved and
logical devices not affected. This bit is ignored in Motherboard PnP mode.
Bit 2 - Reset CSN to 0.
03h
Wake[CSN]
A write to this port causes all cards that have a CSN that matches the write data
in bits 7-0 to go from the Sleep state to either the Isolation state, if the write data
for this command is zero, or the Config state, if the write data is not zero. It also
resets the pointer to the byte-serial device.
This register is write-only.
04h
005
06h
Resource Data This address holds the next byte of resource information. The Status register must
be polled until bit 0 of this register is set to 1 before this register can be read.
This register is read-only.
Status
When bit 0 of this register is set to 1, the next data byte is available for reading
from the Resource Data register.
This register is read-only.
Card Select
Writing to this port assigns a CSN to a card. The CSN is a value uniquely assigned
Number (CSN) to each ISA card after the serial identification process so that each card may be
individually selected during a Wake[CSN] command.
This register is read/write.
07h
Logical Device This register selects the current logical device. All reads and writes of memory, I/O,
Number
interrupt and DMA configuration information access the registers of the logical
device written here. In addition, the I/O Range Check and Activate commands
operate only on the selected logical device.
This register is read/write.
Vendor defined registers.
20h - 2Fh
Card Level,
Vendor Defined
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22
Configuration
TABLE 2-5. Plug and Play (PnP) Logical Device Control Registers
Index
Name
Activate
Definition
0030h
For each logical device there is one Activate register that controls whether or not
the logical device is active on the ISA bus.
This is a read/write register.
Before a logical device is activated, I/O Range Check must be disabled.
Bit 0 - Logical Device Activation Control
0: Do not activate the logical device.
1: Activate the logical device.
Bits 7-1 - Reserved
These bits are reserved and return 0 on reads.
0031h
I/O Range Check This register is used to perform a conflict check on the I/O port range programmed
for use by a logical device.
This register is read/write.
Bit 0 - I/O Range Check control
0: The logical device drives 00AAh.
1: The logical device responds to I/O reads of the logical device's assigned I/O
range with a 0055h when I/O Range Check is enabled.
Bit 1 - Enable I/O Range Check
0: I/O Range Check is disabled.
1: I/O Range Check is enabled. (I/O Range Check is valid only when the logical
device is inactive).
Bits 7-2 - Reserved
These bits are reserved and return 0 on reads.
TABLE 2-6. Plug and Play (PnP) I/O Space Configuration Registers
Index
Name
Definition
60h
I/O Port Base
Read/write value indicating the selected I/O lower limit address bits 15-8 for I/O
Address Bits (15-8) descriptor 0. Bits 7-3 (for A15-11) are read only 00000b.
Descriptor 0
61h
62h
63h
I/O Port Base
Address Bits (7-0) descriptor 0.
Descriptor 0
Read/write value indicating the selected I/O lower limit address bits 7-0 for I/O
I/O Port Base
Read/write value indicating the selected I/O lower limit address bits 15-8 for I/O
Address Bits (15-8) descriptor 1. Bits 7-3 (for A15-11) are ready only 00000b.
Descriptor 1
I/O Port Base
Address Bits (7-0) descriptor 1.
Descriptor 1
Read/write value indicating the selected I/O lower limit address bits 7-0 for I/O
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23
Configuration
TABLE 2-7. Plug and Play (PnP) Interrupt Configuration Registers
Index
Name
Definition
70h
Interrupt Request Read/write value indicating selected interrupt level.
Level Select 0
Bits3-0 select the interrupt level used for interrupt 0. A value of 1 selects IRQL 1, a
value of 15 selects IRQL 15. IRQL 0 is not a valid interrupt selection and
(represents no interrupt selection.
71h
Interrupt Request Read/write value that indicates the type and level of the interrupt request level
Type Select 0
selected in the previous register.
If a card supports only one type of interrupt, this register may be read-only.
Bit 0 - Type of the interrupt request selected in the previous register.
0: Edge
1: Level
Bit1 - Level of the interrupt request selected in the previous register. (See also
Section 9.1).
0: Low polarity. (Implies open-drain output with strong pull-up for a short time,
followed by weak pull-up).
1: High polarity. (Implies push-pull output).
TABLE 2-8. Plug and Play (PnP) DMA Configuration Registers
Index
Name
Definition
74h
DMA Channel
Select 0
Read/write value indicating selected DMA channel for DMA 0.
Bits 2-0 select the DMA channel for DMA 0. A value of 0 selects DMA channel 0;
a value of 7 selects DMA channel 7.
Selecting DMA channel 4, the cascade channel, indicates that no DMA channel is
active.
75h
DMA Channel
Select 1
Read/write value indicating selected DMA channel for DMA 1
Bits 2-0 select the DMA channel for DMA 1. A value of 0 selects DMA channel 0;
a value of 7 selects DMA channel 7.
Selecting DMA channel 4, the cascade channel, indicates that no DMA channel is
active.
TABLE 2-9. Plug and Play (PnP) Logical Device Configuration Registers
Index
Name
Definition
F0h-FEh
Logical Device Vendor defined.
Configuration
Vendor Defined
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24
Configuration
2.3.2
Configuration Register Summary
The tables in this section specify the Index, type (read/write),
reset values and configuration register or action that controls
each register associated with each function.
Access to the KBC Configuration Registers for Logical De-
vice 6 (see TABLE 2-17 "KBC Configuration Registers for
Keyboard - Logical Device 6" on page 28) is controlled by
bit 4 of the SIOCF1 Register. Setting this bit to 1 locks the
KBC Configuration Registers and disables access to Logi-
cal Device 6. All writes are ignored and all reads return 0
when you attempt to access the locked registers. However,
locking the KBC configuration registers does not affect ac-
cess to the KBC Command Data and Status Registers.
When the reset value is not fixed, the table indicates what
controls the value or points to another section that provides
this information.
Soft reset is related to a reset executed by utilizing the reset
bit (bit 0) of the Configuration Control Register. (See TABLE
2-4 "Plug and Play (PnP) Standard Control Registers" on
page 22.
TABLE 2-10. Card Control Registers
Index Type
Hard Reset
Soft Reset
Configuration Register or Action
Set RD_DATA Port.
00h
01h
02h
03h
04h
05h
06h
07h
20h
W
R
00h
PnP ISA
Serial Isolation.
W
PnP ISA
00h
PnP ISA
PnP ISA
Configuration Control.
Wake[CSN].
W
R
Resource Data.
R
Status.
R/W
R/W
R
00h
00h
E0h
PnP ISA
PnP ISA
E0h
Card Select Number (CSN).
Logical Device Number.
Read only SID Register.
Bits 2-0 - Revision ID
Bit 7-3 - Chip ID
21h
22h
27h
R/W
R/W
R
See Section 2.4.2.
See Section 2.4.3.
xx
No Effect
No Effect
xx
SuperI/O Configuration 1 Register (SIOCF1).
SuperI/O Configuration 2 Register (SIOCF2).
SRID Register.
Bits 7-0 - Revision ID
2Eh
xx
xx
Reserved for National Semiconductor use only.
TABLE 2-11. FDC Configuration Registers - Logical Device 0
Index R/W
Hard Reset
Soft Reset
Configuration Register or Action
Activate.
30h
R/W
00h or 01h
00h or 01h
See CFG0 in
Section 2.1.1.
See CFG0 in See also FER1 of the Power Management device
Section 2.1.1. (Logical Device 4).
31h
60h
R/W
R/W
00h
03h
00h
03h
I/O Range Check.
Base Address MSB Register.
Bits 7-3 (for A15-11) are read only, 00000b.
61h
R/W
F2h
F2h
Base Address LSB Register.
Bits 2 and 0 (for A2 and A0) are read only, 0,0.
70h
71h
R/W
R/W
06h
03h
06h
03h
Interrupt Select.
Interrupt Type.
Bit 1 is read/write; other bits are read only.
74h
75h
F0h
F1h
R/W
R
02h
02h
DMA Channel Select.
04h
04h
Report no DMA assignment.
SuperI/O FDC Configuration Register.
Drive ID Register.
R/W
R/W
See Section 2.5.1.
See Section 2.5.2.
No Effect
No Effect
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25
Configuration
TABLE 2-12. Parallel Port Configuration Registers - Logical Device 1
Index R/W
Hard Reset
Soft Reset
Configuration Register or Action
Activate.
30h
R/W
00h
00h
See also FER1 of the Power Management device
(Logical Device 4).
31h
60h
R/W
R/W
00h
02h
00h
02h
I/O Range Check.
Base Address MSB register.
Bits 7-3 (for A15-11) are read only, 00000b.
61h
R/W
78h
78h
Base Address LSB register.
Bits 1,0 (for A1,0) are read only, 00b.
See Section 2.2.2 on page 20.
70h
71h
R/W
R/W
07h
00h
07h
00h
Interrupt Select.
Interrupt Type.
Bit 0 is read only. It reflects the interrupt type
dictated by the Parallel Port operation mode and
configured by the SuperI/O Parallel Port
Configuration register. This bit is set to 1 (level
interrupt) in Extended Mode and cleared (edge
interrupt) in all other modes.
Bit 1 is a read/write bit.
Bits 7-2 are read only.
74h
75h
F0h
R/W
R
04h
04h
04h
04h
DMA Channel Select.
Report no DMA assignment.
R/W
See Section 2.6
No Effect
SuperI/O Parallel Port Configuration register.
TABLE 2-13. UART2 and Infrared Configuration Registers - Logical Device 2
Index R/W
Hard Reset
Soft Reset
Configuration Register or Action
Activate.
30h
R/W
00h
00
See also FER1 of the Power Management device
(Logical Device 4).
31h
60h
R/W
R/W
00h
02h
00h
02h
I/O Range Check.
Base Address MSB register.
Bits 7-3 (for A15-11) are read only, 00000b.
61h
R/W
F8h
F8h
Base Address LSB register.
Bit 2-0 (for A2-0) are read only, 000b.
70h
71h
R/W
R/W
03h
03h
03h
03h
Interrupt Select.
Interrupt Type.
Bit 1 is R/W; other bits are read only.
74h
75h
F0h
R/W
R/W
R/W
04h
04h
04h
04h
DMA Channel Select 0 (RX_DMA).
DMA Channel Select 1 (TX_DMA).
SuperI/O UART2 Configuration register.
See Section 2.7
No Effect
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26
Configuration
TABLE 2-14. UART1 Configuration Registers - Logical Device 3
Index R/W
Hard Reset
Soft Reset
Configuration Register or Action
Activate.
30h R/W
00h
00h
See also FER1 of the Power Management device
(Logical Device 4).
31h R/W
60h R/W
00h
03h
00h
03h
I/O Range Check.
Base Address MSB Register.
Bits 7-3 (for A15-11) are read only, 00000b.
61h R/W
F8h
F8h
Base Address LSB Register.
Bits 2-0 (for A2-0) are read only as 000b.
70h R/W
71h R/W
04h
03h
04h
03h
Interrupt Select.
Interrupt Type.
Bit 1 is read/write. Other bits are read only.
74h
75h
R
R
04h
04h
04h
04h
Report no DMA Assignment.
Report no DMA Assignment.
F0h R/W
See Section 2.8
No Effect
SuperI/O UART 1 Configuration register.
TABLE 2-15. Power Management Configuration Registers - Logical Device 4
Index R/W
Hard Reset
Soft Reset
Configuration Register or Action
Activate.
30h
R/W
00
00
When bit 0 is cleared, the registers of this logical
device are not accessible. The registers are
maintained.
31h
60h
R/W
R/W
00h
00h
00h
00h
I/O Range Check.
Base Address MSB register.
Bits 7-3 (for A15-11) are read only, 00000b.
61h
R/W
00h
00h
Base Address LSB Register.
Bit 0 (for A0) is read only 0.
74h
75h
R
R
04h
04h
04h
04h
Report no DMA assignment.
Report no DMA assignment.
TABLE 2-16. KBC Configuration Registers for Mouse - Logical Device 5
Index R/W
Hard Reset
Soft Reset
Configuration Register or Action
Activate.
30h
R/W
00h
00h
When the mouse of the KBC mouse is inactive,
the IRQ selected by the Mouse Interrupt Select
Register (index 70h) is not asserted.
This register has no effect on host KBC
commands handling the PS/2 mouse.
70h
71h
R/W
R/W
0Ch
02h
0Ch
02h
Mouse Interrupt (KBC IRQ12 pin) Select.
Mouse Interrupt Type.
Bits 1,0 are read/write; other bits are read only.
74h
75h
R
R
04h
04h
04h
04h
Report no DMA assignment.
Report no DMA assignment.
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27
Configuration
TABLE 2-17. KBC Configuration Registers for Keyboard - Logical Device 6
Index R/W
Hard Reset
Soft Reset
Configuration Register or Action
Activate.
30h
R/W
01h
No Effect
See also FER1 of Power Management device
(Logical Device 4).
31h
60h
R/W
R/W
00h
00h
No Effect
No Effect
I/O Range Check.
Base Address MSB Register.
Bits 7-3 (for A15-11) are read only, 00000b.
Base Address LSB Register.
61h
62h
63h
R/W
R/W
R/W
60h
00h
64h
No Effect
No Effect
No Effect
Bits 2-0 are read only 000b.
Command Base Address MSB Register.
Bits 7-3 (for A15-11) are read only, 00000b.
Command Base Address LSB.
Bits 2-0 are read only 100b.
70h
71h
R/W
RW
01h
02h
No Effect
No Effect
KBC Interrupt (KBC IRQ1 pin) Select.
KBC Interrupt Type.
Bits 1,0 are read/write; others are read only.
Report no DMA assignment.
74h
75h
F0h
R
R
04h
04h
No Effect
No Effect
No Effect
Report no DMA assignment.
R/W
See Section 2.9.
SuperI/O KBC Configuration Register.
2.4 CARD CONTROL REGISTERS
SuperI/O Configuration 1
0
Register (SIOCF1),
This section describes the registers at first level indexes in
the range 20h - 2Fh.
7
0
6
0
5
0
4
3
2
1
1
Index 21h
0
x
x
x
Reset
2.4.1
SID Register
Required
BADDR0
This read-only register contains the identity number of the
chip. The PC87309VLJ is identified by the value E0h in this
register.
BADDR1
PC-AT or PS/2 Drive Mode Select
CFG0
KBC-Lock
Lock Scratch Bit
SID
7
1
6
1
5
1
4
3
2
0
1
0
Register,
0
0
0
0
Reset
Index 20h
1
1
1
0
0
0
0
0
Required
General Purpose Scratch Bits
Bit 1,0 - BADDR1 and BADDR0
Initialized on reset by BADDR1 and BADDR0 strap pins
(BADDR0 on bit 0). These bits select the addresses of
the configuration Index and Data registers and the PnP
ISA Serial Identifier. See TABLE 2-1 "Strap Pins and
Base Addresses" on page 20.
Chip ID
Bit 2 - PC-AT or PS/2 Drive Mode Select
0: PS/2 drive mode.
2.4.2
SuperI/O Configuration 1 Register (SIOCF1)
This register can be read or written. It is reset by hardware
according to the BADDRs and the CFG0 strap pins see TA-
BLE 2-1 "Strap Pins and Base Addresses" on page 20.
1: PC-AT drive mode. (Default)
Bit 3 - CFG0 Bit
Initialized on reset by CFG0 strap pin. This read-only bit
selects between Full-IR and Two-UART modes.
0: Full-IR mode.
1: Two-UART mode.
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28
Configuration
Bit 4 - KBC-Lock
Bit 1 - MTR1/P12 Select
0: Pin 46 is MTR1
This bit Locks the access to the configuration registers
of the KBC, Logical Device 6.
1: Pin 46 is P12 (open drain with MTR1 current sink
characteristics)
0: Access is enabled.
1: Access is disabled. Writes are ignored and reads
returns 0 upon access to Logical Device 6.
Bit 2 - DR0,1 Function
DR0 and DR1 function in a single, motor-drive-select
operation. DR0 is affected only when MTR0 is de-se-
lected (bit 0 is set to 1); DR1 is affected only when MTR1
is de-selected (bit 1 is set to 1).
Bit 5 - Lock Scratch Bit
This bit controls bits 7 and 6 of this register. Once this
bit is set to 1 by software, it can be cleared to 0 only by
a hardware reset.
0: No change in DR0,1 function
0: Bits 7 and 6 of this register are read/write bits.
1: Bits 7 and 6 of this register are read only bits.
1: DR0,1 become a logical OR of DR0,1 and MTR0,1
when bits 0,1 are set to 1, respectively.
Bit 3 - DR1/DENSEL Select
0: Pin 48 is DR1
Bits 7,6 - General Purpose Scratch Bits
When bit 5 is set to 1, these bits are read only. After re-
set they can be read or written. Once changed to read-
only, they can be changed back to be read/write bits
only by a hardware reset.
1: Pin 48 is DENSEL
Bits 5,4 - IRRX/P12/DRATE0 Select
X0:Pin 43 is IRRX1
2.4.3
SuperI/O Configuration 2 Register (SIOCF2)
01: Pin 43 is P12
11: Pin 43 is DRATE0
This is a read/write register in Two-UART mode only. (In
Full-IR mode, it is a read only 00h register and cannot be
modified.) It controls the function multiplexing of the follow-
ing pins:
Bit 6 - IRTX/DENSEL Select
0: Pin 44 is IRTX
1: Pin 44 is DENSEL (with IRTX DC characteristics)
●
Pin 43 - IRRX/P12/DRATE0
●
Bit 7 - Reserved
Pin 44 - IRTX/DENSEL
This is read only 0.
●
Pin 45 - MTR0/DRATE0
●
2.4.4
SRID Register
Pin 46 - MTR1/P12
●
This read-only register contains the identity number of the
chip revision. SRID is incremented on each revision.
Pin 48 - DR1/DENSEL
In addition, it controls the function of DR0,1 pins when
MTR0,1 are de-selected.
SRID
Register,
Index 27h
7
6
x
5
x
4
3
2
1
0
Configuring the same function by software on more than
one pin is illegal, and may cause unpredictable results.
x
x
x
x
x
x
Reset
Required
SuperI/O Configuration 2
7
0
6
0
5
0
4
3
2
0
1
0
Register (SIOCF2),
Index 22h
0
0
0
0
Reset
Required
MTR0/DRATE0 Select
Chip Revision ID
MTR1/P12 Select
DR0,1 Function
DR1/DENSEL Select
IRRX1/P12/DRATE0 Select
IRTX/DENSEL Select
Reserved
Bit 0 - MTR0/DRATE0 Select
0: Pin 45 is MTR0
1: Pin 45 is DRATE0 (with MTR0 DC characteristics)
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29
Configuration
2.5.2
2.5 FDC CONFIGURATION REGISTERS (LOGICAL
DEVICE 0)
Drive ID Register
This read/write register is reset by hardware to 00h. These
bits control bits 5 and 4 of the enhanced TDR register.
2.5.1
SuperI/O FDC Configuration Register
This read/write register is reset by hardware to 20h.
7
0
6
0
5
0
4
3
2
0
1
0
Drive ID Register,
Index F1h
0
0
0
0
Reset
Super I/O FDC
Configuration
Register,
7
0
6
0
5
1
4
3
2
0
1
0
Required
0
0
0
0
Reset
Required
Index F0h
Drive 0 ID
TRI-STATE Control
Drive 1 ID
Reserved
DENSEL Polarity Control
TDR Register Mode
Four Drive Control
Reserved
Bits 1,0 - Drive 0 ID
These bits are reflected on bits 5 and 4, respectively, of
the Tape Drive Register (TDR) of the FDC when drive 0
is accessed. See Section 3.3.4 "Tape Drive Register
(TDR)" on page 41.
Bit 0 - TRI-STATE Control
When set, this bit causes the FDC pins to be in TRI-
STATE (except the IRQ and DMA pins) when the FDC is
inactive (disabled).
Bits 3,2 - Drive 1 ID
This bit is ORed with a bit of PMC1 register of Logical
Device 4.
These bits are reflected on bits 5 and 4, respectively, of
the TDR register of the FDC when drive 1 is accessed.
See Section 3.3.4 "Tape Drive Register (TDR)" on page
41.
0: FDC pins are not put in TRI-STATE.
1: FDC pins are put in TRI-STATE.
Bits 7-4 - Reserved
Bits 4-1 - Reserved
2.6 SUPERI/O PARALLEL PORT CONFIGURATION
REGISTER (LOGICAL DEVICE 1)
Bit 5 - DENSEL Polarity Control
0: DENSEL is active low for 500 Kbps or 1 Mbps data
rates.
This read/write register is reset by hardware to F2h. To
maintain compatibility with future chips, it is recommended
not to change bits 7-4 during normal operation. Before
changing from any EPP mode to another mode, initialize
bits 3-0 of CTR to 0100b. (See 4.2.4 on page 81.)
1:
DENSEL is active high for 500 Kbps or 1 Mbps
data rates. (Default)
Bit 6 - TDR Register Mode
0: PC-AT Compatible drive mode (bits 7 through 2 of
TDR are not driven).
SuperI/O Parallel Port
7
1
6
1
5
1
4
3
2
0
1
0
Configuration Register,
Index F0h
1: Enhanced drive mode (bits 7 through 2 of TDR are
driven on TDR read).
1
0
1
0
Reset
Required
Bit 7 - Four Drive Control
0: Two floppy drives are directly controlled by DR1-0,
MTR1-0.
TRI-STATE Control
Clock Enable
Reserved
Reserved
Configuration Bits within the Parallel Port
1: Four floppy drives are controlled with the aid of an
external decoder.
Parallel Port Mode Select
Bit 0 - TRI-STATE Control
When set, this bit causes the parallel port pins to be in
TRI-STATE (except IRQ and DMA pins) when the paral-
lel port is inactive (disabled). This bit is ORed with a bit
of the PMC1 register of Logical Device4.
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30
Configuration
2.7 SUPERI/O UART2 AND INFRARED
Bit 1 - Clock Enable
CONFIGURATION REGISTER (LOGICAL DEVICE 2)
0: Parallel port clock disabled.
This read/write register is reset by hardware to 02h.
ECP modes and EPP timeout are not functional
when the logical device is active. Registers are
maintained.
SuperI/O UART2
7
0
6
0
5
0
4
3
2
0
1
0
1: Parallel port clock enabled.
Configuration Register,
Index F0h
0
0
1
0
Reset
All operation modes are functional when the logical
device is active. This bit is ANDed with a bit of the
PMC3 register of the Power Management device
(Logical Device4).
Required
TRI-STATE Control for
UART2 Pins
Power Mode Control
Bit 2,3 - Reserved
Busy Indicator
Bit 4 - Configuration Bits within the Parallel Port
0: The registers at base (address) + 403h, base +
404h and base + 405h are not accessible (reads
and writes are ignored).
Reserved
Bank Select Enable
1: When IEEE1284 mode is selected by bits 7
through 5, the registers at base (address) + 403h,
base + 404h and base + 405h are accessible.
Bit 0 - TRI-STATE Control for UART2 signals
This bit controls the TRI-STATE status of UART signals
(except IRQ and DMA signals) when UART2 is inactive
(disabled). This bit is ORed with a bit of the PMC1 reg-
ister of the Power Management device (Logical
Device4).
This option supports run-time configuration within
the Parallel Port address space. An 8-byte (and
1024-byte) aligned base address is required to ac-
cess these registers. See Chapter 4 "Parallel Port
(Logical Device 1)" on page 79 for details.
0: Signals not in TRI-STATE.
1: Signals in TRI-STATE.
Bit 7-5 - Parallel Port Mode Select
Bit 5 is the LSB.
Bit 1 - Power Mode Control
0: Low power mode.
Selection of EPP 1.7 or 1.9 in ECP mode 4 is controlled
by bit 4 of the Control2 configuration register of the par-
allel port at offset 02h. See Section 4.5.17 "Control2
Register" on page 93.
UART2 Clock disabled. UART2 output signals are
set to their default state. The RI input signal can be
programmed to generate an interrupt. Registers
are maintained.
000: SPP Compatible mode. PD7-0 are always output
signals.
001: SPP Extended mode. PD7-0 direction controlled
by software.
1: Normal power mode.
UART2 clock enabled. The UART2 is functional
when the logical device is active. This bit is ANDed
with a bit of the PMC3 register of the Power Man-
agement device (Logical Device 4).
010:EPP 1.7 mode.
011:EPP 1.9 mode.
100:IEEE1284 mode (selects IEEE1284 register set),
with no support for EPP mode.
Bit 2 - Busy Indicator
101:Reserved.
110:Reserved.
This read-only bit can be used by power management
software to decide when to power down UART2 logical
device. This bit is also accessed via the PMC3 register
of the Power Management device (Logical Device 4).
111:IEEE1284 mode (selects IEEE1284 register set),
with EPP mode selectable as mode 4.
0: No transfer in progress.
1: Transfer in progress.
Bits 6-3 - Reserved
Bit 7 - Bank Select Enable
Enables bank switching for UART2. If this bit is cleared,
all attempts to access the extended registers are ig-
nored.
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Configuration
2.8 SUPERI/O UART1 CONFIGURATION REGISTER 2.10 CONFIGURATION REGISTER BITMAPS
(LOGICAL DEVICE 3)
This read/write register is reset by hardware to 02h. Its bits
function like the bits in the SuperI/O UART2 Configuration
register
SID
7
1
6
1
5
1
4
3
2
0
1
0
Register,
0
0
0
0
Reset
Index 20h
1
1
1
0
0
0
0
0
Required
SuperI/O UART1
7
0
6
0
5
0
4
3
2
0
1
0
Configuration Register,
Index F0h
0
0
1
0
Reset
Required
TRI-STATE Control for
UART1 Pins
Chip ID
Power Mode Control
Busy Indicator
Reserved
Bank Select Enable
SuperI/O Configuration 1
0
Register (SIOCF1),
7
0
6
0
5
0
4
3
2
1
1
Index 21h
x
0
x
0
Reset
2.9 SUPERI/O KBC CONFIGURATION REGISTER
(LOGICAL DEVICE 6)
Required
BADDR0
This read/write register is reset by hardware to 40h.
BADDR1
PC-AT or PS/2 Drive Mode Select
CFG0
KBC-Lock
Lock Scratch Bit
SuperI/O KBC
Configuration
Register,
7
0
6
1
5
0
4
3
2
0
1
0
0
0
0
0
Reset
Required
Index F0h
TRI-STATE Control
General Purpose Scratch Bits
SuperI/O Configuration 2
Register (SIOCF2),
7
0
6
0
5
0
4
3
2
0
1
0
Reserved
0
0
0
0
Reset
Index 22h
Required
KBC Clock Source
MTR0/DRATE0 Select
MTR1/P12 Select
DR0,1 Function
DR1/DENSEL Select
IRRX1/P12/DRATE0 Select
Bit 0 - TRI-STATE Control
When set, it causes the KBC pins (including the mouse
clock and mouse data, but excluding DMA and IRQ), to be
in TRI-STATE when the KBC is inactive (disabled).
Bits 5-1 - Reserved
IRTX/DENSEL Select
Reserved
Bits 7,6 - KBC Clock Source
Bit 6 is the LSB. The clock source can be changed only
when the KBC is inactive (disabled).
SRID
7
x
6
x
5
x
4
3
2
1
0
Register,
00: 8 MHz
x
x
x
x
x
Reset
Index 27h
01: 12 MHz
10: 16 MHz.
11: Reserved.
Required
Chip Revision ID
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Configuration
SuperI/O UART1,2
Configuration Register,
Index F0h
SuperI/O KBC
Configuration
Register,
7
0
6
1
5
0
4
3
2
0
1
0
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
0
Reset
0
0
0
0
Reset
Required
Index F0h
Required
TRI-STATE Control for
UART Pins
Power Mode Control
TRI-STATE Control
Busy Indicator
Reserved
Reserved
Bank Select Enable
KBC Clock Source
Super I/O FDC
Configuration
Register,
7
0
6
0
5
1
4
3
2
0
1
0
0
0
0
0
Reset
Required
Index F0h
TRI-STATE Control
Reserved
DENSEL Polarity Control
TDR Register Mode
Four Drive Control
7
0
6
0
5
0
4
3
2
0
1
0
Drive ID Register,
Index F1h
0
0
0
0
Reset
Required
Drive 0 ID
Drive 1 ID
Reserved
SuperI/O Parallel Port
Configuration Register,
Index F0h
7
1
6
1
5
1
4
3
2
0
1
0
1
0
1
0
Reset
Required
TRI-STATE Control
Clock Enable
Reserved
Reserved
Configuration Bits within the Parallel Port
Parallel Port Mode Select
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The Floppy Disk Controller (FDC) (Logical Device 0)
The FDC supports all the DP8473 MODE command fea-
3.0 The Floppy Disk Controller (FDC)
(Logical Device 0)
tures as well as some additional features. These include
control over the enabling of the FIFO for read and write op-
erations, disabling burst mode for the FIFO, a bit that will
configure the disk interface outputs as open-drain output
signals, and programmability of the DENSEL output signal.
The Floppy Disk Controller (FDC) is suitable for all PC-AT,
EISA, PS/2, and general purpose applications. DP8473 and
N82077 software compatibility is provided. Key features in-
clude a 16-byte FIFO, PS/2 diagnostic register support, per-
pendicular recording mode, CMOS disk input and output
logic, and a high performance Digital Data Separator (DDS).
DRATE0 and DENSEL pins are not available in the default
configuration of Two-UART mode. You may optionally se-
lect them on other FDC pins or on IR pins. When working
with no DRATE0 or DENSEL, you must set the BIOS and
the floppy drive to support this operation.
Figure 3-1 shows a functional block diagram of the FDC.
The rest of this chapter describes the FDC functions, data
transfer, the FDC registers, the phases of FDC commands,
the result phase status registers and the FDC commands,
in that order.
3.1.1
Microprocessor Interface
The Floppy Disk Controller (FDC) receives commands,
transfers data, and returns status information via an FDC
microprocessor interface. This interface consists of the
A9-3, AEN, RD, and WR signals, which access the chip for
read and write operations; the data signals D7-0; the ad-
dress lines A2-0, which select the appropriate register (see
TABLE 3-1 on page 38) an IRQ signal, and the DMA inter-
face signals DRQ, DACK, and TC.
3.1 FDC FUNCTIONS
FDC functions are enabled when the FDC Function Enable
bit (bit 3) of the Function Enable Register 1 (FER1) at offset
00h in logical device 8 is set to 1. See Section 7.2.3 on page
155.
The PC87309 is software compatible with the DP8473 and
82077 Floppy Disk Controllers. Upon a power-on reset, the
16-byte FIFO is disabled. Also, the disk interface output sig-
nals are configured as active push-pull output signals,
which are compatible with both CMOS input signals and
open-collector resistor terminated disk drive input signals.
3.1.2
System Operation Modes
The FDC operates in PC-AT or PS/2 drive mode, depending
on the value of bit 2 of the SuperI/O Configuration 1 register
at index 21h. See Section 2.4.2 on page 28.
The FIFO can be enabled with the CONFIGURE command.
The FIFO can be very useful at high data rates, with sys-
tems that have a long DMA bus latency, or with multi-task-
ing systems such as the EISA or MCA bus structures.
Internal Control and Data Bus
Main Status
Register
(MSR)
RD
WR
Status
DRATE0
Register A
DENSEL
Interface
Logic
FDC Chip
Select
DIR
Status
Register B
DR1
16-Byte
FIFO
A2-0
Address
Decoder
DR0
Reset
D7-0
Digital Input
Register
(DIR)
HDSEL
MTR0
Disk
Input
and
PC8477B
Micro-Engine
and
MTR1
STEP
FDC DMA
Acknowledge
Output
Logic
Digital Output
Register
WGATE
WDATA
DSKCHG
Timing/Control
Logic
DMA
Enable
Logic
TC
(DOR)
FDC DMA
Request
Data Rate
Selection
Register
(DSR)
Write
Precompen-
sator
INDEX
RDATA
TRK0
WP
Interrupt
2 KB x 16
Micro-Code
Digital
Data
Separator
(DDS)
Configuration
Control
FDC Clock
Register
(CCR)
FIGURE 3-1. FDC Functional Block Diagram
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The Floppy Disk Controller (FDC) (Logical Device 0)
FIGURE 3-2 shows the dynamic window margin in the per-
PC-AT Drive Mode
formance of the FDC at different data rates, generated us-
ing a FlexStar FS-540 floppy disk simulator and a
proprietary dynamic window margin test program written by
National Semiconductor.
The PC-AT register set is enabled. The DMA enable bit in
the Digital Output Register (DOR) becomes valid (the ap-
propriate IRQ and DRQ signals can be put in TRI-STATE).
TC and DENSEL become active high signals (default to a
5.25" floppy disk drive).
250,300, 500 Kbps and 1 Mbps
PS/2 Drive Mode
80
70
60
50
40
30
20
10
This drive mode supports the PS/2 models 50/60/80 config-
uration and register set. The value of the DMA enable bit in
the Digital Output Register (DOR) becomes unimportant
(the IRQ and DRQ signals assigned to the FDC are always
valid). TC and DENSEL become active low signals (default
to 3.5" floppy drive).
3.2 DATA TRANSFER
3.2.1
Data Rates
The FDC supports the standard PC data rates of 250, 300
and 500 Kbps, as well as 1 Mbps. High performance tape
and floppy disk drives that are currently emerging in the PC
world, transfer data at 1 Mbps. The FDC also supports the
perpendicular recording mode, a new format used for some
high capacity disk drives at 1 Mbps.
-14-12-10 -8 -6 -4 -2 0
2 4 4 8 10 12 14
The internal digital data separator needs no external com-
ponents. It improves the window margin performance stan-
dards of the DP8473, and is compatible with the strict data
separator requirements of floppy disk drives and tape
drives.
Motor Speed Variation (% of Nominal)
Typical Performance at 500 Kbps,
V
DD = 5.0 V, 25˚ C
The FDC contains write precompensation circuitry that de-
faults to 125 nsec for 250, 300, and 500 Kbps (41.67 nsec
at 1 Mbps). These values can be overridden in software to
disable write precompensation or to provide levels of pre-
compensation up to 250 nsec.
FIGURE 3-2. PC87309 Dynamic Window Margin
Performance
The x axis measures MSV. MSV is translated directly to the
actual rate at which the data separator reads data from the
disk. In other words, a faster than nominal motor results in
a higher data rate.
The FDC has internal 24 mA data bus buffers which allow
direct connection to the system bus. The internal 40 mA to-
tem-pole disk interface buffers are compatible with both
CMOS drive input signals and 150 resistor terminated disk
drive input signals.
The dynamic window margin performance curve also indi-
cates how much bit jitter (or window margin) can be tolerat-
ed by the data separator. This parameter is shown on the y-
axis of the graph. Bit jitter is caused by the magnetic inter-
action of adjacent data pulses on the disk, which effectively
shifts the bits away from their nominal positions in the mid-
dle of the bit window. Window margin is commonly mea-
sured as a percentage. This percentage indicates how far a
data bit can be shifted early or late with respect to its nomi-
nal bit position, and still be read correctly by the data sepa-
rator. If the data separator cannot correctly decode a shifted
bit, then the data is misread and a CRC error results.
3.2.2
The Data Separator
The internal data separator is a fully digital PLL. The fully
digital PLL synchronizes the raw data signal read from the
disk drive. The synchronized signal is used to separate the
encoded clock and data pulses. The data pulses are broken
down into bytes, and then sent to the microprocessor by the
controller.
The FDC supports data transfer rates of 250, 300, 500 Kbps
and 1 Mbps in Modified Frequency Modulation (MFM) for-
mat.
The dynamic window margin performance curve supplies
two pieces of information:
The FDC has a dynamic window margin and lock range per-
formance capable of handling a wide range of floppy disk
drives. In addition, the data separator operates under a va-
riety of conditions, including high fluctuations in the motor
speed of tape drives that are compatible with floppy disk
drives.
●
The maximum range of MSV (also called “lock range”)
that the data separator can handle with no read errors.
●
The maximum percentage of window margin (or bit jitter)
that the data separator can handle with no read errors.
Thus, the area under the dynamic window margin curves in
FIGURE 3-2 is the range of MSV and bit jitter that the FDC
can handle with no read errors. The internal digital data sep-
arator of the FDC performs much better than comparable
digital data separator designs, and does not require any ex-
ternal components.
The dynamic window margin is the primary indicator of the
quality and performance level of the data separator. It indi-
cates the toleration of the data separator for Motor Speed
Variation (MSV) of the drive spindle motor and bit jitter (or
window margin).
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35
The Floppy Disk Controller (FDC) (Logical Device 0)
The controller maximizes the internal digital data separator
In 2.88 MB drives, the pre-erase head leads the read/write
head by 200 µm, which translates to 38 bytes at 1 Mbps (19
bytes at 500 Kbps).
by implementing a read algorithm that enhances the lock
characteristics of the fully digital Phase-Locked Loop (PLL).
The algorithm minimizes the effect of bad data on the syn-
chronization between the PLL and the data.
It does this by forcing the fully digital PLL to re-lock to the
clock reference frequency any time the data separator at-
tempts to lock to a non-preamble pattern. See the state di-
agram of this read algorithm in FIGURE 3-3.
Read/
Write
Head
Pre-
Erase
Head
200 µm
(38 bytes @ 1 Mbps)
Read Gate = 0
Data Field
Preamble
End of
Intersector
Gap 2
= 41 x 4Eh
PLL idle
locked
ID Field
to clock.
Operation
FIGURE 3-4. Perpendicular Recording Drive
Read/Write Head and Pre-Erase Head
Read Gate = 1
completed.
For both conventional and perpendicular drives, WGATE is
asserted with respect to the position of the read/write head.
With conventional drives, this means that WGATE is assert-
ed when the read/write head is located at the beginning of
the preamble to the data field.
PLL
locking
Read ID
field or
to data.
data field.
Wait six bits.
With 2.88 MB drives, since the preamble must be erased
before it is rewritten, WGATE should be asserted when the
pre-erase head is located at the beginning of the preamble
to the data field. This means that WGATE should be assert-
ed when the read/write head is at least 38 bytes (at 1 Mbps)
before the preamble. TABLES 3-14 on page 63 and 3-15 on
page 63 show how the perpendicular format affects gap 2
and, consequently, WGATE timing, for different data rates.
Not
sixth bit.
Three address
marks not found.
Three address
marks found.
Wait for
first bit that
is not a
preamble
bit.
Check for
three address
mark bytes.
Because of the 38-byte spacing between the read/write
head and the pre-erase head at 1 Mbps, the gap 2 length of
22 bytes used in the standard IBM disk format is not long
enough. The format standard for 2.88 MB drives at 1 Mbps
called the Perpendicular Format, increases the length of
gap 2 to 41 bytes. See FIGURE 3-5 on page 59.
Bit is not
preamble.
Bit is
preamble.
Not third
address mark.
FIGURE 3-3. Read Algorithm State Diagram
Perpendicular Recording Mode Support
The PERPENDICULAR MODE command puts the Floppy
Disk Controller (FDC) into perpendicular recording mode,
which allows it to read and write perpendicular media. Once
this command is invoked, the read, write and format com-
mands can be executed in the normal manner. The perpen-
dicular mode of the FDC functions at all data rates,
adjusting format and write data parameters accordingly.
See Section 3.7.9 on page 62 for more details.
3.2.3
The FDC is fully compatible with perpendicular recording
mode disk drives at all data transfer rates. These perpendic-
ular drives are also called 4 Mbyte (unformatted) or 2.88
Mbyte (formatted) drives. This refers to their maximum stor-
age capacity.
Perpendicular recording orients the magnetic flux changes
(which represent bits) vertically on the disk surface, allow-
ing for a higher recording density than conventional longitu-
dinal recording methods. This increased recording density
increases data rate by up to 1 Mbps, thereby doubling the
storage capacity. In addition, the perpendicular 2.88 MB
drive is read/write compatible with 1.44 MB and 720 KB dis-
kettes (500 Kbps and 250 Kbps respectively).
3.2.4
Data Rate Selection
The FDC sets the data rate in two ways. For PC compatible
software, the Configuration Control Register (CCR) at offset
07h programs the data rate for the FDC. The lower bits D1
and D0 in the CCR set the data rate. The other bits should
be set to zero. TABLE 3-5 on page 43 shows how to encode
the desired data rate.
The 2.88 MB drive has unique format and write data timing
requirements due to its read/write head and pre-erase head
design. This is illustrated in FIGURE 3-4.
The lower two bits of the Data rate Select Register (DSR) at
offset 04h can also set the data rate. These bits are encod-
ed like the corresponding bits in the CCR. The remainder of
the bits in the DSR have other functions. See the descrip-
tion of the DSR in Section 3.3.6 on page 43 for more details.
Unlike conventional disk drives which have only a
read/write head, the 2.88 MB drive has both a pre-erase
head and read/write head. With conventional disk drives,
the read/write head, itself, can rewrite the disk without prob-
lems. 2.88 MB drives need a pre-erase head to erase the
magnetic flux on the disk surface before the read/write head
can write to the disk surface. The pre-erase head is activat-
ed during disk write operations only, i.e. FORMAT and
WRITE DATA commands.
The data rate is determined by the last value written to ei-
ther the CCR or the DSR. Either the CCR or the DSR can
override the data rate selection of the other register. When
the data rate is selected, the micro-engine and data sepa-
rator clocks are scaled appropriately.
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36
The Floppy Disk Controller (FDC) (Logical Device 0)
3.2.5
Write Precompensation
Recovery from Low-Power Mode
Write precompensation enables the WDATA output signal
to adjust for the effects of bit shift on the data as it is written
to the disk surface.
There are two ways the FDC section can recover from the
power-down state.
Power up is triggered by a software reset via the DOR or
DSR. Since a software reset requires initialization of the
controller, this method might be undesirable.
Bit shift is caused by the magnetic interaction of data bits as
they are written to the disk surface. It shifts these data bits
away from their nominal position in the serial MFM data pat-
tern. Bit shift makes it much harder for a data separator to
read data and can cause soft read errors.
Power up is also triggered by a read or write to either the
Data Register (FIFO) or Main Status Register (MSR). This
is the preferred way to power up since all internal register
values are retained. It may take a few milliseconds for the
clock to stabilize, and the microprocessor will be prevented
from issuing commands during this time through the normal
MSR protocol. That means that bit 7, the Request for Mas-
ter (RQM) bit, in the MSR will be a 0 until the clock has sta-
bilized. When the controller has completely stabilized after
power up, the RQM bit in the MSR is set to 1 and the con-
troller can continue where it left off.
Write precompensation predicts where bit shift could occur
within a data pattern. It then shifts the individual data bits
early, late, or not at all so that when they are written to the
disk, the shifted data bits are back in their nominal position.
The FDC supports software programmable write precom-
pensation. Upon power up, the default write precompensa-
tion values shown in TABLE 3-7 on page 43, are used. In
addition, the default starting track number for write precom-
pensation is track zero
3.2.7
Reset
You can use the DSR to change the write precompensation
using any of the values in TABLE 3-6 on page 43. Also, the
CONFIGURE command can change the starting track num-
ber for write precompensation.
The FDC can be reset by hardware or software.
A hardware reset consists of pulsing the Master Reset (MR)
input signal. A hardware reset sets all of the user address-
able registers and internal registers to their default values.
The SPECIFY command values are unaffected by reset, so
they must be initialized again.
3.2.6
FDC Low-Power Mode Logic
The FDC of the PC87309 supports two low-power modes,
manual and automatic.
The major default conditions affected by reset are:
In low-power mode, the micro-code is driven from the clock.
Therefore, it is disabled while the clock is off. Upon entering
the power-down state, bit 7, the RQM (Request For Master)
bit, in the Main Status Register (MSR) of the FDC is cleared
to 0.
●
FIFO disabled
●
DMA disabled
●
Implied seeks disabled
●
Drive polling enabled
For details about entering and exiting low-power mode by
setting bit 6 of the Data rate Select Register (DSR) or by ex-
ecuting the LOW PWR option of the FDC MODE command,
see Recovery from Low-Power Mode later in this section,
Section 3.3.6 on page 43 and Section 3.7.7 on page 60.
A software reset can be triggered by bit 2 of the Digital Out-
put Register (DOR) or bit 7 of the Data rate Select Register
(DSR). Bit 7 of DSR clears itself, while bit 2 of DOR does
not clear itself.
The DSR, Digital Output Register (DOR), and the Configu-
ration Control Register (CCR) are unaffected and remain
active in power-down mode. Therefore, you should make
sure that the motor and drive select signals are turned off.
If the LOCK bit in the LOCK command was set to 1 before
the software reset, the FIFO, THRESH, and PRETRK pa-
rameters in the CONFIGURE command will be retained. In
addition, the FWR, FRD, and BST parameters in the MODE
command will be retained if LOCK is set to 1. This function
eliminates the need for total initialization of the controller af-
ter a software reset.
If the power to an external clock driving the PC87309 will be
independently removed while the FDC is in power-down
mode, it must not be done until 2 msec after the LOW PWR
option of the FDC MODE command is issued.
After a hardware (assuming the FDC is enabled in the FER)
or software reset, the Main Status Register (MSR) is imme-
diately available for read access by the microprocessor. It
will return a 00h value until all the internal registers have
been updated and the data separator is stabilized.
Manual Low-Power Mode
Manual low power is enabled by writing a 1 to bit 6 of the
DSR. The chip will power down immediately. This bit will be
cleared to 0 after power up.
When the controller is ready to receive a command byte, the
MSR returns a value of 80h (Request for Master (RQM, bit
7) bit is set). The MSR is guaranteed to return the 80h value
within 250 µsec after a hardware or software reset.
Manual low power can also be triggered by the MODE com-
mand. Manual low power mode functions as a logical OR
function between the DSR low power bit and the LOW PWR
option of the MODE command.
All other user addressable registers other than the Main
Status Register (MSR) and Data Register (FIFO) can be ac-
cessed at any time, even during software reset.
Automatic Low-Power Mode
Automatic low-power mode switches the controller to low
power 500 msec (at the 500 Kbps MFM data rate) after it
has entered the Idle state. Once automatic low-power mode
is set, it does not have to be set again, and the controller au-
tomatically goes into low-power mode after entering the Idle
state.
3.3 THE REGISTERS OF THE FDC
The FDC registers are mapped to the offset address shown
in TABLE 3-1 on page 38, with the base address range pro-
vided by the on-chip address decoder. For PC-AT or PS/2
applications, the offset address range of the diskette con-
troller is 00h through 07h from the index of logical device 0.
Automatic low-power mode can only be set with the LOW
PWR option of the MODE command.
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The Floppy Disk Controller (FDC) (Logical Device 0)
TABLE 3-1. The FDC Registers and Addresses
Bit 0 - Head Direction
This bit indicates the direction of the head of the Floppy
Disk Drive (FDD). Its value is the inverse of the value of
the DIR interface output signal.
Offset
Symbol
Description
R/W
A2 A1 A0
0: DIR is not active, i.e., the head of the FDD steps
outward. (Default)
SRA Status Register A
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
1
1
1
0
1
0
1
0
0
1
0
1
1
R
R
1: DIR is active, i.e., the head of the FDD steps inward.
SRB Status Register B
DOR Digital Output Register
TDR Tape Drive Register
MSR Main Status Register
DSR Data Rate Select Register
FIFO Data Register (FIFO)
R/W
R/W
R
Bit 1 - Write Protect (WP)
This bit indicates whether or not the selected Floppy
Disk Drive (FDD) is write protected. Its value reflects the
status of the WP disk interface input signal.
W
0: WP is active, i.e., the FDD in the selected drive is
write protected.
R/W
X
-
(Bus in TRI-STATE)
Digital Input Register
1: WP is not active, i.e., the FDD in the selected drive
is not write protected.
DIR
R
CCR CCR Configuration
Control Register
W
Bit 2 - Beginning of Track (INDEX)
This bit indicates the beginning of a track. Its value re-
flects the status of the INDEX disk interface input signal.
The FDC supports two system operation modes: PC-AT
drive mode and PS/2 drive mode (MicroChannel systems).
Section 3.1.2 on page 34 describes each mode and “Bit 2 -
PC-AT or PS/2 Drive Mode Select” on page 28 describes
how each is enabled.
0: INDEX is active, i.e., it is the beginning of a track.
1: INDEX is not active, i.e., it is not the beginning of a
track.
Bit 3 - Head Select
Unless specifically indicated otherwise, all fields in all regis-
ters are valid in both drive modes.
This bit indicates which side of the Floppy Disk Drive
(FDD) is selected by the head. Its value is the inverse of
the HDSEL disk interface output signal.
The FDC supports plug and play, as follows:
●
The FDC interrupt can be routed on one of the following
0: HDSEL is not active, i.e., the head of the FDD se-
lects side 0. (Default)
ISA interrupts: IRQ3-IRQ7, IRQ9-IRQ12 and IRQ15
(see PNP2 register).
1: HDSEL is active, i.e., the head of the FDD selects
side 1.
●
The FDC DMA signals can be routed to one of three 8-
bit ISA DMA channels (see PNP2 register); and its base
address is software configurable (see FBAL and FBAH
registers).
Bit 4 - At Track 0 (TRK0)
This bit indicates whether or not the head of the Floppy
Disk Drive (FDD) is at track 0. Its value reflects the sta-
tus of the TRK0 disk interface input signal.
●
Upon reset, the DMA of the FDC is routed to the DRQ2
and DACK2 pins.
0: TRK0 is active, i.e., the head of the FDD is at track 0.
3.3.1
Status Register A (SRA)
1: TRK0 is not active, i.e., the head of the FDD is not
at track 0.
Status Register A (SRA) monitors the state of assigned IRQ
signal and some of the disk interface signals. SRA is a read-
only register that is valid only in PS/2 drive mode.
Bit 5 - Step
This bit indicates whether or not the head of the Floppy
Disk Drive (FDD) should move during a seek operation.
Its value is the inverse of the STEP disk interface output
signal.
SRA can be read at any time while PS/2 drive mode is ac-
tive. In PC-AT drive mode, all bits are in TRI-STATE during
a microprocessor read.
0: STEP is not active, i.e., the head of the FDD
moves. (Default)
PS/2 Drive Mode
7
0
6
5
0
4
3
2
1
0
Status Register
A (SRA)
1: STEP is active (low), i.e., the head of the FDD does
not move.
0
0
Reset
Offset 00h
Required
Bit 6 - Reserved
Head Direction
Bit 7 - IRQ Pending
WP
INDEX
Head Select
TRK0
Step
Reserved
IRQ Pending
This bit signals the completion of the execution phase of
certain FDC commands. Its value reflects the status of
the IRQ signal assigned to the FDC.
0: The IRQ signal assigned to the FDC is not active.
1: The IRQ signal assigned to the FDC is active, i.e.,
the FDD has completed execution of certain FDC
commands.
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The Floppy Disk Controller (FDC) (Logical Device 0)
Status Register B (SRB) 0: Either no write data was sent or an even number of
3.3.2
bits of write data was sent. (Default)
Status Register B (SRB) is a read-only diagnostic register
that is valid only in PS/2 drive mode.
1: An odd number of bits of write data was sent.
SRB can be read at any time while PS/2 drive mode is ac-
tive. In PC-AT drive mode, all bits are in TRI-STATE during
a microprocessor read.
Bit 5 - Drive Select Status
This bit reflects the status of drive select bit 0 in the Dig-
ital Output Register (DOR). See Section 3.3.3.
It is cleared after a hardware reset and unaffected by a
software reset.
PS/2 Drive Mode
7
1
1
6
1
1
5
0
4
3
2
1
0
SRB Register
Offset 01h
0: Either drive 0 or 2 is selected. (Default)
1: Either drive 1 or 3 is selected.
0
0
0
0
0
Reset
Required
Bits 7,6 - Reserved
These bits are reserved and are always 1.
MTR0
MTR1
WGATE
RDATA
WDATA
Drive Select Status
Reserved
Reserved
3.3.3
Digital Output Register (DOR)
DOR is a read/write register that can be written at any time.
It controls the drive select and motor enable disk interface
output signals, enables the DMA logic and contains a soft-
ware reset bit.
The contents of the DOR is set to 00h after a hardware re-
set, and is unaffected by a software reset.
Bit 0 - Motor 0 Status (MTR0)
TABLE 3-2 shows how the bits of DOR select a drive and
enable a motor when the FDC is enabled (bit 3 of the Func-
tion Enable Register 1 (FER1) at offset 00h of logical device
8 is 1) and bit 7 of the SuperI/O FDC Configuration register
at index F0h is 1. Bit patterns not shown produce states that
should not be decoded to enable any drive or motor.
This bit indicates the complement of the MTR0 output
pin.
This bit is cleared to 0 by a hardware reset and unaffect-
ed by a software reset.
0: MTR0 not active; motor 0 off (default).
1: MTR0 active; motor 0 on.
When the FDC is enabled and bit 7 of the of the SuperI/O
FDC Configuration register at index F0h is 1, MTR1 pre-
sents a pulse that is the inverse of WR. This pulse is active
whenever an I/O write to address 02h occurs. This pulse is
delayed for between 25 and 80 nsec after the leading edge
of WR. The leading edge of this pulse can be used to clock
data into an external latch (e.g., 74LS175).
Bit 1 - Motor 1 Status (MTR1)
This bit indicates the complement of the MTR1 output
pin.
This bit is cleared to 0 by a hardware reset and unaffect-
ed by a software reset.
TABLE 3-2. Drive and Motor Pin Encoding for Four
Drive Configurations and Drive Exchange Support
0: MTR1 not active; motor 1 off (default).
1: MTR1 active.; motor 1 on.
Control
Digital Output
Register Bits
Signals
Bit 2 - Write Circuitry Status (WGATE)
Decoded Functions
This bit indicates the complement of the WGATE output
pin.
MTR DR
7 6 5 4 3 2 1 0 1 0 1 0
0: WGATE not active. The write circuitry of the select-
ed FDD is enabled (default).
Activate Drive 0
and Motor 0
x x x 1 x x 0 0
x x 1 x x x 0 1
x 1 x x x x 1 0
1 x x x x x 1 1
x x x 0 x x 0 0
x x 0 x x x 0 1
x 0 x x x x 1 0
0 x x x x x 1 1
-
-
-
-
-
-
-
-
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
1: WGATE active. The write circuitry of the selected
FDD is disabled.
Activate Drive 1
and Motor 1
Bit 3 - Read Data Status (RDATA)
Activate Drive 2
and Motor 2
If read data was sent, this bit indicates whether an odd
or even number of bits was sent.
Every inactive edge transition of the RDATA disk inter-
face output signal causes this bit to change state.
Activate Drive 3
and Motor 3
0: Either no read data was sent or an even number of
bits of read data was sent. (Default)
Activate Drive 0 and
Deactivate Motor 0
1: An odd number of bits of read data was sent.
Activate Drive 1 and
deactivate Motor 1
Bit 4 - Write Data Status (WDATA)
Activate Drive 2 and
Deactivate Motor 2
If write data was sent, this bit indicates whether an odd
or even number of bits was sent.
Activate Drive 3 and
Deactivate Motor 3
Every inactive edge transition of the WDATA disk inter-
face output signal causes this bit to change state.
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The Floppy Disk Controller (FDC) (Logical Device 0)
Usually, the motor enable and drive select output signals for
Bit 3 - DMA Enable (DMAEN)
a particular drive are enabled together. TABLE 3-3 shows
the DOR hexadecimal values that enable each of the four
drives.
In PC-AT drive mode, this bit enables DMA operations
by controlling DACK, TC and the appropriate DRQ and
IRQ DMA signals. In PC-AT mode, this bit is set to 0 af-
ter reset.
TABLE 3-3. Drive Enable Hexadecimal Values
In PS/2 drive mode, this bit is reserved, and DACK, TC
and the appropriate DRQ and IRQ signals are enabled.
During reset, these signals remain enabled.
Drive
DOR Value (Hex)
0
1
2
3
1C
2D
4E
8F
0: In PC-AT drive mode, DMA operations are dis-
abled. DACK and TC are disabled, and the appro-
priate DRQ and IRQ signals are put in TRI-STATE.
(Default)
1: In PC-AT drive mode, DMA operations are enabled,
i.e., DACK, TC and the appropriate DRQ and IRQ
signals are all enabled.
The motor enable and drive select signals for drives 2 and
3 are only available when four drives are supported, i.e., bit
7 of the SuperI/O FDC Configuration register at index F0h
is 1, or when drives 2 and 0 are exchanged. These signals
require external logic.
Bit 4- Motor Enable 0
If four drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 1), this bit may
control the motor output signal for drive 0, depending on
the remaining bits of this register. See TABLE 3-2 on
page 39.
7
0
6
0
5
0
4
3
2
0
1
0
Digital Output
Register (DOR)
Offset 02h
0
0
0
0
Reset
If two drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 0), this bit controls
the motor output signal for drive 0.
Required
0: The motor signal for drive 0 is not active.
1: The motor signal for drive 0 is active.
Drive Select
Reset Controller
DMAEN
Motor Enable 0
Motor Enable 1
Motor Enable 2
Motor Enable 3
Bit 5 - Motor Enable 1
If four drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 1), this bit may
control the motor output signal for drive 0, depending on
the remaining bits of this register. See TABLE 3-2.
If two drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 0), this bit controls
the motor output signal for drive 1.
Bits 1,0 - Drive Select
These bits select a drive, so that only one drive select
output signal is active at a time.
0: The motor signal for drive 1 is not active.
1: The motor signal for drive 1 is active.
See “Bit 7 - Four Drive Control” on page 30 and “Bits 3,2
- Logical Drive Control (Enhanced TDR Mode Only)” on
page 41 for more information.
Bit 6 - Motor Enable 2
00: Drive 0 is selected. (Default)
01: Drive 1 is selected.
If drives 2 and 0 are exchanged (see "Bits 3,2 - Logical
Drive Control (Enhanced TDR Mode Only)" on page
41), or if four drives are supported (bit 7 of the SuperI/O
FDC Configuration register at index F0h is 1), this bit
controls the motor output signal for drive 2. See TABLE
3-2.
10: If four drives are supported, or drives 2 and 0 are
exchanged, drive 2 is selected.
11: If four drives are supported, drive 3 is selected.
0: The motor signal for drive 2 is not active.
1: The motor signal for drive 2 is active.
Bit 2 - Reset Controller
This bit can cause a software reset. The controller re-
mains in a reset state until this bit is set to 1.
Bit 7 - Motor Enable 3
A software reset affects the CONFIGURE and MODE
commands. See Sections 3.7.2 on page 55 and 3.7.7 on
page 60, respectively. A software reset does not affect
the Data rate Select Register (DSR), Configuration Con-
trol Register (CCR) and other bits of this register (DOR).
If four drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 1), this bit may
control the motor output signal for drive 3, depending on
the remaining bits of this register. See TABLE 3-2.
0: The motor signal for drive 3 is not active.
1: The motor signal for drive 3 is active.
This bit must be low for at least 100 nsec. There is
enough time during consecutive writes to the DOR to re-
set software by toggling this bit.
0: Reset controller. (Default)
1: No reset.
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The Floppy Disk Controller (FDC) (Logical Device 0)
Tape Drive Register (TDR)
3.3.4
Enhanced TDR Mode
The TDR register is a read/write register that acts as the
Floppy Disk Controller’s (FDC) drive type register.
7
6
5
4
3
2
1
0
Tape Drive
Register (TDR)
Offset 03h
1
0
0
Reset
AT Compatible TDR Mode
Required
In this mode, the TDR assigns a drive number to the tape
drive support mode of the data separator. All other logical
drives can be assigned as floppy drive support. Bits 7-2 are
in TRI-STATE during read operations.
Tape Drive Select 1,0
Logical Drive Exchange
Drive ID0 Information
Enhanced TDR Mode
In this mode, all the bits of the TDR define operations with
Enhanced floppy disk drives.
Drive ID1 Information
Reserved
Reserved
AT Compatible TDR Mode
7
6
5
4
3
2
1
0
Tape Drive
Register (TDR)
Offset 03h
1
0
0
Reset
Required
Tape Drive Select 1,0
Not Used
TRI-STATE During Read Operations
TABLE 3-4. TDR Bit Utilization and Reset Values in Different Drive Modes
Bits of TDR
Bit 6 of SuperI/O
Logical Drive
TDR Mode
FDC Configuration Drive ID1 Drive ID0
Register
Drive Select
Exchange
5
4
3
2
1
0
Not used. Floated in TRI-STATE during read
operations.
PC-AT
0
1
0
0
0
0
Compatible
Enhanced
1
1
0
0
Bits 1,0 - Tape Drive Select 1,0
01: Disk drive and motor control signal assignment to
pins exchanged between logical drives 0 and 1.
These bits assign a logical drive number to a tape drive.
Drive 0 is not available as a tape drive and is reserved
as the floppy disk boot drive.
10: Disk drive and motor control signal assignment to
pins exchanged between logical drives 0 and 2.
00: No drive selected.
01: Drive 1 selected.
10: Drive 2 selected.
11: Drive 3 selected.
11: Reserved. Unpredictable results when configured.
Bits 5,4 - Drive ID1,0 Information
If the value of bits 1,0 of the Digital Output Register
(DOR) are 00, these bits reflect the ID of drive 0, i.e., the
value of bits 1,0, respectively, of the Drive ID register at
index F1h. See “Bits 1,0 - Drive 0 ID” on page 30.
Bits 3,2 - Logical Drive Control (Enhanced TDR Mode Only)
These read/write bits control logical drive exchange be-
tween drives 0 and 2, only.
If the value of bits 1,0 of the Digital Output Register
(DOR) are 01, these bits reflect the ID of drive 1, i.e., the
value of bits 3,2, respectively, of the Drive ID register at
index F1h. See “Bits 3,2 - Drive 1 ID” on page 30.
They enable software to exchange the physical floppy
disk drive and motor control signals assigned to pins.
Drive 3 is never exchanged for drive 2.
Bits 7,6 - Reserved.
When four drives are configured, i.e., bit 7 of SuperI/O
FDC Configuration register at index F0h is 1, logical
drives are not exchanged.
These bits are reserved and are read as 11b.
00: No logical drive exchange.
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The Floppy Disk Controller (FDC) (Logical Device 0)
Main Status Register (MSR)
This bit is cleared to 0 after the first byte in the result
3.3.5
phase of the SENSE INTERRUPT command is read for
drive 2.
This read-only register indicates the current status of the
Floppy Disk Controller (FDC), indicates when the disk con-
troller is ready to send or receive data through the Data
Register (FIFO) and controls the flow of data to and from the
Data Register (FIFO).
0: Not busy.
1: Busy.
Bit 3 - Drive 3 Busy
The MSR can be read at any time. It should be read before
each byte is transferred to or from the Data Register (FIFO)
except during a DMA transfer. No delay is required when
reading this register after a data transfer.
This bit indicates whether or not drive 3 is busy.
It is set to 1 after the last byte of the command phase
of a SEEK or RECALIBRATE command is issued for
drive 3.
The microprocessor can read the MSR immediately after a
hardware or software reset, or recovery from a power down.
The MSR contains a value of 00h, until the FDC clock has
stabilized and the internal registers have been initialized.
This bit is cleared to 0 after the first byte in the result
phase of the SENSE INTERRUPT command is read for
drive 3.
When the FDC is ready to receive a new command, it re-
ports a value of 80h for the MSR to the microprocessor.
System software can poll the MSR until the MSR is ready.
The MSR must report an 80h value (RQM set to 1) within
2.5 msec after reset or power up.
0: Not busy.
1: Busy.
Bit 4 - Command in Progress
This bit indicates whether or not a command is in
progress. It is set after the first byte of the command
phase is written. This bit is cleared after the last byte of
the result phase is read.
Read Operations
7
0
6
0
5
0
4
3
2
1
0
Main Status
Register (MSR)
Offset 04h
0
0
0
0
0
Reset
If there is no result phase in a command, the bit is
cleared after the last byte of the command phase is
written.
Required
0: No command is in progress.
1: A command is in progress.
Drive 0 Busy
Drive 1 Busy
Drive 2 Busy
Drive 3 Busy
Command in Progress
Non-DMA Execution
Data I/O Direction
RQM
Bit 5 - Non-DMA Execution
This bit indicates whether or not the controller is in the
execution phase of a byte transfer operation in non-
DMA mode.
This bit is used for multiple byte transfers by the micro-
processor in the execution phase through interrupts or
software polling.
Bit 0 - Drive 0 Busy
0: The FDC is not in the execution phase.
1: The FDC is in the execution phase.
This bit indicates whether or not drive 0 is busy.
It is set to 1 after the last byte of the command phase of
a SEEK or RECALIBRATE command is issued for drive
0.
Bit 6 - Data I/O (Direction)
Indicates whether the controller is expecting a byte to be
written or read, to or from the Data Register (FIFO).
This bit is cleared to 0 after the first byte in the result
phase of the SENSE INTERRUPT command is read for
drive 0.
0: Data will be written to the FIFO.
1: Data will be read from the FIFO.
0: Not busy.
1: Busy.
Bit 7 - Request for Master (RQM)
Bit 1 - Drive 1 Busy
This bit indicates whether or not the controller is ready
to send or receive data from the microprocessor through
the Data Register (FIFO). It is cleared to 0 immediately
after a byte transfer and is set to 1 again as soon as the
disk controller is ready for the next byte.
This bit indicates whether or not drive 1 is busy.
It is set to 1 after the last byte of the command phase of
a SEEK or RECALIBRATE command is issued for drive
1.
During a Non-DMA execution phase, this bit indicates
the status of the interrupt.
This bit is cleared to 0 after the first byte in the result
phase of the SENSE INTERRUPT command is read for
drive 1.
0: Not ready. (Default)
1: Ready to transfer data.
0: Not busy.
1: Busy.
Bit 2 - Drive 2 Busy
This bit indicates whether or not drive 2 is busy.
It is set to 1 after the last byte of the command phase
of a SEEK or RECALIBRATE command is issued for
drive 2.
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The Floppy Disk Controller (FDC) (Logical Device 0)
3.3.6
Data Rate Select Register (DSR)
TABLE 3-6. Write Precompensation Delays
This write-only register is used to program the data transfer
rate, amount of write precompensation, power down mode,
and software reset.
DSR Bits
Duration of Delay
4
3
2
The data transfer rate is programmed via the CCR, not the
DSR, for PC-AT, PS/2 and MicroChannel applications. Oth-
er applications can set the data transfer rate in the DSR.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Default (TABLE 3-7)
41.7 nsec
The data rate of the floppy controller is determined by the
most recent write to either the DSR or CCR.
83.3 nsec
125.0 nsec
166.7 nsec
208.3 nsec
250.0 nsec
0.0 nsec
The DSR is unaffected by a software reset. A hardware re-
set sets the DSR to 02h, which corresponds to the default
precompensation setting and a data transfer rate of 250
Kbps.
Write Operations
7
0
6
0
5
0
4
3
2
1
0
Data Rate Select
Register (DSR)
Offset 04h
TABLE 3-7. Default Precompensation Delays
0
0
0
1
0
Reset
Data Rate
Precompensation Delay
Required
1 Mbps
500 Kbps
300 Kbps
250 Kbps
41.7 nsec
125.0 nsec
125.0 nsec
125.0 nsec
Data Transfer Rate Select
Precompensation Delay Select
Undefined
Low Power
Software Reset
Bit 5 - Undefined
Should be set to 0.
Bit 6 - Low Power
Bits 1,0 - Data Transfer Rate Select
This bit triggers a manual power down of the FDC in
which the clock and data separator circuits are turned
off. A manual power down can also be triggered by the
MODE command.
These bits determine the data transfer rate for the Flop-
py Disk Controller (FDC), depending on the supported
speeds. TABLE 3-5 shows the data transfer rate select-
ed by each value of this field.
After a manual power down, the FDC returns to normal
power after a software reset, or an access to the Data
Register (FIFO) or the Main Status Register (MSR).
These bits are unaffected by a software reset, and are
set to 10 (250 Kbps) after a hardware reset.
0: Normal power.
TABLE 3-5. Data Transfer Rate Encoding
1: Trigger power down.
DSR Bits
Bit 7 - Software Reset
Data Transfer Rate
1
0
This bit controls the same kind of software reset of the
FDC as bit 2 of the Digital Output Register (DOR). The
difference is that this bit is automatically cleared to 0 (no
reset) 100 nsec after it was set to 1.
0
0
1
1
0
1
0
1
500 Kbps
300 Kbps
250 Kbps
1 Mbps
See also “Bit 2 - Reset Controller” on page 40.
0: No reset. (Default)
1: Reset.
Bits 4-2 - Precompensation Delay Select
3.3.7
Data Register (FIFO)
This field sets the write precompensation delay that the
Floppy Disk Controller (FDC) imposes on the WDATA
disk interface output signal, depending on the supported
speeds. TABLE shows the delay for each value of this
field.
The Data Register of the FDC is a read/write register that is
used to transfer all commands, data and status information
between the microprocessor and the FDC.
During the command phase, the microprocessor writes
command bytes into the Data Register after polling the
RQM (bit 7) and DIO (bit 6) bits in the MSR. During the re-
sult phase, the microprocessor reads result bytes from the
Data Register after polling the RQM and DIO bits in the
MSR.
In most cases, the default delays shown in TABLE 3-7
are adequate. However, alternate values may be used
for specific drive and media types.
Track 0 is the default starting track number for precom-
pensation. The starting track number can be changed
using the CONFIGURE command.
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The Floppy Disk Controller (FDC) (Logical Device 0)
Use of the FIFO buffer lengthens the interrupt latency peri-
od and, thereby, reduces the chance of a disk overrun or
underrun error occurring. Typically, the FIFO buffer is used
at a 1 Mbps data transfer rate or with multi-tasking operating
systems.
7
6
5
4
3
2
1
0
Data Register
(FIFO)
Reset
Offset 05h
Required
Enabling and Disabling the FIFO Buffer
The 16-byte FIFO buffer can be used for DMA, interrupt, or
software polling type transfers during the execution of a
read, write, format or scan command.
The FIFO buffer is enabled and its threshold is set by the
CONFIGURE command.
Data
When the FIFO buffer is enabled, only execution phase byte
transfers use it. If the FIFO buffer is enabled, it is not dis-
abled after a software reset if the LOCK bit is set in the
LOCK command.
3.3.8
Digital Input Register (DIR)
This read-only diagnostic register is used to detect the state
of the DSKCHG disk interface input signal and some diag-
nostic signals. DIR is unaffected by a software reset.
The FIFO buffer is always disabled during the command
and result phases of a controller operation. A hardware re-
set disables the FIFO buffer and sets its threshold to zero.
The MODE command can also disable the FIFO for read or
write operations separately.
The bits of the DIR register function differently depending
on whether the FDC is operating in PC-AT drive mode or in
PS/2 drive mode. See Section 3.1.2 on page 34.
After a hardware reset, the FIFO buffer is disabled to main-
tain compatibility with PC-AT systems.
In PC-AT drive mode, bits 6 through 0 are in TRI-STATE to
prevent conflict with the status register of the hard disk at
the same address as the DIR.
Burst Mode Enabled and Disabled
The FIFO buffer can be used with burst mode enabled or
disabled by the MODE command.
Read Operations, PC-AT Drive Mode
In burst mode, the DRQ or IRQ signal assigned to the FDC
remains active until all of the bytes have been transferred to
or from the FIFO buffer.
7
6
1
5
4
3
2
1
0
Digital Input
Register (DIR)
Offset 07h
1
1
1
1
Reset
Required
When burst mode is disabled, the appropriate DRQ or IRQ
signal is deactivated for 350 nsec to allow higher priority
transfer requests to be processed.
FIFO Buffer Response Time
During the execution phase of a command involving data
transfer to or from the FIFO buffer, the maximum time the
system has to respond to a data transfer service request is
calculated by the following formula:
Reserved, In TRI-STATE
DSKCHG
Read Operations, PS/2 Drive Mode
Max_Time = (THRESH + 1) x 8 x tDRP – (16 x tICP
)
This formula applies for all data transfer rates, whether the
FIFO buffer is enabled or disabled. THRESH is a 4-bit value
programmed by the CONFIGURE command, which sets
the threshold of the FIFO buffer. If the FIFO buffer is dis-
abled, THRESH is zero in the above formula. The last term
in the formula, (16 x tICP) is an inherent delay due to the mi-
crocode overhead required by the FDC. This delay is also
data rate dependent. Section 10.3.14 on page 183 specifies
7
6
5
4
3
2
1
0
Digital Input
Register (DIR)
Offset 07h
1
1
1
1
1
Reset
Required
High Density
DRATE0 Status
DRATE1 Status
minimum and maximum values for tDRP and tICP
.
The programmable FIFO threshold (THRESH) is useful in
adjusting the FDC to the speed of the system. A slow sys-
tem with a sluggish DMA transfer capability requires a high
value for THRESH. this gives the system more time to re-
spond to a data transfer service request (DRQ for DMA
mode or IRQ for interrupt mode). Conversely, a fast system
with quick response to a data transfer service request can
use a low value for THRESH.
Reserved
DSKCHG
Bit 0 - High Density (PS/2 Drive Mode Only)
In PC-AT drive mode, this bit is reserved, in TRI-STATE
and used by the status register of the hard disk.
In PS/2 drive mode, this bit indicates whether the data
transfer rate is high or low.
0: The data transfer rate is high, i.e., 1 Mbps or 500 Kbps.
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The Floppy Disk Controller (FDC) (Logical Device 0)
1: The data transfer rate is low, i.e., 300 Kbps or 250 Kbps.
Bits 7-2 - Reserved
These bits should be set to 0.
Bits 2,1 - Data Rate Select 1,0 (DRATE1,0)
(PS/2 Drive Mode Only)
3.4 THE PHASES OF FDC COMMANDS
In PC-AT drive mode, these bits are reserved, in TRI-
STATE and used by the status register of the hard disk.
FDC commands may be in the command phase, the execu-
tion phase or the result phase. The active phase determines
how data is transferred between the Floppy Disk Controller
(FDC) and the host microprocessor. When no command is
in progress, the FDC may be either idle or polling a drive.
In PS/2 drive mode, these bits indicate the status of the
DRATE1,0 bits programmed in DSR or CCR, whichever
is written last.
The significance of each value for these bits depends on
the supported speeds. See TABLE 3-5 on page 43.
3.4.1
Command Phase
During the command phase, the microprocessor writes a
series of bytes to the Data Register (FIFO). The first com-
mand byte contains the opcode for the command, which the
controller can interpret to determine how many more com-
mand bytes to expect. The remaining command bytes con-
tain the parameters required for the command.
00: Data transfer rate is 500 Kbps.
01: Data transfer rate is 300 Kbps.
10: Data transfer rate is 250 Kbps.
11: Data transfer rate is 1 Mbps.
Bits 6-3 - Reserved
The number of command bytes varies for each command.
All command bytes must be written in the order specified in
the Command Description Table in Section 3.7 on page 53.
The execution phase starts immediately after the last byte
in the command phase is written.
These bits are reserved and are always 1. In PC-AT
mode these bits are also in TRI-STATE. They are used
by the status register of the fixed hard disk.
Bit 7 - Disk Changed (DSKCHG)
Prior to performing the command phase, the Digital Output
Register (DOR) should be set and the data rate should be
set with the Data rate Select Register (DSR) or the Config-
uration Control Register (CCR).
This bit reflects the status of the DSKCHG disk interface
input signal.
During power down this bit is invalid, if it is read by the
software.
The Main Status Register (MSR) controls the flow of com-
mand bytes, and must be polled by the software before writ-
ing each command phase byte to the Data Register (FIFO).
Prior to writing a command byte, bit 7 of MSR (RQM, Re-
quest for Master) must be set and bit 6 of MSR (DIO, Data
I/O direction) must be cleared.
0: DSKCHG is not active.
1: DSKCHG is active.
3.3.9
Configuration Control Register (CCR)
This write-only register can be used to set the data transfer
rate (in place of the DSR) for PC-AT, PS/2 and MicroChan-
nel applications. Other applications can set the data trans-
fer rate in the DSR. See Section 3.3.6 on page 43.
After the first command byte is written to the Data Register
(FIFO), bit 4 of MSR (CMD PROG, Command in Progress)
is also set and remains set until the last result phase byte is
read. If there is no result phase, the CMD PROG bit is
cleared after the last command byte is written.
This register is not affected by a software reset.
The data rate of the floppy controller is determined by the
last write to either the CCR register or to the DSR register.
A new command may be initiated after reading all the result
bytes from the previous command. If the next command re-
quires selection of a different drive or a change in the data
rate, the DOR and DSR or CCR should be updated, accord-
ingly. If the command is the last command, the software
should deselect the drive.
Write Operations
7
0
6
0
5
0
4
3
2
0
1
0
Configuration Control
Register (CCR)
Normally, command processing by the controller core and
updating of the DOR, DSR, and CCR registers by the micro-
processor are operations that can occur independently of
one another. Software must ensure that the these registers
are not updated while the controller is processing a com-
mand.
0
0
1
0
Reset
Offset 07h
Required
DRATE0
DRATE1
3.4.2
Execution Phase
During the execution phase, the Floppy Disk Controller
(FDC) performs the desired command.
Reserved
Commands that involve data transfers (e.g., read, write and
format operations) require the microprocessor to write or
read data to or from the Data Register (FIFO) at this time.
Some commands, such as SEEK or RECALIBRATE, con-
trol the read/write head movement on the disk drive during
the execution phase via the disk interface signals. Execu-
tion of other commands does not involve any action by the
microprocessor or disk drive, and consists of an internal op-
eration by the controller.
Bits 1,0 - Data Transfer Rate Select 1,0 (DRATE 1,0)
These bits determine the data transfer rate for the Flop-
py Disk Controller (FDC), depending on the supported
speeds.
TABLE 3-5 on page 43 shows the data transfer rate se-
lected by each value of this field.
These bits are unaffected by a software reset, and are
set to 10 (250 Kbps) after a hardware reset.
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The Floppy Disk Controller (FDC) (Logical Device 0)
Data can be transferred between the microprocessor and
has not yet reached its threshold trigger condition. This
guarantees that all current sector bytes are read from the
FIFO before the next sector byte transfer begins.
the controller during execution in DMA mode, interrupt
transfer mode or software polling mode. The last two modes
are non-DMA modes. All data transfer modes work with the
FIFO enabled or disabled.
Burst Mode Enabled - DRQ remains active until enough
bytes have been read from the controller to empty the
FIFO.
DMA mode is used if the system has a DMA controller. This
allows the microprocessor to do other tasks while data
transfer takes place during the execution phase.
Burst Mode Disabled - DRQ is deactivated after each
read transfer. If the FIFO is not completely empty, DRQ
is asserted again after a 350 nsec delay. This allows
other higher priority DMA transfers to take place be-
tween floppy disk transfers.
If a non-DMA mode is used, an interrupt is issued for each
byte transferred during the execution phase. Also, instead
of using the interrupt during a non-DMA mode transfer, the
Main Status Register (MSR) can be polled by software to in-
dicate when a byte transfer is required.
In addition, this mode allows the controller to work cor-
rectly in systems where the DMA controller is put into a
read verify mode, where only DACK signals are sent to
the FDC, with no RD pulses. This read verify mode of
the DMA controller is used in some PC software. When
burst mode is disabled, a pulse from the DACK input
signal may be issued by the DMA controller, to correctly
clocks data from the FIFO.
DMA Mode - FIFO Disabled
DMA mode is selected by writing a 0 to the DMA bit in the
SPECIFY command and by setting bit 3 of the DOR (DMA
enabled) to 1.
In the execution phase when the FIFO is disabled, each
time a byte is ready to be transferred, a DMA request (DRQ)
is generated in the execution phase. The DMA controller
should respond to the DRQ with a DMA acknowledge
(DACK) and a read or write pulse. The DRQ is cleared by
the leading edge of the active low DACK input signal. After
the last byte is transferred, an interrupt is generated, indi-
cating the beginning of the result phase.
Write Data Transfers
Whenever the number of bytes in the FIFO is less than or
equal to THRESH, a DRQ is generated. This is the trigger
condition for the FIFO write data transfers from the micro-
processor to the FDC.
Burst Mode Enabled - DRQ remains active until enough
bytes have been written to the controller to completely
fill the FIFO.
During DMA operations, FDC address signals are ignored
since AEN input signal is 1. The DACK signal acts as the
chip select signal for the FIFO, in this case, and the state of
the address lines A2-0 is ignored. The Terminal Count (TC)
signal can be asserted by the DMA controller to terminate
the data transfer at any time. Due to internal gating, TC is
only recognized when DACK is low.
Burst Mode Disabled - DRQ is deactivated after each
write transfer. If the FIFO is not full, DRQ is asserted
again after a 350 nsec delay. Deactivation of DRQ al-
lows other higher priority DMA transfers to take place
between floppy disk transfers.
PC-AT Drive Mode
The FIFO has a byte counter which monitors the number of
bytes being transferred to the FIFO during write operations
whether burst mode is enabled or disabled. When the last
byte of a sector is transferred to the FIFO, DRQ is deacti-
vated even if the FIFO has not been completely filled. Thus,
the FIFO is cleared after each sector is written. Only after
the FDC has determined that another sector is to be written,
is DRQ asserted again. Also, since DRQ is deactivated im-
mediately after the last byte of a sector is written to the
FIFO, the system will not be delayed by deactivation of
DRQ and is free to do other operations.
In PC-AT drive mode when the FIFO is disabled, the con-
troller is in single byte transfer mode. That is, the system
has the time it takes to transfer one byte, to service a DMA
request (DRQ) from the controller. DRQ is deactivated be-
tween bytes.
PS/2 Drive Mode
In PS/2 drive mode, for DMA transfers with the FIFO dis-
abled, instead of single byte transfer mode, the FIFO is en-
abled with THRESH = 0Fh. Thus, DRQ is asserted when
one byte enters the FIFO during a read, and when one byte
can be written to the FIFO during a write. DRQ is deactivat-
ed by the leading edge of the DACK input signal, and is as-
serted again when DACK becomes inactive high. This
operation is very similar to burst mode transfer with the
FIFO enabled except that DRQ is deactivated between
bytes.
Read and Write Data Transfers
The DACK input signal from the DMA controller may be held
active during an entire burst, or a pulse may be issued for
each byte transferred during a read or write operation. In
burst mode, the FDC deactivates DRQ as soon as it recog-
nizes that the last byte of a burst was transferred.
If a DACK pulse is issued for each byte, the leading edge of
this pulse is used to deactivate DRQ. If a DACK pulse is is-
sued, RD or WR is not required. This is the case during the
read-verify mode of the DMA controller.
DMA Mode - FIFO Enabled
Read Data Transfers
Whenever the number of bytes in the FIFO is greater than
or equal to (16 − THRESH), a DRQ is generated. This is the
trigger condition for the FIFO read data transfers from the
floppy controller to the microprocessor.
If DACK is held active during the entire burst, the trailing
edge of the RD or WR pulse is used to deactivate DRQ.
DRQ is deactivated within 50 nsec of the leading edge of
DACK, RD, or WR. This quick response should prevent the
DMA controller from transferring extra bytes in most of the
applications.
When the last byte in the FIFO has been read, DRQ be-
comes inactive. DRQ is asserted again when the FIFO trig-
ger condition is satisfied. After the last byte of a sector is
read from the disk, DRQ is again generated even if the FIFO
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46
The Floppy Disk Controller (FDC) (Logical Device 0)
Burst mode may be used to hold the IRQ signal active dur-
Overrun Errors
ing a burst, or burst mode may be disabled to toggle the IRQ
signal for each byte of a burst. The Main Status Register
(MSR) is always valid to the microprocessor. For example,
during a read command, after the last byte of data has been
read from the disk and placed in the FIFO, the MSR still in-
dicates that the execution phase is active, and that data
needs to be read from the Data Register (FIFO). Only after
the last byte of data has been read by the microprocessor
from the FIFO does the result phase begin.
An overrun or underrun error terminates the execution of a
command, if the system does not transfer data within the al-
lotted data transfer time. (See Section 3.3.7 on page 43.)
This puts the controller in the result phase.
During a read overrun, the microprocessor is required to
read the remaining bytes of the sector before the controller
asserts the appropriate IRQ signifying the end of execution.
During a write operation, an underrun error terminates the
execution phase after the controller has written the remain-
ing bytes of the sector with the last correctly written byte to
the FIFO. Whether there is an error or not, an interrupt is
generated at the end of the execution phase, and is cleared
by reading the first result phase byte.
The overrun and underrun error procedures for non-DMA
mode are the same as for DMA mode. Also, whether there
is an error or not, an interrupt is generated at the end of the
execution phase, and is cleared by reading the first result
phase byte.
DACK asserted alone, without a RD or WR pulse, is also
counted as a transfer. If pulses of RD or WR are not being
issued for each byte, a DACK pulse must be issued for each
byte so that the Floppy Disk Controller(FDC) can count the
number of bytes correctly.
Software Polling
If non-DMA mode is selected and interrupts are not suitable,
the microprocessor can poll the MSR during the execution
phase to determine when a byte is ready to be transferred.
The RQM bit (bit 7) in the MSR reflects the state of the IRQ
signal. Otherwise, the data transfer is similar to the interrupt
mode described above, whether the FIFO is enabled or dis-
abled.
The VERIFY command, allows easy verification of data
written to the disk without actually transferring the data on
the data bus.
Interrupt Transfer Mode - FIFO Disabled
3.4.3
Result Phase
If interrupt transfer (non-DMA) mode is selected, the appro-
priate IRQ signal is asserted instead of DRQ, when each
byte is ready to be transferred.
During the result phase, the microprocessor reads a series
of result bytes from the Data Register (FIFO). These bytes
indicate the status of the command. They may indicate
whether the command executed properly, or may contain
some control information.
The Main Status Register (MSR) should be read to verify
that the interrupt is for a data transfer. The RQM and NON
DMA bits (bits 7 and 5, respectively) in the MSR are set to
1. The interrupt is cleared when the byte is transferred to or
from the Data Register (FIFO). To transfer the data in or out
of the Data register, you must use the address bits of the
FDC together and RD or WR must be active, i.e., A2-0 must
be valid. It is not enough to just assert the address bits of
the FDC. RD or WR must also be active for a read or write
transfer to be recognized.
See the specific commands in Section 3.7 on page 53 or
Section 3.3.7 on page 43 for details.
These result bytes are read in the order specified for that
particular command. Some commands do not have a result
phase. Also, the number of result bytes varies with each
command. All result bytes must be read from the Data Reg-
ister (FIFO) before the next command can be issued.
The microprocessor should transfer the byte within the data
transfer service time (see Section 3.3.7 on page 43). If the
byte is not transferred within the time allotted, an overrun er-
ror is indicated in the result phase when the command ter-
minates at the end of the current sector.
As it does for command bytes, the Main Status Register
(MSR) controls the flow of result bytes, and must be polled
by the software before reading each result byte from the
Data Register (FIFO). The RQM bit (bit 7) and DIO bit (bit 6)
of the MSR must both be set before each result byte can be
read.
An interrupt is also generated after the last byte is trans-
ferred. This indicates the beginning of the result phase. The
RQM and DIO bits (bits 7 and 6, respectively) in the MSR
are set to 1, and the NON DMA bit (bit 5) is cleared to 0. This
interrupt is cleared by reading the first result byte.
After the last result byte is read, the Command in Progress
bit (bit 4) of the MSR is cleared, and the controller is ready
for the next command.
For more information, see Section 3.5 on page 48.
Interrupt Transfer Mode - FIFO Enabled
3.4.4
Idle Phase
Interrupt transfer (non-DMA) mode with the FIFO enabled is
very similar to interrupt transfer mode with the FIFO dis-
abled. In this case, the appropriate IRQ signal is asserted
instead of DRQ, under the same FIFO threshold trigger con-
ditions.
After a hardware or software reset, after the chip has recov-
ered from power-down mode or when there are no com-
mands in progress the controller is in the idle phase. The
controller waits for a command byte to be written to the Data
Register (FIFO). The RQM bit is set, and the DIO bit is
cleared in the MSR.
The MSR should be read to verify that the interrupt is for a
data transfer. The RQM and non-DMA bits (bits 7 and 5, re-
spectively) in the MSR are set. To transfer the data in or out
of the Data register, you must use the address bits of the
FDC together and RD or WR must be active, i.e., A2-0 must
be valid. It is not enough to just assert the address bits of
the FDC. RD or WR must also be active for a read or write
transfer to be recognized.
After receiving the first command (opcode) byte, the con-
troller enters the command phase. When the command is
completed the controller again enters the idle phase. The
Digital Data Separator (DDS) remains synchronized to the
reference frequency while the controller is idle. While in the
idle phase, the controller periodically enters the drive polling
phase.
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47
The Floppy Disk Controller (FDC) (Logical Device 0)
Bits 1,0 - Logical Drive Selected
3.4.5
Drive Polling Phase
These two binary encoded bits indicate the logical drive
selected at the end of the execution phase.
National Semiconductor’s FDC supports the polling mode
of old 8-inch drives, as a means of monitoring any change
in status for each disk drive present in the system. This sup-
port provides backward compatibility with software that ex-
pects it.
The value of these bits is reflected in bits 1,0 of the SR3
register, described in Section 3.5.4 on page 50.
00: Drive 0 selected.
01: Drive 1 selected.
In the idle phase, the controller enters a drive polling phase
every 1 msec, based on a 500 Kbps data transfer rate. In
the drive polling phase, the controller checks the status of
each of the logical drives (bits 0 through 3 of the MSR). The
internal ready line for each drive is toggled only after a hard-
ware or software reset, and an interrupt is generated for
drive 0.
10: If four drives are supported, or drives 2 and 0 are
exchanged, drive 2 is selected.
11: If four drives are supported, drive 3 is selected.
Bit 2 - Head Selected
This bit indicates which side of the Floppy Disk Drive
(FDD) is selected. It reflects the status of the HDSEL
signal at the end of the execution phase.
At this point, the software must issue four SENSE INTER-
RUPT commands to clear the status bit for each drive, un-
less drive polling is disabled via the POLL bit in the
CONFIGURE command. See “Bit 4 - Disable Drive Polling
(POLL)” on page 55. The CONFIGURE command must be
issued within 500 µsec (worst case) of the hardware or soft-
ware reset to disable drive polling.
The value of this bit is reflected in bit 2 of the ST3 regis-
ter, described in Section 3.5.4 on page 50.
0: Side 0 is selected.
1: Side 1 is selected.
Even if drive polling is disabled, drive stepping and delayed
power-down occur in the drive polling phase. The controller
checks the status of each drive and, if necessary, it issues
a pulse on the STEP output signal with the DIR signal at the
appropriate logic level.
Bit 3 - Not used.
This bit is not used and is always 0.
Bit 4 - Equipment Check
The controller also uses the drive polling phase to automat-
ically trigger power down. When the specified time that the
motor may be off expires, the controller waits 512 msec,
based on data transfer rates of 500 Kbps and 1 Mbps, be-
fore powering down, if this function is enabled via the
MODE command.
After a RECALIBRATE command, this bit indicates
whether the head of the selected drive was at track 0,
i.e., whether or not TRK0 was active. This information is
used during the SENSE INTERRUPT command.
0: Head was at track 0, i.e., a TRK0 pulse occurred
after a RECALIBRATE command.
If a new command is issued while the FDC is in the drive
polling phase, the MSR does not indicate a ready status for
the next parameter byte until the polling sequence com-
pletes the loop. This can cause a delay between the first
and second bytes of up to 500 µsec at 250 Kbps.
1: Head was not at track 0, i.e., no TRK0 pulse oc-
curred after a RECALIBRATE command.
Bit 5 - SEEK End
This bit indicates whether or not a SEEK, RELATIVE
SEEK, or RECALIBRATE command was completed by
the controller. Used during a SENSE INTERRUPT com-
mand.
3.5 THE RESULT PHASE STATUS REGISTERS
In the result phase of a command, result bytes that hold sta-
tus information are read from the Data Register (FIFO) at
offset 05h. These bytes are the result phase status regis-
ters.
0: SEEK, RELATIVE SEEK, or RECALIBRATE com-
mand not completed by the controller.
The result phase status registers may only be read from the
Data Register (FIFO) during the result phase of certain
commands, unlike the Main Status Register (MSR), which
is a read only register that is always valid.
1: SEEK, RELATIVE SEEK, or RECALIBRATE com-
mand was completed by the controller.
Bits 7,6 - Interrupt Code (IC)
These bits indicate the reason for an interrupt.
00: Normal termination of command.
3.5.1
Result Phase Status Register 0 (ST0)
01: Abnormal termination of command. Execution of
command was started, but was not successfully
completed.
7
0
6
0
5
0
4
3
2
0
1
0
Result Phase Status
Register 0 (ST0)
0
0
0
0
Reset
10: Invalid command issued. Command issued was not
recognized as a valid command.
Required
11: Internal drive ready status changed state during the
drive polling mode. This only occurs after a hard-
ware or software reset.
Logical Drive Selected
(Execution Phase)
Head Selected (Execution Phase)
Not Used
Equipment Check
SEEK End
Interrupt Code
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48
The Floppy Disk Controller (FDC) (Logical Device 0)
3.5.2
Result Phase Status Register 1 (ST1)
Bit 5 - CRC Error
This bit indicates whether or not the FDC detected a Cy-
clic Redundancy Check (CRC) error.
7
0
6
0
5
0
4
3
2
0
1
0
Result Phase Status
Register 1 (ST1)
0: No CRC error detected.
1: CRC error detected.
0
0
0
0
Reset
Required
Bit 5 of the result phase Status register 2 (ST2) in-
dicates when and where the error occurred. See
Section 3.5.3.
Missing Address Mark
Drive Write Protected
Missing Data
Not Used
Overrun or Underrun
CRC Error
Not Used
End of Track
Bit 6 - Not Used
This bit is not used and is always 0.
Bit 7 - End of Track
This bit is set to 1 when the FDC transfers the last byte
of the last sector without the TC signal becoming active.
The last sector is the End of Track sector number pro-
grammed in the command phase.
Bit 0 - Missing Address Mark
0: The FDC did not transfer the last byte of the last
sector without the TC signal becoming active.
This bit indicates whether or not the Floppy Disk Con-
troller (FDC) failed to find an address mark in a data field
during a read, scan, or verify command.
1: The FDC transferred the last byte of the last sector
without the TC signal becoming active.
0: No missing address mark.
1: Address mark missing.
3.5.3
Result Phase Status Register 2 (ST2)
Bit 0 of the result phase Status register 2 (ST2) in-
dicates the when and where the failure occurred.
See Section 3.5.3 on page 49.
7
0
6
0
5
0
4
3
2
0
1
0
Result Phase Status
Register 2 (ST2)
0
0
0
0
Reset
Bit 1 - Drive Write Protected
Required
When a write or format command is issued, this bit indi-
cates whether or not the selected drive is write protect-
ed, i.e., the WP signal is active.
Missing Address
Mark Location
Bad Track
Scan Not Satisfied
Scan Equal Hit
Wrong Track
CRC Error in Data Field
Control Mark
Not Used
0: Selected drive is not write protected, i.e., WP is not
active.
1: Selected drive is write protected, i.e., WP is active.
Bit 2 - Missing Data
This bit indicates whether or not data is missing for one
of the following reasons:
— Controller cannot find the sector specified in the
command phase during the execution of a read,
write, scan, or VERIFY command. An Address Mark
(AM) was found however, so it is not a blank disk.
Bit 0 - Missing Address Mark Location
If the FDC cannot find the address mark of a data field
or of an address field during a read, scan, or verify com-
mand, i.e., bit 0 of ST1 is 1, this bit indicates when and
where the failure occurred.
— Controller cannot read any address fields without a
CRC error during a READ ID command.
0: The FDC failed to detect an address mark for the
address field after two disk revolutions.
— Controller cannot find starting sector during execu-
tion of READ A TRACK command.
1: The FDC failed to detect an address mark for the
data field after it found the correct address field.
0: Data is not missing for one of these reasons.
1: Data is missing for one of these reasons.
Bit 1 - Bad Track
Bit 3 - Not Used
This bit indicates whether or not the FDC detected a bad
track
This bit is not used and is always 0.
0: No bad track detected.
1: Bad track detected.
Bit 4 - Overrun or Underrun
This bit indicates whether or not the FDC was serviced
by the microprocessor soon enough during a data trans-
fer in the execution phase. For read operations, this bit
indicates a data overrun. For write operations, it indi-
cates a data underrun.
The desired sector is not found. If the track number
recorded on any sector on the track is FFh and this
number is different from the track address specified
in the command phase, then there is a hard error in
IBM format.
0: FDC was serviced in time.
1: FDC was not serviced fast enough. Overrun or un-
derrun occurred.
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49
The Floppy Disk Controller (FDC) (Logical Device 0)
Bit 2 - Scan Not Satisfied
3.5.4
Result Phase Status Register 3 (ST3)
This bit indicates whether or not the value of the data
byte from the microprocessor meets any of the condi-
tions specified by the scan command used.
7
0
6
0
5
0
4
3
2
0
1
0
Result Phase Status
Register 3 (ST3)
0
0
0
0
Reset
Section 3.7.16 on page 69 and Table 3-20 on page 70
describe the conditions.
Required
0: The data byte from the microprocessor meets at
least one of the conditions specified.
Logical Drive Selected
(Command Phase)
1: The data byte from the microprocessor does not
meet any of the conditions specified.
Head Selected (Command Phase)
Not Used
Track 0
Not Used
Drive Write Protected
Not Used
Bit 3 - Scan Satisfied
This bit indicates whether or not the value of the data
byte from the microprocessor was equal to a byte on the
floppy disk during any scan command.
0: No equal byte was found.
Bits 1,0 - Logical Drive Selected
1: A byte whose value is equal to the byte from the
microprocessor was found on the floppy disk.
These two binary encoded bits indicate the logical drive
selected at the end of the command phase.
Bit 4 - Wrong Track
The value of these bits is the same as bits 1,0 of the SR0
register, described in Section 3.5.1 on page 48.
This bit indicates whether or not there was a problem
finding the sector because of the track number.
00: Drive 0 selected.
01: Drive 1 selected.
0: Sector found.
1: Desired sector not found.
10: If four drives are supported, or drives 2 and 0 are
exchanged, drive 2 is selected.
The desired sector is not found. The track number
recorded on any sector on the track is different
from the track address specified in the command
phase.
11: If four drives are supported, drive 3 is selected.
Bit 2 - Head Selected
This bit indicates which side of the Floppy Disk Drive
(FDD) is selected. It reflects the status of the HDSEL
signal at the end of the command phase.
Bit 5 - CRC Error in Data Field
When the FDC detected a CRC error in the correct sec-
tor (bit 5 of the result phase Status register 1 (ST1) is 1),
this bit indicates whether it occurred in the address field
or in the data field.
The value of this bit is the same as bit 2 of the SR0 reg-
ister, described in Section 3.5.1 on page 48.
0: Side 0 is selected.
1: Side 1 is selected.
0: The CRC error occurred in the address field.
1: The CRC error occurred in the data field.
Bit 3 - Not Used
Bit 6 - Control Mark
This bit is not used and is always 1.
When the controller tried to read a sector, this bit indi-
cates whether or not it detected a deleted data address
mark during execution of a READ DATA or scan com-
mands, or a regular address mark during execution of a
READ DELETED DATA command.
Bit 4 - Track 0
This bit Indicates whether or not the head of the select-
ed drive is at track 0.
0: The head of the selected drive is not at track 0, i.e.,
TRK0 is not active.
0: No control mark detected.
1: Control mark detected.
1: The head of the selected drive is at track 0, i.e.,
TRK0 is active.
Bit 7 - Not Used
This bit is not used and is always 0.
Bit 5 - Not Used
This bit is not used and is always 1.
Bit 6 - Drive Write Protected
This bit indicates whether or not the selected drive is
write protected, i.e., the WP signal is active (low).
0: Selected drive is not write protected, i.e., WP is not
active.
1: Selected drive is write protected, i.e., WP is active.
Bit 7 - Not Used
This bit is not used and is always 0.
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50
The Floppy Disk Controller (FDC) (Logical Device 0)
3.6 FDC REGISTER BITMAPS
3.6.1
Standard
PS/2 Drive Mode
Enhanced Drive Mode
7
6
5
4
3
2
1
0
Tape Drive
Register (TDR)
Offset 03h
7
0
6
5
0
4
3
2
1
0
Status Register
A (SRA)
1
0
0
Reset
0
0
Reset
Offset 00h
Required
Required
Head Direction
Tape Drive Select 1,0
Logical Drive Exchange
Drive ID0 Information
WP
INDEX
Head Select
TRK0
Step
Reserved
IRQ Pending
Drive ID1 Information
Reserved
Reserved
PS/2 Drive Mode
Read Operations
7
6
0
5
0
4
3
2
1
0
7
1
1
6
1
1
5
0
4
3
2
0
1
0
Main Status
Register (MSR)
Offset 04h
Status Register
B (SRB)
0
0
0
0
0
0
Reset
0
0
0
0
Reset
Offset 01h
Required
Required
Drive 0 Busy
Drive 1 Busy
Drive 2 Busy
Drive 3 Busy
Command in Progress
Non-DMA Execution
Data I/O Direction
RQM
MTR0
MTR1
WGATE
RDATA
WDATA
Drive Select Status
Reserved
Reserved
7
0
6
0
5
0
4
3
2
0
1
0
Write Operations
Digital Output
Register (DOR)
Offset 02h
7
0
6
0
5
4
3
2
0
1
0
0
0
0
0
Reset
Data Rate Select
Register (DSR)
Offset 04h
0
0
0
1
0
Reset
Required
Required
Drive Select
Reset Controller
DMAEN
Motor Enable 0
Motor Enable 1
Motor Enable 2
Motor Enable 3
DRATE0
DRATE1
Precompensation Delay Select
Undefined
Low Power
Software Reset
PC-AT Compatible Drive Mode
7
6
5
4
3
2
1
0
Tape Drive
Register (TDR)
Offset 03h
7
6
5
4
3
2
1
0
Data Register
(FIFO)
1
0
0
Reset
Reset
Offset 05h
Required
Required
Tape Drive Select 1,0
Data
Not Used
TRI-STATE During Read Operations
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51
The Floppy Disk Controller (FDC) (Logical Device 0)
3.6.2
Result Phase Status
Read Operations, PC-AT Drive Mode
7
6
1
5
4
3
2
1
0
7
0
6
0
5
0
4
3
2
0
1
0
Digital Input
Register (DIR)
Offset 07h
Result Phase Status
Register 0 (ST0)
1
1
1
1
Reset
0
0
0
0
Reset
Required
Required
Logical Drive Selected
(Execution Phase)
Head Selected (Execution Phase)
Not Used
Equipment Check
SEEK End
Reserved, In TRI-STATE
DSKCHG
Interrupt Code
Read Operations, PS/2 Drive Mode
7
0
6
5
0
4
3
2
0
1
0
Result Phase Status
Register 1 (ST1)
7
6
1
5
1
4
3
2
1
0
Digital Input
0
0
0
0
0
Reset
Register (DIR)
1
1
1
Reset
Required
Offset 07h
Required
Missing Address Mark
Drive Write Protected
Missing Data
Not Used
Overrun or Underrun
CRC Error
Not Used
End of Track
High Density
DRATE0 Status
DRATE1 Status
Reserved
DSKCHG
7
0
6
0
5
0
4
3
2
0
1
0
Result Phase Status
Register 2 (ST2)
Write Operations
0
0
0
0
Reset
7
0
6
0
5
0
4
3
2
0
1
0
Configuration Control
Register (CCR)
Required
0
0
1
0
Reset
Offset 07h
Missing Address
Mark Location
Required
Bad Track
Scan Not Satisfied
Scan Equal Hit
Wrong Track
CRC Error in Data Field
Control Mark
Not Used
DRATE0
DRATE1
Reserved
7
0
6
0
5
0
4
3
2
0
1
0
Result Phase Status
Register 3 (ST3)
0
0
0
0
Reset
Required
Logical Drive Selected
(Command Phase)
Head Selected (Command Phase)
Not Used
Track 0
Not Used
Drive Write Protected
Not Used
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52
The Floppy Disk Controller (FDC) (Logical Device 0)
3.7 COMMAND SET
TABLE 3-8. FDC Command Set Summary
The first command byte for each command in the FDC com-
mand set is the opcode byte. The FDC uses this byte to de-
termine how many command bytes to expect.
Opcode
Command
7
6
5
4
3
2
1
0
If an invalid command byte is issued to the controller, it im-
mediately enters the result phase and the status is 80h, sig-
nifying an invalid command.
CONFIGURE
DUMPREG
FORMAT TRACK
INVALID
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
1
1
1
1
0
1
0
1
TABLE 3-8 shows the FDC commands in alphabetical order
with the opcode, i.e., the first command byte, for each.
MFM
Invalid Opcode
In this table:
LOCK
0
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
0
1
0
●
MT is a multi-track enable bit (See “Bit 7 - Multi-Track
MODE
0
0
(MT)” on page 64.)
NSC
●
MFM is a modified frequency modulation parameter
PERPENDICULAR
MODE
(See “Bit 6 - Modified Frequency Modulation (MFM)”
on page 57.)
0
0
0
1
0
0
0
0
1
0
1
1
1
1
0
0
0
0
●
READ DATA
MT MFM SK
MT MFM SK
SK is a skip control bit. (See “Bit 5 - Skip Control (SK)”
on page 64.)
READ DELETED
DATA
Section 3.7.1 explains some symbols and abbreviations
you will encounter in the descriptions of the commands.
READ ID
0
0
0
1
MFM
MFM
0
0
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
1
All phases of each command are described in detail, start-
ing with Section 3.7.2 on page 55, with bitmaps of each byte
in each phase.
READ TRACK
RECALIBRATE
RELATIVE SEEK
SCAN EQUAL
DIR
Only named bits and fields are described in detail. When a
bitmap shows a value (0 or 1) for a bit, that bit must have
that value and is not described.
MT MFM SK
SCAN HIGH OR
EQUAL
MT MFM SK
1
1
1
0
1
SCAN LOW OR
EQUAL
MT MFM SK
1
0
0
1
1
0
0
1
1
0
1
0
1
1
0
SEEK
0
0
0
0
0
0
0
SENSE DRIVE
STATUS
SENSE INTERRUPT
SET TRACK
SPECIFY
0
0
0
0
1
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
0
0
1
0
VERIFY
MT MFM SK
VERSION
0
0
0
0
WRITE DATA
MT MFM
WRITE DELETED
DATA
MT MFM
0
0
1
0
0
1
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53
The Floppy Disk Controller (FDC) (Logical Device 0)
Abbreviations Used in FDC Commands LOCK Lock enable bit in the LOCK command. Used to
3.7.1
prevent certain parameters from being affected by
a software reset.
BFR Buffer enable bit set in the MODE command. En-
ables open-collector output buffers.
LOW PWR
BST Burst mode disable control bit set in MODE com-
mand. Disables burst mode for the FIFO, if the
FIFO is enabled.
Low Power control bits set in the MODE command.
MFM Modified Frequency Modulation parameter used in
FORMAT TRACK, read, VERIFY and write com-
mands.
DC3-0 Drive Configuration for drives 3-0. Used to config-
ure a logical drive to conventional or perpendicular
mode in the PERPENDICULAR MODE command.
MFT Motor Off Time. Now called Delay After Processing
time. This delay is set by the SPECIFY command.
DENSEL
MNT Motor On Time. Now called Delay Before Process-
ing time. This delay is set by the SPECIFY com-
mand.
Density Select control bits set in the MODE com-
mand.
DIR Direction control bit used in RELATIVE SEEK com-
MSB Most Significant Byte controls which whether the
most or least significant byte is read or written in
the SET TRACK command.
mand to indicate step in or out.
DMA DMA mode enable bit set in the SPECIFY com-
mand.
MT
Multi-Track enable bit used in read, write, scan and
VERIFY commands.
DS1-0 Drive Select for bits 1,0 used in most commands.
Selects the logical drive.
OW
Overwrite control bit set in the PERPENDICULAR
MODE command.
EC
Enable Count control bit set in the VERIFY com-
mand. When this bit is 1, SC (Sectors to read
Count) command byte is required.
POLL Enable Drive Polling bit set in the CONFIGURE
command.
EIS
Enable Implied Seeks. Set in the CONFIGURE
command.
PRETRK
Precompensation Track Number set in the CON-
FIGURE command
EOT End of Track parameter set in read, write, scan,
and VERIFY commands.
PTR Present Track number. Contains the internal 8-bit
track number or the least significant byte of the 12-
bit track number of one of the four logical disk
drives. PTR is set in the SET TRACK command.
ETR Extended Track Range set in the MODE command.
FIFO First-In First-Out buffer. Also a control bit set in the
CONFIGURE command to enable or disable the
FIFO.
R255 Recalibration control bit set in MODE command.
Sets maximum number of STEP pulses during
RECALIBRATE command to 255.
FRD FIFO Read Disable control bit set in the MODE
command
RTN Relative Track Number used in the RELATIVE
FWR FIFO Write disable control bit set in the MODE
SEEK command.
command.
SC
SK
Sector Count control bit used in the VERIFY com-
mand.
Gap 2 The length of gap 2 in the FORMAT TRACK com-
mand and the portion of it that is rewritten in the
WRITE DATA command depend on the drive mode,
i.e., perpendicular or conventional. FIGURE 3-5 on
page 59 illustrates gap 2 graphically. For more de-
tails, see “Bits 1,0 - Group Drive Mode Configura-
tion (GDC)” on page 62.
Skip control bit set in read and scan and VERIFY
operations.
SRT Step Rate Time set in the SPECIFY command. De-
termines the time between STEP pulses for SEEK
and RECALIBRATE operations.
Gap 3 Gap 3 is the space between sectors, excluding the
synchronization field. It is defined in the FORMAT
TRACK command. See FIGURE 3-5 on page 59.
ST0-3
Result phase Status registers 3-0 that contain sta-
tus information about the execution of a command.
See Sections 3.5.1 on page 48 through 3.5.4 on
page 50.
GDC Group Drive Configuration for all drives. Configures
all logical drives as conventional or perpendicular.
Used in the PERPENDICULAR MODE command.
Formerly, GAP2 and WG.
THRESH
FIFO threshold parameter set in the CONFIGURE
command
HD
Head Select control bit used in most commands.
Selects Head 0 or 1 of the disk.
TMR Timer control bit set in the MODE command. Af-
IAF
Index Address Field control bit set in the MODE
command. Enables the ISO Format during the
FORMAT command.
fects the timers set in the SPECIFY command.
WG Formerly, the Write Gate control bit. Now included
in the Group Drive mode Configuration (GDC) bits
in the PERPENDICULAR MODE command.
IPS
Implied Seek enable bit set in the MODE, read,
write, and scan commands.
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The Floppy Disk Controller (FDC) (Logical Device 0)
WLD Wildcard bit in the MODE command used to enable
Bit 6 - Enable Implied Seeks (EIS)
or disable the wildcard byte (FFh) during scan com-
mands.
This bit enables or disables implied seek operations. A
software reset disables implied seeks, i.e., clears this bit
to 0.
WNR Write Number controls whether to read an existing
track number or to write a new one in the SET
TRACK command.
Bit 5 of the MODE command (Implied Seek (IPS) can
override the setting of this bit and enable implied seeks
even if they are disabled by this bit.
3.7.2
The CONFIGURE Command
When implied seeks are enabled, a seek or sense inter-
rupt operation is performed before execution of the read,
write, scan, or verify operation.
The CONFIGURE command controls some operation
modes of the controller. It should be issued during the ini-
tialization of the FDC after power up.
0: Implied seeks disabled. The MODE command can
still enable implied seek operations. (Default)
The bits in the CONFIGURE registers are set to their default
values after a hardware reset.
1: Implied seeks enabled for read, write, scan and
VERIFY operations, regardless of the value of the
IPS bit in the MODE command.
Command Phase
Fourth Command Phase Byte, Bits 7-0,
Precompensation Track Number (PRETRK)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
0
This byte identifies the starting track number for write
precompensation. The value of this byte is programma-
ble from track 0 (00h) to track 255 (FFh).
EIS FIFO POLL
Threshold (THRESH)
If the LOCK bit (bit 7 of the opcode of the LOCK com-
mand) is 0, after a software reset this byte indicates
track 0 (00h).
Precompensation Track Number (PRETRK)
If the LOCK bit is 1, PRETRK retains its previous value
after a software reset.
Third Command Phase Byte
Bits 3-0 - The FIFO Threshold (THRESH)
Execution Phase
These bits specify the threshold of the FIFO during the
execution phase of read and write data transfers.
Internal registers are written.
This value is programmable from 00h to 0Fh. A software
reset sets this value to 00 if the LOCK bit (bit 7 of the op-
code of the LOCK command) is 0. If the LOCK bit is 1,
THRESH retains its value.
Result Phase
None.
3.7.3
The DUMPREG Command
Use a high value of THRESH for systems that respond
slowly and a low value for fast systems.
The DUMPREG command supports system run-time diag-
nostics, and application software development and debug-
ging.
Bit 4 - Disable Drive Polling (POLL)
This bit enables and disabled drive polling. A software
reset clears this bit to 0.
DUMPREG has a one-byte command phase (the opcode)
and a 10-byte result phase, which returns the values of pa-
rameters set in other commands. See the commands that
set each parameter for a detailed description of the param-
eter.
When drive polling is enabled, an interrupt is generated
after a reset.
When drive polling is disabled, if the CONFIGURE com-
mand is issued within 500 msec of a hardware or soft-
ware reset, then an interrupt is not generated. In
addition, the four SENSE INTERRUPT commands to
clear the Ready Changed State of the four logical drives
is not required.
Command Phase
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
0
0: Enable drive polling. (Default)
1: Disable drive polling.
Execution Phase
Bit 5 - Enable FIFO (FIFO)
Internal registers read.
This bit enables and disables the FIFO for execution
phase data transfers.
If the LOCK bit (bit 7 of the opcode of the LOCK com-
mand) is 0, a software reset disables the FIFO, i.e., sets
this bit to 1.
If the LOCK bit is 1, this bit retains its previous value af-
ter a software reset.
0: FIFO enabled for read and write operations.
1: FIFO disabled. (Default)
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55
The Floppy Disk Controller (FDC) (Logical Device 0)
The value of this is determined by bit 7 of the opcode of
Result Phase
the LOCK command.
7
6
5
4
3
2
1
0
0: Bits in this command are set to their default values
after a software reset. (Default)
Byte of Present Track Number (PTR) Drive 0
Byte of Present Track Number (PTR) Drive 1
Byte of Present Track Number (PTR) Drive 2
Byte of Present Track Number (PTR) Drive 3
1: Bits in this command are unaffected by a software
reset.
Ninth and Tenth Result Phase Bytes
These bytes reflect the values in the third and fourth
command phase bytes of the CONFIGURE command.
See Section 3.7.2 on page 55.
Step Rate Time (SRT)
Delay Before Processing
Sectors per Track or End of Track (EOT) Sector #
Delay After Processing
DMA
3.7.4
The FORMAT TRACK Command
This command formats one track on the disk in IBM, ISO, or
Toshiba perpendicular format.
LOCK
0
0
DC3 DC2 DC1 DC0
EIS FIFO POLL THRESH
Precompensation Track Number (PRETRK)
GDC
After a pulse from the INDEX signal is detected, data pat-
terns are written on the disk including all gaps, Address
Marks (AMs), address fields and data fields. See FIGURE
3-5 on page 59.
The format of the track is determined by the following pa-
rameters:
After a hardware or software reset, parameters in this phase
are reset to their default values. Some of these parameters
are unaffected by a software reset, depending on the state
of the LOCK bit.
●
The MFM bit in the opcode (first command) byte, which
indicates the type of the disk drive and the data transfer
rate and determines the format of the address marks
and the encoding scheme.
See the command that determines the setting for the bit or
field for details.
●
The Index Address Format (IAF) bit (bit 6 in the second
First through Fourth Result Phase Bytes, Bits 7-0,
Present Track Number (PTR) Drives 3-0
command phase byte) in the MODE command, which
selects IBM or ISO format.
Each of these bytes contains either the internal 8-bit
track number or the least significant byte of the 12-bit
track number of the corresponding logical disk drive.
●
The Group Drive Configuration (GDC) bits in the PER-
PENDICULAR MODE command, which select either
conventional or Toshiba perpendicular format.
Fifth and Sixth Result Phase Bytes, Bits 7-0,
Step Rate Time, Motor Off Time, Motor On Time and DMA
●
A bytes-per-sector code, which determines the sector
size. See TABLE 3-10 on page 57.
These fields are all set by the SPECIFY command. See
Section 3.7.21 on page 73.
●
A sectors per track parameter, which specifies how
many sectors are formatted on the track.
Seventh Result Phase Byte -
Sectors Per Track or End of Track (EOT)
●
The data pattern byte, which is used to fill the data field
of each sector.
This byte varies depending on what commands have
been previously executed.
TABLE 3-9 on page 57 shows typical values for these pa-
rameters for specific PC compatible diskettes.
If the last command issued was a FORMAT TRACK
command, and no read or write commands have been
issued since then, this byte contains the sectors per
track value.
To allow flexible formatting, the microprocessor must sup-
ply the four address field bytes (track number, head num-
ber, sector number, bytes-per-sector code) for each sector
formatted during the execution phase. This allows non-se-
quential sector interleaving.
If a read or a write command was executed more recent-
ly than a FORMAT TRACK command, this byte speci-
fies the number of the sector at the End of the Track
(EOT).
This transfer of bytes from the microprocessor to the con-
troller can be done in DMA or non-DMA mode (See Section
3.4.2 on page 45), with the FIFO enabled or disabled.
Eighth Result Phase Byte
Bits 5-0 - DC3-0, GDC
The FORMAT TRACK command terminates when a pulse
from the INDEX signal is detected a second time, at which
point an interrupt is generated.
Bits 5-0 of the second command phase byte of the PER-
PENDICULAR MODE command set bits 5-0 of this byte.
See “Bits 5-2 -Drive 3-0 Mode Configuration (DC3-0)”
on page 63.
Bit 7 - LOCK
This bit controls how the other bits in this command re-
spond to a software reset. See Section 3.7.6 on page
60.
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56
The Floppy Disk Controller (FDC) (Logical Device 0)
First Command Phase Byte, Opcode
Command Phase
Bit 6 - Modified Frequency Modulation (MFM)
7
6
5
4
3
2
1
0
This bit indicates the type of the disk drive and the data
transfer rate, and determines the format of the address
marks and the encoding scheme.
0
MFM
X
0
0
1
1
0
1
X
X
X
X
HD
DS1 DS0
0: FM mode, i.e., single density.
1: MFM mode, i.e., double density.
Bytes-Per-Sector Code
Sectors per Track
Bytes in Gap 3
Data Pattern
TABLE 3-9. Typical Values for PC Compatible Diskette Media
Bytes-Per-Sector End of Track (EOT) Bytes in Gap 2 1 Bytes in Gap 3 2
Bytes in Data
Media Type
Field (decimal)
Code (hex)
Sector # (hex)
(hex)
(hex)
360 KB
1.2 MB
512
512
512
512
512
02
02
02
02
02
09
0F
09
12
24
2A
1B
1B
1B
1B
50
54
50
6C
53
720 KB
1.44 MB
2.88 MB3
1. Gap 2 is specified in the command phase of read, write, scan, and verify commands. Although this is the
recommended value, the FDC ignores this byte in read, write, scan and verify commands.
2. Gap 3 is the suggested value for the programmable GAP3 that is used in the FORMAT TRACK com-
mand and is illustrated in FIGURE 3-5 on page 59.
3. The 2.88 MB diskette media is a barium ferrite media intended for use in perpendicular recording drives
at the data rate of up to 1 Mbps.
Second Command Phase Byte
Third Command Phase Byte -Bytes-Per-Sector Code
This byte contains a code in hexadecimal format that in-
dicates the number of bytes in a data field.
Bits 1,0 - Logical Drive Select (DS1,0)
These bits indicate which logical drive is active. They re-
flect the values of bits 1,0 of the Digital Output Register
(DOR) described in “Bits 1,0 - Drive Select” on page 40
and of result phase status registers 0 and 3 (ST0 and
ST3) described in Sections 3.5.1 on page 48 and 3.5.4
on page 50.
TABLE 3-10 on page 57 shows the number of bytes in
a data field for each code.
TABLE 3-10. Bytes per Sector Codes
Bytes-Per-Sector Code (hex) Bytes in Data Field
00: Drive 0 is selected. (Default)
01: Drive 1 is selected.
00
01
02
03
04
05
06
07
128
256
10: If four drives are supported, or drives 2 and 0 are
exchanged, drive 2 is selected.
512
11: If four drives are supported, drive 3 is selected.
1024
2048
4096
8192
16384
Bit 2 - Head Select (HD)
This bit indicates which side of the Floppy Disk Drive
(FDD) is selected by the head. Its value is the inverse of
the HDSEL disk interface output signal.
This bit reflects the value of bit 3 of Status Register A
(SRA) described in Section 3.3.1 on page 38 and bit 2
of result phase status registers 0 and 3 (ST0 and ST3)
described in Sections 3.5.1 on page 48 and 3.5.4 on
page 50, respectively.
Fourth Command Phase Byte - Sectors Per Track
The value in this byte specifies how many sectors there
are in the track.
0: HDSEL is not active, i.e., the head of the FDD se-
lects side 0. (Default)
Fifth Command Phase Byte - Bytes in Gap 3
1: HDSEL is active, i.e., the head of the FDD selects
side 1.
The number of bytes in gap 3 is programmable. The
number to program for Gap 3 depends on the data
transfer rate and the type of the disk drive. TABLE 3-11
on page 58 shows some typical values to use for Gap 3.
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57
The Floppy Disk Controller (FDC) (Logical Device 0)
FIGURE 3-5 on page 59 illustrates the track format for
Execution Phase
each of the formats recognized by the FORMAT TRACK
command.
The system transfers four ID bytes (track number, head
number, sector number and bytes-per-sector code) per sec-
tor to the Floppy Disk Controller (FDC) in either DMA or
non-DMA mode. Section 3.4.2 on page 45 describes these
modes.
Sixth Command Phase Byte - Data Pattern
This byte contains the contents of the data field.
The entire track is formatted. The data block in the data field
of each sector is filled with the data pattern byte.
Only the first three status bytes in this phase are significant.
TABLE 3-11. Typical Gap 3 Values
Drive Type and
Bytes in Data Bytes-Per-Sector End of Track (EOT) Bytes in Gap 2 1 Bytes in Gap 3 2
Data Transfer Rate Field (decimal)
Code (hex)
Sector # (hex)
(hex)
(hex)
256
256
01
01
02
02
03
04
05
010
02
02
03
04
05
06
12
10
08
09
04
02
01
1A
0F
12
08
04
02
01
0A
20
2A
2A
80
C8
C8
0E
1B
1B
35
99
C8
C8
0C
32
50
50
F0
FF
FF
36
54
6C
74
FF
FF
FF
250 Kbps
MFM
512
512
1024
2048
4096
256
500 Kbps
MFM
512
512
1024
2048
4096
8192
1. Gap 2 is specified in the command phase of read, write, scan, and verify commands. Although this is the rec-
ommended value, the FDC ignores this byte in read, write, scan and verify commands.
2. Gap 3 is the suggested value for use in the FORMAT TRACK command. This is the programmable Gap 3
illustrated in FIGURE 3-5 on page 59.
Result Phase
3.7.5
The INVALID Command
If an INVALID command (illegal opcode byte in the com-
mand phase) is received by the Floppy Disk Controller
(FDC), the controller responds with the result phase Status
Register 0 (ST0) in the result phase. See Section 3.5.1 on
page 48.
7
6
5
4
3
2
1
0
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
Undefined
The controller does not generate an interrupt during this
condition. Bits 7 and 6 in the MSR (see Section 3.3.6 on
page 43) are both set to 1, indicating to the microprocessor
that the controller is in the result phase and the contents of
ST0 must be read.
Undefined
Undefined
Command Phase
Undefined
7
6
5
4
3
2
1
0
Invalid Opcodes
Execution Phase
None.
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58
The Floppy Disk Controller (FDC) (Logical Device 0)
Result Phase
The system reads the value 80h from ST0 indicating that an
invalid command was received.
7
6
5
4
3
2
1
0
Result Phase Status Register 0 (STO) (80h)
Index Pulse
AM
T
r
a
c
k
H
e
a
d
S
e
c
t
o
r
#
B
y
t
e
s
C
R
C
Gap 2 SYNC
22 of 12 of
AM
Data
C
R
C
Gap 3 Gap 4
Program-
able
Gap 0 SYNC
80 of 12 of
IAM
Gap 1 SYNC
50 of 12 of
IBM
Format
(MFM)
4E
00
4E
00
4E
00
3 of
A1* FE
3 of
C2* FC
FB
or
3 of
A1*
F8
Toshiba
Perpendicular
Format
AM
T
r
a
c
k
H
e
a
d
S
e
c
t
o
r
#
B
y
t
e
s
C
R
C
Gap 2 SYNC
41 of 12 of
AM
Data
C
R
C
Gap 3 Gap 4
Program-
able
Gap 0 SYNC
80 of 12 of
IAM
Gap 1 SYNC
50 of 12 of
4E
00
4E
00
4E
00
3 of
A1* FE
3 of
C2* FC
FB
or
3 of
A1*
F8
Index
Field
Address
AM
T
r
a
c
k
H
e
a
d
S
e
c
t
o
r
#
B
y
t
e
s
C
R
C
Gap 2 SYNC
22 of 12 of
AM
Data
C
R
C
Gap 3 Gap 4
Program-
able
Gap 1 SYNC
32 of 12 of
ISO
Format
(MFM)
4E
00
4E
00
3 of
A1* FE
FB
or
3 of
A1*
F8
Address Field
Repeated for each sector
Data Field
A1* = Data Pattern of A1, Clock Pattern of 0A. All other data rates use gap 2 = 22 bytes.
C2* = Data Pattern of C2, Clock Pattern of 14
FIGURE 3-5. IBM, Perpendicular, and ISO Formats Supported by the FORMAT TRACK Command
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59
The Floppy Disk Controller (FDC) (Logical Device 0)
0: Track number is stored as a standard 8-bit value
3.7.6
The LOCK Command
compatible with the IBM, ISO, and Toshiba Perpen-
dicular formats.
The LOCK command can be used to keep the FIFO en-
abled and to retain the values of some parameters after a
software reset.
This allows access of up to 256 tracks during a
seek operation. (Default)
After the command byte of the LOCK command is written,
its result byte must be read before the opcode of the next
command can be read. The LOCK command is not execut-
ed until its result byte is read by the microprocessor.
1: Track number is stored as a 12-bit value.
The upper four bits of the track value are stored in
the upper four bits of the head number in the sector
address field.
If the part is reset after the command byte of the LOCK com-
mand is written but before its result byte is read, then the
LOCK command is not executed. This prevents accidental
execution of the LOCK command.
This allows access of up to 4096 tracks during a
seek operation. With this bit set, an extra byte is re-
quired in the SEEK command phase and SENSE
INTERRUPT result phase.
Command Phase
Bits 3,2 - Low-Power Mode (LOW PWR)
7
6
5
4
3
2
1
0
These bits determine whether or not the FDC powers
down and, if it does, they specific how long it will take.
LOCK
0
0
1
0
1
0
0
These bits disable power down, i.e., are cleared to 0, af-
ter a software reset.
Bit 7 - Control Reset Effect (LOCK)
00: Disables power down. (Default)
01: Automatic power down.
This bit determines how the FIFO, THRESH, and
PRETRK bits in the CONFIGURE command and, the
FWR, FRD, and BST bits in the MODE command are af-
fected by a software reset.
At a 500 Kbps data transfer rate, the FDC goes into
low-power mode 512 msec after it becomes idle.
At a 250 Kbps data transfer rate, the FDC goes into
low-power mode 1 second after it becomes idle.
0: Set default values after a software reset. (Default)
1: Values are unaffected by a software reset.
10: Manual power down.
The FDC powers down mode immediately.
11: Not used.
Execution Phase
Internal register is written.
Bit 5 - Implied Seek (IPS)
Result Phase
This bit determines whether the Implied Seek (IPS) bit
in a command phase byte of a read, write, scan, or verify
command is ignored or READ.
7
6
5
4
3
2
1
0
0
0
0
LOCK
0
0
0
0
A software reset clears this bit to its default value of 0.
0: The IPS bit in the command byte of a read, write,
scan, or verify is ignored. (Default)
Bit 4 - Control Reset Effect (LOCK)
Same as bit 7 of opcode in command phase.
Implied seeks can still be enabled by the Enable
Implied Seeks (EIS) bit (bit 6 of the third command
phase byte) in the CONFIGURE command.
3.7.7 The MODE Command
1: The IPS bit in the command byte of a read, write,
scan, or verify is read.
This command selects the special features of the controller.
The bits in the command bytes of the MODE command are
set to their default values after a hardware reset.
If it is set to 1, the controller performs seek and
sense interrupt operations before executing the
command.
Command Phase
Bit 6 - Index Address Format (IAF)
7
6
5
4
3
2
1
0
This bit determines whether the controller formats
tracks with or without an index address field.
0
0
0
0
0
0
0
0
0
0
1
ETR
0
A software reset clears this bit to its default value of 0.
TMR IAF
IPS
LOW PWR
0: The controller formats tracks with an index address
field. (IBM and Toshiba Perpendicular format).
FWR FRD BST R255
DENSEL BFR WLD
0
0
0
Head Settle Factor
1: The controller formats tracks without an index ad-
dress field. (ISO format).
0
0
0
0
0
0
0
Bit 7 - Motor Timer Values (TMR)
Second Command Phase Byte
Bit 0 - Extended Track Range (ETR)
This bit determines which group of values to use to cal-
culate the Delay Before Processing and Delay After Pro-
cessing times. The value of each is programmed using
the SPECIFY command, which is described in TABLES
3-23 on page 74 and 3-24 on page 74.
This bit determines how the track number is stored. It is
cleared to 0 after a software reset.
A software reset clears this bit to its default value of 0.
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60
The Floppy Disk Controller (FDC) (Logical Device 0)
0: Use the TMR = 0 group of values. (Default)
1: Disable FIFO. All write data transfers take place
without the FIFO.
1: Use the TMR = 1 group of values.
Fourth Command Phase Byte
Bits 3-0 - Head Settle Factor
Third Command Phase Byte
Bit 4 - RECALIBRATE Step Pulses (R255)
This field is used to specify the maximum time allowed
for the read/write head to settle after a seek during an
implied seek operation.
This bit determines the maximum number of RECALI-
BRATE step pulses the controller issues before termi-
nating with an error, depending on the value of the
Extended Track Range (ETR) bit, i.e., bit 0 of the sec-
ond command phase byte in the MODE command.
The value specified by these bits (the head settle factor)
is multiplied by the multiplier for selected data rate to
specify a head settle time that is within the range for that
data rate.
A software reset clears this bit to its default value of 0.
0: If ETR (bit 0) = 0, the controller issues a maximum
of 85 recalibration step pulses.
Use the following formula to determine the head settle
factor that these bits should specify:
If ETR (bit 0) = 1, the controller issues a maximum
of 3925 recalibration step pulses. (Default)
Head Settle Factor x Multiplier = Head Settle Time
TABLE 3-12 on page 61 shows the multipliers and head
settle time ranges for each data transfer rate. The de-
fault head settle factor, i.e., value for these bits, is 8.
1: If ETR (bit 0) = 0, the controller issues a maximum
of 255 recalibration step pulses.
If ETR (bit 0) = 1, the controller issues a maximum
of 4095 recalibration step pulses.
TABLE 3-12. Multipliers and Head Settle Time Ranges
for Different Data Transfer Rates
Bit 5 - Burst Mode Disable (BST)
Data Transfer
Rate (Kbps)
Head Settle
Time Range (msec)
This bit enables or disables burst mode, if the FIFO is
enabled (bit 5 in the CONFIGURE command is 0). If the
FIFO is not enabled in the CONFIGURE command, then
the value of this bit is ignored.
Multiplier
250
300
8
6.666
4
0 - 120
0 - 100
0 - 60
A software reset enables burst mode, i.e., clears this bit
to its default value of 0, if the LOCK bit (bit 7 of the op-
code of the LOCK command) is 0. If it is 1, BST retains
its value after a software reset.
500
1000
2
0 - 30
0: Burst mode enabled for FIFO execution phase data
transfers. (Default)
Bit 4 - Scan Wild Card (WLD)
This bit determines whether or not a value of FFh from
either the microprocessor or the disk is recognized dur-
ing a scan command as a wildcard character.
1: Burst mode disabled.
The FDC issues one DRQ or IRQ6 pulse for each
byte to be transferred while the FIFO is enabled.
0: A value of FFh from either the microprocessor or
the disk during a scan command is interpreted as a
wildcard character that always matches. (Default)
Bit 6 - FIFO Read Disable (FRD)
This bit enables or disables the FIFO for microprocessor
read transfers from the controller, if the FIFO is enabled
(bit 5 in the CONFIGURE command is 0). If the FIFO is
not enabled in the CONFIGURE command, then the val-
ue of this bit is ignored.
1: The scan commands do not recognize a value of
FFh as a wildcard character.
Bit 5 - CMOS Disk Interface Buffer Enable (BFR)
This bit configures drive output signals.
A software reset enables the FIFO for reads, i.e., clears
this bit to its default value of 0, if the LOCK bit (bit 7 of
the opcode of the LOCK command) is 0. If it is 1, FRD
retains its value after a software reset.
0: Drive output signals are configured as standard 4
mA push-pull output signals (40 mA sink, 4 mA
source). (Default)
1: Drive output signals are configured as 40 mA open-
drain output signals.
0: Enable FIFO. Execution phase of microprocessor
read transfers use the internal FIFO. (Default)
1: Disable FIFO. All read data transfers take place
without the FIFO.
Bits 7,6 - Density Select Pin Configuration (DENSEL)
This field can configure the polarity of the Density Select
output signal (DENSEL) as always low or always high,
as shown in Table 4-3. This allows the user more flexi-
bility with new drive types.
Bit 7 - FIFO Write Enable or Disable (FWR)
This bit enables or disables write transfers to the con-
troller, if the FIFO is enabled (bit 5 in the CONFIGURE
command is 0). If the FIFO is not enabled in the CON-
FIGURE command, then the value of this bit is ignored.
This field overrides the DENSEL polarity defined by the
DENSEL polarity bit of the SuperI/O FDC configuration
register at index F0h and described in Section 2.5.1 on
page 30.
A software reset enables the FIFO for writes, i.e., clears
this bit to its default value of 0, if the LOCK bit (bit 7 of
the opcode of the LOCK command) is 0. If it is 1, FWR
retains its value after a software reset.
00: The DENSEL signal is always low.
01: The DENSEL signal is always high.
10: The DENSEL signal is undefined.
0: Enable FIFO. Execution phase microprocessor
write transfers use the internal FIFO. (Default)
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The Floppy Disk Controller (FDC) (Logical Device 0)
11: The polarity of the DENSEL signal is defined by the
3.7.9
The PERPENDICULAR MODE Command
DENSEL Polarity bit (bit 5) of the SuperI/O FDC
configuration register. See page “Bit 5 - DENSEL
Polarity Control” on page 30. (Default)
The PERPENDICULAR MODE command configures each
of the four logical disk drives for perpendicular or conven-
tional mode via the logical drive configuration bits 1,0 or 5-
2, depending on the value of bit 7. The default mode is con-
ventional. Therefore, if the drives in the system are conven-
tional, it is not necessary to issue a PERPENDICULAR
MODE command.
TABLE 3-13. DENSEL Encoding
Bit 7
Bit 6
DENSEL Pin Definition
0
0
1
1
0
1
0
1
DENSEL low
DENSEL high
undefined
This command supports the unique FORMAT TRACK and
WRITE DATA requirements of perpendicular (vertical) re-
cording disk drives with a 4 MB unformatted capacity.
Perpendicular recording drives operate in extra high density
mode at 1 or 2 Mbps, and are downward compatible with
1.44 MB and 720 KB drives at 500 kbps (high density) and
250 kbps (double density), respectively.
Set by bit 5 of the SuperI/O FDC
configuration register at offset F0h.
Execution Phase
If the system includes perpendicular drives, this command
should be issued during initialization of the FDC. Then,
when a drive is accessed for a FORMAT TRACK or WRITE
DATA command, the FDC adjusts the command parame-
ters based on the data rate. See TABLE 3-14 on page 63.
Internal registers are written.
Result Phase
None.
Precompensation is set to zero for perpendicular drives at
any data rate.
3.7.8
The NSC Command
Perpendicular recording type disk drives have a pre-erase
head that leads the read or write head by 200 µm, which
translates to 38 bytes at a 1 Mbps data transfer rate (19
bytes at 500 Kbps).
The NSC command can be used to distinguish between the
FDC versions and the 82077.
Command Phase
The increased space between the two heads requires a
larger gap 2 between the address field and data field of a
sector at 1 or 2 Mbps. See Perpendicular Format in FIG-
URE 3-5 on page 59. A gap 2 length of 41 bytes (at 1 or 2
Mbps) ensures that the preamble in the data field is com-
pletely pre-erased by the pre-erase head.
7
6
5
4
3
2
1
0
0
0
0
1
1
0
0
0
Execution Phase
Result Phase.
Also, during WRITE DATA operations to a perpendicular
drive, a portion of gap 2 must be rewritten by the controller
to guarantee that the data field preamble has been pre-
erased. See TABLE 3-14 on page 63.
7
6
5
4
3
2
1
0
Command Phase
0
1
1
1
0
0
1
1
7
6
5
4
3
2
1
0
The result phase byte of the NSC command identifies the
floppy disk controller (FDC) as a PC87309 by returning a
value of 73h.
0
0
0
0
1
0
0
1
0
OW
DC3 DC2 DC1 DC0
GDC
The 82077 and DP8473 return the value 80h, signifying an
invalid command.
Second Command Phase Byte
Bits 3-0 of this result byte are subject to change by NSC,
and specify the version of the Floppy Disk Controller (FDC)
A hardware reset clears all the bits to zero (conventional
mode for all drives). PERPENDICULAR MODE command
bits may be written at any time.
The settings of bits 1 and 0 in this byte override the logical
drive configuration set by bits 5 through 2. If bits 1 and 0 are
both 0, bits 5 through 2 configure the logical disk drives as
conventional or perpendicular. Otherwise, bits 2 and 0 con-
figure them. See TABLE 3-21 on page 72.
Bits 1,0 - Group Drive Mode Configuration (GDC)
These bits configure all the logical disk drives as con-
ventional or perpendicular. If the Overwrite bit (OW, bit
7) is 0, this setting may be overridden by bits 5-2.
It is not necessary to issue the FORMAT TRACK com-
mand if all drives are conventional.
These bits are cleared to 0 by a software reset.
00: Conventional. (Default)
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The Floppy Disk Controller (FDC) (Logical Device 0)
Bit 7 - Overwrite (OW)
01: Perpendicular. ( 500 Kbps)
10: Conventional.
This bit enables or disables changes in the mode of the
logical drives by bits 5-2.
11: Perpendicular. (1 or 2 Mbps)
0: Changes in mode of logical drives via bits 5-2 are
ignored. (Default)
1: Changes enabled.
Bits 5-2 -Drive 3-0 Mode Configuration (DC3-0)
If bits 1,0 are both 0, and bit 7 is 1, these bits configure
logical drives 3-0 as conventional or perpendicular. Bits
5-2 (DC3–0) correspond to logical drives 3-0, respec-
tively.
Execution Phase
Internal registers are written.
These bits are not affected by a software reset.
0: Conventional drive. (Default)
Result Phase
None.
It is not necessary to issue the FORMAT TRACK
command for conventional drives.
1: Perpendicular drive.
TABLE 3-14. Effect of Drive Mode and Data Rate on FORMAT TRACK and WRITE DATA Commands
Length of Gap 2 in FORMAT
TRACK Command
Portion of Gap 2 Rewritten in
WRITE DATA Command
Data Rates
Drive Mode
250, 300 or 500 Kbps
Conventional
Perpendicular
22 bytes
22 bytes
0 bytes
19 bytes
1 or 2 Mbps
Conventional
Perpendicular
22 bytes
41 bytes
0 bytes
38 bytes
TABLE 3-15. Effect of GDC Bits on FORMAT TRACK and WRITE DATA Commands
GDC Bits
Length of Gap 2 in
FORMAT TRACK Command
Portion of Gap 2 Rewritten in
Drive Mode
WRITE DATA Command
1
0
0
0
1
1
0
Conventional
Perpendicular (≤500 Kbps)
Conventional
22 bytes
22 bytes
22 bytes
41 bytes
0 bytes
19 bytes
0 bytes
1
0
1
Perpendicular (1 or 2 Mbps)
38 bytes
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The Floppy Disk Controller (FDC) (Logical Device 0)
3.7.10 The READ DATA Command
Bit 7 - Multi-Track (MT)
This bit controls whether or not the controller continues
to side 1 of the disk after reaching the last sector of side
0.
The READ DATA command reads logical sectors that con-
tain a normal data address mark from the selected drive and
makes the data available to the host microprocessor.
0: Single track. The controller stops at the last sector
of side 0.
Command Phase
1: Multiple tracks. the controller continues to side 1 af-
ter reaching the last sector of side 0.
7
6
5
4
3
2
1
0
MT MFM SK
IPS
0
0
1
1
0
Second Command Phase Byte
X
X
X
X
HD
DS1 DS0
Bits 1,0 - Logical Drive Select (DS1,0)
Track Number
Head Number
Sector Number
These bits indicate which logical drive is active. See
“Bits 1,0 - Logical Drive Select (DS1,0)” on page 57.
00: Drive 0 is selected. (Default)
01: Drive 1 is selected.
Bytes-Per-Sector Code
10: If four drives are supported, or drives 2 and 0 are
exchanged, drive 2 is selected.
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
Data Length (Obsolete)
11: If four drives are supported, drive 3 is selected.
Bit 2 - Head (HD)
This bit indicates which side of the Floppy Disk Drive
(FDD) is selected by the head. Its value is the inverse of
the HDSEL disk interface output signal.See “Bit 2 -
Head Select (HD)” on page 57.
The READ DATA command phase bytes must specify the
following ID information for the desired sector:
●
Track number
0: HDSEL is not active, i.e., the head of the FDD se-
lects side 0. (Default)
●
Head number
1: HDSEL is active, i.e., the FDD head selects side 1.
●
Sector number
●
Bit 7 - Implied Seek (IPS)
Bytes-per-sector code (See TABLE 3-10 on page 57.)
This bit indicates whether or not an implied seek should
be performed. See also, “Bit 5 - Implied Seek (IPS)” on
page 60.
●
End of Track (EOT) sector number. This allows the con-
troller to read multiple sectors.
●
A software reset clears this bit to its default value of 0.
0: No implied seek operations. (Default)
The value of the data length byte is ignored and must be
set to FFh.
After the last command phase byte is written, the controller
waits the Delay Before Processing time (see TABLE 3-24
on page 74) for the selected drive. During this time, the
drive motor must be turned on by enabling the appropriate
drive and motor select disk interface output signals via the
bits of the Digital Output Register (DOR). See Section 3.3.3
on page 39.
1: The controller performs seek and sense interrupt
operations before executing the command.
Third Command Phase Byte - Track Number
The value in this byte specifies the number of the track
to read.
Fourth Command Phase Byte - Head Number
The value in this byte specifies head to use.
First Command Phase Byte
Bit 5 - Skip Control (SK)
Fifth Command Phase Byte - Sector Number
This controls whether or not sectors containing a delet-
ed address mark will be skipped during execution of the
READ DATA command. See TABLE 3-16 on page 65.
The value in this byte specifies the sector to read.
Sixth Command Phase Byte - Bytes-Per-Sector Code
0: Do not skip sector with deleted address mark.
1: Skip sector with deleted address mark.
This byte contains a code in hexadecimal format that in-
dicates the number of bytes in a data field. TABLE 3-10
on page 57 indicates the number of bytes that corre-
sponds to each code.
Bit 6 - Modified Frequency Modulation (MFM)
This bit indicates the type of the disk drive and the data
transfer rate, and determines the format of the address
marks and the encoding scheme.
Seventh Command Phase Byte - End of Track (EOT) Sector
Number
0: FM mode, i.e., single density.
1: MFM mode, i.e., double density.
This byte specifies the number of the sector at the End
Of the Track (EOT).
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64
The Floppy Disk Controller (FDC) (Logical Device 0)
Eighth Command Phase Byte - Bytes Between Sectors -
Gap 3
The value in this byte specifies how many bytes there
If a deleted data mark is found, and Skip (SK) control is set
to 1 in the opcode command phase byte, the controller skips
this sector and searches for the next sector address field as
described above. The effect of Skip Control (SK) on the
READ DATA command is summarized in TABLE 3-16 on
page 65.
are between sectors. See “Fifth Command Phase Byte
- Bytes in Gap 3” on page 57.
Ninth Command Phase Byte - Data Length (Obsolete)
The value in this byte is ignored and must be set to FFh.
TABLE 3-16. Skip Control Effect on READ DATA
Command
Execution Phase
Skip
Control
(SK)
Control
Mark Bit 6
of ST2
Data
Type
Sector
Read?
Result
In this phase, data read from the disk drive is transferred to
the system via DMA or non-DMA modes. See Section 3.4.2
on page 45.
Normal
Termination
0
0
Normal
Deleted
Y
Y
0
1
The controller looks for the track number specified in the
third command phase byte. If implied seeks are enabled,
the controller also performs all operations of a SENSE IN-
TERRUPT command and of a SEEK command (without is-
suing these commands). Then, the controller waits the head
settle time. See bits 3-0 of the fourth command phase byte
of the MODE command in “Bits 3-0 - Head Settle Factor” on
page 61.
No More
Sectors Read
Normal
Termination
1
1
Normal
Deleted
Y
N
0
1
Sector Skipped
After finding the data field, the controller transfers data
bytes from the disk drive to the host until the bytes-per-sec-
tor count has been reached, or until the host terminates the
operation by issuing the Terminal Count (TC) signal, reach-
ing the end of the track or reporting an overrun.
The controller then starts the data separator and waits for
the data separator to find the address field of the next sec-
tor. The controller compares the ID information (track num-
ber, head number, sector number, bytes-per-sector code) in
that address field with the corresponding information in the
command phase bytes of the READ DATA command.
See also Section 3.4 on page 45.
If the contents of the bytes do not match, then the controller
waits for the data separator to find the address field of the
next sector. The process is repeated until a match or an
error occurs.
The controller then generates a Cyclic Redundancy Check
(CRC) value for the sector and compares the result with the
CRC value at the end of the data field.
After reading the sector, the controller reads the next logical
sector unless one or more of the following termination con-
ditions occurs:
Possible errors, the conditions that may have caused them
and the actions that result are:
●
The microprocessor aborted the command by writing to
the FIFO.
●
The DMA controller asserted the Terminal Count (TC)
signal to indicate that the operation terminated. The In-
terrupt Code (IC) bits (bits 7,6) in ST0 are set to normal
termination (00). See “Bits 7,6 - Interrupt Code (IC)” on
page 48.
If there is no disk in the drive, the controller gets stuck.
The microprocessor must then write a byte to the FIFO
to advance the controller to the result phase.
●
●
Two pulses of the INDEX signal were detected since the
search began, and no valid ID was found.
The last sector address (of side 1, if the Multi-Track en-
able bit (MT) was set to 1) was equal to the End of Track
sector number. The End of Track bit (bit 7) in ST1 is set.
The IC bits in ST0 are set to abnormal termination (01).
This is the expected condition during non-DMA transfers.
If the track address differs, either the Wrong Track bit
(bit 4) or the Bad Track bit (bit 1) (if the track address is
FFh) is set in result phase Status register 2 (ST2). See
Section 3.5.3 on page 49.
●
Overrun error. The Overrun bit (bit 4) in ST1 is set. The
If the head number, sector number or bytes-per-sector
code did not match, the Missing Data bit (bit 2) is set in
result phase Status register 1 (ST1).
Interrupt Code (IC) bits (bits 7,6) in ST0 are set to abnor-
mal termination (01). If the microprocessor cannot ser-
vice a transfer request in time, the last correctly read
byte is transferred.
If the Address Mark (AM) was not found, the Missing Ad-
dress Mark bit (bit 0) is set in ST1.
●
CRC error. CRC Error bit (bit 5) in ST1 and CRC Error in
Data Field bit (bit 5) in ST2, are set. The Interrupt Code (IC)
bits (bits 7,6) in ST0 are set to abnormal termination (01).
Section 3.5.2 on page 49 describes the bits of ST1.
●
A CRC error was detected in the address field. In this
If the Multi-Track (MT) bit was set in the opcode command
byte, and the last sector of side 0 has been transferred, the
controller continues with side 1.
case the CRC Error bit (bit 5) is set in ST1.
Once the address field of the desired sector is found, the
controller waits for the data separator to find the data field
for that sector.
If the data field (normal or deleted) is not found within the
expected time, the controller terminates the operation, en-
ters the result phase and sets bit 0 (Missing Address Mark)
in ST1.
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The Floppy Disk Controller (FDC) (Logical Device 0)
3.7.11 The READ DELETED DATA Command
Result Phase
The READ DELETED DATA command reads logical sec-
tors containing a Address Mark (AM) for deleted data from
the selected drive and makes the data available to the host
microprocessor.
7
6
5
4
3
2
1
0
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
Track Number
This command is like the READ DATA command, except for the
setting of the Control Mark bit (bit 6) in ST2 and the skipping of
sectors. See description of execution phase. See READ DATA
command for a description of the command bytes.
Command Phase
Head Number
7
6
5
4
3
2
1
0
Sector Number
MT MFM SK
IPS
0
1
1
0
0
Bytes-Per-Sector Code
X
X
X
X
HD
DS1 DS0
Upon terminating the execution phase of the READ DATA
command, the controller asserts IRQ6, indicating the begin-
ning of the result phase. The microprocessor must then
read the result bytes from the FIFO.
Track Number
Head Number
Sector Number
The values that are read back in the result bytes are shown
in TABLE 3-17 on page 66. If an error occurs, the result
bytes indicate the sector read when the error occurred.
Bytes-Per-Sector Code
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
Data Length (Obsolete)
Execution Phase
Data read from disk drive is transferred to the system in
DMA or non-DMA modes. See Section 3.4.2 on page 45.
See TABLE 3-17 on page 66 for the state of the result bytes
when the command terminates normally. The effect of Skip
Control (SK) on the READ DELETED DATA command is
summarized in TABLE 3-18 on page 67.
TABLE 3-17. Result Phase Termination Values with No Error
ID Information in Result Phase
Bytes-per-Sector
Multi-Track
(MT)
Head #
(HD)
End of Track (EOT)
Sector Number
Track Number Head Number Sector Number
Code
0
0
0
0
< EOT1 Sector #
= EOT1 Sector #
< EOT1 Sector #
= EOT1 Sector #
< EOT1 Sector #
= EOT1 Sector #
< EOT1 Sector #
= EOT1 Sector #
No Change
Track3 # + 1
No Change
No Change
Sector2 # + 1
1
No Change
No Change
Sector2 # + 1
1
0
0
1
1
1
1
1
1
0
0
1
1
No Change
No Change
No Change
No Change
1
No Change
No Change
No Change
No Change
No Change
No Change
Track3 # + 1
No Change
Sector2 # + 1
1
No Change
No Change
Sector2 # + 1
1
No Change
0
Track3 # + 1
1. End of Track sector number from the command phase.
2. The number of the sector last operated on by controller.
3. Track number programmed in the command phase
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The Floppy Disk Controller (FDC) (Logical Device 0)
TABLE 3-18. SK Effect on READ DELETED DATA
Command
Second Command Phase Byte
See “Second Command Phase Byte” on page 57 for a
description of the Drive Select (DS1,0) and Head Select
(HD) bits.
Skip
Control
(SK)
Control
Mark Bit 6
of ST2
Data Sector
Type Read?
Result
Execution Phase
0
Normal
Deleted
Y
Y
1
No More
Sectors Read
There is no data transfer during the execution phase of this
command. An interrupt is generated when the execution
phase is completed.
0
0
Normal
Termination
The READ ID command does not perform an implied seek.
After waiting the Delay Before Processing time, the control-
ler starts the data separator and waits for the data separator
to find the address field of the next sector. If an error condi-
tion occurs, the Interrupt Code (IC) bits in ST0 are set to ab-
normal termination (01), and the controller enters the result
phase.
1
1
Normal
Deleted
N
Y
1
0
Sector Skipped
Normal
Termination
Result Phase
Possible errors are:
7
6
5
4
3
2
1
0
●
The microprocessor aborted the command by writing to
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
Track Number
the FIFO.
If there is no disk in the drive, the controller gets stuck.
The microprocessor must then write a byte to the FIFO
to advance the controller to the result phase.
●
Two pulses of the INDEX signal were detected since the
search began, and no Address Mark (AM) was found.
Head Number
When the Address Mark (AM) is not found, the Missing
Address Mark bit (bit 0) is set in ST1. Section 3.5.2 on
page 49 describes the bits of ST1.
Sector Number
Bytes-Per-Sector Code
Result Phase
7
6
5
4
3
2
1
0
3.7.12 The READ ID Command
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
Track Number
The READ ID command finds the next available address
field and returns the ID bytes (track number, head number,
sector number, bytes-per-sector code) to the microproces-
sor in the result phase.
The controller reads the first ID Field header bytes it can
find and reports these bytes to the system in the result
bytes.
Head Number
Sector Number
Command Phase
Bytes-Per-Sector Code
7
6
5
4
3
2
1
0
0
MFM
X
0
0
1
0
1
0
X
X
X
X
HD
DS1 DS0
After the last command phase byte is written, the controller
waits the Delay Before Processing time (see TABLE 3-24
on page 74) for the selected drive. During this time, the
drive motor must be turned on by enabling the appropriate
drive and motor select disk interface output signals via the
bits of the Digital Output Register (DOR). See Section 3.3.3
on page 39.
First Command Phase Byte, Opcode
See “Bit 6 - Modified Frequency Modulation (MFM)” on
page 57.
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The Floppy Disk Controller (FDC) (Logical Device 0)
3.7.13 The READ A TRACK Command the controller sets CRC Error (bit 5) in ST1, but contin-
ues to read the sector.
The READ A TRACK command reads sectors from the se-
lected drive, in physical order, and makes the data available
to the host.
●
If there is a CRC error in the data field, the controller
sets the CRC Error bit (bit 5) in ST1 and CRC Error in
Data Field bit (bit 5) in ST2, but continues reading sec-
tors.
Command Phase
●
The controller reads a maximum of End of Track (EOT)
physical sectors. There is no support for multi-track
reads.
7
6
5
4
3
2
1
0
0
MFM
X
0
0
0
0
1
0
IPS
X
X
X
HD
DS1 DS0
Result Phase
Track Number
Head Number
Sector Number
7
6
5
4
3
2
1
0
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
Track Number
Bytes-Per-Sector Code
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
Data Length (Obsolete)
Head Number
The command phase bytes of the READ A TRACK com-
mand are like those of the READ DATA command, except
for the MT and SK bits. Multi-track and skip operations are
not allowed in the READ A TRACK command. Therefore,
bits 7 and 5 of the opcode command phase byte (MT and
SK, respectively) must be 0.
Sector Number
Bytes-Per-Sector Code
3.7.14 The RECALIBRATE Command
The RECALIBRATE command issues pulses that make the
head of the selected drive step out until it reaches track 0.
First Command Phase Byte, Opcode
See “Bit 6 - Modified Frequency Modulation (MFM)” on
page 57.
Command Phase
Second Command Phase Byte
7
6
5
4
3
2
1
0
See “Second Command Phase Byte” on page 57 for a
description of the Drive Select (DS1,0) and Head Select
(HD) bits.
0
0
0
0
0
1
1
1
X
X
X
X
X
HD
DS1 DS0
See “Bit 5 - Implied Seek (IPS)” on page 60 for a de-
scription of the Implied Seek (IPS) bit.
Second Command Phase Byte
Third through Ninth Command Phase Bytes
See Section 3.7.10 on page 64.
See “Second Command Phase Byte” on page 57 for a
description of the Drive Select (DS1,0) and Head Select
(HD) bits.
Execution Phase
Execution Phase
Data read from the disk drive is transferred to the system in
DMA or non-DMA modes. See Section 3.4.2 on page 45.
After the last command byte is issued, the Drive Busy bit for
the selected drive is set in the Main Status Register (MSR).
See bits 3-0 in Section 3.3.5 on page 42.
Execution of this command is like execution of the READ
DATA command except for the following differences:
The controller waits the Delay Before Processing time (see
TABLE 3-24 on page 74) for the selected drive., and then
becomes idle. See Section 3.4.4 on page 47.
●
The controller waits for a pulse from the INDEX signal
before it searches for the address field of a sector.
If the microprocessor writes to the FIFO before the IN-
DEX pulse is detected, the command enters the result
phase with the Interrupt Code (IC) bits (bits 7,6) in ST0
set to abnormal termination (01).
Then, the controller issues pulses until the TRK0 disk inter-
face input signal becomes active or until the maximum num-
ber of RECALIBRATE step pulses have been issued.
TABLE 3-19 on page 69 shows the maximum number of
RECALlBRATE step pulses that may be issued, depending
on the RECALIBRATE Step Pulses (R255) bit, bit 0 in the
second command phase byte of the MODE command
(page 60), and the Extended Track Range (ETR) bit, bit 4 of
the third command byte of the MODE command (see Sec-
tion 3.7.7 on page 60).
●
All the ID bytes of the sector address are compared, ex-
cept the sector number. Instead, the sector number is
set to 1, and then incremented for each successive sec-
tor read.
●
If no match occurs when the ID bytes of the sector ad-
dress are compared, the controller sets the Missing
Data bit (bit 2) in ST1, but continues to read the sector.
If there is a CRC error in the address field being read,
If the number of tracks on the disk drive exceeds the maxi-
mum number of RECALIBRATE step pulses, it may be nec-
essary to issue another RECALIBRATE command.
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The Floppy Disk Controller (FDC) (Logical Device 0)
TABLE 3-19. Maximum RECALIBRATE Step Pulses for
Values of R255 and ETR
The controller waits the Delay Before Processing time (see
TABLE 3-24 on page 74) for the selected drive., and then
becomes idle. See Section 3.4.4 on page 47.
Maximum Number of
RECALIBRATE Step Pulses
Then, the controller enters the idle phase and issues RTN
STEP pulses until the TRK0 disk interface input signal be-
comes active or until the specified number (RTN) of STEP
pulses have been issued. After the RELATIVE SEEK oper-
ation is complete, the controller generates an interrupt.
R255
ETR
0
1
0
1
0
0
1
1
85 (default)
255
3925
Software should ensure that the RELATIVE SEEK com-
mand is issued for only one drive at a time. This is because
the drives are actually selected via the Digital Output Reg-
ister (DOR), which can only select one drive at a time.
4095
The pulses actually occur while the controller is in the drive
polling phase. See Section 3.4.5 on page 48.
No command, except the SENSE INTERRUPT command,
should be issued while a RELATIVE SEEK command is in
progress.
An interrupt is generated after the TRK0 signal is asserted,
or after the maximum number of RECALIBRATE step puls-
es is issued.
Result Phase
Software should ensure that the RECALIBRATE command
is issued for only one drive at a time. This is because the
drives are actually selected via the Digital Output Register
(DOR), which can only select one drive at a time.
None.
3.7.16 The SCAN EQUAL, the SCAN LOW OR EQUAL
and the SCAN HIGH OR EQUAL Commands
No command, except a SENSE INTERRUPT command,
should be issued while a RECALIBRATE command is in
progress.
The scan commands compare data read from the disk with
data sent from the microprocessor. This comparison pro-
duces a match for each scan command, as follows, and as
shown in TABLE 3-20 on page 70:
Result Phase
●
SCAN EQUAL - Disk data equals microprocessor da-
ta.
None.
3.7.15 The RELATIVE SEEK Command
●
SCAN LOW OR EQUAL - Disk data is less than or
equal to microprocessor data.
The RELATIVE SEEK command issues STEP pulses that
make the head of the selected drive step in or out a pro-
grammable number of tracks.
●
SCAN HIGH OR EQUAL - Disk data is greater than or
equal to microprocessor data.
Command Phase
Command Phase
7
6
5
4
3
2
1
0
SCAN EQUAL
1
DIR
X
0
0
1
1
1
1
7
6
5
4
3
2
1
0
X
X
X
X
HD
DS1 DS0
MT MFM SK
IPS
1
0
0
0
1
Relative Track Number (RTN)
X
X
X
X
HD
DS1 DS0
Track Number
Head Number
Sector Number
First Command Phase Byte, Opcode, Bit - 6 Step Direction
DIR
This bit defines the step direction.
0: Step head out.
1: Step head in.
Bytes-Per-Sector Code
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
Sector Step Size
Second Command Phase Byte
See “Second Command Phase Byte” on page 57 for a
description of the Drive Select (DS1,0) and Head Select
(HD) bits.
Third Command Phase Byte - Relative Track Number
(RTN)
This value specifies how many tracks the head should
step in or out from the current track.
Execution Phase
After the last command byte is issued, the Drive Busy bit for
the selected drive is set in the Main Status Register (MSR).
See bits 3-0 in Section 3.3.5 on page 42.
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The Floppy Disk Controller (FDC) (Logical Device 0)
If all sectors read are skipped, the command terminates
SCAN LOW OR EQUAL
with bit 3 of ST2 set to 1, i.e., disk data equals microproces-
sor data.
7
6
5
4
3
2
1
0
MT MFM SK
IPS
1
1
0
0
1
Result Phase
X
X
X
X
HD
DS1 DS0
7
6
5
4
3
2
1
0
Track Number
Head Number
Sector Number
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
Track Number
Bytes-Per-Sector Code
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
Sector Step Size
Head Number
Sector Number
Bytes-Per-Sector Code
SCAN HIGH OR EQUAL
TABLE 3-20 shows how all the scan commands affect bits
3,2 of the Status 2 (ST2) result phase register. See Section
3.5.3 on page 49.
7
6
5
4
3
2
1
0
MT MFM SK
IPS
1
1
1
0
1
TABLE 3-20. The Effect of Scan Commands on the ST2
Register
X
X
X
X
HD
DS1 DS0
Track Number
Head Number
Sector Number
Result Phase Status
Register 2 (ST2)
Command
Condition
Bit 3 - Scan Bit 2 - Scan
Satisfied
Not Satisfied
Bytes-Per-Sector Code
SCAN
EQUAL
1
0
0
1
Disk = µP
Disk ≠ µP
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
Sector Step Size
SCAN LOW
OR EQUAL
1
0
0
0
0
1
Disk = µP
Disk < µP
Disk > µP
First through Eighth Command Phase Bytes -
All Scan Commands
SCAN HIGH
OR EQUAL
1
0
0
0
0
1
Disk = µP
Disk > µP
Disk < µP
See READ DATA command for a description of the first
eight command phase bytes.
3.7.17 The SEEK Command
Ninth Command Phase Byte, Sector Step Size
The SEEK command issues pulses of the STEP signal to
the selected drive, to move it in or out until the desired track
number is reached.
During execution, the value of this byte is added to the cur-
rent sector number to determine the next sector to read.
Software should ensure that the SEEK command is issued
for only one drive at a time. This is because the drives are
actually selected via the Digital Output Register (DOR),
which can only select one drive at a time. See Section 3.3.3
on page 39.
Execution Phase
The most significant bytes of each sector are compared
first. If wildcard mode is enabled in bit 4 of the fourth com-
mand phase byte in the MODE command ( "Bit 4 - Scan
Wild Card (WLD)" on page 61), a value of FFh from either
the disk or the microprocessor always causes a match.
No command, except a SENSE INTERRUPT command,
should be issued while a SEEK command is in progress.
After each sector is read, if there is no match, the next sec-
tor is read. The next sector is the current sector number plus
the Sector Step Size specified in the ninth command phase
byte.
The scan operation continues until the condition is met, the
End of Track (EOT) is reached or the Terminal Count (TC)
signal becomes active.
Read error conditions during scan commands are the same
as read error conditions during the execution phase of the
READ DATA command. See Section 3.7.10 on page 64.
If the Skip Control (SK) bit is set to 1, sectors with deleted
data marks are ignored.
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The Floppy Disk Controller (FDC) (Logical Device 0)
3.7.18 The SENSE DRIVE STATUS Command
Command Phase
The SENSE DRIVE STATUS command indicates which
drive and which head are selected, whether or not the head
is at track 0 and whether or not the track is write protected
in result phase Status register 3 (ST3). See Section 3.5.4 on
page 50.
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
1
X
X
X
X
X
HD
DS1 DS0
This command does not generate an interrupt.
Number of Track to Seek
MSN of Track # to Seek
Command Phase
7
6
5
4
3
2
1
0
When bit 2 of the second command phase byte (ETR) in the
MODE command is set to 1, the track number is stored as
a 12-bit value. See “Bit 0 - Extended Track Range (ETR)”
on page 60.
0
0
0
0
0
1
0
0
X
X
X
X
X
HD
DS1 DS0
In this case, a fourth command byte should be written in the
command phase to hold the Most Significant Nibble (MSN),
i.e., the four most significant bits, of the number of the track
to seek. Otherwise (ETR bit in MODE is 0), this command
phase byte is not required. and, only three command bytes
should be written.
See READ DATA command for a description of these bits.
Execution Phase
Disk drive status information is detected and reported.
After the last command byte is issued, the Drive Busy bit for
the selected drive is set in the Main Status Register (MSR).
See bits 3-0 in Section 3.3.5 on page 42.
Result Phase
7
6
5
4
3
2
1
0
The controller waits the Delay Before Processing time (see
TABLE 3-24 on page 74) for the selected drive, before issu-
ing the first STEP pulse. After waiting the Delay Before Pro-
cessing time, the controller becomes idle. See Section 3.4.4
on page 47.
Result Phase Status Register 3 (ST3)
See Section 3.5.4 on page 50.
3.7.19 The SENSE INTERRUPT Command
Second Command Phase Byte
The SENSE INTERRUPT command returns the cause of
an interrupt that is caused by the change in status of any
disk drive.
See READ DATA command for a description of these
bits.
If a SENSE INTERRUPT command is issued when no inter-
rupt is pending it is treated as an invalid command.
Third Command Phase Byte, Number of Track to Seek
The value in this byte is the number of the track to seek.
When to Issue SENSE INTERRUPT
Fourth Command Phase Byte,
Bits 7-4 - MSN of Track Number
The SENSE INTERRUPT command is issued to detect ei-
ther of the following causes of an interrupt:
If the track number is stored as a 12-bit value, these bits
contain the Most Significant Nibble (MSN), i.e., the four
most significant bits, of the number of the track to seek.
●
The FDC became ready during the drive polling phase
for an internally selected drive. See Section 3.4.5 on
page 48. This can occur only after a hardware or soft-
ware reset.
Otherwise (the ETR bit in the MODE command is 0), this
command phase byte is not required.
●
A SEEK, RELATIVE SEEK or RECALIBRATE com-
mand terminated.
Execution Phase
During the execution phase of the SEEK command, the
track number to seek to is compared with the present track
number. The controller determines how many STEP pulses
to issue and the DIR disk interface output signal indicates
which direction the head should move.
Interrupts caused by these conditions are cleared after the
first result byte has been read. Use the Interrupt Code (IC)
(bits 7,6) and SEEK End bits (bit 5) of result phase Status
register 0 (ST0) to identify the cause of these interrupts. See
“Bit 5 - SEEK End” on page 48 and TABLE 3-21 on page 72.
The SEEK command issues step pulses while the controller
is in the drive polling phase. The step pulse rate is deter-
mined by the value programmed in the second command
phase byte of the SPECIFY command.
An interrupt is generated one step pulse period after the last
step pulse is issued. A SENSE INTERRUPT command
should be issued to determine the cause of the interrupt.
Result Phase
None.
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The Floppy Disk Controller (FDC) (Logical Device 0)
In this case, a third result byte should be read to hold the
Most Significant Nibble (MSN), i.e., the four most significant
bits, of the number of the current track.
TABLE 3-21. Interrupt Causes Reported by SENSE
INTERRUPT
Otherwise (ETR bit in MODE is 0), this command phase
byte is not required. and, only two result phase bytes should
be read First Command Phase Byte, Result Phase
Status Register 0
Bits of
ST0
Interrupt Cause
7
6
5
See Section 3.5.1 on page 48.
1
1
0 FDC became ready during drive polling mode.
Second Command Phase Byte,
Present Track Number (PTR)
SEEK, RELATIVE SEEK or RECALIBRATE
not completed.
The value in this byte is the number of the current track.
0
0
0
1
1 SEEK, RELATIVE SEEK or RECALIBRATE
terminated normally.
Fourth Command Phase Byte,
Bits 7-4 - MSN of Track Number
1 SEEK, RELATIVE SEEK or RELCALIBRATE
terminated abnormally.
If the track number is stored as a 12-bit value, these bits
contain the Most Significant Nibble (MSN), i.e., the four
most significant bits, of the number of the track to seek.
When SENSE INTERRUPT is not Necessary
Otherwise (the ETR bit in the MODE command is 0), this
result phase byte is not required.
Interrupts that occur during most command operations do
not need to be identified by the SENSE INTERRUPT. The
microprocessor can identify them by checking the Request
for Master (RQM) bit (bit 7) of the Main Status Register
(MSR). See “Bit 7 - Request for Master (RQM)” on page 42.
3.7.20 The SET TRACK Command
This command is used to verify (read) or change (write) the
number of the present track.
It is not necessary to issue a SENSE INTERRUPT com-
mand to detect the following causes of Interrupts:
This command could be useful for recovery from disk track-
ing errors, where the true track number could be read from
the disk using the READ ID command, and used as input to
the SET TRACK command to correct the Present Track
number (PTR) stored internally.
●
The result phase of any of the following commands
started:
— READ DATA, READ DELETED DATA, READ A
TRACK, READ ID
Terminating this command does not generate an interrupt
— WRITE DATA, WRITE DELETED
— FORMAT TRACK
Command Phase
— SCAN EQUAL, SCAN EQUAL OR LOW, SCAN
7
6
5
4
3
2
1
0
EQUAL OR HIGH
— VERIFY
0
0
WNR
0
1
1
0
1
0
0
0
0
1
●
Data is being transferred in non-DMA mode, during the
execution phase of some command.
MSB DS1 DS0
Byte of Present Track Number (PTR)
Interrupts caused by these conditions are cleared automat-
ically, or by reading or writing information from or to the
Data Register (FIFO).
When bit 2 of the second command phase byte (ETR) in the
MODE command is set to 1, the track number is stored as
a 12-bit value. See “Bit 0 - Extended Track Range (ETR)”
on page 60.
Command Phase
7
6
5
4
3
2
1
0
In this case, issue SET TRACK twice - once for the Most
Significant Byte (MSB) of the number of the current track
and once for the Least Significant Byte (LSB).
0
0
0
0
1
0
0
0
Otherwise (ETR bit in MODE is 0), issue SET TRACK only
once, with bit 2 (MSB) of the second command phase byte
set to 0.
Execution Phase
Status of interrupt is reported.
Result Phase.
7
6
5
4
3
2
1
0
Result Phase Status Register 0 (ST0)
Byte of Present Track Number (PTR)
MSN of PTR
When bit 2 of the second command phase byte (ETR) in the
MODE command is set to 1, the track number is stored as
a 12-bit value. See “Bit 0 - Extended Track Range (ETR)”
on page 60.
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The Floppy Disk Controller (FDC) (Logical Device 0)
First Command Phase Byte, Bit 6 - Write Track Number
(WNR)
0: Read the existing track number.
3.7.21 The SPECIFY Command
The SPECIFY command sets initial values for the following
time periods:
The result phase byte already contains the track
number, and the third byte in the command phase
is a dummy byte.
●
The delay before command processing starts, formerly
called Motor On Time (MNT)
●
The delay after command processing terminates, for-
merly called Motor Off Time (MFT)
1: Change the track number by writing a new value to
the result phase byte.
●
The interval step rate time.
Second Command Phase Byte
The FDC uses the Digital Output Register (DOR) to enable
the drive and motor select signals. See Section 3.3.3 on
page 39.
Bits 1,0 - Logical Drive Select (DS1,0)
These bits indicate which logical drive is active. See
“Bits 1,0 - Logical Drive Select (DS1,0)” on page 57.
The delays may be used to support the µPD765, i.e., to in-
sert delays from selection of a drive motor until a read or
write operation starts, and from termination of a command
until the drive motor is no longer selected, respectively.
00: Drive 0 is selected.
01: Drive 1 is selected.
10: If four drives are supported, or drives 2 and 0 are
exchanged, drive 2 is selected.
The parameters used by this command are undefined after
power up, and are unaffected by any reset. Therefore, soft-
ware should always issue a SPECIFY command as part of
an initialization routine to initialize these parameters.
11: If four drives are supported, drive 3 is selected.
Bit 2 - Most Significant Byte (MSB)
Terminating this command does not generate an interrupt.
This bit, together with bits 1,0, determines the byte to
read or write. See TABLE 3-22 on page 73.
Command Phase.
0: Least significant byte of the track number.
1: Most significant byte of the track number.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
1
TABLE 3-22. Defining Bytes to Read or Write Using
SET TRACK
Step Rate Time (SRT)
Delay After Processing
DMA
MSB
2
DS1
1
DS0
0
Delay Before Processing
Byte to Read or Write
Second Command Phase Byte
Bits 3-0 - Delay After Processing Factor
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Drive 0 (LSB)
Drive 0 (MSB)
Drive 1 (LSB)
Drive 1 (MSB)
Drive 2 (LSB)
Drive 2 (MSB)
Drive 3 (LSB)
Drive 3 (MSB)
These bits specify a factor that is multiplied by a con-
stant to determine the delay after command processing
ends, i.e., from termination of a command until the drive
motor is no longer selected.
The value of the Motor Timer Values (TMR) bit (bit 7) of
the second command phase byte in the MODE com-
mand determines which group of constants and delay
ranges to use. See “Bit 7 - Motor Timer Values (TMR)”
on page 60.
The specific constant that will be multiplied by this factor
to determine the actual delay after processing for each
data transfer rate is shown in TABLE 3-23 on page 74.
Execution Phase
Internal register is read or written.
Use the smallest possible value for this factor, except 0,
i.e., 1. If this factor is 0, the value16 is used.
Result Phase
7
6
5
4
3
2
1
0
Bits 7-4 - STEP Time Interval Value (SRT)
These bits specify a value that is used to calculate the
time interval between successive STEP signal pulses
during a SEEK, IMPLIED SEEK, RECALIBRATE, or
RELATIVE SEEK command.
Byte of Present Track Number(PTR)
This byte is one byte of the track number that was read or
written, depending on the value of WNR in the first com-
mand byte.
TABLE 3-25 on page 74 shows how this value is used
to calculate the actual time interval.
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The Floppy Disk Controller (FDC) (Logical Device 0)
TABLE 3-23. Constant Multipliers for Delay After Processing Factor and Delay Ranges
Bit 7 of MODE (TMR) = 0
Bit 7 of MODE (TMR) = 1
Data Transfer
Rate (bps)
Constant Multiplier Permitted Range (msec) Constant Multiplier Permitted Range (msec)
1 M
8
16
8 -128
16 - 256
26.7 - 427
32 - 512
512
512
512 - 8192
512 - 8192
853 - 13653
1024 -16384
500 K
300 K
250 K
80 / 3
32
2560 / 3
1024
TABLE 3-24. Constant Multipliers for Delay Before Processing Factor and Delay Ranges
Bit 7 of MODE (TMR) = 0
Bit 7 of MODE (TMR) = 1
Data Transfer
Rate (bps)
Constant Multiplier Permitted Range (msec) Constant Multiplier Permitted Range (msec)
1 M
1
1
1 -128
1 -128
32
32
32 - 4096
32 - 4096
53 - 6827
64 - 8192
500 K
300 K
250 K
10 / 3
4
3.3 - 427
4 - 512
160 / 3
64
TABLE 3-25. STEP Time Interval Calculation
Execution Phase
Internal registers are written.
Data Transfer Calculation of Time
Permitted
Rate (bps)
Interval
Range (msec)
Result Phase
1 M
(16 − SRT) / 2
(16 − SRT)
0.5 - 8
1 - 16
None.
500 K
300 K
250 K
3.7.22 The VERIFY Command
(16 − SRT) x 1.67
(16 − SRT) x 2
1.67 - 26.7
2 - 32
The VERIFY command verifies the contents of data and/or
address fields after they have been formatted or written.
VERIFY reads logical sectors containing a normal data Ad-
dress Mark (AM) from the selected drive, without transfer-
ring the data to the host.
Third Command Phase Byte
Bit 0 - DMA
The TC signal cannot terminate this command since no
data is transferred. Instead, VERIFY simulates a TC signal
by setting the Enable Count (EC) bit to1. In this case, VER-
IFY terminates when the number of sectors read equals the
number of sectors to read, i.e., Sectors to read Count (SC).
If SC = 0 then 256 sectors will be verified.
This bit selects the data transfer mode in the execution
phase of a read, write, or scan operation.
Data can be transferred between the microprocessor
and the controller during execution in DMA mode or in
non-DMA mode, i.e., interrupt transfer mode or software
polling mode.
When EC is 0, VERIFY ends when the End of the Track
(EOT) sector number equals the number of the sector
checked. In this case, the ninth command phase byte is not
needed and should be set to FFh.
See Section 3.4.2 on page 45 for a description of these
modes.
0: DMA mode is selected.
1: Non-DMA mode is selected.
TABLE 3-26 on page 75 shows how different values for the
VERIFY parameters affect termination.
Bits 3-0 - Delay Before Processing Factor
Command Phase
These bits specify a factor that is multiplied by a con-
stant to determine the delay before command process-
ing starts, i.e., from selection of a drive motor until a
read or write operation starts.
7
6
5
4
3
2
1
0
MT MFM SK
EC
1
0
1
1
0
The value of the Motor Timer Values (TMR) bit (bit 7) of
the second command phase byte in the MODE com-
mand determines which group of constants and delay
ranges to use. See “Bit 7 - Motor Timer Values (TMR)”
on page 60.
X
X
X
X
HD
DS1 DS0
Track Number
Head Number
Sector Number
The specific constant that will be multiplied by this factor
to determine the actual delay before processing for
each data transfer rate is shown in TABLE 3-24 on page
74.
Bytes-Per-Sector Code
Use the smallest possible value for this factor, except 0,
i.e., 1. If this factor is 0, the value128 is used.
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The Floppy Disk Controller (FDC) (Logical Device 0)
Result Phase
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
Sectors to read Count (SC)
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
Track Number
First Command Phase Byte
See Section 3.7.10 on page 64 for a description of these
bits.
Head Number
Sector Number
Second Command Phase Byte
Bytes-Per-Sector Code
Bits 2-0 - Drive Select (DS1,0) and Head (HD) Select
TABLE 3-26 on page 75 shows how different conditions af-
fect the termination status.
See the description of the Drive Select bits (DS1,0) and
the Head (HD) in Section 3.7.10 on page 64.
TABLE 3-26. VERIFY Command Termination
Conditions
Bit 7 - Enable Count Control (EC)
This bit controls whether the End of Track sector num-
ber or the Sectors to read Count (SC) triggers termina-
tion of the VERIFY command.
Sector Count (SC) or
End of Track (EOT) Value
Termination
Status
MT EC
0
0
1
SC should be FFh
EOT ≤ Sectors per Side1
No Errors
See also TABLE 3-26 on page 75.
0: Terminate VERIFY when the number of last sector
read equals the End of Track (EOT) sector number.
SC should be FFh
Abnormal
Termination
The ninth command phase byte (Sectors to read
Count, SC), is not needed and should be set to FFh.
EOT > Sectors per Side
0
SC ≤ Sectors per Side
and
SC ≤ EOT
SC > Sectors Remaining2
No Errors
1: Terminate VERIFY when number of sectors read
equals the number of sectors to read, i.e., Sectors
to read Count (SC).
Abnormal
or
Termination
Third through Eighth Command Phase Bytes
See Section 3.7.10 on page 64.
SC > EOT
1
1
0
1
SC should be FFh
No Errors
Always set the End of Track (EOT) sector number to the
number of the last sector to be checked on each side of
the disk. If EOT is greater than the number of sectors
per side, the command terminates with an error and no
useful Address Mark (AM) or CRC data is returned.
EOT ≤ Sectors per Side
SC should be FFh
Abnormal
Termination
EOT > Sectors per Side
SC ≤ Sectors per Side
and
No Errors
No Errors
Ninth Command Phase Byte, Sectors to Read Count (SC)
SC ≤ EOT
This byte specifies the number of sectors to read. If the
Enable Count (EC) control bit (bit 7) of the second com-
mand byte is 0, this byte is not needed and should be
set to the value FFh.
SC ≤ (EOT x 2)
and
EOT ≤ Sectors per Side
SC > (EOT x 2)
Abnormal
Termination
Execution Phase
Data is read from the disk, as the controller checks for valid
address marks in the address and data fields.
1. Number of formatted sectors per side of the disk.
2. Number of formatted sectors left which can be read,
including side 1 of the disk, if MT is 1.
This command is identical to the READ DATA command,
except that it does not transfer data during the execution
phase. See Section 3.7.10 on page 64.
If the Multi-Track (MT) parameter is 1 and SC is greater
than the number of remaining formatted sectors on side 0,
verification continues on side 1 of the disk.
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The Floppy Disk Controller (FDC) (Logical Device 0)
If there is no match, the controller waits to find the next sec-
3.7.23 The VERSION Command
tor address field. This process continues until the desired
sector is found. If an error condition occurs, the Interrupt
Control (IC) bits (bits 7,6) in ST0 are set to abnormal termi-
nation, and the controller enters the result phase. See “Bits
7,6 - Interrupt Code (IC)” on page 48.
The VERSION command returns the version number of the
current Floppy Disk Controller (FDC).
Command Phase
Possible errors are:
Execution Phase
●
The microprocessor aborted the command by writing to
the FIFO.
None.
If there is no disk in the drive, the controller gets stuck.
The microprocessor must then write a byte to the FIFO
to advance the controller to the result phase.
Result Phase
The result phase byte returns a value of 90h for an FDC that
is compatible with the 82077.
●
Two pulses of the INDEX signal were detected since the
search began, and no valid ID was found.
Other controllers, i.e., the DP8473 and other NEC765 com-
patible controllers, return a value of 80h (invalid command).
If the track address differs, either the Wrong Track bit
(bit 4) or the Bad Track bit (bit 1) (if the track address is
FFh is set in result phase Status register 2 (ST2). See
Section 3.5.3 on page 49.
3.7.24 The WRITE DATA Command
The WRITE DATA command receives data from the host
and writes logical sectors containing a normal data Address
Mark (AM) to the selected drive.
If the head number, sector number or bytes-per-sector
code did not match, the Missing Data bit (bit 2) is set in
result phase Status register 1 (ST1).
This command is like the READ DATA command, except
that the data is transferred from the microprocessor to the
controller instead of the other way around.
If the Address Mark (AM) is not found, the Missing Ad-
dress Mark bit (bit 0) is set in ST1.
Section 3.5.2 on page 49 describes the bits of ST1.
Command Phase
●
A CRC error was detected in the address field. In this
7
6
5
4
3
2
1
0
case the CRC Error bit (bit 5) is set in ST1.
●
MT MFM
IPS
0
0
0
1
0
1
The controller detected an active the Write Protect (WP)
disk interface input signal, and set bit 1 of ST1 to 1.
X
X
X
X
HD
DS1 DS0
If the correct address field is found, the controller waits for
all (conventional drive mode) or part (perpendicular drive
mode) of gap 2 to pass. See FIGURE 3-5 on page 59. The
controller then writes the preamble field, Address Marks
(AM) and data bytes to the data field. The microprocessor
transfers the data bytes to the controller.
Track Number
Head Number
Sector Number
Bytes-Per-Sector Code
After writing the sector, the controller reads the next logical
sector, unless one or more of the following termination con-
ditions occurs:
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
Data Length (Obsolete)
●
The DMA controller asserted the Terminal Count (TC)
signal to indicate that the operation terminated. The In-
terrupt Code (IC) bits (bits 7,6) in ST0 are set to normal
termination (00). See “Bits 7,6 - Interrupt Code (IC)” on
page 48.
See Section 3.7.10 on page 64 for a description of these
bytes.
●
The controller waits the Delay Before Processing time be-
fore starting execution.
The last sector address (of side 1, if the Multi-Track en-
able bit (MT) was set to 1) was equal to the End of Track
sector number. The End of Track bit (bit 7) in ST1 is set.
The IC bits in ST0 are set to abnormal termination (01).
This is the expected condition during non-DMA trans-
fers.
If implied seeks are enabled, i.e., IPS in the second com-
mand phase byte is 1, the operations performed by SEEK
and SENSE INTERRUPT commands are performed (with-
out these commands being issued).
●
Overrun error. The Overrun bit (bit 4) in ST1 is set. The
Execution Phase
Interrupt Code (IC) bits (bits 7,6) in ST0 are set to abnor-
mal termination (01). If the microprocessor cannot ser-
vice a transfer request in time, the last correctly written
byte is written to the disk.
Data is transferred from the system to the controller via
DMA or non-DMA modes and written to the disk.See Sec-
tion 3.4.2 on page 45 for a description of these data transfer
modes.
If the Multi-Track (MT) bit was set in the opcode command
byte, and the last sector of side 0 has been transferred, the
controller continues with side 1.
The controller starts the data separator and waits for it to
find the address field of the next sector. The controller com-
pares the address ID (track number, head number, sector
number, bytes-per-sector code) with the ID specified in the
command phase.
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The Floppy Disk Controller (FDC) (Logical Device 0)
Result Phase
Result Phase.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
Track Number
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
Track Number
Head Number
Head Number
Sector Number
Sector Number
Bytes-Per-Sector Code
Bytes-Per-Sector Code
Upon terminating the execution phase of the WRITE DATA
command, the controller asserts IRQ6, indicating the begin-
ning of the result phase. The microprocessor must then
read the result bytes from the FIFO.
Upon terminating the execution phase of the WRITE DATA
command, the controller asserts IRQ6, indicating the begin-
ning of the result phase. The microprocessor must then
read the result bytes from the FIFO.
The values that are read back in the result bytes are shown
in TABLE 3-17 on page 66. If an error occurs, the result
bytes indicate the sector read when the error occurred.
The values that are read back in the result bytes are shown
in TABLE 3-17 on page 66. If an error occurs, the result
bytes indicate the sector read when the error occurred.
3.7.25 The WRITE DELETED DATA Command
The WRITE DELETED DATA command receives data from
the host and writes logical sectors containing a deleted data
Address Mark (AM) to the selected drive.
This command is identical to the WRITE DATA command,
except that a deleted data AM, instead of a normal data AM,
is written to the data field.
Command Phase
7
6
5
4
3
2
1
0
MT MFM
IPS
0
0
1
0
0
1
X
X
X
X
HD
DS1 DS0
Track Number
Head Number
Sector Number
Bytes-Per-Sector Code
End of Track (EOT) Sector Number
Bytes Between Sectors - Gap 3
Data Length (Obsolete)
See Section 3.7.10 on page 64 and Section 3.7.24 on page
76 for a description of these bytes.
Execution Phase
Data is transferred from the system to the controller in DMA
or non-DMA modes, and written to the disk. See Section
3.4.2 on page 45 for a description of these data transfer
modes.
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The Floppy Disk Controller (FDC) (Logical Device 0)
3.8 EXAMPLE OF A FOUR-DRIVE CIRCUIT USING THE PC87309
Figure 3-6 shows one implementation of a four-drive circuit. Refer to TABLE 3-2 on page 39 to see how to encode the drive
and motor bits for this configuration.
74LS139
7407 (2)
Decoded Signal for Drive 0
Decoded Signal for Drive 1
Decoded Signal for Drive 2
Decoded Signal for Drive 3
Decoded Signal for Motor 0
Decoded Signal for Motor 1
Decoded Signal for Motor 2
Decoded Signal for Motor 3
1Y0
G1
A1
B1
DR0
DR1
1Y1
1Y2
1Y3
2Y0
2Y1
2Y2
2Y3
PC87309
MTR0
G2
A2
B2
Hex Buffers
ICC = 40 mA
Open Collector
FIGURE 3-6. PC87309 Four Floppy Disk Drive Circuit
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Parallel Port (Logical Device 1)
The PC87309 enters ECP mode by default after reset.
4.0 Parallel Port (Logical Device 1)
The ECP configuration supports several modes that are
determined by bits 7-5 of the ECP Extended Control
Register (ECR) at offset 402h. Section 4.6 "DETAILED
ECP MODE DESCRIPTIONS" on page 95 describes
these modes in detail. The ECR register is described in
Section 4.5.12 "Extended Control Register (ECR)" on
page 91.
The Parallel Port is a communications device that transfers
parallel data between the system and an external device.
Originally designed to output data to an external printer, the
use of this port has grown to include bidirectional communi-
cations, increased data rates and additional applications
(such as network adaptors).
4.1 PARALLEL PORT CONFIGURATION
4.1.2
Configuring Operation Modes
The PC87309 Parallel Port device offers a wide range of op-
erational configurations. It utilizes the most advanced proto-
cols in current use, while maintaining full backward
compatability to support existing hardware and software. It
supports two Standard Parallel Port (SPP) modes of opera-
tion for parallel printer ports (as found in the IBM PC-AT,
PS/2 and Centronics systems), two Enhanced Parallel Port
(EPP) modes of operation, and one Extended Capabilities
Port (ECP) mode. This versatility is achieved by user soft-
ware control of the mode in which the device functions.
The operation mode of the parallel port is determined by
configuration bits that are controlled by software. If ECP
mode is set upon initial system configuration, the operation
mode may also be changed during run-time.
●
Configuration at System Initialization (Static) - The
parallel port operation mode is determined at initial sys-
tem configuration by bits 7-5 of the SuperI/O Parallel
Port Configuration register at index F0h
●
Configuration at System Initialization with Run-
The IEEE 1284 standard establishes a widely accepted
handshake and transfer protocol that ensures transfer data
integrity. This parallel interface fully supports the IEEE 1284
standard of parallel communications, in both Legacy and
Plug and Play configurations, in all modes except the EPP
revision 1.7 mode described in the next section.
Time Reconfiguration (Dynamic) - When ECP mode
is selected as the static all other operational modes may
be run from this state. In this case the operation mode
is determined by bits 7-5 of the parallel port Extended
Control register (ECR) at parallel port base address +
402h and by bits 7 and 4 of the Control2 register at sec-
ond level offset 2. These registers are accessed via the
internal ECP Mode Index and Data registers at parallel
port base address + 403 and parallel port base address
+ 404h, respectively.
4.1.1
Parallel Port Operation Modes
The PC87309 parallel port supports Standard Parallel Port
(SPP), Enhanced Parallel Port (EPP) and Extended Capa-
bilities Port (ECP) configurations.
TABLE 4-1 "Parallel Port Mode Selection" on page 80
shows how to configure the parallel port for the different op-
eration modes.
●
In the Standard Parallel Port (SPP) configuration, data
rates of several hundred bytes per second are
achieved. This configuration supports the following op-
eration modes:
TABLE 2-3 "Parallel Port Address Range Allocation" on
page 21 shows how to allocate a range for the base address
of the parallel port for each mode. Parallel port address de-
coding is described in Section 2.2.2 "Address Decoding" on
page 20.
— In SPP Compatible mode the port is write-only (for
data). Data transfers are software-controlled and are
accompanied by status and control handshake sig-
nals.
The parallel port supports Plug and Play operation. Its inter-
rupt can be routed on one of the following ISA interrupts:
IRQ1 to IRQ15 except for IRQ 2 and 13. Its DMA signals
can be routed to one of three 8-bit ISA DMA channels. See
Section 4.5.19 "PP Confg0 Register" on page 94.
— PP FIFO mode enhances SPP Compatible mode by
the addition of an output data FIFO, and operation
as a state-machine operation instead of software-
controlled operation.
The parallel port device is activated by setting bit 4 of the
system Function Enable Register 1 (FER1) to 1. See Sec-
tion 7.2.3 "Function Enable Register 1 (FER1)" on page
155.
— In SPP Extended mode, the parallel port becomes a
read/write port, that can transfer a full data byte in ei-
ther direction.
●
The Enhanced Parallel Port (EPP) configuration sup-
ports two modes that offer higher bi-directional through-
put and more efficient hardware-based handling.
4.1.3
Output Pin Protection
The parallel port output pins are protected against potential
damage from connecting an unpowered port to a powered-
up printer.
— The EPP revision 1.7 mode lacks a comprehensive
handshaking scheme to ensure data transfer integ-
rity between communicating devices with dissimilar
data rates. This is the only mode that does not meet
the requirements of the IEEE 1284 standard hand-
shake and transfer protocol.
4.2 STANDARD PARALLEL PORT (SPP) MODES
Compatible SPP mode is a data write-only mode that out-
puts data to a parallel printer, using handshake bits, under
software control.
— EPP revision 1.9 mode offers data transfer enhance-
ment, while meeting the IEEE 1284 standard.
In SPP Extended mode, parallel data transfer is bi-direc-
tional. TABLE 4-12 "Parallel Port Pin Out" on page 101 lists
the output signals for the standard 25-pin, D-type connec-
tor. TABLE 4-2 "Parallel Port Reset States" on page 80 lists
the reset states for handshake output pins in this mode.
●
The Extended Capabilities Port (ECP) configuration ex-
tends the port capabilities beyond EPP modes by add-
ing a bi-directional 16-level FIFO with threshold
interrupts, for PIO and DMA data transfer, including de-
mand DMA operation. In this mode, the device becomes
a hardware state-machine with highly efficient data
transfer control by hardware in real-time.
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Parallel Port (Logical Device 1)
TABLE 4-1. Parallel Port Mode Selection
SuperI/O Parallel Port Extended Control Register Control2 Register
Configuration Register (ECR) of the Parallel Port of the Parallel Port
Configuration
Time
2
3
(Index F0h)1
(Offset 402h)
(Offset 02h)
Operation Mode
7 6 5
7 6 5
4
SPP Compatible
SPP Extended
EPP Revision 1.7
EPP Revision 1.9
SPP Compatible
PP FIFO
0 0 0
0 0 1
0 1 0
0 1 1
-
-
-
-
-
-
-
-
-
-
Configuration at
System Initial-
ization
-
-
(Static)
-
-
4
1 0 0
or
1 1 1
0 0 0
0 1 0
4
4
Configuration at
System Initial-
ization with
Run-Time Re-
configuration
(Dynamic)
SPP Extended
0 0 1
-
4
4
EPP Revision 1.7
EPP Revision 1.9
0
1
1 1 1
1 0 0
1 0 0
or
ECP(Default)
0 1 1
-
-
1 1 1
1. Section 2.6 "SUPERI/O PARALLEL PORT CONFIGURATION REGISTER (LOGICAL DEVICE 1)" on page 30
describes the bits of the SuperI/O Parallel Port configuration register.
2. See Section 4.5.12 "Extended Control Register (ECR)" on page 91
3. Before modifying this bit, set bit 4 of the SuperI/O Parallel Port configuration register at index F0h to 1.
4. Use bit 7 of the Control2 register at second level offset 2 of the parallel port to further specify compatibility. See
Section 4.5.17 "Control2 Register" on page 93.
TABLE 4-2. Parallel Port Reset States
4.2.2
SPP Data Register (DTR)
This bidirectional data port transfers 8-bit data in the direc-
tion determined by bit 5 of SPP register CTR at offset 02h
and mode.
Signal
Reset Control
State After Reset
SLIN
INIT
MR
MR
MR
MR
MR
TRI-STATE
Zero
The read or write operation is activated by the system RD
and WR strobes.
AFD
TRI-STATE
TRI-STATE
TRI-STATE
TABLE 4-4 "SPP DTR Register Read and Write Modes"
tabulates DTR register operation.
STB
IRQ5,7
TABLE 4-4. SPP DTR Register Read and Write Modes
4.2.1
SPP Modes Register Set
Bit 5 of
CTR
Mode
RD WR
Result
In all Standard Parallel Port (SPP) modes, port operation is
controlled by the registers listed in TABLE 4-3 "Standard
Parallel Port (SPP) Registers".
x
1
0
0
1
Data written to PD7-0.
SPP Com-
patible
Data read from the out-
put latch
All register bit assignments are compatible with the assign-
ments in existing SPP devices.
x
0
1
1
1
0
0
Data written to PD7-0.
Data written is latched
A single Data Register DTR is used for data input and out-
put (see Section 4.2.2 "SPP Data Register (DTR)"). The di-
rection of data flow is determined by the system setting in
bit 5 of the Control Register CTR.
SPP Ex-
tended
Data read from output
latch.
0
1
0
0
1
1
TABLE 4-3. Standard Parallel Port (SPP) Registers
Data read from PD7-0.
Offset
Name
Description
R/W
In SPP Compatible mode, the parallel port does not write
data to the output signals. Bit 5 of the CTR register has no
effect in this state. If data is written (WR goes low), the data
is sent to the output signals PD7-0. If a read cycle is initiated
(RD goes low), the system reads the contents of the output
latch, and not data from the PD7-0 output signals.
00h
DTR
Data
R/W
01h
02h
03h
STR
CTR
Status
Control
-
R
R/W
In SPP Extended mode, the parallel port can read and write
external data via PD7-0. In this mode, bit 5 sets the direction
for data in or data out, while read or write cycles are possi-
ble in both settings of bit 5.
TRI-STATE
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80
Parallel Port (Logical Device 1)
If bit 5 of CTR is cleared to 0, data is written to the output
Bit 2 - IRQ Status
signals PD7-0 when a write cycle occurs. (if a read cycle oc-
curs in this setting, the system reads the output latch, not
data from PD7-0).
In all modes except SPP Extended, this bit is always 1.
In SPP Extended mode this bit is the IRQ status bit. It re-
mains high unless the interrupt request is enabled (bit 4 of
CTR set high). This bit is high except when latched low
when the ACK signal makes a low to high transition, indi-
cating a character is now being transferred to the printer.
If bit 5 of CTR is set to 1, data is read from the output signals
PD7-0 when a read cycle occurs. A write cycle in this setting
only writes to the output latch, not to the output signals PD7-
0.
Reading this bit resets it to 1.
The reset value of this register is 0.
0: Interrupt requested in SPP Extended mode.
1: No interrupt requested. (Default)
7
0
6
0
5
0
4
3
2
0
1
0
SPP Data Register
(DTR)
Bit 3 - ERR Status
0
0
0
0
Reset
Offset 00h
This bit reflects the current state of the printer error sig-
nal, ERR. The printer sets this bit low when there is a
printer error.
Required
D0
0: Printer error.
D1
1: No printer error.
D2
D3
Bit 4 - SLCT Status
D4
Data Bits
This bit reflects the current state of the printer select sig-
nal, SLCT. The printer sets this bit high when it is on-line
and selected.
D5
D6
D7
0: No printer selected.
4.2.3
Status Register (STR)
1: Printer selected and online.
This read-only register holds status information. A system
write operation to STR is an invalid operation that has no ef-
fect on the parallel port.
Bit 5 - PE Status
This bit reflects the current state of the printer paper end
signal (PE). The printer sets this bit high when it detects
the end of the paper.
7
1
6
1
5
1
4
3
2
1
1
0
SPP Status Register
(STR)
0: Printer has paper.
1
1
1
1
Reset
Offset 01h
1: End of paper in printer.
Required
Bit 6 - ACK Status
Time-Out Status
Reserved
IRQ Status
ERR Status
SLCT Status
PE Status
ACK Status
Printer Status
This bit reflects the current state of the printer acknowl-
edge signal, ACK. The printer pulses this signal low af-
ter it has received a character and is ready to receive
another one. This bit follows the state of the ACK pin.
0: Character reception complete.
1: No character received.
Bit 7 - Printer Status
This bit reflects the current state of the printer BUSY sig-
nal. The printer sets this bit low when it is busy and can-
not accept another character.
Bit 0 - Time-Out Status
In EPP modes only, this is the time-out status bit. In all
other modes this bit has no function and has the con-
stant value 1.
This bit is the inverse of the (BUSY/WAIT) pin.
0: Printer busy.
This bit is cleared when an EPP mode is enabled.
Thereafter, this bit is set to 1 when a time-out occurs in
an EPP cycle and is cleared when STR is read.
1: Printer not busy.
4.2.4
SPP Control Register (CTR)
In EPP modes:
The control register provides all the output signals that con-
trol the printer. Except for bit 5, it is a read and write register.
0: An EPP mode is set. No time-out occurred since
STR was last read.
Normally when the Control Register (CTR) is read, the bit
values are provided by the internal output data latch. These
bit values can be superseded by the logic level of the STB,
AFD, INIT, and SLIN signals, if these signals are forced high
or low by external voltage. To force these signals high or
low the corresponding bits should be set to their inactive
states (e.g., AFD, STB and SLIN should all be 0; INIT
should be 1).
1: Time-out occurred on EPP cycle (minimum of 10
µsec). (Default)
Bit 1 - Reserved
This bit is reserved and is always 1.
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Parallel Port (Logical Device 1)
Section 4.3.10 "EPP Mode Transfer Operations" on page 1: In SPP Compatible mode, IRQx follows ACK transi-
85 describes the transfer operations that are possible in
EPP modes.
tions.
In SPP Extended mode, IRQx is set active on the trail-
ing edge of ACK.
In EPP modes, IRQx follows ACK transitions, or is
set when an EPP time-out occurs.
7
1
6
1
5
0
4
3
2
1
1
0
SPP Control Register
(CTR)
0
0
0
0
Reset
Offset 02h
Required
Bit 5 - Direction Control
This bit determines the direction of the parallel port in
SPP Extended mode only. In the (default) SPP Compat-
ible mode, this bit has no effect, since the port functions
for output only.
Data Strobe Control
Automatic Line Feed Control
Printer Initialization Control
Parallel Port Input Control
Interrupt Enable
Direction Control
Reserved
Reserved
This is a read/write bit in EPP modes. In SPP modes it
is a write only bit. A read from it returns 1.
In SPP Compatible mode and in EPP modes it does not
control the direction. See TABLE 4-4 "SPP DTR Regis-
ter Read and Write Modes" on page 80.
0: Data output to PD7-0 in SPP Extended mode dur-
ing write cycles. (Default)
Bit 0 - Data Strobe Control
Bit 0 directly controls the data strobe signal to the printer
via the STB signal.
1: Data input from PD7-0 in SPP Extended mode dur-
ing read cycles.
This bit is the inverse of the STB signal.
Bits 7,6 - Reserved
Bit 1 - Automatic Line Feed Control
These bits are reserved and are always 1.
This bit directly controls the automatic line feed signal to
the printer via the AFD pin. Setting this bit high causes
the printer to automatically feed after each line is printed.
4.3 ENHANCED PARALLEL PORT (EPP) MODES
EPP modes allow greater throughput than SPP modes by
supporting faster transfer times (8, 16 or 32-bit data trans-
fers in a single read or write operation) and a mechanism
that allows the system to address peripheral device regis-
ters directly. Faster transfers are achieved by automatically
generating the address and data strobes.
This bit is the inverse of the AFD signal.
0: No automatic line feed (Default)
1: Automatic line feed
Bit 2 - Printer Initialization Control
The connector pin assignments for these modes are listed
in TABLE 4-12 "Parallel Port Pin Out" on page 101.
Bit 2 directly controls the signal to initialize the printer via
the INIT pin. Setting this bit to low initializes the printer.
EPP modes support revision 1.7 and revision 1.9 of the
IEEE 1284 standard, as shown in TABLE 4-1 "Parallel Port
Mode Selection" on page 80.
The value of the INIT signal reflects the value of this bit.
The default setting of 1 on this bit prevents printer initial-
ization in SPP mode, and enables ECP mode after re-
set.
In Legacy mode, EPP modes are supported for a parallel
port whose base address is 278h or 378h, but not for a par-
allel port whose base address is 3BCh. (There are no EPP
registers at 3BFh.) In both Legacy and Plug and Play
modes, bits 2, 1 and 0 of the parallel port base address
must be 000 in EPP modes.
0: Initialize Printer
1: No action (Default)
Bit 3 - Select Input Signal Control
SPP-type data transactions may be conducted in EPP
modes. The appropriate registers are available for this
type of transaction. (See TABLE 4-5 "Enhanced Parallel
Port (EPP) Registers".) As in the SPP modes, software
must generate the control signals required to send or re-
ceive data.
This bit directly controls the select in signal to the printer
via the SLIN signal. Setting this bit high selects the print-
er.
It is the inverse of the SLIN signal.
This bit must be cleared to 0 before enabling the EPP or
ECP mode.
4.3.1
EPP Register Set
0: Printer not selected. (Default)
1: Printer selected and online.
TABLE 4-5 lists the EPP registers. All are single-byte regis-
ters.
Bit 4 - Interrupt Enable
Bits 0, 1 and 3 of the CTR register must be 0 before the EPP
registers can be accessed, since the signals controlled by
these bits are controlled by hardware during EPP accesses.
Once these bits are set to 0 by the software driver, multiple
EPP access cycles may be invoked.
Bit 4 controls the interrupt generated by the ACK signal.
Its function changes slightly depending on the parallel
port mode selected.
In ECP mode, this bit should be set to 0.
When EPP modes are enabled, the software can perform
SPP Extended mode cycles. In other words, if there is no
access to one of the EPP registers, EPP Address (ADDR)
In the following description, IRQx indicates an interrupt
allocated for the parallel port.
0: In SPP Compatible, SPP Extended and EPP
modes, IRQx is floated. (Default)
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Parallel Port (Logical Device 1)
or EPP Data Registers 0-3 (DATA0-3), EPP modes behave
4.3.3
SPP or EPP Status Register (STR)
like SPP Extended mode, except for the interrupt, which is
pulse triggered instead of level triggered.
This status port is read only. A read presents the current
status of the five pins on the 25-pin D-shell connector, and
the IRQ.
Bit 7 of STR (BUSY status) must be set to 1 before writing
to DTR in EPP modes to ensure data output to PD7-0.
The enhanced parallel port monitors the IOCHRDY signal
during EPP cycles. If IOCHRDY is driven low for more then
10 µsec, an EPP time-out event occurs, which aborts the
cycle by asserting IOCHRDY, thus releasing the system
from a stuck EPP peripheral device. (This time-out event is
only functional when the clock is applied to this logical de-
vice).
7
1
6
1
5
1
4
3
2
1
1
0
SPP or EPP Status
Register (STR)
Offset 01h
1
1
1
1
Reset
Required
Time-Out Status
Reserved
IRQ Status
ERR Status
SLCT Status
PE Status
ACK Status
Printer Status
When the cycle is aborted, ASTRB or DSTRB becomes in-
active, and the time-out event is signaled by asserting bit 0
of STR. If bit 4 of CTR is 1, the time-out event also pulses
the IRQ5 or IRQ7 signals when enabled. (IRQ5 and IRQ7
can be routed to any other IRQ lines via the Plug and Play
block).
EPP cycles to the external device are activated by invoking
read or write cycles to the EPP.
The bits of this register have the identical function in EPP
mode as in SPP mode. See Section 4.2.3 "Status Register
(STR)" on page 81 for a detailed description of each bit.
TABLE 4-5. Enhanced Parallel Port (EPP) Registers
4.3.4
SPP or EPP Control Register (CTR)
Offset
Name
Description
Mode
SPP or EPP R/W
SPP or EPP
SPP or EPP R/W
R/W
This control port is read or write. A write operation to it sets
the state of four pins on the 25-pin D-shell connector, and
controls both the parallel port interrupt enable and direction.
00h
01h
02h
03h
04h
05h
06h
07h
DTR
STR
SPP Data
SPP Status
SPP Control
EPP Address
R
CTR
ADDR
EPP
EPP
EPP
EPP
EPP
R/W
R/W
R/W
R/W
R/W
7
1
6
1
5
0
4
3
2
0
1
0
SPP or EPP Control
Register (CTR)
0
0
0
0
Reset
DATA0 EPP Data Port 0
DATA1 EPP Data Port 1
DATA2 EPP Data Port 2
DATA3 EPP Data Port 3
Offset 02h
Required
Data Strobe Control
Automatic Line Feed Control
Printer Initialization Control
Parallel Port Input Control
Interrupt Enable
Direction Control
Reserved
Reserved
4.3.2
SPP or EPP Data Register (DTR)
The DTR register is the SPP Compatible or SPP Extended
data register. A write to DTR sets the state of the eight data
pins on the 25-pin D-shell connector.
7
0
6
0
5
0
4
3
2
0
1
0
SPP or EPP Data
Register (DTR)
Offset 00h
The bits of this register have the identical function in EPP
modes as in SPP modes. See Section 4.2.4 "SPP Control
Register (CTR)" on page 81 for a detailed description of
each bit.
0
0
0
0
Reset
Required
D0
4.3.5
EPP Address Register (ADDR)
D1
This port is added in EPP modes to enhance system
throughput by enabling registers in the remote device to be
directly addressed by hardware.
D2
D3
D4
This port can be read or written. Writing to it initiates an EPP
device or register selection operation.
D5
Data Bits
D6
D7
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Parallel Port (Logical Device 1)
4.3.8
EPP Data Register 2 (DATA2)
7
0
6
0
5
0
4
3
2
0
1
0
EPP Address
Register (ADDR)
Offset 03h
This is the third EPP data register. It is only accessed to
transfer bits 16 through 23 of a 32-bit read or write to EPP
Data Register 0 (DATA0).
0
0
0
0
Reset
Required
7
0
6
0
5
0
4
3
2
0
1
0
EPP Data Register 2
(DATA2)
A0
0
0
0
0
Reset
A1
Offset 06h
A2
Required
A3
A4
D16
EPP Device or
Register Selection
Address Bits
A5
D17
D18
D19
D20
D21
D22
D23
A6
A7
4.3.6
EPP Data Register 0 (DATA0)
EPP Device
Read or Write Data
DATA0 is a read/write register. Accessing it initiates device
read or write operations of bits 7 through 0.
4.3.9
EPP Data Register 3 (DATA3)
7
0
6
0
5
0
4
3
2
0
1
0
EPP Data Register 0
(DATA0)
This is the fourth EPP data register. It is only accessed to
transfer bits 24 through 31 of a 32-bit read or write to EPP
Data Register 0 (DATA0).
0
0
0
0
Reset
Offset 04h
Required
D0
7
0
6
0
5
0
4
3
2
0
1
0
EPP Data Register 3
(DATA3)
D1
0
0
0
0
Reset
D2
Offset 07h
D3
Required
D4
EPP Device
Read or Write Data
D5
D24
D6
D25
D26
D27
D28
D29
D30
D31
D7
4.3.7
EPP Data Register 1 (DATA1)
EPP Device
Read or Write Data
DATA1 is only accessed to transfer bits 15 through 8 of a
16-bit read or write to EPP Data Register 0 (DATA0).
7
0
6
0
5
0
4
3
2
0
1
0
EPP Data Register 1
(DATA1)
0
0
0
0
Reset
Offset 05h
Required
D8
D9
D10
D11
D12
D13
D14
D15
EPP Device
Read or Write Data
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Parallel Port (Logical Device 1)
4.3.10 EPP Mode Transfer Operations
puts D7-0 in TRI-STATE.
The EPP transfer operations are address read or write, and
data read or write. An EPP transfer is composed of a sys-
tem read or write cycle from or to an EPP register, and an
EPP read or write cycle from a peripheral device to an EPP
register or from an EPP register to a peripheral device.
D7-0
RD
EPP 1.7 Address Write
WAIT
The following procedure selects a peripheral device or reg-
ister as illustrated in FIGURE FIGURE 4-1 "EPP 1.7 Ad-
dress Write".
ASTRB
WRITE
PD7-0
1. The system writes a byte to the EPP Address register.
WR becomes low to latch D7-0 into the EPP Address
register. The latch drives the EPP Address register onto
PD7-0 and the EPP pulls WRITE low.
2. The EPP pulls ASTRB low to indicate that data was
sent.
IOCHRDY
3. If WAIT was low during the system write cycle,
IOCHRDY becomes low. When WAIT becomes high,
the EPP pulls IOCHRDY high.
FIGURE 4-2. EPP 1.7 Address Read
EPP 1.7 Data Write and Read
4. When IOCHRDY becomes high, it causes WR to be-
come high. If WAIT is high during the system write cycle,
then the EPP does not pull IOCHRDY to low.
This procedure writes to the selected peripheral device or
register.
EPP 1.7 data read or write operations are similar to EPP 1.7
Address register read or write operations, except that the
data strobe (DSTRB signal), and the EPP Data register, re-
place the address strobe (ASTRB signal) and the EPP Ad-
dress register, respectively.
5. When WR becomes high, it causes the EPP to pull first
ASTRB and then WRITE to high. The EPP can change
PD7-0 only when WRITE and ASTRB are both high.
D7-0
WR
4.3.11 EPP 1.7 and 1.9 Data Write and Read
Operations
EPP 1.9 Address Write
WAIT
The following procedure selects a peripheral or register as
shown in FIGURE FIGURE 4-3 "EPP 1.9 Address Write".
ASTRB
WRITE
PD7-0
1. The system writes a byte to the EPP Address register.
2. The EPP pulls IOCHRDY low, and waits for WAIT to be-
come low.
3. When WAIT becomes low, the EPP pulls WRITE to low
and drives the latched byte onto PD7-0. If WAIT was al-
ready low, steps 2 and 3 occur concurrently.
IOCHRDY
4. The EPP pulls ASTRB low and waits for WAIT to be-
come high.
FIGURE 4-1. EPP 1.7 Address Write
EPP 1.7 Address Read
5. When WAIT becomes high, the EPP stops pulling
IOCHRDY low, and waits for WR to become high.
The following procedure reads from the EPP Address reg-
ister as shown in FIGURE FIGURE 4-2 "EPP 1.7 Address
Read".
6. When WR becomes high, the EPP pulls ASTRB high,
and waits for WAIT to become low.
7. If no EPP write is pending when WAIT becomes low, the
EPP pulls WRITE to high. Otherwise, WRITE remains
low, and the EPP may change PD7-0.
1. The system reads a byte from the EPP Address register.
RD goes low to gate PD7-0 into D7-0.
2. The EPP pulls ASTRB low to signal the peripheral to
start sending data.
3. If WAIT is low during the system read cycle. Then the
EPP pulls IOCHRDY low. When WAIT becomes high,
the EPP stops pulling IOCHRDY to low.
4. When IOCHRDY becomes high, it causes RD to be-
come high. If WAIT is high during the system read cycle
then the EPP does not pull IOCHRDY to low.
5. When RD becomes high, it causes the EPP to pull
ASTRB high. The EPP can change PD7-0 only when
ASTRB is high. After ASTRB becomes high, the EPP
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Parallel Port (Logical Device 1)
4.4 EXTENDED CAPABILITIES PARALLEL PORT
(ECP)
D7-0
WR
In the Extended Capabilities Parallel Port (ECP) modes, the
device is a state machine that supports a 16-byte FIFO that
can be configured for either direction, command and data
FIFO tags (one per byte), a FIFO threshold interrupt for both
directions, FIFO empty and full status bits, automatic gen-
eration of strobes (by hardware) to fill or empty the FIFO,
transfer of commands and data, and Run Length Encoding
(RLE) expanding (decompression) as explained below. The
FIFO can be accessed by PIO or system DMA cycles.
WAIT
ASTRB
WRITE
PD7-0
4.4.1
ECP Modes
ECP modes are enabled as described in TABLE 4-1 "Par-
allel Port Mode Selection" on page 80. The ECP mode is se-
lected at reset by setting bits 7-5 of the SuperI/O Parallel
Port Configuration register at index F0h (see Section 2.6
"SUPERI/O PARALLEL PORT CONFIGURATION REGIS-
TER (LOGICAL DEVICE 1)" on page 30) to 100 or 111.
Thereafter, the mode is controlled via the bits 7-5 of the
ECP Extended Control Register (ECR) at offset 402h of the
parallel port. See Section 4.5.12 "Extended Control Regis-
ter (ECR)" on page 91.
IOCHRDY
FIGURE 4-3. EPP 1.9 Address Write
EPP 1.9 Address Read
The following procedure reads from the address register.
TABLE 4-9 "ECP Modes Encoding" on page 92 lists the
ECP modes. See TABLE 4-11 "ECP Modes" on page 96
and Section 4.6 "DETAILED ECP MODE DESCRIPTIONS"
on page 95 for more detailed descriptions of these modes.
1. The system reads a byte from the EPP address register.
When RD becomes low, the EPP pulls IOCHRDY low,
and waits for WAIT to become low.
2. When WAIT becomes low, the EPP pulls ASTRB low
and waits for WAIT to become high. If WAIT was already
low, steps 2 and 3 occur concurrently.
4.4.2
Software Operation
Software should operate as described in “Extended Capa-
bilities Port Protocol and ISA Interface Standard”.
3. When WAIT becomes high, the EPP stops pulling IO-
CHRDY low, and waits for RD to become high.
Some of these operations are:
4. When RD becomes high, the EPP latches PD7-0 (to
provide sufficient hold time), pulls ASTRB high, and puts
D7-0 in TRI-STATE.
●
Software should enable ECP after bits 3-0 of the parallel
port Control Register (CTR) are set to 0100.
●
When ECP is enabled, software should switch modes
only through modes 000 or 001.
D7-0
RD
●
When ECP is enabled, the software should change di-
rection only in mode 001.
●
Software should not switch from mode 010 or 011, to
mode 000 or 001, unless the FIFO is empty.
WAIT
●
Software should switch to mode 011 when bits 0 and 1
ASTRB
WRITE
PD7-0
of DCR are 0.
●
Software should switch to mode 010 when bit 0 of DCR
is 0.
●
Software should disable ECP only in mode 000 or 001.
●
Software should switch to mode 100 when bits 0, 1 and
IOCHRDY
3 of the DCR are 0.
●
Software should switch from mode 100 to mode 000 or
FIGURE 4-4. EPP 1.9 Address Read
001 only when bit 7 of the DSR (BUSY) is 1. Otherwise,
an on-going EPP cycle can be aborted.
EPP 1.9 Data Write and (Backward) Data Read
●
When the ECP is in mode 100, software should write 0
to bit 5 of the DCR before performing EPP cycles.
This procedure writes to the selected peripheral drive or
register.
Software may switch from mode 011 backward to modes
000 or 001, when there is an on-going ECP read cycle. In
this case, the read cycle is aborted by deasserting AFD.
The FIFO is reset (empty) and a potential byte expansion
(RLE) is automatically terminated since the new mode is
000 or 001.
EPP 1.9 data read and write operations are similar to EPP
1.9 address read and write operations, except that the data
strobe (DSTRB signal) and EPP Data register replace the
address strobe (ASTRB signal) and the EPP Address reg-
ister, respectively.
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Parallel Port (Logical Device 1)
4.4.3
Hardware Operation
4.5 ECP MODE REGISTERS
The ECP uses an internal clock, which can be frozen to re-
duce power consumption during power down. In this power-
down state the DMA is disabled, all interrupts (except ACK)
are masked, and the FIFO registers are not accessible (ac-
cess is ignored). The other ECP registers are unaffected by
power-down and are always accessible when the ECP is
enabled. During power-down the FIFO status and contents
become inaccessible, and the system reads bit 2 of ECR as
0, bit 1 of ECR as 1 and bit 0 of ECR as 1, regardless of the
actual values of these bits. The FIFO status and contents
are not lost, however, and when the clock activity resumes,
the values of these bits resume their designated functions.
The ECP registers are each a byte wide, and are listed in
TABLE Table 4-6 in order of their offsets from the base ad-
dress of the parallel port. In addition, the ECP has control
registers at second level offsets, that are accessed via the
EIR and EDR registers. See 4.5.2 "Second Level Offsets"
on page 88.
TABLE 4-6. Extended Capabilities Parallel Port (ECP)
Registers
Modes
(ECR Bits)
Offset Symbol
Description
R/W
7 6 5
When the clock is frozen, an on-going ECP cycle may be
corrupted, but the next ECP cycle will not start even if the
FIFO is not empty in the forward direction, or not full in the
backward direction. If the ECP clock starts or stops toggling
during a system cycle that accesses the FIFO, the cycle
may yield wrong data.
000h
DATAR Parallel Port Data
Register
0 0 0
0 0 1
R/W
000h
001h
002h
400h
AFIFO ECP Address FIFO
0 1 1
W
R
DSR
DCR
Status Register
All Modes
ECP output signals are inactive when the ECP is disabled.
Control Register All Modes R/W
Only the FIFO, DMA and RLE do not function when the
clock is frozen. All other registers are accessible and func-
tional. The FIFO, DMA and RLE are affected by ECR mod-
ifications, i.e., they are reset when exits from modes 010 or
011 are carried out even while the clock is frozen.
CFIFO Parallel Port Data
FIFO
0 1 0
W
400h
400h
DFIFO
TFIFO
ECP Data FIFO
Test FIFO
0 1 1
1 1 0
1 1 1
R/W
R/W
R
400h CNFGA Configuration Reg-
ister A
401h CNFGB Configuration Reg-
ister B
1 1 1
R
402h
ECR
Extended Control All Modes R/W
Register
403h
EIR
Extended Index
Register
All Modes R/W
404h
405h
EDR
EAR
Extended Data
Register
All Modes R/W
Extended Auxiliary All Modes R/W
Status Register
Control Registers at Second Level Offsets
00h
02h
04h
05h
Control0
Control2
All Modes R/W
All Modes R/W
All Modes R/W
All Modes R/W
Control4
PP Confg0
4.5.1
Accessing the ECP Registers
The AFIFO, CFIFO, DFIFO and TFIFO registers access the
same ECP FIFO. The FIFO is accessed at Base + 000h, or
Base + 400h, depending on the mode field of ECR and the
register.
The FIFO can be accessed by system DMA cycles, as well
as system PIO cycles.
When the DMA is configured and enabled (bit 3 of ECR is 1
and bit 2 of ECR is 0) the ECP automatically (by hardware)
issues DMA requests to fill the FIFO (in the forward direc-
tion when bit 5 of DCR is 0) or to empty the FIFO (in the
backward direction when bit 5 of DCR is 1). All DMA trans-
fers are to or from these registers. The ECP does not assert
DMA requests for more than 32 consecutive DMA cycles.
The ECP stops requesting the DMA when TC is detected
during an ECP DMA cycle.
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Parallel Port (Logical Device 1)
A “Demand DMA” feature reduces system overhead
4.5.4
ECP Address FIFO (AFIFO) Register
caused by DMA data transfers. When this feature is en-
abled by bit 6 of the PP Config0 register at second level off-
set 05h, it prevents servicing of DMA requests until after
four have accumulated and are held pending. See “Bit 6 -
Demand DMA Enable” on page 94.
The ECP Address FIFO Register (AFIFO) is write only. In
the forward direction (when bit 5 of DCR is 0) a byte written
into this register is pushed into the FIFO and tagged as a
command.
Reading this register returns undefined contents. Writing to
this register in a backward direction (when bit 5 of DCR is 1)
has no effect and the data is ignored.
Writing into a full FIFO, and reading from an empty FIFO,
are ignored. The written data is lost, and the read data is un-
defined. The FIFO empty and full status bits are not affected
by such accesses.
Bits 7-5 of ECR = 011
Some registers are not accessible in all modes of operation,
or may be accessed in one direction only. Accessing a non
accessible register has no effect. Data read is undefined;
data written is ignored; and the FIFO does not update. The
SPP registers (DTR, STR and CTR) are not accessible
when the ECP is enabled.
7
0
6
0
5
0
4
3
2
0
1
0
ECP Address Register
(AFIFO)
0
0
0
0
Reset
Offset 000h
Required
A0
To improve noise immunity in ECP cycles, the state ma-
chine does not examine the control handshake response
lines until the data has had time to switch.
A1
A2
A3
In ECP modes:
A4
●
DATAR replaces DTR of SPP/EPP
Address Bits
A5
●
A6
DSR replaces STR of SPP/EPP
A7
●
DCR replaces CTR of SPP/EPP
4.5.5
ECP Status Register (DSR)
4.5.2
Second Level Offsets
This read-only register displays device status. Writes to this
DSR have no effect and the data is ignored.
The EIR, EDR, and EAR registers support enhanced con-
trol and status features. When bit 4 of the Parallel Port Con-
figuration register is 1 (as described in Section 2.6
"SUPERI/O PARALLEL PORT CONFIGURATION REGIS-
TER (LOGICAL DEVICE 1)" on page 30), EIR and EDR
serve as index and data registers, respectively.
This register should not be confused with the DSR register
of the Floppy Disk Controller (FDC).
7
6
5
4
3
2
1
1
0
ECP Status Register
(DSR)
EIR and EDR at offsets 403 and 404, respectively, access
the control registers (Control0, Control2, Control4 and PP
Config0) at second level offsets 00h, 02h, 04h and 05h, re-
spectively. These control registers are functional only. Ac-
cessing these registers is possible when bit 4 of the
SuperI/O Parallel Port Configuration register at index F0h of
Logical Device 1 is 1 and when bit 2 or 10 of the base ad-
dress is 1.
1
1
Reset
Offset 001h
1
1
Required
EPP Time-Out Status
Reserved
Reserved
ERR Status
SLCT Status
PE Status
ACK Status
Printer Status
4.5.3
ECP Data Register (DATAR)
The ECP Data Register (DATAR) register is the same as
the DTR register (see Section 4.2.2 "SPP Data Register
(DTR)" on page 80), except that a read always returns the
values of the PD7-0 signals instead of the register latched
data.
Bits 0 - EPP Time-Out Status
In EPP modes only, this is the time-out status bit. In all
other modes this bit has no function and has the con-
stant value 1.
Bits 7-5 of ECR = 000 or 001
7
0
6
0
5
0
4
3
2
0
1
0
ECP Data Register
(DATAR)
This bit is cleared when an EPP mode is enabled.
Thereafter, this bit is set to 1 when a time-out occurs in
an EPP cycle and is cleared when STR is read.
0
0
0
0
Reset
Offset 000h
Required
In EPP modes:
0 - An EPP mode is set. No time-out occurred since
STR was last read.
D0
D1
1: Time-out occurred on EPP cycle (minimum of 10
D2
µsec). (Default)
D3
D4
Data Bits
Bits 2,1: Reserved
D5
These bits are reserved and are always 1.
D6
D7
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Parallel Port (Logical Device 1)
In mode 011, AFD is activated by both ECP hardware
Bit 3 - ERR Status
and by software using this bit.
0: No automatic line feed. (Default)
1: Automatic line feed.
This bit reflects the status of the ERR signal.
0: Printer error.
1: No printer error.
Bit 2 - Printer Initialization Control
Bit 4 - SLCT Status
Bit 2 directly controls the signal to initialize the printer via
the INIT signal. Setting this bit to low initializes the print-
er. The INIT signal follows this bit.
This bit reflects the status of the Select signal. The print-
er sets this signal high when it is online and selected
0: Printer not selected. (Default)
1: Printer selected and on-line.
0: Initialize printer. (Default)
1: No action
Bit 5 - PE Status
Bit 3 - Parallel Port Input Control
This bit reflects the status of the Paper End (PE) signal.
0: Paper not ended.
This bit directly controls the select input device signal to
the printer via the SLIN signal. It is the inverse of the
SLIN signal.
1: No paper in printer.
This bit must be set to 1 before enabling the EPP or
ECP modes.
Bit 6 - ACK Status
This bit reflects the status of the ACK signal. This signal
is pulsed low after a character is received.
0: The printer is not selected.
1: The printer is selected.
0: Character received.
1: No character received. (Default)
Bit 4 - Interrupt Enable
Bit 4 enables the interrupt generated by the ACK signal.
In ECP mode, this bit should be set to 0. This bit does
not float the IRQ pin.
Bit 7 - Printer Status
This bit reflects the inverse of the state of the BUSY sig-
nal.
0: Masked. (Default)
1: Enabled.
0: Printer is busy (cannot accept another character
now).
1: Printer not busy (ready for another character).
Bit 5 - Direction Control
This bit determines the direction of the parallel port.
4.5.6
ECP Control Register (DCR)
This is a read/write bit in EPP mode. In SPP mode it is
a write only bit. A read from it returns 1. In SPP Compat-
ible mode and in EPP mode it does not control the direc-
tion. See TABLE 4-4 "SPP DTR Register Read and
Write Modes" on page 80.
Reading this register returns the register content (not the
signal values, as in SPP mode).
7
1
6
1
5
0
4
3
2
0
1
0
ECP Control
Register (DCR)
Offset 002h
The ECP drives the PD7-0 pins in the forward direction,
but does not drive them in the backward direction.
0
0
0
0
Reset
Required
This bit is readable and writable. In modes 000 and 010
the direction bit is forced to 0, internally, regardless of
the data written into this bit.
Data Strobe Control
Automatic Line Feed Control
Printer Initialization Control
Parallel Port Input Control
Interrupt Enable
Direction Control
Reserved
Reserved
0: ECP drives forward in output mode. (Default)
1: ECP direction is backward.
Bits 7,6 - Reserved
These bits are reserved and are always 1.
Bit 0 - Data Strobe Control
Bit 0 directly controls the data strobe signal to the printer
via the STB signal. It is the inverse of the STB signal.
0: The STB signal is inactive in all modes except 010
and 011. In these modes, it may be active or inac-
tive as set by the software.
1: In all modes, STB is active.
Bit 1 - Automatic Line Feed Control
This bit directly controls the automatic feed XT signal to
the printer via the AFD signal. Setting this bit high caus-
es the printer to automatically feed after each line is
printed. This bit is the inverse of the AFD signal.
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Parallel Port (Logical Device 1)
Parallel Port Data FIFO (CFIFO) Register The FIFO does not stall when overwritten or underrun (ac-
4.5.7
cess is ignored). Bytes are always read from the top of the
FIFO, regardless of the direction bit setting (bit 5 of DCR).
For example if 44h, 33h, 22h, 11h is written into the FIFO,
reading the FIFO returns 44h, 33h, 22h, 11h (in the same
order it was written).
The Parallel Port FIFO (CFIFO) register is write only. A byte
written to this register by PIO or DMA is pushed into the
FIFO and tagged as data.
Reading this register has no effect and the data read is un-
defined.
Bits 7-5 of ECR = 110
Bits 7-5 of ECR = 010
7
0
6
0
5
0
4
3
2
0
1
0
Test FIFO
Register (TFIFO)
Offset 400h
7
0
6
0
5
0
4
3
2
1
0
Parallel Port FIFO
Register (CFIFO)
Offset 400h
0
0
0
0
Reset
0
0
0
0
0
Reset
Required
Required
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
Data Bits
D5
Data Bits
D5
D6
D6
D7
D7
4.5.10 Configuration Register A (CNFGA)
4.5.8
ECP Data FIFO (DFIFO) Register
This register is read only. Reading CNFGA always returns
100 on bits 2 through 0 and 0001 on bits 7 through 4.
This bi-directional FIFO functions as either a write-only de-
vice when bit 5 of DCR is 0, or a read-only device when it is 1.
Writing this register has no effect and the data is ignored.
In the forward direction (bit 5 of DCR is 0), a byte written to
the ECP Data FIFO (DFIFO) register by PIO or DMA is
pushed into the FIFO and tagged as data. Reading this reg-
ister when set for write-only has no effect and the data read
is undefined.
Bits 7-5 of ECR = 111
7
0
6
0
5
0
4
3
2
1
1
0
Configuration Register A
(CNFGA)
1
0
0
0
Reset
In the backward direction (bit 5 of DCR is 1), the ECP auto-
matically issues ECP read cycles to fill the FIFO.
Offset 400h
0
0
0
1
1
0
0
Required
Reading from this register pops a byte from the FIFO. Writ-
ing to this register when it is set for read-only has no effect,
and the data written is ignored.
Always 0
Always 0
Always 1
Bit 7 of PP Confg0
Always 1
Always 0
Always 0
Always 0
Bits 7-5 of ECR = 011
7
0
6
0
5
0
4
3
2
0
1
0
ECP Data FIFO
Register (DFIFO)
Offset 400h
0
0
0
0
Reset
Required
Bits 2-0 - Reserved
D0
These bits are reserved and are always 100.
D1
D2
Bit 3 - Bit 7 of PP Confg0
D3
This bit reflects the value of bit 7 of the ECP PP Confg0
register (second level offset 05h), which has no specific
function. Whatever value is put in bit 7 of PP Confg0 will
appear in this bit.
D4
Data Bits
D5
D6
D7
This bit reflects a specific system configuration parame-
ter, as opposed to other devices, e.g., 8-bit data word
length.
4.5.9
Test FIFO (TFIFO) Register
A byte written into the Test FIFO (TFIFO) register is pushed
into the FIFO. A byte read from this register is popped from
the FIFO. The ECP does not issue an ECP cycle to transfer
the data to or from the peripheral device.
Bit 7-4 - Reserved
These bits are reserved and are always 0001.
The TFIFO is readable and writable in both directions. In the
forward direction (bit 5 of DCR is 0) PD7-0 are driven, but
the data is undefined.
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Parallel Port (Logical Device 1)
4.5.11 Configuration Register B (CNFGB)
TABLE 4-8. ECP Mode Interrupt Selection
Configuration register B (CNFGB) is read only. Reading this
register returns the configured parallel port interrupt line
and DMA channel, and the state of the interrupt line.
Bit 5 Bit 4 Bit 3
Interrupt Selection
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Selected by jumpers.
IRQ7 selected.
IRQ9 selected.
IRQ10 selected.
IRQ11 selected.
IRQ14 selected.
IRQ15 selected.
IRQ5 selected.
Writing to this register has no effect and the data is ignored.
Bits 7-5 of ECR = 111
7
0
6
0
5
x
4
3
2
0
1
0
Configuration Register B
(CNFGB)
x
x
0
0
Reset
Offset 401h
Required
DMA Channel Select
Reserved
Bit 6 - IRQ Signal Value
This bit holds the value of the IRQ signal configured by
the Interrupt Select register (index 70h of this logical de-
vice).
Interrupt Select
IRQ Signal Value
Reserved
Bit 7 - Reserved
This bit is reserved and is always 0.
Bits 1,0 - DMA Channel Select
4.5.12 Extended Control Register (ECR)
These bits reflect the value of bits 1,0 of the PP Config0
register (second level offset 05h). Microsoft’s ECP Pro-
tocol and ISA Interface Standard defines these bits as
shown in TABLE 4-7 "ECP Mode DMA Selection".
This register controls the ECP and parallel port functions. On
reset this register is initialized to 00010xx1 (bits 1 and 2 de-
pend on the clock status). IOCHRDY is driven low on an ECR
read when the ECR status bits do not hold updated data.
Bits 1,0 of PP Config0 are read/write bits, but CNFGB
bits are read only.
Upon reset, these bits are initialized to 00.
7
0
6
0
5
0
4
3
2
1
0
Extended Control
Register (ECR)
Offset 402h
1
0
1
Reset
TABLE 4-7. ECP Mode DMA Selection
Required
Bit 1 Bit 0
DMA Configuration
FIFO Empty
0
0
1
1
0
1
0
1
8-bit DMA selected by jumpers. (Default)
DMA channel 1 selected.
FIFO Full
ECP Interrupt Service
ECP DMA Enable
ECP Interrupt Mask
DMA channel 2 selected.
DMA channel 3 selected.
Bit 2 - Reserved
ECP Mode Control
This bit is reserved and is always 0.
Bit 0 - FIFO Empty
Bits 5-3 - Interrupt Select Bits
This bit continuously reflects the FIFO state, and there-
fore can only be read. Data written to this bit is ignored.
These bits reflect the value of bits 5-3 of the PP Config0
register at second level index 05h. Microsoft’s ECP Pro-
tocol and ISA Interface Standard defines these bits as
shown in TABLE 4-8 "ECP Mode Interrupt Selection".
When the ECP clock is frozen this bit is read as 1, re-
gardless of the actual FIFO state.
0: The FIFO has at least one byte of data.
1: The FIFO is empty or ECP clock is frozen.
Bits 5-3 of PP Config0 are read/write bits, but CNFGB
bits are read only.
Upon reset, these bits have undefined values.
Bit 1 - FIFO Full
This bit continuously reflects the FIFO state, and there-
fore can only be read. Data written to this bit is ignored.
When the ECP clock is frozen this bit is read as 1, re-
gardless of the actual FIFO state.
0: The FIFO has at least one free byte.
1: The FIFO is full or ECP clock frozen.
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Parallel Port (Logical Device 1)
TABLE 4-9. ECP Modes Encoding
Bit 2 - ECP Interrupt Service
This bit enables servicing of interrupt requests. It is set
to 1 upon reset, and by the occurrence of interrupt
events. It is set to 0 by software.
ECR Bit Encoding
Mode Name
Bit 7
Bit 6
Bit 5
While this bit is 1, neither the DMA nor the interrupt
events listed below will generate an interrupt.
0
0
0
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
0
0
1
Standard
PS/2
While this bit is 0, the interrupt setup is “armed” and an
interrupt is generated on occurrence of an interrupt
event.
Parallel Port FIFO
ECP FIFO
While the ECP clock is frozen, this bit always returns a
0 value, although it retains its proper value and may be
modified.
EPP Mode
FIFO Test
When one of the following interrupt events occurs while
this bit is 0, an interrupt is generated and this bit is set
to 1 by hardware.
Configuration
4.5.13 ECP Extended Index Register (EIR)
— DMA is enabled (bit 3 of ECR is 1) and terminal
count is reached.
The parallel port is partially configured by bits within the log-
ical device address space. These configuration bits are ac-
cessed via this read/write register and the Extended Data
Register (EDR) (see Section 4.5.14 "ECP Extended Data
Register (EDR)" on page 93), when bit 4 of the SuperI/O
Parallel Port Configuration register at index F0h of Logical
Device 1 is set to 1. See Section 2.6 on page 30.
— FIFO write threshold reached (no DMA - bit 3 of ECR
is 0; forward direction (bit 5 of DCR is 0), and there
are eight or more bytes free in the FIFO).
— FIFO read threshold reached (no DMA - bit 3 of ECR
is 0; read direction set - bit 5 of DCR is 1, and there
are eight or more bytes to read from the FIFO).
The configuration bits within the parallel port address space
are initialized to their default values on reset, and not when
the parallel port is activated.
0: The DMA and the above interrupts are not dis-
abled.
1: The DMA and the above three interrupts are dis-
abled.
7
0
6
0
5
0
4
3
2
0
1
0
ECP Extended Index
Register (EIR)
Bit 3 - ECP DMA Enable
0
0
0
0
Reset
Offset 403h
0: The DMA request signal (DRQ3-0) is set to TRI-
STATE and the appropriate acknowledge signal
(DACK3-0) is assumed inactive.
Required
1: The DMA is enabled and the DMA starts when bit 2
of ECR is 0.
Second Level Offset
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 4 - ECP Interrupt Mask
0: An interrupt is generated on ERR assertion (the
high-to-low edge of ERR). An interrupt is also gen-
erated while ERR is asserted when this bit is
changed from 1 to 0; this prevents the loss of an in-
terrupt between ECR read and ECR write.
Bits 2-0 - Second Level Offset
1: No interrupt is generated.
Data written to these bits is used as a second level off-
set for accesses to a specific control register. Second
level offsets of 00h, 02h, 04h and 05h are supported. At-
tempts to access registers at any other offset have no
effect.
Bits 7-5 - ECP Mode Control
These bits set the mode for the ECP device. See Sec-
tion 4.6 "DETAILED ECP MODE DESCRIPTIONS" on
page 95 for a more detailed description of operation in
each of these ECP modes. The ECP modes are listed in
TABLE 4-9 "ECP Modes Encoding" and described in
detail in TABLE 4-11 "ECP Modes" on page 96.
TABLE 4-10. Second Level Offsets
Second Level
Offset
Control
Register Name
Described in
Section
00h
02h
04h
05h
Control0
Control2
4.5.16
4.5.17
4.5.18
4.5.19
Control4
PP Confg0
000:Access the Control0 register.
010:Access the Control2 register.
100:Access the Control4 register.
101:Access the PP Confg0 register.
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Parallel Port (Logical Device 1)
Bits 7-3 - Reserved
4.5.16 Control0 Register
These bits are treated as 0 for offset calculations. Writ-
ing any other value to them has no effect.
Upon reset, this register is initialized to 00h.
These bits are read only. They return 00000 on reads
and must be written as 00000.
7
0
6
0
5
0
4
3
2
0
1
0
Control0 Register
Second Level
Offset 00h
0
0
0
0
Reset
4.5.14 ECP Extended Data Register (EDR)
Required
This read/write register is the data port of the control regis-
ter indicated by the index stored in the EIR. Reading or writ-
ing this register reads or writes the data in the control
register whose second level offset is specified by the EIR.
EPP Time-Out
Interrupt Mask
Reserved
Reserved
Reserved
Freeze Bit
DCR Register Live
Reserved
Reserved
ECP Extended Data
Register (EDR)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
0
Reset
Offset 404h
Required
D0
Bit 0 - EPP Time-Out Interrupt Mask
0: The EPP time-out is masked.
1: The EPP time-out is generated.
D1
D2
D3
D4
Bit 3-1 - Reserved
Bit 4 - Freeze Bit
Data Bits
D5
D6
D7
In mode 011, setting this bit to 1 freezes part of the in-
terface with the peripheral device, and clearing this bit to
0 releases and initializes it.
Bits 7-0 - Data Bits
These read/write data bits transfer data to and from the
Control Register pointed at by the EIR register.
In all other modes the value of this bit is ignored.
Bit 5 - DCR Register Live
4.5.15 ECP Extended Auxiliary Status Register (EAR)
When this bit is 1, reading DCR (see Section 4.5.6 "ECP
Control Register (DCR)" on page 89) reads the interface
control lines pin values regardless of the mode selected.
Upon reset, this register is initialized to 00h.
Otherwise, reading the DCR reads the content of the
register.
ECP Extended Auxiliary
7
0
6
0
5
0
4
3
2
0
1
0
Status Register (EAR)
0
0
0
0
Reset
Offset 405h
Bits 7, 6 - Reserved
Required
4.5.17 Control2 Register
Upon reset, this register is initialized to 00h.
7
0
6
0
5
0
4
3
2
0
1
0
Control2 Register
Second Level
Offset 02h
Reserved
0
0
0
0
Reset
Required
FIFO Tag
Bits 6-0 - Reserved
Bit 7 - FIFO Tag
Reserved
Revision 1.7 or 1.9 Select
Reserved
Channel Address Enable
SPP Compatability
Read only. In mode 011, when bit 5 of the DCR is 1
(backward direction), this bit reflects the value of the tag
bit (BUSY status) of the word currently in the bottom of
the FIFO.
In other modes this bit is indeterminate.
Bits 3-0 - Reserved
Bit 4 - EPP 1.7/1.9 Select
Selects EPP version 1.7 or 1.9.
0: EPP version 1.7.
1: EPP version 1.9.
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Parallel Port (Logical Device 1)
Bit 3 - Reserved
Bit 5 - Reserved
Bit 6 - Channel Address Enable
Bits 6-4 - Parallel Port DMA Request Inactive Time
When this bit is 1, mode is 011, direction is backward,
there is an input command (BUSY is 0), and bit 7 of the
data is 1, the command is written into the FIFO.
This field specifies the minimum number of clock cycles
that the parallel port DMA signals remain inactive after
being deactivated by the fairness mechanism.
The default value is 000, which specifies 8 clock cycles.
Bit 7 - SPP Compatibility
Otherwise, the number of clock cycles is 8 + 32n, where
n is the value of these bits.
See “Bits 7-5 - ECP Mode Control” on page 92 for a de-
scription of each mode.
0: Modes 000, 001 and 100 are identical to ECP.
Bit 7 - Reserved
1: Modes 000 and 001 of the ECP are identical with
Compatible and Extended modes of the SPP (see
Section 4.1 "PARALLEL PORT CONFIGURATION"
on page 79), and mode 100 of the ECP is compati-
ble with EPP mode.
4.5.19 PP Confg0 Register
Upon reset this register is initialized to 00h.
7
0
6
0
5
0
4
3
2
0
1
0
PP Confg0 Register
Second Level
Modes 000, 001 and 100 differ as follows:
0
0
0
0
Reset
000, 001 and 100 – Reading DCR returns pin values of
bits 3-0.
Offset 05h
Required
000 and 001 – Reading DCR returns 1 for bit 5.
000, or 001 or 100 when bit 5 of DCR is 0 (forward di-
rection) – Reading DATAR returns register latched
value instead of pin values.
ECP DMA Channel Number
PE Internal Pull-up or Pull-down
000, 001, and 100, when bit 4 of DCR is 0 – IRQx is
floated.
ECP IRQ Number
Demand DMA Enable
Bit 3 of CNFGA
001 – IRQx is a level interrupt generated on the trailing
edge of ACK. Bit 2 of the DSR is the IRQ status bit
(same behavior as bit 2 of the STR).
4.5.18 Control4 Register
Bits 1, 0 - ECP DMA Channel Number
Upon reset this register is initialized to 00000111.
These bits identify the ECP DMA channel number, as
reflected on bits 1 and 0 of the ECP CNFGB register.
See Section 4.5.11 "Configuration Register B (CNFGB)"
on page 91. Actual ECP DMA routing is controlled by
the DMA channel select register (index 74h) of this log-
ical device.
This register enables control of the fairness mechanism of
the DMA by programming the maximum number of bus cy-
cles that the parallel port DMA request signals can remain
active, and the minimum number of clock cycles that they
will remain inactive after they were deactivated.
Microsoft’s ECP protocol and ISA interface standard de-
fine bits 1 and 0 of CNFGB as shown in TABLE 4-7
"ECP Mode DMA Selection" on page 91.
7
0
6
0
5
0
4
3
2
1
1
0
Control4 Register
Second Level
Offset 04h
0
0
1
1
Reset
Required
Bit 2 - Paper End (PE) Internal Pull-up or Pull-down Resistor
Select
0: PE has a nominal 25 KΩ internal pull-down resis-
tor.
PP DMA Request
Active Time
1: PE has a nominal 25 KΩ internal pull-up resistor.
Reserved
Bits 5- 3 - ECP IRQ Number
These bits identify the ECP IRQ number, as reflected on
bits 5 through 3 of the ECP CNFGB register. See Sec-
tion 4.5.11 "Configuration Register B (CNFGB)" on
page 91. Actual ECP IRQ routing is controlled by inter-
rupt select register (index 70h) of this logical device.
PP DMA Request Inactive Time
Reserved
Bits 2- 0 - Parallel Port DMA Request Active Time
Microsoft’s ECP protocol and ISA interface standard de-
fines bits 5 through 3 of CNFGB, as shown in TABLE
4-8 "ECP Mode Interrupt Selection" on page 91.
This field specifies the maximum number of consecutive
bus cycles that the parallel port DMA signals can remain
active.
The default value is 111, which specifies 32 cycles.
When these bits are 0, the number is 1 cycle.
Bit 6 - Demand DMA Enable
If enabled, DRQ is asserted when a FIFO threshold of 4
is reached or when flush-time-out expires, except when
DMA fairness prevents DRQ assertion. The threshold of
4 is for four empty entries forward and for four valid en-
tries backward.
Otherwise, the number is 4(n+1) where n is the value of
these bits.
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Parallel Port (Logical Device 1)
Once DRQ is asserted, it is held asserted for four DMA
Forward Direction (Bit 5 of DCR = 0)
transfers, as long as the FIFO is able to process these
four transfers, i.e., FIFO not empty backward.
When the ECP is in forward direction and the FIFO is not full
(bit 1 of ECR is 0) the FIFO can be filled by software writes
to the FIFO registers (AFIFO and DFIFO in mode 011, and
CFIFO in mode 010).
When these four transfers are done, the DRQ behaves
as follows:
— If DMA fairness prevents DRQ assertion (as in the
case of 32 consecutive DMA transfers) then DRQ
becomes low.
When DMA is enabled (bit 3 of ECR is 1 and bit 2 of ECR is
0) the ECP automatically issues DMA requests to fill the
FIFO with data bytes (not including command bytes).
— If the FIFO is not able to process another four trans-
When the ECP is in forward direction and the FIFO is not
empty (bit 0 of ECR is 0) the ECP pops a byte from the FIFO
and issues a write signal to the peripheral device. The ECP
drives AFD according to the operation mode (bits 7-5 of
ECR) and according to the tag of the popped byte as fol-
lows:
fers (below threshold), then DRQ is becomes low.
— If the FIFO is able to process another four transfers
(still above the threshold and no fairness to prevent
DRQ assertion), then DRQ is held asserted as de-
tailed above.
The flush time-out is an 8-bit counter that counts 256
clocks of 24 MHz and triggers DRQ assertion when the
terminal-count is reached, i.e., when flush time-out ex-
pires). The counter is enabled for counting backward
when the peripheral state machine writes a byte and
DRQ is not asserted. Once enabled, it counts the 24
MHz clocks. The counter is reset and disabled when
DRQ is asserted. The counter is also reset and disabled
for counting forward and when demand the DMA is dis-
abled.
●
In Parallel Port FIFO mode (mode 010) AFD is con-
trolled by bit 1 of DCR.
●
In ECP mode (mode 011) AFD is controlled by the
popped tag. AFD is driven high for normal data bytes
and driven low for command bytes.
ECP (Forward) Write Cycle
An ECP write cycle starts when the ECP drives the popped
tag onto AFD and the popped byte onto PD7-0. When
BUSY is low the ECP asserts STB. In 010 mode the ECP
deactivates STB to terminate the write cycle. In 011 mode
the ECP waits for BUSY to be high.
This mechanism is reset whenever ECP mode is
changed, the same way the FIFO is flushed in this case.
0: Disabled.
1: Enabled.
When BUSY is high, the ECP deactivates STB, and chang-
es AFD and PD7-0 only after BUSY is low.
Bit 7 - Bit 3 of CNFGA
This bit may be utilized by the user. The value of this bit
is reflected on bit 3 of the ECP CNFGA register.
4.6 DETAILED ECP MODE DESCRIPTIONS
TABLE 4-11 "ECP Modes" on page 96 summarizes the func-
tionality of the ECP in each mode. The following Sections de-
scribe how the ECP functions in each mode, in detail.
4.6.1
Software Controlled Data Transfer (Modes 000
and 001)
Software controlled data transfer is supported in modes 000
and 001. The software generates peripheral-device cycles
by modifying the DATAR and DCR registers and reading
the DSR, DCR and DATAR registers. The negotiation
phase and nibble mode transfer, as defined in the IEEE
1284 standard, are performed in these modes.
In these modes the FIFO is reset (empty) and is not func-
tional, the DMA and RLE are idle.
Mode 000 is for the forward direction only; the direction bit
(bit 5 of DCR) is forced to 0 and PD7-0 are driven. Mode 001
is for both the forward and backward directions. The direc-
tion bit controls whether or not pins PD7-0 are driven.
4.6.2
Automatic Data Transfer (Modes 010 and 011)
Automatic data transfer (ECP cycles generated by hard-
ware) is supported only in modes 010 and 011 (Parallel Port
and ECP FIFO modes). Automatic DMA access to fill or
empty the FIFO is supported in modes 010, 011 and 110.
Mode 010 is for the forward direction only; the direction bit
is forced to 0 and PD7-0 are driven. Mode 011 is for both
the forward and backward directions. The direction bit con-
trols whether PD7-0 are driven.
Automatic Run Length Expanding (RLE) is supported in the
backward direction.
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Parallel Port (Logical Device 1)
TABLE 4-11. ECP Modes
ECP Mode
(ECR Bits)
ECP Mode
Name
Operation Description
7
6
5
0
0
0
Standard Write cycles are under software control.
STB, AFD, INIT and SLIN are open-drain output signals.
Bit 5 of DCR is forced to 0 (forward direction) and PD7-0 are driven.
The FIFO is reset (empty).
Reading DATAR returns the last value written to DATAR.
0
0
0
0
1
1
1
0
1
PS/2
Read and write cycles are under software control.
The FIFO is reset (empty).
STB, AFD, INIT and SLIN are push-pull output signals.
Parallel Port Write cycles are automatic, i.e., under hardware control (STB is controlled by hardware).
FIFO
Bit 5 of DCR is forced to 0 internally (forward direction) and PD7-0 are driven.
STB, AFD, INIT and SLIN are push-pull output signals.
ECP FIFO The FIFO direction is automatic, i.e., controlled by bit 5 of DCR.
Read and write cycles to the device are controlled by hardware (STB and AFD are
controlled by hardware).
STB, AFD, INIT and SLIN are push-pull output signals.
1
0
0
EPP
EPP mode is enabled by bits 7 through 5 of the SuperI/O Parallel Port Configuration
register, as described in Section 2.6.
In this mode, registers DATAR, DSR, and DCR are used as registers at offsets 00h, 01h and
02h of the EPP instead of registers DTR, STR, and CTR.
STB, AFD, INIT, and SLIN are push-pull output buffers.
When there is no access to one of the EPP registers (ADDR, DATA0, DATA1, DATA2 or
DATA3), mode 100 behaves like mode 001, i.e., software can perform read and write cycles.
The software should check that bit 7 of the DSR is 1 before reading or writing the DATAR
register, to avoid corrupting an ongoing EPP cycle.
1
1
0
1
1
0
Reserved
FIFO Test The FIFO is accessible via the TFIFO register.
The ECP does not issue ECP cycles to fill or empty the FIFO.
1
1
1
Configuration CNFGA and CNFGB registers are accessible.
data byte, regardless of its BUSY state (even if it is low).
This byte is pushed into the FIFO (RLC+1) times (e.g. for
RLC=0, push the byte once. For RLC=127 push the byte
128 times).
AFD
PD7-0
When the ECP is in the backward direction, and the FIFO is
not empty (bit 0 of ECR is 0), the FIFO can be emptied by
software reads from the FIFO register (true only for the
TFIFO in mode 011, not for AFIFO or CFIFO reads).
STB
BUSY
When DMA is enabled (bit 3 of ECR is 1 and bit 2 of ECR is
0) the ECP automatically issues DMA requests to empty the
FIFO (only in mode 011).
FIGURE 4-5. ECP Forward Write Cycle
ECP (Backward) Read Cycle
Backward Direction (Bit 5 of DCR is 1)
An ECP read cycle starts when the ECP drives AFD low.
When the ECP is in the backward direction, and the FIFO is
not full (bit 1 of ECR is 0), the ECP issues a read cycle to
the peripheral device and monitors the BUSY signal. If
BUSY is high the byte is a data byte and it is pushed into the
FIFO. If BUSY is low the byte is a command byte.
The peripheral device drives BUSY high for a normal data
read cycle, or drives BUSY low for a command read cycle,
and drives the byte to be read onto PD7-0.
When ACK is asserted the ECP drives AFD high. When
AFD is high the peripheral device deasserts ACK. The ECP
reads the PD7-0 byte, then drives AFD low. When AFD is
low the peripheral device may change BUSY and PD7-0
states in preparation for the next cycle
The ECP checks bit 7 of the command byte. If it is high the
byte is ignored, if it is low the byte is tagged as an RLC byte
(not pushed into the FIFO but used as a Run Length Count
to expand the next byte read). Following an RLC read the
ECP issues a read cycle from the peripheral device to read
the data byte to be expanded. This byte is considered a
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Parallel Port (Logical Device 1)
In the forward direction PD7-0 are driven, but the data is un-
.
defined. This mode can be used to measure the system-
ECP cycle throughput, usually with DMA cycles. This mode
can also be used to check the FIFO depth and its interrupt
threshold, usually with PIO cycles.
PD7-0
BUSY
AFD
ACK
4.6.5
Configuration Registers Access (Mode 111)
The two configuration registers, CNFGA and CNFGB, are
accessible only in this mode.
FIGURE 4-6. ECP (Backward) Read Cycle
Notes:
4.6.6
Interrupt Generation
An interrupt is generated when any of the events described
in this section occurs. Interrupt events 2, 3 and 4 are level
events. They are shaped as interrupt pulses, and are
masked (inactive) when the ECP clock is frozen.
1. FIFO-full condition is checked before every expanded
byte push.
2. Switching from modes 010 or 011 to other modes re-
moves pending DMA requests and aborts pending RLE
expansion.
Event 1
Bit 2 of ECR is 0, bit 3 of ECR is 1 and TC is asserted
during ECP DMA cycle. Interrupt event 1 is a pulse
event.
3. FIFO pushes and pops are neither synchronized nor
linked at the hardware level. The FIFO will not delay
these operations, even if performed concurrently. Care
must be taken by the programmer to utilize the empty
and full FIFO status bits to avoid corrupting PD7-0 or
D7-0 while a previous FIFO port access not complete.
Event 2
Bit 2 of ECR is 0, bit 3 of ECR is 0, bit 5 of DCR is 0 and
there are eight or more bytes free in the FIFO.
This event includes the case when bit 2 of ECR is
cleared to 0 and there are already eight or more bytes
free in the FIFO (modes 010, 011 and 110 only).
4. In the forward direction, the empty bit is updated when
the ECP cycle is completed, not when the last byte is
popped from the FIFO (valid cleared on cycle end).
Event 3
5. The one-bit command/data tag is used only in the for-
ward direction.
Bit 2 of ECR is 0, bit 3 of ECR is 0, bit 5 of DCR is 1 and
there are eight or more bytes to be read from the FIFO.
4.6.3
Automatic Address and Data Transfers
(Mode 100)
This event includes the case when bit 2 of ECR is
cleared to 0 and there are already eight or more bytes
to be read from the FIFO (modes 011 and 110 only).
Automatic address and data transfer (EPP cycles generat-
ed by hardware) is supported in mode 100. Fast transfers
are achieved by automatically generating the address and
data strobes.
Event 4
Bit 4 of ECR is 0 and ERR is asserted (high to low edge)
or ERR is asserted when bit 4 of ECR is modified from
1 to 0.
In this mode, the FIFO is reset (empty) and is not functional,
the DMA and RLE are idle.
This event may be lost when the ECP clock is frozen.
The direction of the automatic data transfers is determined
by the RD and WR signals. The direction of software data
transfer can be forward or backward, depending on bit 5 of
the DCR. Bit 5 of the DCR determines the default direction
of the data transfers only when there is no on-going EPP cy-
cles.
Event 5
When bit 4 of DCR is 1 and ACK is deasserted (low-to-
high edge).
This event behaves as in the normal SPP mode, i.e., the
IRQ signal follows the ACK signal transition.
In EPP mode 100, registers DATAR, DSR and DCR are
used instead of DTR, STR and CTR respectively.
Some differences are caused by the registers. Reading DA-
TAR returns pins values instead of register value returned
when reading DTR. Reading DSR returns register value in-
stead of pins values returned when reading STR. Writing to
the DATAR during an on-going EPP 1.9 forward cycle (i.e.
- when bit 7 of DSR is 1) causes the new data to appear im-
mediately on PD7-0, instead of waiting for BUSY to become
low to switch PD7-0 to the new data when writing to the
DTR.
In addition, the bit 4 of the DCR functions differently relative
to bit 4 of the CTR (IRQ float).
4.6.4
FIFO Test Access (Mode 110)
Mode 110 is for testing the FIFO in PIO and DMA cycles.
Both read and write operations (pop and push) are support-
ed, regardless of the direction bit.
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Parallel Port (Logical Device 1)
4.7 PARALLEL PORT REGISTER BITMAPS
4.7.1
EPP Modes
7
0
6
0
5
0
4
3
2
0
1
0
EPP Data
Register 0
Offset 04h
0
0
0
0
Reset
7
0
6
0
5
0
4
3
2
0
1
0
SPP or EPP Data
Register (DTR)
Offset 00h
Required
0
0
0
0
Reset
Required
D0
D1
D0
D2
D1
D3
D2
D4
EPP Device
Read or Write Data
D3
D5
D4
D6
D5
D7
Data Bits
D6
D7
7
6
0
5
0
4
0
3
0
2
0
1
0
EPP Data
Register 1
Offset 05h
7
1
6
1
5
1
4
1
3
1
2
1
1
0
SPP or EPP Status
Register(STR)
Offset 01h
0
0
0
Reset
1
1
Reset
Required
Required
D8
Time-Out Status
D9
Reserved
IRQ Status
ERR Status
SLCT Status
PE Status
ACK Status
Printer Status
D10
D11
D12
D13
D14
EPP Device
Read or Write Data
D15
7
0
6
0
5
0
4
3
2
0
1
0
EPP Data
Register 2
Offset 06h
7
1
6
1
5
0
4
3
2
0
1
0
SPP or EPP Control
Register (CTR)
0
0
0
0
Reset
0
0
0
0
Reset
Offset 02h
Required
Required
D16
Data Strobe Control
Automatic Line Feed Control
Printer Initialization Control
Parallel Port Input Control
Interrupt Enable
Direction Control
Reserved
Reserved
D17
D18
D19
D20
D21
D22
EPP Device
Read or Write Data
D23
7
0
6
0
5
0
4
3
2
0
1
0
7
0
6
0
5
0
4
3
2
0
1
0
EPP Address
Register
EPP Data
Register 3
Offset 07h
0
0
0
0
Reset
0
0
0
0
Reset
Offset 03h
Required
Required
A0
D24
A1
D25
D26
D27
D28
D29
D30
D31
A2
A3
A4
EPP Device or
Register Selection
Address Bits
A5
EPP Device
Read or Write Data
A6
A7
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Parallel Port (Logical Device 1)
4.7.2
ECP Modes
Bits 7-5 of ECR = 010
Bits 7-5 of ECR = 000 or 001
7
0
6
0
5
0
4
3
2
0
1
0
Parallel Port FIFO
Register (CFIFO)
Offset 400h
7
0
6
0
5
0
4
3
2
1
0
ECP Data Register
(DATAR)
0
0
0
0
Reset
0
0
0
0
0
Reset
Offset 000h
Required
Required
D0
D0
D1
D1
D2
D2
D3
D3
D4
D4
Data Bits
D5
Data Bits
D5
D6
D6
D7
D7
Bits 7-5 of ECR = 011
Bits 7-5 of ECR = 011
7
0
6
0
5
0
4
0
3
2
1
0
ECP Data FIFO
Register (DFIFO)
Offset 400h
7
0
6
0
5
0
4
3
2
0
1
0
ECP Address Register
(AFIFO)
0
0
0
0
Reset
0
0
0
0
Reset
Offset 000h
Required
Required
D0
A0
D1
A1
D2
A2
D3
A3
D4
A4
Data Bits
D5
Address Bits
A5
D6
A6
D7
A7
Bits 7-5 of ECR = 110
7
6
5
4
3
2
1
1
0
ECP Status Register
(DSR)
7
0
6
0
5
0
4
0
3
2
0
1
0
Test FIFO
Register (TFIFO)
Offset 400h
1
1
Reset
0
0
0
Reset
Offset 001h
Required
Required
EPP Time-Out Status
Reserved
Reserved
ERR Status
SLCT Status
PE Status
ACK Status
Printer Status
D0
D1
D2
D3
D4
Data Bits
D5
D6
D7
Bits 7-5 of ECR = 111
7
1
6
1
5
0
4
3
2
0
1
0
ECP Control
Register (DCR)
Offset 002h
7
0
6
0
5
0
4
1
3
2
1
1
0
Configuration Register A
0
Reset
0
0
0
0
Reset
(CNFGA)
Offset 400h
0
0
Required
0
0
0
1
1
0
0
Required
Data Strobe Control
Automatic Line Feed Control
Printer Initialization Control
Parallel Port Input Control
Interrupt Enable
Direction Control
Reserved
Reserved
Always 0
Always 0
Always 1
Bit 7 of PP Confg0
Always 1
Always 0
Always 0
Always 0
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99
Parallel Port (Logical Device 1)
Bits 7-5 of ECR = 111
ECP Extended Auxiliary
Status Register (EAR)
7
0
6
0
5
0
4
3
2
0
1
0
7
0
6
0
5
0
4
3
2
0
1
0
Configuration Register B
0
Reset
0
0
0
0
Reset
Offset 405h
(CNFGB)
Offset 401h
0
0
0
Required
Required
DMA Channel Select
Reserved
Reserved
Interrupt Select
IRQ Signal Value
Reserved
FIFO Tag
7
0
6
0
5
0
4
3
2
0
1
0
Control0 Register
Second Level
Offset 00h
7
0
6
0
5
0
4
3
2
1
0
Extended Control
Register(ECR)
Offset 402h
0
0
0
0
Reset
1
0
1
Reset
Required
Required
EPP Time-Out
Interrupt Mask
FIFO Empty
Reserved
Reserved
Reserved
Freeze Bit
DCR Register Live
FIFO Full
ECP Interrupt Service
ECP DMA Enable
ECP Interrupt Mask
ECP Mode Control
Reserved
7
0
6
0
5
0
4
3
2
0
1
0
7
0
6
0
5
0
4
3
2
0
1
0
ECP Extended Index
Register (EIR)
Control2 Register
Second Level
Offset 02h
0
0
0
0
Reset
0
0
0
0
Reset
Offset 403h
Required
Required
Reserved
Reserved
Reserved
Reserved
Revision 1.7 or 1.9 Select
Reserved
Channel Address Enable
SPP Compatability
Second Level Offset
Reserved
Reserved
Reserved
Reserved
Reserved
ECP Extended Data
Register (EDR)
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
0
Reset
Offset 404h
Required
D0
D1
D2
D3
D4
Data Bits
D5
D6
D7
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100
Parallel Port (Logical Device 1)
4.8 PARALLEL PORT PIN/SIGNAL LIST
TABLE 4-12 shows the standard 25-pin, D-type connector definition for parallel port operations.
TABLE 4-12. Parallel Port Pin Out
Connector
Pin
SPP, ECP
Mode
Pin No.
I/O EPP Mode I/O
1
2
67
75
76
77
78
79
80
81
82
68
66
70
69
74
71
72
73
STB
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
ACK
BUSY
PE
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
WRITE
PD0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
3
PD1
4
PD2
5
PD3
6
PD4
7
PD5
8
PD6
9
PD7
10
11
12
13
14
15
16
17
18 - 23
25
ACK
I
WAIT
PE
I
I
I
SLCT
AFD
ERR
INIT
SLIN
GND
GND
I
SLCT
DSTRB
ERR
INIT
I
I/O
I
I/O
I
I/O
I/O
I/O
I/O
ASTRB
GND
GND
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101
Enhanced Serial Port with IR -UART2 (Logical Device 2)
5.2 FUNCTIONAL MODES OVERVIEW
5.0 Enhanced Serial Port with IR -
UART2 (Logical Device 2)
This multi-mode module can be configured to act as any
one of several different functions. Although each mode is
unique, certain system resources and features are common
to some or to all modes.
This module provides advanced, versatile serial communi-
cations features with infrared capabilities. It supports four
modes of operation: UART, Sharp-IR, IrDA 1.0 SIR (hereaf-
ter called SIR) and Consumer-IR (also called TV-Remote or
Consumer remote-control). In UART mode, the module can
function as a standard 16450 or 16550, or as an Extended
UART.
5.2.1
UART Modes: 16450 or 16550, and Extended
UART modes support serial data communications with a re-
mote peripheral device or modem using a wired interface.
The device transmits and receives data concurrently in full-
duplex operation, performing parallel-to-serial and serial-to-
parallel conversion and other functions required to ex-
change parallel data with the system. It also interfaces with
external devices using a programmable serial communica-
tions format.
Existing 16550-based legacy software is completely and
transparently supported. Module organization and specific
fallback mechanisms switch the module to 16550 compati-
bility mode upon reset or when initialized by 16550 soft-
ware.
The following UART modes are supported:
You can configure this module for either partial or full infra-
red communication support, as follows:
●
16450 or 16550 mode (Non-Extended modes)
l Mode 1: Full-IR Mode (CFG0 = 0)
●
Extended mode
Fully IR-compliant device only. All the UART compli-
ance pins of UART2 are not available (i.e. the outputs
are not routed and the inputs are assumed inactive).
Any attempt to work with the port as a UART in this
mode has no effect.
The 16450 or 16550 mode is functionally and software-
compatible with the standard 16450 or 16550 UARTs. This
is the default mode of operation after power up, after reset
or when initialized by software written for the 16450 or
16550 UART (Special mechanisms switch the module auto-
matically to 16550 UART mode when standard 16550 soft-
ware is run).
l Mode 2: Two-UART Mode (CFG0 = 1)
Works as UART or as partially IR-compliant device. The
IR interface includes only two signals, IRTX and IRRX1.
The IRSL2-0 pins and ID3-0 inputs are not available in
this mode. Any attempt to work with IRRX2 and/or to
manipulate IRSL2-0 in this mode has no effect.
The 16550 UART mode has all the features of the 16450
mode, with the addition of 16-byte data FIFOs for more effi-
cient data I/O.
In Extended mode, additional features become available
that enhance the UART performance, such as additional in-
terrupts and DMA ability (see “Extended UART Mode” on
page 104).
This module does not recognize the operation mode, and
there is no hardware protection against invalid usage or
configuration. The software must therefore avoid any invalid
operation of the UART2 in either one of these two modes.
The UART supports baud rates of up to 115.2 Kbps in 16450
or 16550 mode, and up to 1.5 Mbps in Extended mode.
This module includes two DMA channels; the device can
use either 1 or 2 of these channels. One channel is required
for infrared-based applications, since infrared communica-
tion works in half duplex fashion. Two channels would nor-
mally be needed to handle high-speed full duplex UART
based applications.
5.2.2
Sharp-IR, IrDA SIR Infrared Modes
The Sharp-IR mode provides bidirectional communication
by transmitting and receiving infrared radiation. In this
mode, infrared I/O circuits was added to the UART, which
operates at 38.4 Kbps in half-duplex, using normal UART
serial data formats with Digital Amplitude Shift Keying
(DASK) modulation. The modulation/demodulation can be
operated internally or externally.
5.1 FEATURES
●
Fully compatible with 16550 and 16450 devices
●
Automatic fallback to 16550 compatibility mode
●
In SIR mode, the system functions similarly to the Sharp-IR
mode, but at 115.2 Kbps.
Extended UART mode
●
UART baud rates up to 1.5 Mbps
5.2.3
Consumer IR Mode
●
Sharp-IR with selectable internal or external modula-
tion/demodulation
Consumer-IR mode supports all the protocols presently
used in remote-controlled home entertainment equipment:
RC-5, RC-6, RECS 80, NEC and RCA. The serial format is
not compatible with UART operation, and specific circuitry
performs all the hardware tasks required for signal condi-
tioning and formatting. The software is responsible for the
generation of the infrared code to be transmitted, and for the
interpretation of the received code.
●
IrDA 1.0 SIR with data rates up to 115.2 Kbps
●
Consumer-IR (TV-Remote) mode
●
Full duplex infrared capability for diagnostics
●
Transmission deferral (in Consumer-IR mode)
●
Selectable 16-level transmission and reception FIFOs
5.3 REGISTER BANK OVERVIEW
(RX_FIFO & TX_FIFO respectively)
●
Eight register banks, each containing eight registers, con-
trol UART operation. All registers use the same 8-byte ad-
dress space to indicate offsets 00h through 07h, and the
active bank must be selected by the software.
Multiple optical transceiver support
●
Automatic or manual transceiver configuration
●
Support for Plug-n-Play infrared adapters
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102
Enhanced Serial Port with IR -UART2 (Logical Device 2)
The register bank organization enables access to the banks
TABLE 5-1. Register Bank Summary
IR
as required for activation of all module modes, while main-
taining transparent compatibility with 16450 or 16550 soft-
ware, which activates only the registers and specific bits
used in those devices. For details, See Section 5.4.
Bank UART
Main Functions
Mode
0
1
2
Global Control and Status
Legacy Bank
✓
✓
✓
✓
The Bank Selection Register (BSR) selects the active bank
and is common to all banks. See Figure 5-1. Therefore,
each bank defines seven new registers.
✓
Baud Generator Divisor,
Extended Control and Status
✓
3
Module Revision ID and
Shadow Registers
BANK 7
BANK 6
✓
✓
4
5
6
IR mode setup
Infrared Control
✓
✓
✓
BANK 5
BANK 4
BANK 3
BANK 2
Infrared Physical Layer
Configuration
BANK 1
7
Consumer-IR and Optical
Transceiver Configuration
✓
BANK 0
Offset 07h
Offset 06h
Offset 05h
Offset 04h
Banks 0 and 1 are the 16550 register banks. The registers
in these banks are equivalent to the registers contained
in the 16550 UARTs and are accessed by 16550 soft-
ware drivers as if the module was a 16550. Bank 1 con-
tains the legacy Baud Generator Divisor Ports. Bank 0
registers control all other aspects of the UART function,
including data transfers, format setup parameters, inter-
rupt setup and status monitoring.
LCR/BSR
Common
Register
Throughout
All Banks
Bank 2 contains the non-legacy Baud Generator Divisor
Ports, and controls the extended features special to this
UART, that are not included in the 16550 repertoire.
These include DMA usage. See ”Extended UART
Mode” on page 104.
Offset 02h
Offset 01h
Offset 00h
Bank 3 contains the Module Revision ID and shadow regis-
ters. The Module Revision ID (MRID) register contains
a code that identifies the revision of the module when
read by software. The shadow registers contain the
identical content as reset-when-read registers within
bank 0. Reading their contents from the shadow regis-
ters lets the system read the register content without re-
setting them.
16550 Banks
FIGURE 5-1. Register Bank Architecture
The default bank selection after system reset is 0, which
places the module in the UART 16550 mode. Additionally,
setting the baud in bank 1 (as required to initialize the 16550
UART) switches the module to a Non-Extended UART
mode. This ensures that running existing 16550 software
will switch the system to the 16550 configuration without
software modification.
Bank 4 contains setup parameters for the Infra-red modes.
Bank 5 registers control infrared parameters related to the
logical system I/O parameters.
Table 5-1 shows the main functions of the registers in each
bank. Banks 0-3 control both UART and infrared modes of
operation; banks 4-7 control and configure the infrared
modes only.
Bank 6 registers control physical characteristics involved
in infrared communications (e.g. pulse width selection).
Bank 7 registers are dedicated to Consumer-IR configura-
tion and control.
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103
Enhanced Serial Port with IR -UART2 (Logical Device 2)
5.4 UART MODES – DETAILED DESCRIPTION
The system can monitor this module status at any time. Sta-
tus information includes the type and condition of the trans-
fer operation in process, as well as any error conditions
(e.g., parity, overrun, framing, or break interrupt).
The UART modes support serial data communications with a
remote peripheral device or modem using a wired interface.
The module provides receive and transmit channels that
can operate concurrently in full-duplex mode. This module
performs all functions required to conduct parallel data in-
terchange with the system and composite serial data ex-
change with the external data channel, including:
The module resources include modem control capability
and a prioritized interrupt system. Interrupts can be pro-
grammed to match system requirements, minimizing the
CPU overhead required to handle the communications link.
●
Format conversion between the internal parallel data
Programmable Baud Generator
format and the external programmable composite seri-
al format. See Figure 5-2.
This module contains a programmable Baud Generator that
generates the clock rates for serial data communication
(both transmit and receive channels). It divides its input
clock by any divisor value from 1 to 216 - 1. The output clock
frequency of the Baud Generator must be programmed to
be sixteen times the baud value. A 24 MHz input frequency
is divided by a prescale value (PRESL field of EXCR2 - see
page 121. Its default value is 13) and by a 16-bit program-
mable divisor value contained in the Baud Generator Divi-
sor High and Low registers (BGD(H) and BGD(L) - see page
119). Each divisor value yields a clock signal (BOUT) and a
further division by 16 produces the baud clock for the serial
data stream. It may also be output as a test signal when en-
abled (see bit 7 of EXCR1 on page 120.)
●
Serial data timing generation and recognition
●
Parallel data interchange with the system using a
choice of bi-directional data transfer mechanisms
●
Status monitoring for all phases of the communica-
tions activity
The module supplies modem control registers, and a prior-
itized interrupt system for efficient interrupt handling.
5.4.1
16450 or 16550 UART Mode
The module defaults to 16450 mode after power up or reset.
UART 16550 mode is equivalent to 16450 mode, with the
addition of a 16-byte data FIFO for more efficient data I/O.
Transparent compatibility is maintained with this UART
mode in this module.
These user-selectable parameters enable the user to gen-
erate a large choice of serial data rates, including all stan-
dard baud rates. A list of baud rates and their settings
appears in Table 5-14 on page 119.
Despite the many additions to the basic UART hardware
and organization, the UART responds correctly to existing
software drivers with no software modification required.
When 16450 software initializes and addresses this mod-
ule, it will in always perform as a 16450 device.
Module Operation
Before module operation can begin, both the communica-
tions format and baud must be programmed by the soft-
ware. The communications format is programmed by
loading a control byte into the LCR register, while the baud
is selected by loading an appropriate value into the Baud
Generator Divisor Registers and the divisor preselect val-
ues (PRESL) into EXCR2 (see page 121).
Data transfer takes place by use of data buffers that inter-
face internally in parallel and with the external data channel
in a serial format. 16-byte data FIFOs may reduce host
overhead by enabling multiple-byte data transfers within a
single interrupt. With FIFOs disabled, this module is equiv-
alent to the standard 16450 UART. With FIFOs enabled, the
hardware functions as a standard 16550 UART.
The software can read the status of the module at any time
during operation. The status information includes full or
empty state for both transmission and reception channels,
and any other condition detected on the received data
stream, like parity error, framing error, data overrun, or
break event.
The composite serial data stream interfaces with the data
channel through signal conditioning circuitry such as
TTL/RS232 converters, modem tone generators, etc.
Data transfer is accompanied by software-generated con-
trol signals, which may be utilized to activate the communi-
cations channel and “handshake” with the remote device.
These may be supplied directly by the UART, or generated
by control interface circuits such as telephone dialing and
answering circuits, etc.
5.4.2
Extended UART Mode
In Extended UART mode of operation, the module configu-
ration changes and additional features become available
which enhance UART capabilities.
●
The interrupt sources are no longer prioritized; they
are presented bit-by-bit in the EIR (see page 110).
●
START
-LSB- DATA 5-8 -MSB-
PARITY
STOP
An auxiliary status and control register replaces the
scratchpad register. It contains additional status and
control flag bits (“Auxiliary Status and Control Register
(ASCR)” on page 117).
FIGURE 5-2. Composite Serial Data
●
The composite serial data stream produced by the UART is
illustrated in Figure 5-2. A data word containing five to eight
bits is preceded by start bits and followed by an optional
parity bit and a stop bit. The data is clocked out, LSB first,
at a predetermined rate (the baud).
The TX_FIFO can generate interrupts when the number
of outgoing bytes in the TX_FIFO drops below a program-
mable threshold. In the Non-Extended UART modes, only
reception FIFOs have the thresholding feature.
●
DMA capability is available.
The data word length, parity bit option, number of start bits
and baud are programmable parameters.
●
Interrupts occur when the transmitter becomes empty
or a DMA event occurs.
The UART includes a programmable Baud Generator that
produces the baud clocks and associated timing signals for
serial communication.
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104
Enhanced Serial Port with IR -UART2 (Logical Device 2)
5.5 SHARP-IR MODE – DETAILED DESCRIPTION
5.7 CONSUMER-IR MODE – DETAILED
DESCRIPTION
This mode supports bidirectional data communication with
a remote device using infrared radiation as the transmission
medium. Sharp-IR uses Digital Amplitude Shift Keying
(DASK) and allows serial communication at baud rates up
to 38.4 Kbaud. The format of the serial data is similar to the
UART data format. Each data word is sent serially begin-
ning with a zero value start bit, followed by up to eight data
bits (LSB first), an optional parity bit, and ending with at
least one stop bit with a binary value of one. A logical zero
is signalled by sending a 500 KHz continuous pulse train of
infrared radiation. A logical 1 is signalled by the absence of
any infrared signal. This module can perform the modula-
tion and demodulation operations internally, or can rely on
the external optical module to perform them.
The Consumer-IR circuitry in this module is designed to op-
timally support all the major protocols presently used in re-
mote-controlled home entertainment equipment: RC-5, RC-
6, RECS 80, NEC and RCA.
This module, in conjunction with an external optical device,
provides the physical layer functions necessary to support
these protocols. These functions include: modulation, de-
modulation, serialization, deserialization, data buffering,
status reporting, interrupt generation, etc.
The software is responsible for the generation of the infra-
red code to be transmitted, and for the interpretation of the
received code.
Sharp-IR device operation is similar to the operation in
UART mode, the main difference being that data transfer
operations are normally performed in half duplex fashion,
and the modem control and status signals are not used. Se-
lection of the Sharp-IR mode is controlled by the Mode Se-
lect (MDSL) bits in the MCR register when the module is in
Extended mode, or by the IR_SL bits in the IRCR1 register
when the module is not in extended mode. This prevents
legacy software, running in non-extended mode, from spu-
riously switching the module to UART mode, when the soft-
ware writes to the MCR register.
5.7.1
Consumer-IR Transmission
The code to be transmitted consists of a sequence of bytes
that represent either a bit string or a set of run-length codes.
The number of bits or run-length codes usually needed to
represent each infrared code bit depends on the infrared
protocol to be used. The RC-5 protocol, for example, needs
two bits or between one and two run-length codes to repre-
sent each infrared code bit.
Transmission is initiated when the CPU or DMA module
writes code bytes into the empty TX_FIFO. Transmission is
normally completed when the CPU sets the S_EOT bit in
the ASCR register (See Section 5.11.10 on page 117), be-
fore writing the last byte, or when the DMA controller acti-
vates the TC (terminal count) signal. Transmission will also
terminate if the CPU simply stops transferring data and the
transmitter becomes empty. In this case, however, a trans-
mitter-underrun condition will be generated, which must be
cleared in order to begin the next transmission.
5.6 SIR MODE – DETAILED DESCRIPTION
This operational mode supports bidirectional data commu-
nication with a remote device using infrared radiation as the
transmission medium.
SIR allows serial communication at baud rates up to
115.2 Kbuad. The serial data format is similar to the UART
data format. Each data word is sent serially beginning with
a 0 value start bit, followed by eight data bits (LSB first), an
optional parity bit, and ending with at least one stop bit with
a binary value of 1.
The transmission bytes are either de-serialized or run-
length encoded, and the resulting bit string modulates a car-
rier signal and is sent to the transmitter LED. The transfer
rate of this bit string, like in the UART mode, is determined
by the value programmed in the Baud Generator Divisor
Registers. Unlike a UART transmission, start, stop and par-
ity bits are not included in the transmitted data stream. A
logic 1 in the bit string keeps the LED off, so no infrared sig-
nal is transmitted. A logic 0, generates a sequence of mod-
ulating pulses which will turn on the transmitter LED.
Frequency and pulse width of the modulating pulses are
programmed by the MCFR and MCPW fields in the
IRTXMC register as well as the TXHSC bit in the RCCFG
register. Sections 5.18.2 and 5.18.3 describe these regis-
ters in detail.
A zero value is signalled by sending a single infrared pulse.
A one value is signalled by not sending any pulse. The width
of each pulse can be either 1.6 µsec or 3/16 of the time re-
quired to transmit a single bit. (1.6 µsec equals 3/16 of the
time required to transmit a single bit at 115.2 Kbps). This
way, each word begins with a pulse for the start bit.
The module operation in SIR is similar to the operation in
UART mode, the main difference being that data transfer
operations are normally performed in half duplex fashion.
Selection of the IrDA 1.0 SIR mode is controlled by the
MDSL bits in the MCR register when the UART is in Extend-
ed mode, or by the IR_SL bits in the IRCR1 register when
the UART is not in Extended mode. This prevents legacy
software, running in Non-Extended mode, from spuriously
switching the module to UART mode, when the software
writes to the MCR register.
The RC_MMD field selects the transmitter modulation
mode. If C_PLS mode is selected, modulating pulses are
generated continuously for the entire logic 0 bit time. If
6_PLS or 8_PLS mode is selected, six or eight pulses are
generated each time a logic 0 bit is transmitted following a
logic 1 bit. The total transmission time for the logic 0 bits
must be equal-to or greater-than 6 or 8 times the period of
the modulation subcarrier, otherwise, fewer pulses will be
transmitted.
C_PLS modulation mode is used for RC-5, RC-6, NEC and
RCA protocols. 8_PLS or 6_PLS modulation mode is used
for the RECS 80 protocol. The 8_PLS or 6_PLS mode al-
lows minimization of the number of bits needed to represent
the RECS 80 infrared code sequence. The current transmit-
ter implementation supports only the modulated modes of
the RECS 80 protocol. It does not support Flash mode.
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
5.7.2
Consumer-IR Reception
5.8 FIFO TIME-OUTS
The Consumer-IR receiver is significantly different from a
UART receiver in two ways. Firstly, the incoming infrared
signals are DASK modulated. Therefore, demodulation may
be necessary. Secondly, there are no start bits in the incom-
ing data stream.
Time-out mechanisms prevent received data from remain-
ing in the RX_FIFO indefinitely, if the programmed interrupt
or DMA thresholds are not reached.
An RX_FIFO time-out generates a Receiver Data Ready in-
terrupt and/or a receiver DMA request if bit 0 of IER and/or
bit 2 of MCR (in Extended mode) are set to 1 respectively.
An RX_FIFO time-out also sets bit 0 of ASCR to 1 if the
RX_FIFO is below the threshold. When a Receiver Data
Ready interrupt occurs, this bit is tested by the software to
determine whether a number of bytes indicated by the
RX_FIFO threshold can be read without checking bit 0 of
the LSR register.
Whenever an infrared signal is detected, receiver opera-
tions depend on whether or not receiver demodulation is en-
abled. If demodulation is disabled, the receiver immediately
becomes active. If demodulation is enabled, the receiver
checks the carrier frequency of the incoming signal, and be-
comes active only if the frequency is within the programmed
range. Otherwise, the signal is ignored and no other action
is taken.
The conditions that must exist for a time-out to occur in the
various modes of operation are described below.
When the receiver enters the active state, the RXACT bit in
the ASCR register is set to 1. Once in the active state, the
receiver keeps sampling the infrared input signal and gen-
erates a bit string where a logic 1 indicates an idle condition
and a logic 0 indicates the presence of infrared energy. The
infrared input is sampled regardless of the presence of in-
frared pulses at a rate determined by the value loaded into
the Baud Generator Divisor Registers. The received bit
string is either de-serialized and assembled into 8-bit char-
acters, or it is converted to run-length encoded values. The
resulting data bytes are then transferred into the RX_FIFO.
When a time-out has occurred, it can only be reset when the
FIFO is read by the CPU or DMA controller.
5.8.1
UART, SIR or Sharp-IR Mode Time-Out Conditions
Two timers (timer1 and timer 2) are used to generate two
different time-out events (A and B, respectively). Timer 1
times out after 64 µsec. Timer 2 times out after four charac-
ter times.
Time-out event A generates an interrupt and sets the
RXF_TOUT bit (bit 0 of ASCR) when all of the following are
true:
The receiver also sets the RXWDG bit in the ASCR register
each time an infrared pulse signal is detected. This bit is au-
tomatically cleared when the ASCR register is read, and it
is intended to assist the software in determining when the
infrared link has been idle for a certain time. The software
can then stop the data reception by writing a 1 into the RX-
ACT bit to clear it and return the receiver to the inactive
state.
●
At least one byte is in the RX_FIFO, and
●
More than 64 µsec or four character times, whichever is
greater, have elapsed since the last byte was loaded
into the RX_FIFO from the receiver logic, and
●
More than 64 µsec or four character times, whichever is
The frequency bandwidth for the incoming modulated infra-
red signal is selected by the DFR and DBW fields in the IR-
RXDC register.
greater, have elapsed since the last byte was read from
the RX_FIFO by the CPU or DMA controller.
Time-out event B activates the receiver DMA request and is
invisible to the software. It occurs when all of the following
are true:
There are two Consumer-IR reception data modes: “Over-
sampled” and “Programmed T Period” mode. For either
mode the sampling rate is determined by the setting of the
Baud Generator Divisor Registers.
●
At least one byte is in the RX_FIFO, and
The “Over-sampled” mode can be used with the receiver
demodulator either enabled or disabled. It should be used
with the demodulator disabled when a detailed snapshot of
the incoming signal is needed, for example to determine the
period of the carrier signal. If the demodulator is enabled,
the stream of samples can be used to reconstruct the in-
coming bit string. To obtain good resolution, a fairly high
sampling rate should be selected.
●
More than 64 µsec or four character times, whichever is
smaller, have elapsed since the last byte was loaded
into the RX_FIFO from the receiver logic, and
●
More than 64 µsec or four character times, whichever is
smaller, have elapsed since the last byte was read from
the RX_FIFO by the CPU or DMA controller.
5.8.2
Consumer-IR Mode Time-Out Conditions
The “Programmed-T-Period” mode should be used with the
receiver demodulator enabled. The T Period represents
one half bit time for protocols using biphase encoding, or
the basic unit of pulse distance for protocols using pulse dis-
tance encoding. The baud is usually programmed to match
the T Period. For long periods of logic low or high, the re-
ceiver samples the demodulated signal at the programmed
sampling rate.
The RX_FIFO time-out, in Consumer-IR mode, is disabled
while the receiver is active. It occurs when all of the follow-
ing are true:
●
At least one byte has been in the RX_FIFO for 64 µsec
or more, and
●
The receiver has been inactive (RXACT = 0) for 64 µsec
Whenever a new infrared energy pulse is detected, the re-
ceiver synchronizes the sampling process to the incoming
signal timing. This reduces timing related errors and elimi-
nates the possibility of missing short infrared pulse se-
quences, especially with the RECS 80 protocol.
or more, and
●
More than 64 µsec have elapsed since the last byte was
read from the RX_FIFO by the CPU or DMA controller.
In addition, the “Programmed-T-Period” sampling minimiz-
es the amount of data used to represent the incoming infra-
red signal, therefore reducing the processing overhead in
the host CPU.
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
5.8.3
Transmission Deferral
5.10 OPTICAL TRANSCEIVER INTERFACE
This feature allows software to send high-speed data in Pro-
grammed Input/Output (PIO) mode without the risk of gen-
erating a transmitter underrun.
This module implements a flexible interface for the external
infrared transceiver. Several signals are provided for this
purpose. A transceiver module with one or two reception
signals, or two transceiver modules can interface directly
with this module without any additional logic.
Transmission deferral is available only in Extended mode
and when the TX_FIFO is enabled. When transmission de-
ferral is enabled (TX_DFR bit in the MCR register set to 1)
and the transmitter becomes empty, an internal flag is set
and locks the transmitter. If the CPU now writes data into
the TX_FIFO, the transmitter does not start sending the
data until the TX_FIFO level reaches 14 at which time the
internal flag is cleared. The internal flag is also cleared and
the transmitter starts transmitting when a time-out condition
is reached. This prevents some bytes from being in the
TX_FIFO indefinitely if the threshold is not reached.
Since various operational modes are supported by this
module, the transmitter power as well as the receiver filter
in the transceiver module must be configured according to
the selected mode.
This module provides four interface pins to control the infra-
red transceiver. ID/IRSL(2-0) are three I/O pins and ID3 is
an Input pin. All of these pins are powered up as inputs.
When in input mode, they can be used to read the identifi-
cation data of Plug-n-Play infrared adapters.
The time-out mechanism is implemented by a timer that is
enabled when the internal flag is set and there is at least one
byte in the TX_FIFO. Whenever a byte is loaded into the
TX_FIFO the timer gets reloaded with the initial value. If no
bytes are loaded for a 64-µsec time, the timer times out and
the internal flag is cleared, thus enabling the transmitter.
When in output mode, the logic levels of IRSL(2-0) can be
either controlled directly by the software by setting bits 2-0
of the IRCFG1 register, or they can be automatically select-
ed by this module whenever the operation mode changes.
The automatic transceiver configuration is enabled by set-
ting the AMCFG bit (bit 7) in the IRCFG4 register to 1. It al-
lows the low-level functional details of the transceiver
module being used to be hidden from the software drivers.
5.9 AUTOMATIC FALLBACK TO A NON-EXTENDED
UART MODE
The automatic fallback feature supports existing legacy
software packages that use the 16550 UART by automati-
cally turning off any Extended mode features and switches
the UART to Non-Extended mode when either of the LB-
GD(L) or LBGD(H) ports in bank 1 is read from or written to
by the CPU.
The operation mode settings for the automatic configuration
are determined by various bit fields in the Infrared Interface
Configuration registers (IRCFG[4-1]) that must be pro-
grammed when the UART is initialized.
The ID0/IRSL0/IRRX2 pin can also be used as an input to
support an additional infrared reception signal. In this case,
however, only two configuration pins are available.
This eliminates the need for user intervention prior to run-
ning a legacy program.
The IRSL0_DS and IRSL21_DS bits in the IRCFG4 register
determines the direction of IRSL(2-0).
In order to avoid spurious fallbacks, alternate baud registers
are provided in bank 2. Any program designed to take ad-
vantage of the UART’s extended features, should not use
LBGD(L) and LBGD(H) to change the baud. It should use
the BGD(L) and BGD(H) registers instead. Access to these
ports will not cause fallback.
5.11 BANK 0 – GLOBAL CONTROL AND STATUS
REGISTERS
In the Non-Extended modes of operation, bank 0 is compat-
ible with both the 16450 and the 16550. Upon reset, this
module defaults to the 16450 mode. In the Extended mode,
all the Registers (except RXD/ TXD) offer additional fea-
tures.
Fallback can occur in any mode. In Extended UART mode,
fallback is always enabled. In this case, when a fallback oc-
curs, the following happens:
●
Transmission and Reception FIFOs switch to 16 levels.
TABLE 5-2. Bank 0 Serial Controller Base Registers
●
A value of 13 is selected for the Baud Generator Prescaler
Register
Name
●
Offset
Description
The BTEST and ETDLBK bits in the EXCR1 register
are cleared.
00h
RXD/ Receiver Data Port/ Transmitter Data
TXD
IER
●
UART mode is selected.
Port
●
A switch to a Non-Extended UART mode occurs.
01h
02h
Interrupt Enable Register
When a fallback occurs in a Non-Extended UART mode, the
last two of the above actions do not take place.
EIR/
FCR
Event Identification Register/
FIFO Control Register
No switch to UART mode occurs if either SIR or Sharp-IR
mode was selected. This prevents spurious switching to
UART mode when a legacy program running in infrared
mode accesses the Baud Generator Divisor Registers from
bank 1.
03h
LCR/
BSR
Link Control Register/
Bank Select Register
04h
05h
06h
07h
MCR
LSR
Modem Control Register
Link Status Register
Modem Status Register
Scratch Register/
Fallback from a Non-Extended mode can be disabled by
setting the LOCK bit in register EXCR2. When LOCK is set
to 1 and the UART is in a Non-Extended mode, two scratch
registers overlaid with LBGD(L) and LBGD(H) are enabled.
Any attempted CPU access of LBGD(L) and LBGD(H) ac-
cesses the scratch registers, and the baud setting is not af-
fected. This feature allows existing legacy programs to run
faster than 115.2 Kbps.
MSR
SCR/
ASCR Auxiliary Status and Control Register
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
5.11.1 Receiver Data Port (RXD) or the Transmitter
Data Port (TXD)
tended mode. The bits of the Interrupt Enable Register
(IER) are defined differently, depending on the operating
mode of the module.
These ports share the same address.
The different modes can be divided into the following four
groups:
RXD is accessed during CPU read cycles. It is used to read
data from the Receiver Holding Register when the FIFOs
are disabled, or from the bottom of the RX_FIFO when the
FIFOs are enabled.
●
Non-Extended (which includes UART, Sharp-IR and
SIR).
●
UART and Sharp-IR in Extended mode.
Receiver Data Port (RXD)
●
SIR in Extended mode.
●
Receiver Data
Port (RXD)
Bank 0,
7
6
5
4
3
2
1
0
Consumer-IR.
Reset
The following sections describe the bits in this register for
each of these modes.
Offset 00h
Required
The reset mode for the IER is the Non-Extended UART
mode.
When edge-sensitive interrupt triggers are employed, user is
advised to clear all IER bits immediately upon entering the in-
terrupt service routine and to re-enable them prior to exiting
(or alternatively, to disable CPU interrupts and re-enable pri-
or to exiting). This will guarantee proper interrupt triggering in
the interrupt controller in case one or more interrupt events
occur during execution of the interrupt routine.
Received Data
If the LSR, MSR or EIR registers are to be polled, interrupt
sources which are identified by self-clearing bits should
have their corresponding IER bits set to 0, to prevent spuri-
ous pulses on the interrupt output pin.
Bits 7-0 - Received Data
Used to access the Receiver Holding Register when the
FIFOs are disabled, or the bottom of the RX_FIFO when
the FIFOs are enabled.
If an interrupt source must be disabled, the CPU can do so
by clearing the corresponding bit in the IER register. How-
ever, if an interrupt event occurs just before the correspond-
ing enable bit in the IER register is cleared, a spurious
interrupt may be generated. To avoid this problem, the
clearing of any IER bit should be done during execution of
the interrupt service routine. If the interrupt controller is pro-
grammed for level-sensitive interrupts, the clearing of IER
bits can also be performed outside the interrupt service rou-
tine, but with the CPU interrupt disabled.
TXD is accessed during CPU write cycles. It is used to write
data to the Transmitter Holding Register when the FIFOs
are disabled, or to the TX_FIFO when the FIFOs are en-
abled.
DMA cycles always access the TXD and RXD ports, regard-
less of the selected bank.
Transmitter Data Port (TXD)
Interrupt Enable Register (IER), in the Non-Extended
Modes (UART, SIR and Sharp-IR)
Transmitter Data
Port (TXD)
Bank 0,
7
6
5
4
3
2
1
0
Upon reset, the IER supports UART, SIR and Sharp-IR in
the Non-Extended modes. See the bitmap of the Interrupt
Enable Register in these modes.
Reset
Required
Offset 00h
IER in Non-Extended Modes
7
0
6
0
5
0
4
3
2
0
1
0
Interrupt Enable
Register (IER)
0
0
0
0
Reset
Bank 0,
Required
Offset 01h
Transmitted Data
RXHDL_IE
TXLDL_IE
LS_IE
MS_IE
Reserved
Reserved
Reserved
Reserved
Bits 7-0 - Transmitted Data
Used to access the Transmitter Holding Register when
the FIFOs are disabled or the top of TX_FIFO when the
FIFOs are enabled.
5.11.2 Interrupt Enable Register (IER)
Bit 0 - Receiver High-Data-Level Interrupt Enable
(RXHDL_IE)
This register controls the enabling of various interrupts.
Some interrupts are common to all operating modes of the
module, while others are mode specific. Bits 4 to 7 can be
set in Extended mode only. They are cleared in Non-Ex-
Setting this bit enables interrupts on Receiver High-
Data-Level, or RX_FIFO Time-Out events (EIR Bits 3-0
are 0100 or 1100. See Table 5-3 on page 110).
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
0: Disable Receiver High-Data-Level and RX_FIFO
Bit 1 - Transmitter Low-Data-Level Interrupt Enable
(TXLDL_IE)
Setting this bit enables interrupts when the TX_FIFO is
Time-Out interrupts (Default).
1: Enable Receiver High-Data-Level and RX_FIFO
Time-Out interrupts.
below the threshold level or the Transmitter Holding
Register is empty.
Bit 1 - Transmitter Low-Data-Level Interrupt Enable
(TXLDL_IE)
0: Disable Transmitter Low-Data-Level Interrupts (De-
fault).
Setting this bit enables interrupts on Transmitter Low
Data-Level-events (EIR Bits 3-0 are 0010. See Table
5-3 on page 110).
1: Enable Transmitter Low-Data-Level Interrupts.
Bit 2 - Link Status Interrupt Enable (LS_IE)
0: Disable Transmitter Low-Data-Level Interrupts (De-
fault).
Setting this bit enables interrupts on Link Status events.
0: Disable Link Status Interrupts (LS_EV) (Default)
1: Enable Link Status Interrupts (LS_EV).
1: Enable Transmitter Low-Data-Level Interrupts.
Bit 2 - Link Status Interrupt Enable (LS_IE)
Bit 3 - Modem Status Interrupt Enable (MS_IE)
Setting this bit enables interrupts on Link Status events.
(EIR Bits 3-0 are 0110. See Table 5-3 on page 110).
Setting this bit enables the interrupts on Modem Status
events.
0: Disable Link Status Interrupts (LS_EV) (Default).
1: Enable Link Status Interrupts (LS_EV).
0: Disable Modem Status Interrupts (MS_EV) (De-
fault)
1: Enable Modem Status Interrupts (MS_EV).
Bit 3 - Modem Status Interrupt Enable (MS_IE)
Setting this bit enables the interrupts on Modem Status
events. (EIR Bits 3-0 are 0000. See Table 5-3 on page
110).
Bit 4 - DMA Interrupt Enable (DMA_IE)
Setting this bit enables the interrupt on terminal count
when the DMA is enabled.
0 - Disable Modem Status Interrupts (MS_EV) (De-
fault).
0: Disable DMA terminal count interrupt (Default)
1: Enable DMA terminal count interrupt.
1: Enable Modem Status Interrupts (MS_EV).
Bit 5 - Transmitter Empty Interrupt Enable (TXEMP_IE)
Bits 7-4- Reserved
Setting this bit enables interrupt generation if the trans-
mitter and TX_FIFO become empty.
These bits are reserved.
Interrupt Enable Register (IER), in the Extended Modes
of UART, Sharp-IR and SIR
0: Disable Transmitter Empty interrupts (Default)
1: Enable Transmitter Empty interrupts.
See the bitmap of the Interrupt Enable Register in these
modes.
Bits 7,6 - Reserved
Reserved.
Extended Mode of UART, Sharp-IR and SIR
Interrupt Enable Register (IER), Consumer-IR Mode
7
0
6
0
5
0
4
3
2
0
1
0
Interrupt Enable
See the bitmap of the Interrupt Enable Register (IER) in this
mode.
Register (IER)
0
0
0
0
Reset
Bank 0,
Required
Offset 01h
Consumer-IR Mode
RXHDL_IE
TXLDL_IE
LS_IE
MS_IE
DMA_IE
TXEMP_IE
Reserved
Reserved
7
0
6
0
5
0
4
3
2
0
1
0
Interrupt Enable
Register (IER)
Bank 0,
0
0
0
0
Reset
Required
Offset 01h
RXHDL_IE
TXLDL_IE
LS_IE or TXUR_IE
MS_IE
DMA_IE
TXEMP_IE
Reserved
Reserved
Bit 0 - Receiver High-Data-Level Interrupt Enable
(RXHDL_IE)
Setting this bit enables interrupts when the RX_FIFO is
equal to or above the RX_FIFO threshold level, or an
RX_FIFO time out occurs.
Bit 1-0 -
Same as in the Extended Modes of UART and Sharp-IR
0: Disable Receiver Data Ready interrupt. (Default)
1: Enable Receiver Data Ready interrupt.
(See previous sections).
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
Bit 2 - Link Status Interrupt Enable (LS_IE) or TX_FIFO
Underrun Interrupt Enable (TXUR_IE)
Non-Extended Modes, Read Cycles
On reception, Setting this bit enables Link Status Interrupts.
Event Identification
Register (EIR)
Bank 0,
7
0
6
0
5
0
4
3
2
0
1
0
On transmission, Setting this bit enables TX_FIFO un-
derrun interrupts.
0
0
0
1
Reset
Offset 02h
0
0
Required
0: Disable Link Status and TX_FIFO underrun inter-
rupts (Default)
IPF - Interrupt Pending
IPR0 - Interrupt Priority 0
IPR1 - Interrupt Priority 1
RXFT - RX_FIFO Time-Out
Reserved
Reserved
FEN0 - FIFOs Enabled
FEN1 - FIFOs Enabled
1: Enable Link Status and TX_FIFO underrun interrupts.
Bit 7-3 - Same as in the Extended Modes of UART and
Sharp-IR (See the section “Interrupt Enable Register (IER),
in the Extended Modes of UART, Sharp-IR and SIR” on
page 109).
5.11.3 Event Identification Register (EIR)
The Event Identification Register (EIR) and the FIFO
Control Register (FCR) (see next register description)
share the same address. The EIR is accessed during CPU
read cycles while the FCR is accessed during CPU write cy-
cles.The Event Identification Register (EIR) indicates the in-
terrupt source. The function of this register changes
according to the selected mode of operation.
Bit 0 - Interrupt Pending Flag (IPF)
0: There is an interrupt pending.
1: No interrupt pending. (Default)
Bits 2,1 - Interrupt Priority 1,0 (IPR1,0)
When bit 0 (IPF) is 0, these bits indicate the pending in-
terrupt with the highest priority. See Table 5-3 on page
110.
Event Identification Register (EIR), Non-Extended Mode
When Extended mode is not selected (EXT_SL bit in
EXCR1 register is set to 0), this register is the same as in
the 16550.
Default value is 00.
Bit 3 - RX_FIFO Time-Out (RXFT)
In a Non-Extended UART mode, this module prioritizes in-
terrupts into four levels. The EIR indicates the highest level
of interrupt that is pending. The encoding of these interrupts
is shown in Table 5-3 on page 110.
In the 16450 mode, this bit is always 0. In the 16550
mode (FIFOs enabled), this bit is set to 1 when an
RX_FIFO read time-out occurred and the associated in-
terrupt is currently the highest priority pending interrupt.
Bits 5,4 - Reserved
Read/Write 0.
Bit 7,6 - FIFOs Enabled (FEN1,0)
0: No FIFO enabled. (Default)
1: FIFOs are enabled (bit 0 of FCR is set to 1).
TABLE 5-3. Non-Extended Mode Interrupt Priorities
Interrupt Set and Reset Functions
EIR Bits
3 2 1 0
Priority
Level
Interrupt Type
Interrupt Source
Interrupt Reset Control
0 0 0 1
0 1 1 0
None
None
−
−
Highest
Link Status
Parity error, framing error, data overrun Read Link Status Register (LSR).
or break event
0 1 0 0
Second
Receiver High Receiver Holding Register (RXD) full, or Reading the RXD or, RX_FIFO level
Data Level
Event
RX_FIFO level equal to or above
threshold.
drops below threshold.
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
Interrupt Set and Reset Functions
EIR Bits
3 2 1 0
Priority
Level
Interrupt Type
Interrupt Source
Interrupt Reset Control
Reading the RXD port.
1 1 0 0
0 0 1 0
0 0 0 0
Second
RX_FIFO Time- At least one character is in the
Out
RX_FIFO, and no character has been
input to or read from the RX_FIFO for 4
character times.
Third
Transmitter Low Transmitter Holding Register or
Reading the EIR Register if this
interrupt is currently the highest
priority pending interrupt, or writing
into the TXD port.
Data Level
Event
TX_FIFO empty.
Fourth
Modem Status Any transition on CTS, DSR or DCD or a Reading the Modem Status Register
low to high transition on RI.
(MSR).
Event Identification Register (EIR), Extended Mode
When FIFOs are enabled, the Parity Error(PE), Frame
Error(FE) and Break(BRK) conditions are only reported
when the associated character reaches the bottom of
the RX_FIFO. An Overrun Error (OE) is reported as
soon as it occurs.
In Extended mode, each of the previously prioritized and
encoded interrupt sources is broken down into individual
bits. Each bit in this register acts as an interrupt pending
flag, and is set to 1 when the corresponding event occurred
or is pending, regardless of the IER register bit setting.
In the Consumer-IR mode, this bit indicates that a Link
Status Event (LS_EV) or a Transmitter Halted Event
(TXHLT_EV) occurred. It is set to 1 when any of the fol-
lowing conditions occurs:
When this register is read the DMA event bit (bit 4) is
cleared if an 8237 type DMA is used. All other bits are
cleared when the corresponding interrupts are acknowl-
edged by reading the relevant register (e.g. reading MSR
clears MS_EV bit).
— A receiver overrun.
— A transmitter underrun.
Bit 3 - Modem Status Event (MS_EV)
Extended Mode, Read Cycles
In UART mode this bit is set to 1 when any of the 0 to 3
bits in the MSR register is set to 1.
Event Identification
Register (EIR)
Bank 0,
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
1
Reset
In any IR mode, the function of this bit depends on the
setting of the IRMSSL bit in the IRCR2 register (see Ta-
ble 5-4 and also “Bit 1 - MSR Register Function Select
in Infrared Mode (IRMSSL)” on page 124).
Offset 02h
Required
RXHDL_EV
TXLDL_EV
LS_EV or TXHLT_EV
MS_EV
DMA_EV
TXEMP-EV
Reserved
Reserved
TABLE 5-4. Modem Status Event Detection Enable
IRMSSL Value
Bit Function
0
1
Modem Status Event (MS_EV)
Forced to 0.
Bit 4 - DMA Event Occurred (DMA_EV)
Bit 0 - Receiver High-Data-Level Event (RXHDL_EV)
When an 8237 type DMA controller is used, this bit is set
to 1 when a DMA terminal count (TC) is signalled. It is
cleared upon read.
When FIFOs are disabled, this bit is set to 1 when a
character is in the Receiver Holding Register.
When FIFOs are enabled, this bit is set to 1 when the
RX_FIFO is above threshold or an RX_FIFO time-out
has occurred.
Bit 5 - Transmitter Empty (TXEMP_EV)
In UART, Sharp-IR and Consumer-IR modes, this bit is
the same as bit 6 of the LSR register. It is set to 1 when
the transmitter is empty.
Bit 1 - Transmitter Low-Data-Level Event (TXLDL_EV)
When FIFOs are disabled, this bit is set to 1 when the
Transmitter Holding Register is empty.
Bits 7,6 - Reserved
Read/Write 0.
When FIFOs are enabled, this bit is set to 1 when the
TX_FIFO is below the threshold level.
Bit 2 - Link Status Event (LS_EV) or Transmitter Halted
Event (TXHLT_EV)
In the UART, Sharp-IR and SIR modes, this bit is set to
1 when a receiver error or break condition is reported.
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
5.11.4 FIFO Control Register (FCR)
TABLE 5-6. RX_FIFO Level Selection
RXFTH (Bits 5,4) RX_FIF0 Threshold
The FIFO Control Register (FCR) is write only. It is used to
enable the FIFOs, clear the FIFOs and set the interrupt
thresholds levels for the reception and transmission FIFOs.
00(Default)
1
4
01
10
11
Write Cycles
8
7
0
6
0
5
0
4
3
2
0
1
0
FIFO Control
Register (FCR)
Bank 0,
14
0
0
0
0
Reset
0
Offset 02h
Required
5.11.5 Link Control Register (LCR) and Bank
Selection Register (BSR)
FIFO_EN
The Link Control Register (LCR) and the Bank Select
Register (BSR) (see the next register) share the same ad-
dress.
RXSR
TXSR
Reserved
TXFTH0
TXFTH1
RXFTH0
RXFTH1
The Link Control Register (LCR) selects the communica-
tions format for data transfers in UART, SIR and Sharp-IR
modes.
Upon reset, all bits are set to 0.
Reading the register at this address location returns the
content of the BSR. The content of LCR may be read from
the Shadow of Link Control Register (SH_LCR) register in
bank 3 (See Section 5.14.2 on page 122). During a write op-
eration to this register at this address location, the setting of
bit 7 (Bank Select Enable, BKSE) determines whether LCR
or BSR is to be accessed, as follows:
Bit 0 - FIFO Enable (FIFO_EN)
When set to 1 enables both the Transmision and Recep-
tion FIFOs. Resetting this bit clears both FIFOs.
In Consumer-IR modes the FIFOs are always enabled
and the setting of this bit is ignored.
●
Bit 1 - Receiver Soft Reset (RXSR)
If bit 7 is 0, the write affects both LCR and BSR.
Writing a 1 to this bit generates a receiver soft reset,
which clears the RX_FIFO and the receiver logic. This
bit is automatically cleared by the hardware.
●
If bit 7 is 1, the write affects only BSR, and LCR remains
unchanged. This prevents the communications format
from being spuriously affected when a bank other than
0 or 1 is accessed.
Bit 2 - Transmitter Soft Reset (TXSR)
Upon reset, all bits are set to 0.
Writing a 1 to this bit generates a transmitter soft reset,
which clears the TX_FIFO and the transmitter logic. This
bit is automatically cleared by the hardware.
Link Control Register (LCR)
Bits 6-0 are only effective in UART, Sharp-IR and SIR
modes. They are ignored in Consumer-IR mode.
Bit 3 - Reserved
Read/Write 0.
Writing to this bit has no effect on the UART operation.
Link Control
Register (LCR)
All Banks,
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
0
Reset
Bits 5,4 - TX_FIFO Threshold Level (TXFTH1,0)
Offset 03h
Required
These bits select the TX_FIFO interrupt threshold level.
An interrupt is generated when the level of the data in
the TX_FIFO drops below the encoded threshold.
WLS0
WLS1
STB
PEN
EPS
STKP
SBRK
BKSE
TABLE 5-5. TX_FIFO Level Selection
TXFTH (Bits 5,4) TX_FIF0 Threshold
00(Default)
1
3
01
10
11
9
13
Bits 1,0 - Character Length Select (WLS1,0)
These bits specify the number of data bits in each trans-
mitted or received serial character. Table 5-7 shows
how to encode these bits.
Bits 7,6 - RX_FIFO Threshold Level (RXFTH1,0)
These bits select the RX_FIFO interrupt threshold level.
An interrupt is generated when the level of the data in
the RX_FIFO is equal to or above the encoded thresh-
old.
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
TABLE 5-7. Word Length Select Encoding
— If SIR mode is selected, pulses are issued continu-
ously on the IRTX pin.
WLS1
WLS0
Character Length
— If Sharp-IR mode is selected and internal modula-
tion is enabled, pulses are issued continuously on
the IRTX pin.
0
0
1
1
0
1
0
1
5 (Default)
6
7
8
— If Sharp-IR mode is selected and internal modula-
tion is disabled, the IRTX pin is forced to a logic 1
state.
To avoid transmission of erroneous characters as a re-
sult of the break, use the following procedure to set
SBRK:
Bits 2 - Number of Stop Bits (STB)
This bit specifies the number of stop bits transmitted
with each serial character.
1. Wait for the transmitter to be empty. (TXEMP = 1).
2. Set SBRK to 1.
0: One stop bit is generated. (Default)
3. Wait for the transmitter to be empty, and clear SBRK
when normal transmission must be restored.
1: If the data length is set to 5-bits via bits 1,0
(WLS1,0), 1.5 stop bits are generated. For 6, 7 or 8
bit word lengths, two stop bits are transmitted. The
receiver checks for one stop bit only, regardless of
the number of stop bits selected.
Bit 7 - Bank Select Enable (BKSE)
0: This register functions as the Link Control Register
(LCR).
Bit 3 - Parity Enable (PEN)
1: This register functions as the Bank Select Register
(BSR).
This bit enable the parity bit See Table 5-8 on page 113.
The parity enable bit is used to produce an even or odd
number of 1s when the data bits and parity bit are
summed, as an error detection device.
5.11.6 Bank Selection Register (BSR)
0: No parity bit is used. (Default)
Bank Selection
7
0
6
0
5
0
4
3
2
0
1
0
Register (BSR)
All Banks,
1: A parity bit is generated by the transmitter and
checked by the receiver.
0
0
0
0
Reset
Offset 03h
Required
Bit 4 - Even Parity Select (EPS)
When Parity is enabled (PEN is 1), this bit, together with
bit 5 (STKP), controls the parity bit as shown in Table
5-8.
0: If parity is enabled, an odd number of logic 1s are
transmitted or checked in the data word bits and
parity bit. (Default)
Bank Selection
1: If parity is enabled, an even number of logic 1s are
transmitted or checked.
BKSE-Bank Selection Enable
The Bank Selection Register (BSR) selects which register
bank is to be accessed next.
Bit 5 - Stick Parity (STKP)
When Parity is enabled (PEN is 1), this bit, together with
bit 4 (EPS), controls the parity bit as show in Table 5-8.
About accessing this register see the description of bit 7 of
the LCR Register.
TABLE 5-8. Bit Settings for Parity Control
Bits 6-0 - Bank Selection
PEN
EPS
STKP
Selected Parity Bit
When bit 7 is set to 1, bits 6-0 of BSR select the bank,
as shown in Table 5-9.
0
1
1
1
1
x
0
1
0
1
x
0
0
1
1
None
Odd
Bit 7 - Bank Selection Enable (BKSE)
0: Bank 0 is selected.
Even
Logic 1
Logic 0
1: Bits 6-0 specify the selected bank.
Bit 6 - Set Break (SBRK)
This bit enables or disables a break. During the break,
the transmitter can be used as a character timer to ac-
curately establish the break duration.
This bit acts only on the transmitter front-end and has no
effect on the rest of the transmitter logic.
When set to 1 the following occurs:
— If a UART mode is selected, the SOUT pin is forced
to a logic 0 state.
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
TABLE 5-9. Bank Selection Encoding
Bit 3 - Interrupt Signal Enable (ISEN) or Loopback DCD
(DCDLP)
In normal operation (standard 16450 or 16550) mode,
BSR Bits
Bank
LCR
this bit controls the interrupt signal and must be set to 1
in order to enable the interrupt request signal.
Selected
7
6
5
4
3
2
1
0
0
1
1
1
1
1
1
1
1
1
1
1
x
0
1
1
1
1
1
1
1
1
1
1
x
x
x
x
1
1
1
1
1
1
1
0
x
x
x
x
0
0
0
0
1
1
1
x
x
x
x
x
0
0
1
1
0
0
1
x
x
x
x
x
0
1
0
1
0
1
x
x
x
x
1
x
0
0
0
0
0
0
0
0
x
x
x
1
0
0
0
0
0
0
0
0
0
LCR is
written
When loopback is enabled, the interrupt output signal is
always enabled, and this bit internally drives DCD.
1
New programs should always keep this bit set to 1 dur-
ing normal operation. The interrupt signal should be
controlled through the Plug-n-Play logic.
1
1
2
LCR is not
written
Bit 4 - Loopback Enable (LOOP)
3
When this bit is set to 1, it enables loopback. This bit ac-
cesses the same internal register as bit 4 of the EXCR1
register. (see “Bit 4 - Loopback Enable (LOOP)” on page
120 for more information on the Loopback mode).
4
5
6
0: Loopback disabled. (Default)
1: Loopback enabled.
7
Reserved
Reserved
Bits 7-5 - Reserved
Read/Write 0.
5.11.7 Modem/Mode Control Register (MCR)
Modem/Mode Control Register (MCR), Extended Mode
This register controls the interface with the modem or data
communications set, and the device operational mode
when the device is in the Extended mode. The register
function differs for Extended and Non-Extended modes.
In Extended mode, this register is used to select the opera-
tion mode (IrDA, Sharp, etc.) of the device and to enable the
DMA interface. In these modes, the interrupt output signal
is always enabled, and loopback can be enabled by setting
bit 4 of the EXCR1 register.
Modem/Mode Control Register (MCR), Non-Extended
Mode
Extended Mode
Non-Extended UART mode
7
0
6
0
5
0
4
3
2
0
1
0
7
0
6
0
5
0
4
3
2
0
1
0
Modem Control
Register (MCR)
Bank 0,
Modem Control
Register (MCR)
Bank 0,
0
0
0
0
Reset
0
0
0
0
Reset
Offset 04h
Required
0
0
0
Offset 04h
Required
DTR
DTR
RTS
DMA_EN
TX_DFR
Reserved
MDSL0
MDSL1
MDSL2
RTS
RILP
ISEN or DCDLP
LOOP
Reserved
Reserved
Reserved
Bit 0 - Data Terminal Ready (DTR)
Bit 0 - Data Terminal Ready (DTR)
This bit controls the DTR signal output. When set to1,
DTR is driven low. When loopback is enabled (LOOP is
set), this bit internally drives both DSR and RI.
This bit controls the DTR signal output. When set to 1,
DTR is driven low. When loopback is enabled (LOOP is
set to 1), this bit internally drives DSR.
Bit 1 - Request To Send (RTS)
Bit 1 - Request To Send (RTS)
This bit controls the RTS signal output. When set to1,
RTS is driven low. When loopback is enabled (LOOP is
set), this bit internally drives both CTS and DCD.
This bit controls the RTS signal output. When set to 1,
drives RTS low. When loopback is enabled (LOOP is
set), this bit drives CTS, internally.
Bit 2 - DMA Enable (DMA_EN)
Bit 2 - Loopback Interrupt Request (RILP)
When set to1, DMA mode of operation is enabled. When
DMA is selected, transmit and/or receive interrupts
should be disabled to avoid spurious interrupts.
When loopback is enabled, this bit internally drives RI.
Otherwise it is unused.
DMA cycles always address the Data Holding Registers
or FIFOs, regardless of the selected bank.
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
Bit 3 - Transmission Deferral (TX_DFR)
For a detailed description of the Transmission Deferral
see “Transmission Deferral” on page 107.
7
0
6
1
5
1
4
3
2
0
1
0
Link Status
Register (LSR)
Bank 0,
0
0
0
0
Reset
0: No transmission deferral enabled. (Default)
1: Transmission deferral enabled.
Offset 05h
Required
This bit is effective only if the Transmission FIFOs is en-
abled.
RXDA
OE
PE
Bit 4 - Reserved
Read/Write 0.
FE
BRK
TXRDY
TXEMP
ER_INF
Bits 7-5 - Mode Select (MDSL2-0)
These bits select the operational mode of the module
when in Extended mode, as shown in Table 5-10.
When the mode is changed, the transmission and re-
ception FIFOs are flushed, Link Status and Modem Sta-
tus Interrupts are cleared, and all of the bits in the
auxiliary status and control register are cleared.
Bit 0 - Receiver Data Available (RXDA)
Set to 1 when the Receiver Holding Register is full.
If the FIFOs are enabled, this bit is set when at least one
character is in the RX_FIFO.
TABLE 5-10. The Module Operation Modes
Cleared when the CPU reads all the data in the Holding
Register or in the RX_FIFO.
MDSL2 MDSL1 MDSL0
Operational Mode
(Bit 7)
(Bit 6)
(Bit 5)
Bit 1 - Overrun Error (OE)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
UART mode (Default)
Reserved
This bit is set to 1 as soon as an overrun condition is de-
tected by the receiver.
Cleared upon read.
Sharp-IR
With FIFOs Disabled:
SIR
An overrun occurs when a new character is completely
received into the receiver front-end section and the CPU
has not yet read the previous character in the receiver
holding register. The new character is discarded, and
the receiver holding register is not affected.
Reserved
Reserved
Consumer-IR
Reserved
With FIFOs Enabled:
An overrun occurs when a new character is completely
received into the receiver front-end section and the
RX_FIFO is full. The new character is discarded, and
the RX_FIFO is not affected.
5.11.8 Link Status Register (LSR)
This register provides status information concerning the
data transfer. They are cleared when one of the following
events occurs:
Bit 2 - Parity Error (PE)
●
.
In UART, Sharp-IR and SIR modes, this bit is set to 1 if
the received data character does not have the correct
parity, even or odd as selected by the parity control bits
of the LCR register.
●
The receiver is soft-reset.
●
The LSR register is read.
Upon reset this register assumes the value of 0x60h.
If the FIFOs are enabled, this error is associated with
the particular character in the FIFO that it applies to.
This error is revealed to the CPU when its associated
character is at the bottom of the RX_FIFO.
The bit definitions change depending upon the operation
mode of the module.
Bits 4 through 1 of the LSR are the error conditions that gen-
erate a Receiver Link Status interrupt whenever any of the
corresponding conditions are detected and that interrupt is
enabled.
This bit is cleared upon read.
Bit 3 - Framing Error (FE)
In UART, Sharp-IR and SIR modes, this bit is set to 1
when the received data character does not have a valid
stop bit (i.e., the stop bit following the last data bit or par-
ity bit is a 0).
The LSR is intended for read operations only. Writing to the
LSR is not permitted
If the FIFOs are enabled, this Framing Error is associat-
ed with the particular character in the FIFO that it ap-
plies to. This error is revealed to the CPU when its
associated character is at the bottom of the RX_FIFO.
After a framing error is detected, the receiver will try to
resynchronize.
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
If the bit following the erroneous stop bit is 0, the receiv-
When bits 0, 1, 2 or 3 is set to 1, a Modem Status Event
(MS_EV) is generated if the MS_IE bit is enabled in the IER
er assumes it to be a valid start bit and shifts in the new
character. If that bit is a 1, the receiver enters the idle
state and awaits the next start bit.
Bits 0 to 3 are set to 0 as a result of any of the following
events:
This bit is cleared upon read.
●
A hardware reset occurs.
●
Bit 4 - Break Event Detected (BRK)
The operational mode is changed and the IRMSSL bit
is 0.
In UART, Sharp-IR and SIR modes this bit is set to 1
when a break event is detected (i.e. when a sequence
of logic 0 bits, equal or longer than a full character trans-
mission, is received). If the FIFOs are enabled, the
break condition is associated with the particular charac-
ter in the RX_FIFO to which it applies. In this case, the
BRK bit is set when the character reaches the bottom of
the RX_FIFO.
●
The MSR register is read.
In the reset state, bits 4 through 7 are indeterminate as they
reflect their corresponding input signals.
Note: The modem status lines can be used as general
purpose inputs. They have no effect on the trans-
mitter or receiver operation.
When a break event occurs, only one zero character is
transferred to the Receiver Holding Register or to the
RX_FIFO.
7
6
5
4
3
2
0
1
0
Modem Status
Register (MSR)
Bank 0,
X
X
X
X
0
0
0
Reset
The next character transfer takes place after at least
one logic 1 bit is received followed by a valid start bit.
Offset 06h
Required
This bit is cleared upon read.
DCTS
Bit 5 - Transmitter Ready (TXRDY)
DDSR
TERI
DDCD
CTS
DSR
This bit is set to 1 when the Transmitter Holding Regis-
ter or the TX_FIFO is empty.
It is cleared when a data character is written to the TXD
register.
RI
DCD
Bit 6 - Transmitter Empty (TXEMP)
This bit is set to 1 when the Transmitter Holding Regis-
ter or the TX_FIFO is empty, and the transmitter front-
end is idle.
Bit 0 - Delta Clear to Send (DCTS)
Set to 1, when the CTS input signal changes state.
This bit is cleared upon read.
Bit 7 - Error in RX_FIFO (ER_INF)
In UART, Sharp-IR and SIR modes, this bit is set to a 1
if there is at least 1 framing error, parity error or break
indication in the RX_FIFO.
Bit 1 - Delta Data Set Ready (DDSR)
Set to 1, when the DSR input signal changes state.
This bit is cleared upon read
This bit is always 0 in the 16450 mode.
This bit is cleared upon read.
Bit 2 - Trailing Edge Ring Indicate (TERI)
5.11.9 Modem Status Register (MSR)
Set to 1, when the RI input signal changes state from
low to high.
The function of this register depends on the selected oper-
ational mode. When a UART mode is selected, this register
provides the current-state as well as state-change informa-
tion of the status lines from the modem or data transmission
module.
This bit is cleared upon read
Bit 3 - Delta Data Carrier Detect (DDCD)
Set to 1, when the DCD input signal changes state.
1: DCD signal state changed.
When any of the infrared modes is selected, the register
function is controlled by the setting of the IRMSSL bit in the
IRCR2 (see page 124). If IRMSSL is 0, the MSR register
works as in UART mode. If IRMSSL is 1, the MSR register
returns the value 30 hex, regardless of the state of the mo-
dem input lines.
Bit 4 - Clear To Send (CTS)
This bit returns the inverse of the CTS input signal.
Bit 5 - Data Set Ready (DSR)
When loopback is enabled, the MSR register works similar-
ly except that its status input signals are internally driven by
appropriate bits in the MCR register since the modem input
lines are internally disconnected. Refer to at the MCR (see
page 114) and to the LOOP & ETDLBK bits at the EXCR1
(see page 120) for more information.
This bit returns the inverse of the DSR input signal.
Bit 6 - Ring Indicate (RI)
This bit returns the inverse of the RI input signal.
Bit 7 - Data Carrier Detect (DCD)
A description of the various bits of the MSR register, with
Loopback disabled and UART Mode selected, is provided
below.
This bit returns the inverse of the DCD input signal.
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
5.11.10 Scratchpad Register (SPR)
In this mode, if the CPU simply stops writing data into
the TX_FIFO at the end of the data stream, a transmitter
underrun is generated and the transmitter stops. In this
case this is not an error, but the software must clear the
underrun before the next transmission can occur. This
bit is automatically cleared by hardware when a charac-
ter is written to the TX_FIFO.
This register shares a common address with the ASCR
Register.
In Non-Extended mode, this is a scratch register (as in the
16550) for temporary data storage.
Non-Extended Modes
Bit 3 - Reserved
Read/Write 0.
7
6
5
4
3
2
1
0
Scratchpad Register
(SCR)
Reset
Bank 0,
Offset 07h
Required
Bit 4 - Reception Watchdog (RXWDG)
In Consumer-IR mode, this is the Reception Watchdog
(RXWDG) bit. It is set to 1 each time a pulse or pulse-
train (modulated pulse) is detected by the receiver. It
can be used by the software to detect a receiver idle
condition. It is cleared upon read.
Bit 5 - Receiver Active (RXACT)
Scratch Data
In Consumer-IR Mode this is the Receiver Active (RX-
ACT) bit. It is set to 1 when an infrared pulse or pulse-
train is received. If a 1 is written into this bit position, the
bit is cleared and the receiver is deactivated. When this
bit is set, the receiver samples the infrared input contin-
uously at the programmed baud and transfers the data
to the RX_FIFO. See “Consumer-IR Reception” on
page 106.
5.11.11 Auxiliary Status and Control Register (ASCR)
This register shares a common address with the previous
one (SCR).
This register is accessed when the Extended mode of op-
eration is selected. The definition of the bits in this case is
dependent upon the mode selected in the MCR register,
bits 7 through 5. This register is cleared upon hardware re-
set Bits 2 and 6 are cleared when the transmitter is “soft re-
set”. Bits 0,1,4 and 5 are cleared when the receiver is “soft
reset”.
Bit 6 - Infrared Transmitter Underrun (TXUR)
In the Consumer-IR mode, this is the Transmitter Un-
derrun flag. This bit is set to 1 when a transmitter under-
run occurs. It is always cleared when a mode other than
Consumer-IR is selected. This bit must be cleared, by
writing 1 into it, to re-enable transmission.
Extended Modes
Bit 7 - Reserved
Read/Write 0.
7
0
6
0
5
0
4
3
2
0
1
0
Auxiliary Status
Register (ASCR)
Bank 0,
0
0
0
0
Reset
5.12 BANK 1 – THE LEGACY BAUD GENERATOR
DIVISOR PORTS
0
Offset 07h
0
0
Required
This register bank contains two Baud Generator Divisor
Ports, and a bank select register.
RXF_TOUT
Reserved
S_EOT
Reserved
RXWDG
RXACT
TXUR
Reserved
The Legacy Baud Generator Divisor (LBGD) port provides
an alternate path to the Baud Divisor Generator register.
This bank is implemented to maintain compatibility with
16550 standard and to support existing legacy software
packages. In case of using legacy software, the addresses
0 and 1 are shared with the data ports RXD/TXD (see page
108). The selection between them is controlled by the value
of the BKSE bit (LCR bit 7 page 112).
Bit 0 - RX_FIFO Time-Out (RXF_TOUT)
TABLE 5-11. Bank 1 Register Set
This bit is read only and set to 1 when an RX_FIFO tim-
eout occurs. It is cleared when a character is read from
the RX_FIFO.
Register
Name
Offset
Description
00h
LBGD(L) Legacy Baud Generator Divisor
Port (Low Byte)
Bit 1 -Reserved
Read/Write 0.
01h
LBGD(H) Legacy Baud Generator Divisor
Port (High Byte)
Bit 2 - Set End of Transmission (S_EOT)
In Consumer-IR mode this is the Set End of Transmis-
sion bit. When a 1 is written into this bit position before
writing the last character into the TX_FIFO, data trans-
mission is gracefully completed.
02h
03h
Reserved
LCR/
BSR
Link Control /
Bank Select Register
04h - 07h
Reserved
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117
Enhanced Serial Port with IR -UART2 (Logical Device 2)
In addition, a fallback mechanism maintains this compatibil- .
ity by forcing the UART to revert to 16550 mode if 16550
software addresses the module after a different mode was
set. Since setting the Baud Divisor values is a necessary ini-
tialization of the 16550, setting the divisor values in bank 1
forces the UART to enter 16550 mode. (This is called fall-
back.)
Legacy Baud Generator Divisor
7
6
5
4
3
2
1
0
Low Byte port
(LBGD(L))
Bank 1,
Reset
Required
Offset 00h
To enable other modes to program their desired baud rates
without activating this fallback mechanism, the Baud Gen-
erator Divisor Port pair in bank 2 should be used.
5.12.1 Legacy Baud Generator Divisor Ports (LBGD(L)
and LBGD(H)),
Least Significant Byte
of Baud Generator
The programmable baud rates in the Non-Extended mode
are achieved by dividing a 24 MHz clock by a prescale value
of 13, 1.625 or 1. This prescale value is selected by the
PRESL field of EXCR2 (see page 121). This clock is subdi-
vided by the two Baud Generator Divisor buffers, which out-
put a clock at 16 times the desired baud (this clock is the
BOUT clock). This clock is used by I/O circuitry, and after a
last division by 16 produces the output baud.
.
Legacy Baud Generator Divisor
7
6
5
4
3
2
1
0
High Byte port
(LBGD(H))
Bank 1,
Reset
Offset 01h
Required
Divisor values between 1 and 216-1 can be used. (Zero is
forbidden). The Baud Generator Divisor must be loaded
during initialization to ensure proper operation of the Baud
Generator. Upon loading either part of it, the Baud Genera-
tor counter is immediately loaded. Table 5-15 on page 120
shows typical baud divisors. After reset the divisor register
contents are indeterminate.
Most Significant Byte
of Baud Generator
Any access to the LBGD(L) or LBGD(H) ports causes a re-
set to the default Non-Extended mode, i.e., 16550 mode
(See “AUTOMATIC FALLBACK TO A NON-EXTENDED
UART MODE” on page 107). To access a Baud Generator
Divisor when in the Extended mode, use the port pair in
bank 2 (BGD on page 119).
5.12.2 Link Control Register (LCR) and Bank Select
Register (BSR)
These registers are the same as the registers at offset 03h
in bank 0.
Table 5-12 shows the bits which are cleared when Fallback
occurs during Extended or Non-Extended modes.
If the UART is in Non-Extended mode and the LOCK bit is
1, the content of the divisor (BGD) ports will not be affected
and no other action is taken.
5.13 BANK 2 – EXTENDED CONTROL AND STATUS
REGISTERS
Bank 2 contains two alternate Baud Generator Divisor ports
and the Extended Control Registers (EXCR1 and EXCR2).
When programming the baud, the new divisor is loaded
upon writing into LBGD(L) and LBGD(H). After reset, the
contents of these registers are indeterminate.
TABLE 5-13. Bank 2 Register Set
Divisor values between 1 and 216-1 can be used. (Zero is
forbidden.) Table 5-14 shows typical baud divisors.
Register
Name
Offset
Description
TABLE 5-12. Bits Cleared On Fallback
UART Mode & LOCK bit before Fallback
00h
BGD(L)
Baud Generator Divisor Port (Low
byte)
01h
BGD(H)
Baud Generator Divisor Port (High
byte)
Extended Non-Extended Non-Extended
Register
Mode
Mode
Mode
02h
EXCR1
Extended Control Register 1
LOCK = x
LOCK = 0
LOCK = 1
03h LCR/BSR Link Control/ Bank Select Register
MCR
2 to 7
none
5 and 7
0 to 5
none
none
none
none
none
04h
05h
06h
07h
EXCR2
Extended Control Register 2
Reserved
EXCR1 0, 5 and 7
EXCR2
IRCR1
0 to 5
TXFLV
RXFLV
TX_FIFO Level
2 and 3
RX_FIFO Level
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118
Enhanced Serial Port with IR -UART2 (Logical Device 2)
5.13.1 Baud Generator Divisor Ports, LSB (BGD(L))
and MSB (BGD(H))
Baud Generator Divisor
0
High Byte Port
7
6
x
5
x
4
3
2
1
These ports perform the same function as the Legacy Baud
Divisor Ports in Bank 1 and are accessed identically, but do
not change the operation mode of the module when access-
ed. Refer to Section 5.12.1 on page 118 for more details.
(BGD(H))
Bank 2,
x
x
x
x
x
x
Reset
Required
Offset 01h
Use these ports to set the baud when operating in Extended
mode to avoid fallback to a Non-Extended operation mode,
i.e., 16550 compatible.When programming the baud, writ-
ing to BGDH causes the baud to change immediately.
Most Significant Byte
of Baud Generator
Baud Generator Divisor
7
6
x
5
x
4
3
2
1
0
Low Byte Port
(BGD(L))
x
x
x
x
x
x
Reset
Bank 2,
Required
Offset 00h
Least Significant Byte
of Baud Generator
TABLE 5-14. Baud Generator Divisor Settings
13 1.625
Prescaler Value
Baud
1
Divisor
% Error
Divisor
% Error
Divisor
% Error
50
75
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
8
0.16%
0.16%
0.19%
0.10%
0.16%
0.16%
0.16%
0.16%
0.16%
0.53%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
---
18461
12307
8391
6863
6153
3076
1538
769
512
461
384
256
192
128
96
0.00%
0.01%
0.01%
0.00%
0.01%
0.03%
0.03%
0.03%
0.16%
0.12%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
---
30000
20000
13636
11150
10000
5000
2500
1250
833
750
625
416
312
208
156
104
78
0.00%
0.00%
0.00%
0.02%
0.00%
0.00%
0.00%
0.00%
0.04%
0.00%
0.00%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
---
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
14400
19200
28800
38400
57600
115200
230400
460800
750000
921600
1500000
64
6
48
4
32
52
3
24
39
2
16
26
1
8
13
---
4
---
---
---
2
---
---
---
---
---
2
0.00%
---
---
---
1
0.16%
---
---
---
---
---
1
0.00%
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119
Enhanced Serial Port with IR -UART2 (Logical Device 2)
5.13.2 Extended Control Register 1 (EXCR1)
nel to either the transmitter or the receiver DMA logic is
then simply controlled by the DMASWP bit. This way,
the infrared device drivers do not need to know the de-
tails of the configuration module.
Use this register to control module operation in the Extend-
ed mode. Upon reset all bits are set to 0.
.
Extended Control and
7
0
6
0
5
0
4
3
2
0
1
0
DMA Swap Configuration
Status Register 1
Logic
Module
0
0
0
0
Reset
(EXCR1)
Bank 2,
Offset 02h
TX -
Channel
DMA
1
Required
RX_DMA
TX_DMA
DMA
EXT_SL
Logic
Routing
Logic
Hand-
shake
Signals
DMANF
DMATH
DMASWP
LOOP
ETDLBK
Reserved
BTEST
TX -
Channel
DMA
Logic
DMASWP
Bit 0 - Extended Mode Select (EXT_SL)
FIGURE 5-3. DMA Control Signals Routing
When set to 1, the Extended mode is selected.
Bit 1 - DMA Fairness Control (DMANF)
Bit 4 - Loopback Enable (LOOP)
This bit controls the maximum duration of DMA burst
transfers.
During loopback, the transmitter output is connected in-
ternally to the receiver input, to enable system self-test
of serial communications. In addition to the data signal,
all additional signals within the UART are interconnect-
ed to enable real transmission and reception using the
UART mechanisms.
0: DMA requests are forced inactive after approxi-
mately 10.5 µsec of continuous transmitter and/or
receiver DMA operation. (Default)
1: A transmission DMA request is deactivated when
the TX_FIFO is full. A reception DMA request is de-
activated when the RX_FIFO is empty.
When this bit is set to 1, loopback is selected. This bit
accesses the same internal register as bit 4 in the MCR
register, when the UART is in a Non-Extended mode.
Loopback behaves similarly in both Non-Extended and
Extended modes.
Bit 2 - DMA FIFO Threshold (DMATH)
This bit selects the TX_FIFO and RX_FIFO threshold
levels used by the DMA request logic to support de-
mand transfer mode.
When Extended mode is selected, the DTR bit in the
MCR register internally drives both DSR and RI, and the
RTS bit drives CTS and DCD.
A transmission DMA request is generated when the
TX_FIFO level is below the threshold.
During loopback, the following actions occur:
A reception DMA request is generated when the
RX_FIFO level reaches the threshold or when a DMA
timeout occurs.
1. The transmitter and receiver interrupts are fully op-
erational. The Modem Status Interrupts are also fully
operational, but the interrupt sources are now the
lower bits of the MCR register. Modem interrupts in
infrared modes are disabled unless the IRMSSL bit
in the IRCR2 register is 0. Individual interrupts are
still controlled by the IER register bits.
Table 5-15 lists the threshold levels for each FIFO.
TABLE 5-15. DMA Threshold Levels
DMA Threshold for FIFO Type
Bit
2. The DMA control signals are fully operational.
Value
3. UART and infrared receiver serial input signals are
disconnected. The internal receiver input signals are
connected to the corresponding internal transmitter
output signals.
RX_FIFO
Tx_FIFO
0
1
4
13
7
10
4. The UART transmitter serial output is forced high
and the infrared transmitter serial output is forced
low, unless the ETDLBK bit is set to 1. In which case
they function normally.
Bit 3 - DMA Swap (DMASWP)
This bit selects the routing of the DMA control signals
between the internal DMA logic and the configuration
module of the chip. When this bit is 0, the transmitter
and receiver DMA control signals are not swapped.
When it is 1, they are swapped. A block diagram illus-
trating the control signals routing is given in Fig. 5-3.
5. The modem status input pins (DSR, CTS, RI and
DCD) are disconnected. The internal modem status
signals, are driven by the lower bits of the MCR reg-
ister.
The swap feature is particularly useful when only one
8237 DMA channel is used to serve both transmitter and
receiver. In this case only one external DRQ/DACK sig-
nal pair will be interconnected to the swap logic by the
configuration module. Routing the external DMA chan-
Bit 5 - Enable Transmitter During Loopback (ETDLBK)
When this bit is set to 1, the transmitter serial output is
enabled and functions normally when loopback is en-
abled.
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120
Enhanced Serial Port with IR -UART2 (Logical Device 2)
through LBGD(L) and LBGD(H) will access the Scratch-
Bit 6 - Reserved
Write 1.
Pad Registers instead. This bit must be set to 0 when
extended mode is selected.
Bit 7 - Baud Generator Test (BTEST)
5.13.5 Reserved Register
When set to 1, this bit routes the Baud Generator output
to the DTR pin for testing purposes.
Upon reset, all bits in Bank 2 register with offset 05h are set to 0.
Bits 7-0 - Reserved
Read/Write 0.
5.13.3 Link Control Register (LCR) and Bank Select
Register (BSR)
These registers are the same as the registers at offset 03h
in bank 0.
5.13.6 TX_FIFO Current Level Register (TXFLV)
This read-only register returns the number of bytes in the
TX_FIFO. It can be used to facilitate programmed I/O
modes during recovery from transmitter underrun in one of
the fast infrared modes.
5.13.4 Extended Control and Status Register 2
(EXCR2)
This register configures the Prescaler and controls the
Baud Divisor Register Lock.
Extended Modes
Upon reset all bits are set to 0.
TX_FIFO Current Level
7
0
6
0
5
0
4
3
2
1
0
Register (TXFLV)
0
0
0
0
0
Reset
Extended Control and
Bank 2,
Offset 06h
7
0
6
0
5
0
4
3
2
0
1
0
and Status Register 2
0
0
0
Required
0
0
0
0
Reset
(EXCR2)
Bank 2,
Offset 04h
TFL0
TFL1
0
0
0
0
0
Required
TFL2
TFL3
TFL4
Reserved
Reserved
PRESL0
PRESL1
Reserved
LOCK
Bits 4-0 - Number of Bytes in TX_FIFO (TFL(4-0))
These bits specify the number of bytes in the TX_FIFO.
Bits 7,6 - Reserved
Read/Write 0.
Bits 3 - 0 - Reserved
Read/Write 0.
Bits 5,4 - Prescaler Select
The prescaler divides the 24 MHz input clock frequency to
provide the clock for the Baud Generator. (See Table 5-16).
TABLE 5-16. Prescaler Select
Bit 5
Bit 4
Prescaler Value
0
0
1
1
0
1
0
1
13
1.625
Reserved
1.0
Bit 6 - Reserved
Read/Write 0.
Bit 7 - Baud Divisor Register Lock (LOCK)
When set to 1, accesses to the Baud Generator Divisor
Register through LBGD(L) and LBGD(H) as well as fall-
back are disabled from non-extended mode.
In this case two scratchpad registers overlaid with LB-
GD(L) and LBGD(H) are enabled, and any attempted
CPU access of the Baud Generator Divisor Register
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
5.13.7 RX_FIFO Current Level Register (RXFLV)
5.14.1 Module Revision ID Register (MRID)
This read-only register returns the number of bytes in the
RX_FIFO. It can be used for software debugging.
This read-only register identifies the revision of the module.
When read, it returns the module ID and revision level. This
module returns the code 2xh, where x indicates the revision
number.
Extended Modes
7
0
6
0
5
0
4
3
2
0
1
0
RX_FIFO Current Level
7
0
6
0
5
1
4
3
2
1
0
Register (RXFLV)
Module Revision ID
Register
0
0
0
0
Reset
Bank 2,
0
x
x
x
x
Reset
Offset 07h
0
0
0
Required
(MRID)
Required
Bank 3,
Offset 00h
RFL0
RFL1
RFL2
RFL3
RFL4
Revision ID(RID 3-0)
Reserved
Module ID(MID 7-4)
Bits 4-0 - Number of Bytes in RX_FIFO (RFL(4-0))
These bits specify the number of bytes in the RX_FIFO.
Bits 3-0 - Revision ID (MID3-0)
The value in these bits identifies the revision level.
Bits 7-5 - Reserved
Read/Write 0.
Bits 7-4 - Module ID (MID7-4)
The value in these bits identifies the module type.
Note: The contents of TXFLV and RXFLV are not frozen
during CPU reads. Therefore, invalid data could be re-
turned if the CPU reads these registers during normal
transmitter and receiver operation. To obtain correct da-
ta, the software should perform three consecutive reads
and then take the data from the second read, if first and
second read yield the same result, or from the third
read, if first and second read yield different results.
5.14.2 Shadow of Link Control Register (SH_LCR)
This register returns the value of the LCR register. The LCR
register is written into when a byte value according to Table
5-9 on page 114, is written to the LCR/BSR registers loca-
tion (at offset 03h) from any bank.
5.14 BANK 3 – MODULE REVISION ID AND SHADOW
REGISTERS
Shadow of
7
0
6
0
5
0
4
3
2
0
1
0
Link Control Register
(SH_LCR)
0
0
0
0
Reset
Bank 3 contains the Module Revision ID register which
identifies the revision of the module, shadow registers for
monitoring various registers whose contents are modified
by being read, and status and control registers for handling
the flow control.
Bank 3,
Offset 01h
Required
WLS0
WLS1
STB
PEN
EPS
STKP
SBRK
BKSE
TABLE 5-17. Bank 3 Register Set
Register
Name
Offset
Description
00h
01h
MRID
Module Revision ID Register
SH_LCR
Shadow of LCR Register
(Read Only)
See “Link Control Register (LCR)” on page 112 for bit de-
scriptions.
02h
03h
SH_FCR Shadow of FIFO Control Register
(Read Only)
LCR/
BSR
Link Control Register/
Bank Select Register
04h-07h
Reserved
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
5.14.3 Shadow of FIFO Control Register (SH_FCR)
5.15.2 Infrared Control Register 1 (IRCR1)
This read-only register returns the contents of the FCR reg-
ister in bank 0.
This register enables the Sharp-IR or SIR infrared mode in
the Non-Extended mode of operation.
Upon reset, all bits are set to 0.
Shadow of
FIFO Control Register
7
0
6
0
5
0
4
3
2
0
1
0
Infrared Control Register1
(SH_FCR)
Bank 3,
Offset 02h
0
0
0
0
Reset
7
0
6
0
5
0
4
3
2
0
1
0
(IRCR1)
Bank 4,
Offset 02h
0
0
0
0
Reset
Required
0
0
0
0
0
0
Required
FIFO_EN
RXSR
TXSR
Reserved
TXFTH0
TXFHT1
RXFTH0
RXFTH1
Reserved
Reserved
IR_SL0
IR_SL1
Reserved
See “FIFO Control Register (FCR)” on page 112 for bit de-
scriptions.
Bits 1,0 - Reserved
Read/Write 0.
5.14.4 Link Control Register (LCR) and Bank Select
Register (BSR)
These registers are the same as the registers at offset 03h
in bank 0.
Bits 3,2 - Sharp-IR or SIR Mode Select (IR_SL1,0), Non-
Extended Mode Only
These bits enable Sharp-IR and SIR modes in Non-Ex-
tended mode. They allow selection of the appropriate in-
frared interface when Extended mode is not selected.
These bits are ignored when Extended mode is selected.
5.15 BANK 4 – IR MODE SETUP REGISTER
TABLE 5-18. Bank 4 Register Set
Register
Name
Offset
Description
Reserved
TABLE 5-19. Sharp-IR or SIR Mode Selection
00-01h
02h
IR_SL1
IR_SL0
Selected Mode
IRCR1
Infrared Control Register 1
0
0
1
1
0
1
0
1
UART (Default)
Reserved
Sharp-IR
SIR
03h
LCR/
BSR
Link Control/
Bank Select Registers
04-07h
Reserved
5.15.1 Reserved Registers
Bits 7-4 - Reserved
Read/Write 0.
Bank 4 registers with offsets 00h and 01h are reserved.
5.15.3 Link Control Register (LCR) and Bank Select
Register (BSR)
These registers are the same as the registers at offset 03h
in bank 0.
5.15.4 Reserved Registers
Bank 4 registers with offsets 04h-07h are reserved.
5.16 BANK 5 – INFRARED CONTROL REGISTERS
TABLE 5-20. Bank 5 Registers
Register
Name
Offset
Description
Reserved
00-02h
03h
LCR/
BSR
Link Control Register/
Bank Select Register
04h
IRCR2 Infrared Control Register 2
Reserved
05h - 07h
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123
Enhanced Serial Port with IR -UART2 (Logical Device 2)
5.17 BANK 6 – INFRARED PHYSICAL LAYER
5.16.1 Reserved Registers
CONFIGURATION REGISTERS
Bank 5 registers with offsets 00h-02h are reserved.
This Bank of registers controls aspects of the framing and
timing of the infrared modes.
5.16.2 (LCR/BSR) Register
These registers are the same as the registers at offset 03h
in bank 0.
TABLE 5-21. Bank 6 Register Set
Register
Name
5.16.3 Infrared Control Register 2 (IRCR2)
Offset
Description
This register controls the basic settings of the infrared
modes.
00h
01h
02h
IRCR3
Infrared Control Register 3
Reserved
Upon reset, the content of this register is 02h.
SIR_PW
SIR Pulse Width Control
(≤ 115 Kbps)
Infrared Control
Register 2
(IRCR2)
7
0
6
0
5
0
4
3
2
0
1
0
03h
LCR/ BSR
Link Control Register/
Bank Select Register
0
0
1
0
Reset
0
Bank 5,
Offset 04h
Required
04h - 07h
Reserved
IR_FDPLX
IRMSSL
5.17.1 Infrared Control Register 3 (IRCR3)
This register enables/disables modulation in Sharp-IR
mode.
Reserved
AUX_IRRX
Upon reset, the content of this register is 20h.
7
0
6
0
5
1
4
3
2
0
1
0
Infrared Control
Register 3
(IRCR3)
Reserved
0
0
0
0
Reset
0
0
0
0
0
0
Required
Bank 6,
Offset 00h
Bit 0 - Enable Infrared Full Duplex Mode (IR_FDPLX)
When set to 1, the infrared receiver is not masked dur-
ing transmission.
Bit 1 - MSR Register Function Select in Infrared Mode
(IRMSSL)
Reserved
This bit selects the behavior of the Modem Status Reg-
ister (MSR) and the Modem Status Interrupt (MS_EV)
when any infrared mode is selected. When a UART
mode is selected, the Modem Status Register and the
Modem Status Interrupt function normally, and this bit is
ignored.
SHMD_DS
SHDM_DS
Bit 0-5 - Reserved
Read/Write 0.
0: MSR register and modem status interrupt work in
the IR modes as in the UART mode (Enables exter-
nal circuitry to perform carrier detection and pro-
vide wake-up events).
Bit 6 - Sharp-IR Modulation Disable (SHMD_DS)
0: Enables internal 500 KHz transmitter modulation.
(Default)
1: The MSR returns 30h, and the Modem Status In-
terrupt is disabled. (Default)
1: Disables internal modulation.
Bits 3,2 -Reserved
Read/Write 0.
Bit 7 - Sharp-IR Demodulation Disable (SHDM_DS)
0: Enables internal 500 KHz receiver demodulation.
(Default)
Bit 4 - Auxiliary Infrared Input Select (AUX_IRRX)
1: Disables internal demodulation.
When set to 1, the infrared signal is received from the
auxiliary input. (Separate input signals may be desired
for different front-end circuits). See Table 5-29 on page
130.
5.17.2 Reserved Register
Bank 6 register with offset 01h is reserved.
5.17.3 SIR Pulse Width Register (SIR_PW)
Bit 5-7 - Reserved
Read/Write 0.
This register sets the pulse width for transmitted pulses in
SIR operation mode. These setting do not affect the receiv-
er. Upon reset, the content of this register is 00h, which de-
faults to a pulse width of 3/16 of the baud.
5.16.4 Reserved Registers
Bank 5 registers with offsets 05h-07h are reserved.
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124
Enhanced Serial Port with IR -UART2 (Logical Device 2)
The Consumer-IR utilizes two carrier frequency ranges (see
also Table 5-26).
7
0
6
0
5
0
4
3
2
0
1
0
SIR Pulse Width
Register
— Low range which spans from 30 KHz to 56 KHz, in
0
0
0
0
Reset
1 KHz increments, and
(SIR_PW)
Bank 6,
Offset 02h
0
0
0
0
Required
— High range which includes three frequencies:
400 KHz, 450 KHz or 480 KHz.
High and low frequencies are specified independently to al-
low separate transmission and reception modulation set-
tings. The transmitter uses the carrier frequency settings in
Table 5-26.
SPW(3-0)
The four registers at offsets 04h through 07h (the infrared
transceiver configuration registers) are provided to config-
ure the Infrared Interface (the transceiver). The transceiver
mode is selected by up to three special output signals
(IRSL2-0). When programmed as outputs these signals are
forced to low when automatic configuration is enabled (AM-
CFG bit set to 1) and a UART mode is selected.
Reserved
Bits 3-0 - SIR Pulse Width Register (SPW)
Two codes for setting the pulse width are available. All
other values for this field are reserved.
5.18.1 Infrared Receiver Demodulator Control
Register (IRRXDC)
0000:Pulse width is 3/16 of the bit period. (Default)
1101:Pulse width is 1.6 µsec.
This register controls settings for Sharp-IR and Consumer
IR reception. After reset, the content of this register is 29h.
This setting selects a subcarrier frequency in a range be-
tween 34.61 KHz and 38.26 KHz for the Consumer-IR
mode, and from 480.0 to 533.3 KHz for the Sharp-IR mode.
The value of this register is ignored in both modes if the re-
ceiver demodulator is disabled. The available frequency
ranges for Consumer-IR and Sharp-IR modes are given in
Tables 5-23 through 5-25.
Bits 7-4 - Reserved
Read/Write 0.
5.17.4 Link Control Register (LCR) and Bank Select
Register (BSR)
These registers are the same as the registers at offset 03h
in Bank 0.
5.17.5 Reserved Registers
Infrared Receiver
Demodulation Control
7
0
6
0
5
1
4
3
2
0
1
0
Bank 6 registers with offsets 04h-07h are reserved.
Register (IRRXDC)
0
1
0
1
Reset
Bank 7,
Offset 00h
5.18 BANK 7 – CONSUMER-IR AND OPTICAL
TRANSCEIVER CONFIGURATION REGISTERS
Required
Bank 7 contains the registers that configure Consumer-IR
functions and infrared transceiver controls. See Table 5-22.
DFR0
DFR1
DFR2
DFR3
DFR4
DBW0
DBW1
DBW2
TABLE 5-22. Bank 7 Register Set
Register
Name
Offset
Description
00h IRRXDC Infrared Receiver Demodulator
Control Register
01h IRTXMC Infrared Transmitter Modulator
Control Register
Bits 4-0 - Demodulator Frequency (DFR(4-0))
These bits select the subcarrier’s center frequency for
the Consumer-IR receiver demodulator. Table 5-25
shows the selection for low speed demodulation (bit 5 of
RCCFG=0, see page 128), and Table 5-24 shows the
selection for high speed demodulation (bit 5 of RC-
CFG=1).
02h
RCCFG Consumer-IR Configuration Reg-
ister
03h LCR/BSR
Link Control Register/
Bank Select Register
04h
IRCFG1 Infrared Interface Configuration
Register 1
Bits 7-5 - Demodulator Bandwidth (DBW(2-0))
05h
06h
Reserved
These bits set the demodulator bandwidth for the select-
ed frequency range. The subcarrier signal frequency
must fall within the specified frequency range in order to
be accepted. Used for both Sharp-IR and Consumer-IR
modes.
IRCFG3 Infrared Interface Configuration
Register 3
07h
IRCFG4 Infrared Interface Configuration
Register 4
See Tables 5-23, 5-25 and bit 5 (RXHSC) of the Con-
sumer-IR Configuration (RCCFG) Register on page
128.
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125
Enhanced Serial Port with IR -UART2 (Logical Device 2)
5.18.2 Infrared Transmitter Modulator Control
Register (IRTXMC)
Infrared Transmitter
Modulation Control
7
0
6
1
5
1
4
3
2
0
1
0
This register controls modulation subcarrier parameters for
Consumer-IR and Sharp-IR mode transmission. For Sharp-
IR, only the carrier pulse width is controlled by this register
- the carrier frequency is fixed at 500 KHz.
0
1
0
1
Reset
Register
(IRTXMC)
Bank 7,
Required
Offset 01h
After reset, the value of this register is 69h, selecting a car-
rier frequency of 36 KHz and an IR pulse width of 7 µsec for
Consumer-IR, or a pulse width of 0.8 µsec for Sharp-IR.
MCFR(4-0)
MCPW(2-0)
Bits 4-0 - Modulation Subcarrier Frequency (MCFR)
These bits set the frequency for the Consumer-IR mod-
ulation subcarrier. The encoding are defined in Table
5-26.
Bits 7-5 - Modulation Subcarrier Pulse Width (MCPW)
Specify the pulse width of the subcarrier clock as shown
in Table 5-27.
TABLE 5-23. Consumer IR, High Speed Demodulator (RXHSC = 1) (Frequency Ranges in KHz)
DBW2-0 (Bits 7, 6 and 5 of IRRXDC)
DFR Bits
4 3 2 1 0
min/max
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
min
max
min
380.95
421.05
436.36
480.00
457.71
502.26
363.63
444.44
417.39
505.26
436.36
533.33
347.82
470.58
400.00
533.33
417.39
564.70
333.33
500.00
384.00
564.70
400.00
600.00
320.00
533.33
369.23
600.00
384.00
640.00
307.69
571.42
355.55
640.00
369.92
685.57
0 0 0 1 1
0 1 0 0 0
0 1 0 1 1
max
min
max
TABLE 5-24. Sharp-IR Demodulator (Frequency Ranges in KHz)
DBW2-0 (Bits 7, 6 and 5 of IRRXDC)
DFR Bits
4 3 2 1 0
min/max
001
010
011
100
101
110
min
480.0
533.3
457.1
564.7
436.4
600.0
417.4
640.0
400.0
685.6
384.0
738.5
x x x x x x
max
TABLE 5-25. Consumer-IR, Low Speed Demodulator (RXHSC = 0) (Frequency Ranges in KHz)
DBW2-0 (Bits 7, 6 and 5 of IRRXDC)
DFR Bits
4 3 2 1 0
min/max
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
min
max
min
max
min
max
min
max
26.66
29.47
28.57
31.57
29.28
32.37
30.07
33.24
25.45
31.11
27.27
33.33
27.95
34.16
28.68
35.05
24.34
32.94
26.08
35.29
26.73
36.17
27.43
37.11
23.33
35.00
25.00
37.50
25.62
38.43
26.29
39.43
22.40
37.33
24.00
40.00
24.60
41.00
25.24
42.06
21.53
40.00
23.07
42.85
23.65
43.92
24.27
45.07
0 0 0 1 0
0 0 0 1 1
0 0 1 0 0
0 0 1 0 1
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
DBW2-0 (Bits 7, 6 and 5 of IRRXDC)
DFR Bits
4 3 2 1 0
min/max
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
min
max
min
max
min
max
min
max
min
max
min
max
min
max
min
max
min
max
min
max
min
max
min
max
min
max
min
max
min
max
min
max
31.74
35.08
32.60
36.00
33.57
37.10
34.61
38.26
35.71
39.47
36.85
40.73
38.10
42.10
39.40
43.55
40.81
45.11
42.32
46.78
43.95
48.58
45.71
50.52
47.62
52.63
49.66
54.90
51.90
57.36
54.38
60.10
30.30
37.03
31.13
38.05
32.04
39.16
33.04
40.38
34.09
41.66
35.18
43.00
36.36
44.44
37.59
45.94
38.95
47.61
40.40
49.37
41.95
51.27
43.63
53.33
45.45
55.55
47.40
57.94
49.54
60.55
51.90
63.44
28.98
39.21
29.78
40.29
30.65
41.47
31.60
42.76
32.60
44.11
33.65
45.52
34.78
47.05
36.00
48.64
37.26
50.41
38.64
52.28
40.13
54.29
41.74
56.47
43.47
58.82
45.34
61.35
47.39
64.11
49.65
67.17
27.77
41.66
28.54
42.81
29.37
44.06
30.29
45.43
31.25
46.87
32.25
48.37
33.33
50.00
34.45
51.68
35.70
53.56
37.03
55.55
38.45
57.68
40.00
60.00
41.66
62.50
43.45
65.18
45.41
68.12
47.58
71.37
26.66
44.44
27.40
45.66
28.20
47.00
29.08
48.46
30.00
50.00
30.96
51.60
32.00
53.33
33.08
55.13
34.28
57.13
35.55
59.25
36.92
61.53
38.40
64.00
40.00
66.66
41.72
69.53
43.60
72.66
45.68
76.13
25.63
47.61
26.34
48.92
27.11
50.35
27.96
51.92
28.84
53.57
29.76
55.28
30.77
57.14
31.80
59.07
32.96
61.21
34.18
63.48
35.50
65.92
36.92
68.57
38.46
71.42
40.11
74.50
41.92
77.85
43.92
81.57
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 0
1 0 0 1 0
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 1 0
1 1 0 1 1
1 1 1 0 1
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
TABLE 5-26. Consumer-IR Carrier Frequency Encoding
Encoding
Consumer-IR
Configuration Register
(RCCFG)
7
0
6
0
5
0
4
3
2
0
1
0
Low Frequency
(TXHSC = 0)
High Frequency
(TXHSC = 1)
0
0
0
0
Reset
MCFR Bits
43210
Bank 7,
0
Offset 02h
Required
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
. . .
reserved
reserved
reserved
30 KHz
31 KHz
32 KHz
33 KHz
34 KHz
35 KHz
36 KHz
37 KHz
38 KHz
39 KHz
40 KHz
41 KHz
. . .
reserved
reserved
reserved
400 KHz
reserved
reserved
reserved
reserved
450 KHz
reserved
reserved
480 KHz
reserved
reserved
reserved
. . .
RC_MMD0
RC_MMD1
TXHSC
Reserved
RCDM_DS
RXHSC
T_OV
R_LEN
Bits 1,0 - Transmitter Modulator Mode (RC_MMD(1,0))
Determines how infrared pulses are generated from the
transmitted bit string. (see Table 5-28).
TABLE 5-28. Transmitter Modulation Mode Selection
RCCFG
Bits
1 0
Modulation Mode
0 0
0 1
1 0
1 1
C_PLS Modulation mode. Pulses are
generated continuously for the entire logic
0 bit time.
11010
11011
11100
11101
11110
11111
53 KHz
54 KHz
55 KHz
56 KHz
56.9 KHz
reserved
reserved
reserved
reserved
reserved
reserved
reserved
8_PLS Modulation Mode. 8 pulses are
generated each time one or more logic 0
bits are transmitted following a logic 1 bit.
6_PLS Modulation Mode. 6 pulses are
generated each time one or more logic 0
bits are transmitted following a logic 1 bit.
Reserved. Result is indeterminate.
TABLE 5-27. Carrier Clock Pulse Width Options
Encoding
MCPW Bits
7 6 5
Bit 2 - Transmitter Subcarrier Frequency Select (TXHSC)
This bit selects the modulation carrier frequency range.
0: Low frequency: 30-56.9 KHz
Low Frequency
(TXHSC = 0)
High Frequency
(TXHSC = 1)
1: High frequency: 400-480 KHz
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Reserved
Reserved
6 µsec
Reserved
Reserved
0.7 µsec
0.8 µsec
0.9 µsec
Reserved
Reserved
Reserved
Bit 3 - Reserved
Read/Write 0.
7 µsec
Bit 4 - Receiver Demodulation Disable (RCDM_DS)
When this bit is 1, the internal demodulator is disabled.
The internal demodulator, when enabled, performs car-
rier frequency checking and envelope detection.
9 µsec
10.6 µsec
Reserved
Reserved
This bit must be set to 1 (disabled), when the demodu-
lation is performed externally, or when oversampling
mode is selected to determine the carrier frequency.
0: Internal demodulation enabled.
1: Internal demodulation disabled.
5.18.3 Consumer-IR Configuration Register (RCCFG)
This register control the basic operation of the Consumer-
IR mode. After reset, the content of this register is 00h.
Bit 5 - Receiver Carrier Frequency Select (RXHSC)
This bit selects the receiver demodulator frequency range.
0: Low frequency: 30-56.9 KHz
1: High frequency: 400-480 KHz
Bit 6 - Receiver Sampling Mode Select(T_OV)
0: Programmed-T-period sampling.
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
If ID/IRSL(2-1) are programmed as input (IRSL21_DS =
1: Oversampling mode.
0) then:
Bit 7 - Run Length Control (R_LEN)
— Upon read, these bits return the logic level of the
pins (allowing external devices to identify them-
selves).
Enables or disables run length encoding/decoding. The
format of a run length code is:
— Data written to these bit positions will be ignored.
YXXXXXXX
If ID/IRSL(2-1) are programmed as output (IRSL21_DS
= 1) then:
where, Y is the bit value and XXXXXXX is the number
of bits minus 1 (Selects from 1 to 128 bits).
— If AMCFG (bit 7 of IRCFG4) is set to 1, these bits
drive the ID/IRSL(2-1) pins when Sharp-IR mode is
selected.
0: Run Length Encoding/decoding is disabled.
1: Run Length Encoding/decoding is enabled.
5.18.4 Link Control/Bank Select Registers (LCR/BSR)
— If AMCFG is 0, these bits will drive the ID/IRSL(2-
1)pins, regardless of the selected mode.
These registers are the same as the registers at offset
03h in bank 0.
Upon read, these bits return the values previously written.
5.18.5 Infrared Interface Configuration Register 1
(IRCFG1)
Bit 3 - Transceiver identification (IRID3)
Upon read, this bit returns the logic level of the ID3 pin.
Data written to this bit position is ignored.
This register holds the transceiver configuration data for
Sharp-IR and SIR modes. It is also used to directly control
the transceiver operation mode when automatic configura-
tion is not enabled. The four least significant bits are also
used to read the identification data of a Plug and Play infra-
red interface adaptor.
Bits 6-4 - SIR Mode Transceiver Configuration (SIRC(2-0))
These bits will drive the ID/IRSL(2-0) pins when AMCFG
(bit 7 of IRCFG4) is 1 and SIR mode is selected. They
are unused when AMCFG is 0 or when the ID/IRSL (2-
0) pins are programmed as inputs. SIRC0 is also un-
used when the IRSL0_DS bit in IRCFG4 is 0.
Infrared Configuration
Register 1
7
0
6
0
5
0
4
3
2
0
1
0
Upon read, these bits return the values previously written.
0
0
0
x
Reset
(IRCFG1)
Bank 7,
Required
Bit 7 - Special Transceiver Mode Selection (STRV_MS)
Offset 04h
When this bit is set to 1, the IRTX output signal is forced
to active high and a timer is started.
The timer times out after 64 µsec, at which time the bit
is reset and the IRTX output signal becomes low again.
The timer is restarted every time a 1 is written to this bit.
IRIC(2-0)
IRID3
Although it is possible to extend the period during which
IRTX remains high beyond 64 µsec, this should be
avoided to prevent damage to the transmitter LED.
SIRC(2-0)
STRV_MS
Writing a zero to this bit has no effect.
5.18.6 Reserved Register
Bit 0 - Transceiver Identification/Control Bit 0 (IRIC0)
The function of this bit depends on whether the
ID0/IRSL0/IRRX2 pin is programmed as an input or an
output.
Bank 7 register with offset 05h is reserved.
5.18.7 Infrared Interface Configuration 3 Register
(IRCFG3)
If ID0/IRSL0/IRRX2 is programmed as an input
(IRSL0_DS = 0) then:
This register sets the external transceiver configuration for
the low speed and high speed Consumer IR modes of op-
eration. Upon reset, the content of this register is 00h.
— Upon read, this bit returns the logic level of the pin
(allowing external devices to identify themselves).
— Data written to this bit position is ignored.
If ID0/IRSL0/IRXX2 is programmed as an output
(IRSL0_DS = 1), then:
7
0
6
0
5
0
4
3
2
0
1
0
Infrared Configuration
Register 3
0
0
0
0
Reset
(IRCFG3)
Bank 7,
— If AMCFG (bit 7 of IRCFG4) is set to 1, this bit drives
the ID0/IRSL0/IRRX2 pin when Sharp-IR mode is
selected.
0
0
Required
Offset 06h
— If AMCFG is 0, this bit will drive the
ID0/IRSL0/IRRX2 pin, regardless of the selected
mode.
RCLC(2-0)
Reserved
Upon read, this bit returns the value previously written.
Bits 2-1 - Transceiver Identification/Control Bits 2-1 (IRIC2-
1)
RCHC(2-0)
Reserved
The function of these bits depends on whether the
ID/IRSL(2-1) pins are programmed as inputs or outputs.
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129
Enhanced Serial Port with IR -UART2 (Logical Device 2)
Bits 2-0 - Consumer-IR Mode Transceiver Configuration,
Bit 5 - ID0/IRSL0/IRRX2 Pin Direction Select (IRSL0_DS)
Low-Speed (RCLC)
This bit determines the direction of the ID0/
IRSL0/IRRX2 pin. See Table 5-29 on page 130.
These bits drive the ID/IRSL(2-0) pins when AMCFG is
1 and Consumer-IR mode with 30-56 KHz receiver car-
rier frequency is selected. They are unused when AM-
0: Pin’s direction is input.
1: Pin’s direction is output.
CFG is
0 or when the ID/IRSL(2-0) pins are
programmed as inputs. Upon read, these bits return the
values previously written.
Bit 6 - Reserved
Read/Write 0.
Bit 3 - Reserved
Read/Write 0.
Bit 7 - Automatic Module Configuration (AMCFG)
When set to 1, this bit enables automatic infrared con-
figuration.
Bits 6-4 - Consumer-IR Mode Transceiver Configuration,
High-Speed (RCHC)
TABLE 5-29. Infrared Receiver Input Selection
These bits drive the IRSL(2-0) pins when AMCFG (bit 7
of IRCFG4) is 1 and Consumer-IR mode with 400-480
KHz receiver carrier frequency is selected. They are un-
used when AMCFG is 0 or when the ID/IRSL(2-0) pins
are programmed as inputs.
Bit 4 of IRCR2
Bit 5 of IRCFG41
(AUX_IRRX)2
Selected IRRX
(IRSL0_DS)
Upon read, these bits return the values previously writ-
ten.
0
0
1
1
0
1
0
1
IRRX1
IRRX2
IRRX1
1
Bit 7 - Reserved
Read/Write 0.
1. IRCFG4 is in bank 7, offset 07h. It is
described on page 130.
5.18.8 Infrared Interface Configuration Register 4
(IRCFG4)
2. AUX_IRRX (bit 4 of IRCR2) is described on
page 124.
This register configures the receiver data path and enables
the automatic selection of the configuration pins.
After reset, this register contains 00h.
7
0
6
0
5
0
4
3
2
0
1
0
Infrared Configuration
Register 4
0
0
0
0
Reset
(IRCFG4)
Bank 7,
0
0
0
0
Required
Offset 07h
Reserved
Reserved
Reserved
IRSL21_DS
RXINV
IRSL0_DS
Reserved
AMCFG
Bits 2-0 - Reserved
Read/write 0.
Bit 3- ID/IRSL(2-1) Pins’ Direction Select (IRSL21_DS)
This bit determines the direction of the ID/IRSL2 and
ID/IRSL1 pins.
0: Pins’ direction is input.
1: Pins’ direction is output.
Bit 4 - IRRX Signal Invert (RXINV)
This bit supports optical transceivers with receive sig-
nals of opposite polarity (active high instead of active
low).
When set to 1 an inverter is put on the path of the input
signal of the receiver.
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
5.19 UART2 WITH IR REGISTER BITMAPS
Read Cycles
Extended Mode, Read Cycles
Event Identification
Register (EIR)
Bank 0,
7
0
6
0
5
0
4
3
2
0
1
0
Receiver Data
Register (RXD)
Bank 0,
7
6
5
4
3
2
1
0
0
0
0
1
Reset
Reset
Offset 02h
0
0
Required
Offset 00h
Required
RXHDL_EV
TXLDL_EV
LS_EV or TXHLT_EV
MS_EV
DMA_EV
TXEMP-EV
Reserved
Reserved
Received Data
Write Cycles
Write Cycles
7
0
6
0
5
0
4
3
2
1
0
FIFO Control
Register (FCR)
Bank 0,
Transmitter Data
Register (TXD)
Bank 0,
7
6
5
4
3
2
1
0
0
0
0
0
0
Reset
Reset
Required
0
Offset 02h
Required
Offset 00h
FIFO_EN
RXSR
TXSR
Reserved
TXFTH0
TXFTH1
RXFTH0
RXFTH1
Transmitted Data
Extended Mode
Link Control
Register (LCR)
All Banks,
7
0
6
0
5
0
4
3
2
0
1
0
7
6
5
4
3
2
0
1
0
Interrupt Enable
Register (IER)
Bank 0,
0
0
0
0
Reset
0
0
0
0
0
0
0
Reset
Offset 03h
Required
0
0
Offset 01h
Required
WLS0
RXHDL_IE
TXLDL_IE
LS_IE or TXUR_IE
MS_IE
DMA_IE
TXEMP_IE
Reserved
Reserved
WLS1
STB
PEN
EPS
STKP
SBRK
BKSE
Non-Extended Modes, Read Cycles
Bank Selection
Register (BSR)
All Banks,
7
0
6
0
5
0
4
3
2
0
1
0
Event Identification
Register (EIR)
Bank 0,
7
6
0
5
0
4
3
2
0
1
0
0
0
0
0
Reset
0
0
0
0
1
Reset
Offset 03h
Required
Offset 02h
0
0
Required
IPF - Interrupt Pending
IPR0 - Interrupt Priority 0
IPR1 - Interrupt Priority 1
RXFT - RX_FIFO Time-Out
Reserved
Reserved
FEN0 - FIFO Enabled
FEN1 - FIFO Enabled
Bank Selected
BKSE-Bank Selection Enable
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
Non-Extended Mode
Non-Extended Mode
7
6
5
4
3
2
1
0
Scratch Register
(SCR)
7
0
6
0
5
0
4
3
2
0
1
0
Modem Control
Register (MCR)
Bank 0,
Reset
0
0
0
0
Reset
Bank 0,
Offset 07h
Required
0
0
0
Required
Offset 04h
DTR
RTS
RILP
ISEN or DCDLP
LOOP
Reserved
Reserved
Reserved
Scratch Data
Extended Mode
Extended Mode
7
0
6
0
5
0
4
3
2
0
1
0
7
6
5
4
3
2
0
1
0
Auxiliary Status
Register (ASCR)
Bank 0,
Modem Control
Register (MCR)
Bank 0,
0
0
0
0
Reset
0
0
0
0
0
0
0
Reset
0
Offset 07h
Offset 04h
Required
Required
DTR
RXF_TOUT
EOF_INF
S_EOT
Reserved
RXWDG
RXACT
TXUR
Reserved
RTS
DMA_EN
TX_DFR
IR_PLS
MDSL0
MDSL1
MDSL2
Legacy Baud Generator Divisor
Non-Extended Mode
7
6
5
4
3
2
1
0
Low Byte Register
7
0
6
1
5
1
4
3
2
0
1
0
Link Status
Register (LSR)
Bank 0,
(LBGD(L)
Bank 1,
Offset 00h
Reset
0
0
0
0
Reset
Required
Offset 05h
Required
RXDA
OE
PE
FE
Least Significant Byte
of Baud Generator
BRK
TXRDY
TXEMP
ER_INF
Legacy Baud Generator Divisor
7
6
5
4
3
2
1
0
7
6
5
4
3
2
0
1
0
0
0
High Byte Register
(LBGD(H))
Modem Status
Register (MSR)
Bank 0,
X
X
X
X
0
Reset
Reset
Bank 1,
Offset 06h
Offset 01h
Required
Required
DCTS
DDSR
TERI
DDCD
CTS
DSR
Most Significant Byte
of Baud Generator
RI
DCD
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
TX_FIFO
Current Level
Register (TXFLV)
Bank 2,
7
0
6
0
5
0
4
3
2
0
1
0
Baud Generator Divisor
Low Byte Register
0
0
0
0
Reset
7
6
x
5
x
4
3
2
1
0
(BGD(L))
0
0
0
x
x
x
x
x
x
Reset
Required
Bank 2,
Offset 00h
Offset 06h
Required
TFL0
TFL1
TFL2
TFL3
TFL4
Least Significant Byte
of Baud Generator
Reserved
RX_FIFO
Current Level
Register (RXFLV)
7
6
5
4
3
2
0
1
0
Baud Generator Divisor
High Byte Register
(BGD(H))
0
0
0
0
0
0
0
Reset
7
6
x
5
x
4
3
2
1
0
0
0
0
Bank 2,
Offset 07h
Required
x
x
x
x
x
x
Reset
Bank 2,
Offset 01h
RFL0
RFL1
Required
RFL2
RFL3
RFL4
Reserved
Most Significant Byte
of Baud Generator
7
0
6
0
5
1
4
3
2
1
0
Module Revision ID
Register
0
x
x
x
x
Reset
(MRID)
Extended Control and
Status Register 1
7
0
6
0
5
0
4
3
2
0
1
0
Required
Bank 3
0
0
0
0
Reset
Offset 00
h
(EXCR1)
Bank 2,
Offset 02h
1
Required
Revision ID(RID 3-0)
EXT_SL
DMANF
DMATH
DMASWP
LOOP
ETDLBK
Reserved
BTEST
Module ID(MID 7-4)
Shadow of
7
0
6
0
5
0
4
3
2
0
1
0
Link Control Register
0
0
0
0
Reset
(SH_LCR)
Bank 3,
Extended Control and
Status Register 2
0
Reset
7
0
6
0
5
0
4
3
2
0
1
0
Required
Offset 01h
0
0
0
(EXCR2)
Bank 2,
Offset 04h
WLS0
0
0
0
0
0
Required
WLS1
STB
PEN
EPS
STKP
SBRK
BKSE
Reserved
PRESL0
PRESL1
Reserved
LOCK
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
Shadow of
FIFO Control Register
7
0
6
0
5
0
4
3
2
0
1
0
7
0
6
0
5
0
4
3
2
0
1
0
SIR Pulse Width
Register
(SH_FCR)
Bank 3,
Offset 02h
0
0
0
0
Reset
0
0
0
0
Reset
(SIR_PW)
Bank 6,
Offset 02h
0
Required
0
0
0
0
Required
FIFO_EN
RXFR
TXFR
Reserved
TXFTH0
TXFHT1
RXFTH0
RXFTH1
SPW(3-0)
Reserved
Infrared Control Register1
7
0
6
0
5
0
4
3
2
0
1
0
Infrared Receiver
Demodulation Control
(IRCR1)
7
0
6
0
5
1
4
3
2
0
1
0
Bank 4,
Offset 02h
0
0
0
0
Reset
Register (IRRXDC)
0
1
0
1
Reset
0
0
0
0
Required
Bank 7,
Offset 00h
Required
DFR0
Reserved
DFR1
DFR2
DFR3
DFR4
DBW0
DBW1
DBW2
IR_SL0
IR_SL1
Reserved
Infrared Control
Register 2
(IRCR2)
7
0
6
0
5
0
4
3
2
0
1
0
Infrared Transmitter
Modulation Control
0
0
1
0
Reset
7
0
6
1
5
1
4
3
2
0
1
0
0
0
0
Bank 5,
Offset 04h
0
1
0
1
Required
Reset
Register
(IRTXMC)
Bank 7,
Required
IR_FDPLX
IRMSSL
Reserved
Reserved
AUX_IRRX
Offset 01h
MCFR(4-0)
Reserved
MCPW(2-0)
7
0
6
0
5
1
4
3
2
0
1
0
Infrared Control
Register 3
(IRCR3)
Consumer-IR Mode
0
0
0
0
Reset
7
0
6
0
5
0
4
3
2
0
1
0
Configuration Register
(RCCFG)
0
0
Required
Bank 6,
Offset 00h
0
0
0
0
Reset
Bank 7,
0
Offset 02h
Required
RC_MMD0
RC_MMD1
TXHSC
Reserved
RCDM_DS
RXHSC
T_OV
R_LEN
Reserved
SHMD_DS
SHDM_DS
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Enhanced Serial Port with IR -UART2 (Logical Device 2)
Infrared Configuration
7
0
6
0
5
0
4
3
2
0
1
0
Register 1
x
Reset
0
0
0
(IRCFG1)
Bank 7,
Offset 04h
Required
IRIC(2-0)
IRID3
SIRC(2-0)
STRV_MS
7
0
6
0
5
0
4
3
2
0
1
0
Infrared Configuration
Register 3
0
0
0
0
Reset
(IRCFG3)
Bank 7,
0
0
Required
Offset 06h
RCLC(2-0)
Reserved
RCHC(2-0)
Reserved
7
0
6
0
5
0
4
3
2
0
1
0
Infrared Configuration
Register 4
0
0
0
0
Reset
(IRCFG4)
Bank 7,
0
0
0
0
Required
Offset 07h
Reserved
IRSL21_DS
RXINV
IRSL0_DS
Reserved
AMCFG
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Enhanced Serial Port - UART1 (Logical Device 3)
The default bank selection after system reset is 0, which
6.0 Enhanced Serial Port - UART1
(Logical Device 3)
places the module in the UART 16550 mode. Additionally,
setting the baud in bank 1 (as required to initialize the 16550
UART) switches the module to a Non-Extended UART
mode. This ensures that running existing 16550 software
will switch the system to the 16550 configuration without
software modification.
UART1 supports serial data communications with a remote
peripheral device or modem using a wired interface. The
module can function as a standard 16450 or 16550, or as
an Extended UART.
Table 6-1 shows the main functions of the registers in each
bank.
This module provides receive and transmit channels that
can operate concurrently in full-duplex mode. This module
performs all functions required to conduct parallel data in-
terchange with the system and composite serial data ex-
change with the external data channel, including:
TABLE 6-1. Register Bank Summary
Bank
Main Functions
●
Format conversion between the internal parallel data
format and the external programmable composite seri-
al format. See Figure 6-2.
0
1
2
Global Control and Status
Legacy Bank
Baud Generator Divisor,
Extended Control and Status
●
Serial data timing generation and recognition.
●
Parallel data interchange with the system using a
choice of bi-directional data transfer mechanisms.
3
Module Revision ID and
Shadow Registers
●
Status monitoring for all phases of communications
Banks 0 and 1 are the 16550 register banks. The registers
in these banks are equivalent to the registers contained
in the 16550 UARTs and are accessed by 16550 soft-
ware drivers as if the module was a 16550. Bank 1 con-
tains the legacy Baud Generator Divisor Ports. Bank 0
registers control all other aspects of the UART function,
including data transfers, format setup parameters, inter-
rupt setup and status monitoring.
activity.
Existing 16550-based legacy software is completely and
transparently supported. Module organization and specific
fallback mechanisms switch the module to 16550 compatibil-
ity mode upon reset or when initialized by 16550 software.
6.1 REGISTER BANK OVERVIEW
Four register banks, each containing eight registers, control
UART operation. All registers use the same 8-byte address
space to indicate offsets 00h through 07h, and the active
bank must be selected by the software.
Bank 2 contains the non-legacy Baud Generator Divisor
Ports, and controls the extended features special to this
UART, that are not included in the 16550 repertoire. See
”Extended UART Mode” on page 137.
The register bank organization enables access to the banks
as required for activation of all module modes, while main-
taining transparent compatibility with 16450 or 16550 soft-
ware, which activates only the registers and specific bits
used in those devices. For details, See Section 6.2.
Bank 3 contains the Module Revision ID and shadow regis-
ters. The Module Revision ID (MRID) register contains
a code that identifies the revision of the module when
read by software. The shadow registers contain the
identical content as reset-when-read registers within
bank 0. Reading their contents from the shadow regis-
ters lets the system read the register content without re-
setting them.
The Bank Selection Register (BSR) selects the active bank
and is common to all banks. See Figure 6-1. Therefore,
each bank defines seven new registers.
6.2 DETAILED DESCRIPTION
BANK 3
BANK 2
BANK 1
The module provides receive and transmit channels that
can operate concurrently in full-duplex mode. This module
performs all functions required to conduct parallel data in-
terchange with the system and composite serial data ex-
change with the external data channel, including:
BANK 0
Offset 07h
Offset 06h
Offset 05h
●
Format conversion between the internal parallel data
format and the external programmable composite seri-
al format. See Figure 6-2.
●
Serial data timing generation and recognition
●
Parallel data interchange with the system using a
choice of bi-directional data transfer mechanisms
Offset 04h
Common
LCR/BSR
●
Register
Status monitoring for all phases of the communica-
tions activity
Throughout
Offset 02h
All Banks
Offset 01h
The module supplies modem control registers, and a prior-
itized interrupt system for efficient interrupt handling.
Offset 00h
16550 Banks
FIGURE 6-1. Register Bank Architecture
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136
Enhanced Serial Port - UART1 (Logical Device 3)
16450 or 16550 UART Mode - see page 148). Each divisor value yields a clock signal
6.2.1
(BOUT) and a further division by 16 produces the baud rate
clock for the serial data stream. It may also be output as a
test signal when enabled (see bit 7 of EXCR1 on page 149.)
The module defaults to 16450 mode after power up or reset.
UART 16550 mode is equivalent to 16450 mode, with the
addition of a 16-byte data FIFO for more efficient data I/O.
Transparent compatibility is maintained with this UART
mode in this module.
These user-selectable parameters enable the user to gen-
erate a large choice of serial data rates, including all stan-
dard baud rates. A list of baud rates and their settings
appears in Table 6-12 on page 148.
Despite the many additions to the basic UART hardware
and organization, the UART responds correctly to existing
software drivers with no software modification required.
When 16450 software initializes and addresses this mod-
ule, it will in always perform as a 16450 device.
Module Operation
Before module operation can begin, both the communica-
tions format and baud rate must be programmed by the soft-
ware. The communications format is programmed by
loading a control byte into the LCR register, while the baud
rate is selected by loading an appropriate value into the
baud rate generator divisor registers and the divisor prese-
lect values (PRESL) into EXCR2 (see page 149).
Data transfer takes place by use of data buffers that inter-
face internally in parallel and with the external data channel
in a serial format. 16-byte data FIFOs may reduce host
overhead by enabling multiple-byte data transfers within a
single interrupt. With FIFOs disabled, this module is equiv-
alent to the standard 16450 UART. With FIFOs enabled, the
hardware functions as a standard 16550 UART.
The software can read the status of the module at any time
during operation. The status information includes full or
empty state for both transmission and reception channels,
and any other condition detected on the received data
stream, like parity error, framing error, data overrun, or
break event.
The composite serial data stream interfaces with the data
channel through signal conditioning circuitry such as
TTL/RS232 converters, modem tone generators, etc.
Data transfer is accompanied by software-generated con-
trol signals, which may be utilized to activate the communi-
cations channel and “handshake” with the remote device.
These may be supplied directly by the UART, or generated
by control interface circuits such as telephone dialing and
answering circuits, etc.
6.2.2
Extended UART Mode
In Extended UART mode of operation, the module configu-
ration changes and additional features become available
which enhance UART capabilities.
●
The interrupt sources are no longer prioritized; they
START
-LSB- DATA 5-8 -MSB-
PARITY
STOP
are presented bit-by-bit in the EIR (see page 140).
●
An auxiliary status and control register replaces the
FIGURE 6-2. Composite Serial Data
scratchpad register. It contains additional status and
control flag bits (“Auxiliary Status and Control Register
(ASCR)” on page 146).
The composite serial data stream produced by the UART is
illustrated in Figure 6-2. A data word containing five to eight
bits is preceded by start bits and followed by an optional
parity bit and a stop bit. The data is clocked out, LSB first,
at a predetermined rate (the baud).
●
The TX_FIFO can generate interrupts when the num-
ber of outgoing bytes in the TX_FIFO drops below a
programmable threshold. In the Non-Extended UART
modes, only reception FIFOs have the thresholding
feature.
The data word length, parity bit option, number of start bits
and baud rate are programmable parameters.
The UART includes a programmable baud rate generator
that produces the baud rate clocks and associated timing
signals for serial communication.
6.3 FIFO TIME-OUTS
Time-out mechanisms prevent received data from remain-
ing in the RX_FIFO indefinitely, if the programmed interrupt
threshold is not reached.
The system can monitor this module status at any time. Sta-
tus information includes the type and condition of the trans-
fer operation in process, as well as any error conditions
(e.g., parity, overrun, framing, or break interrupt).
An RX_FIFO time-out generates a Receiver Data Ready in-
terrupt if bit 0 of IER is set to 1. An RX_FIFO time-out also
sets bit 0 of ASCR to 1 if the RX_FIFO is below the thresh-
old. When a Receiver Data Ready interrupt occurs, this bit
is tested by the software to determine whether a number of
bytes indicated by the RX_FIFO threshold can be read with-
out checking bit 0 of the LSR register.
The module resources include modem control capability
and a prioritized interrupt system. Interrupts can be pro-
grammed to match system requirements, minimizing the
CPU overhead required to handle the communications
Line.
The conditions that must exist for a time-out to occur in the
various modes of operation are described below.
Programmable Baud Generator
When a time-out has occurred, it can only be reset when the
FIFO is read by the CPU.
This module contains a programmable baud rate generator
that generates the clock rates for serial data communication
(both transmit and receive channels). It divides its input
clock by any divisor value from 1 to 216 - 1. The output clock
frequency of the baud rate generator must be programmed
to be sixteen times the baud rate value. A 24 MHz input fre-
quency is divided by a prescale value (PRESL field of
EXCR2 - see page 149. Its default value is 13) and by a 16-
bit programmable divisor value contained in the Baud Gen-
erator Divisor High and Low registers (BGD(H) and BGD(L)
Time-out event A generates an interrupt and sets the
RXF_TOUT bit (bit 0 of ASCR) when all of the following are
true:
●
At least one byte is in the RX_FIFO, and
●
More than 64 µsec or four character times, whichever is
greater, have elapsed since the last byte was loaded
into the RX_FIFO from the receiver logic, and
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137
Enhanced Serial Port - UART1 (Logical Device 3)
●
no bytes are loaded for a 64-µsec time, the timer times out
and the internal flag is cleared, thus enabling the transmit-
ter.
More than 64 µsec or four character times, whichever is
greater, have elapsed since the last byte was read from
the RX_FIFO by the CPU.
6.5 BANK 0 – GLOBAL CONTROL AND STATUS
REGISTERS
6.4 AUTOMATIC FALLBACK TO A NON-EXTENDED
UART MODE
In the Non-Extended modes of operation, bank 0 is compat-
ible with both the 16450 and the 16550. Upon reset, this
module defaults to the 16450 mode. In the Extended mode,
all the Registers (except RXD/ TXD) offer additional fea-
tures.
The automatic fallback feature supports existing legacy
software packages that use the 16550 UART by automati-
cally turning off any Extended mode features and switches
the UART to Non-Extended mode when either of the LB-
GD(L) or LBGD(H) ports in bank 1 is read from or written to
by the CPU.
TABLE 6-2. Bank 0 Serial Controller Base Registers
This eliminates the need for user intervention prior to run-
ning a legacy program.
Register
Name
Offset
Description
In order to avoid spurious fallbacks, alternate baud rate reg-
isters are provided in bank 2. Any program designed to take
advantage of the UART’s extended features, should not use
LBGD(L) and LBGD(H) to change the baud rate. It should
use the BGD(L) and BGD(H) registers instead. Access to
these ports will not cause fallback.
00h
RXD/ Receiver Data Port/ Transmitter Data
TXD
IER
Port
01h
02h
Interrupt Enable Register
EIR/
FCR
Event Identification Register/
FIFO Control Register
Fallback can occur in any mode. In Extended UART mode,
fallback is always enabled. In this case, when a fallback oc-
curs, the following happens:
03h
LCR/
BSR
Line Control Register/
Bank Select Register
●
Transmission and Reception FIFOs switch to 16 levels.
04h
05h
06h
07h
MCR
LSR
Modem Control Register
Line Status Register
Modem Status Register
Scratch Register/
●
A value of 13 is selected for the baud rate generator
prescaler
MSR
●
The BTEST and ETDLBK bits in the EXCR1 register
SCR/
are cleared.
ASCR Auxiliary Status and Control Register
●
UART mode is selected.
6.5.1
Receiver Data Port (RXD) or the Transmitter
Data Port (TXD)
●
A switch to a Non-Extended UART mode occurs.
When a fallback occurs in a Non-Extended UART mode, the
last two of the above actions do not take place.
These ports share the same address.
RXD is accessed during CPU read cycles. It is used to read
data from the Receiver Holding Register when the FIFOs
are disabled, or from the bottom of the RX_FIFO when the
FIFOs are enabled.
Fallback from a Non-Extended mode can be disabled by
setting the LOCK bit in register EXCR2. When LOCK is set
to 1 and the UART is in a Non-Extended mode, two scratch
registers overlaid with LBGD(L) and LBGD(H) are enabled.
Any attempted CPU access of LBGD(L) and LBGD(H) ac-
cesses the scratch registers, and the baud rate setting is not
affected. This feature allows existing legacy programs to
run faster than 115.2 Kbps.
Receiver Data Port (RXD)
Receiver Data
Port (RXD)
Bank 0,
7
6
5
4
3
2
1
0
Reset
6.4.1
Transmission Deferral
Offset 00h
Required
This feature allows software to send high-speed data in Pro-
grammed Input/Output (PIO) mode without the risk of gen-
erating a transmitter underrun.
Transmission deferral is available only in Extended mode
and when the TX_FIFO is enabled. When transmission de-
ferral is enabled (TX_DFR bit in the MCR register set to 1)
and the transmitter becomes empty, an internal flag is set
and locks the transmitter. If the CPU now writes data into
the TX_FIFO, the transmitter does not start sending the
data until the TX_FIFO level reaches 14 at which time the
internal flag is cleared. The internal flag is also cleared and
the transmitter starts transmitting when a time-out condition
is reached. This prevents some bytes from being in the
TX_FIFO indefinitely if the threshold is not reached.
Received Data
Bits 7-0 - Received Data
Used to access the Receiver Holding Register when the
FIFOs are disabled, or the bottom of the RX_FIFO when
the FIFOs are enabled.
The time-out mechanism is implemented by a timer that is
enabled when the internal flag is set and there is at least
one byte in the TX_FIFO. Whenever a byte is loaded into
the TX_FIFO the timer gets reloaded with the initial value. If
TXD is accessed during CPU write cycles. It is used to write
data to the Transmitter Holding Register when the FIFOs
are disabled, or to the TX_FIFO when the FIFOs are en-
abled.
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Enhanced Serial Port - UART1 (Logical Device 3)
IER in Non-Extended Modes
Transmitter Data
Port (TXD)
Bank 0,
7
6
5
4
3
2
1
0
7
0
6
0
5
0
4
3
2
0
1
0
Interrupt Enable
Reset
Required
Register (IER)
0
0
0
0
Reset
Bank 0,
Offset 00h
Required
Offset 01h
RXHDL_IE
TXLDL_IE
LS_IE
MS_IE
Reserved
Reserved
Reserved
Reserved
Transmitted Data
Bits 7-0 - Transmitted Data
Bit 0 - Receiver High-Data-Level Interrupt Enable
(RXHDL_IE)
Used to access the Transmitter Holding Register when
the FIFOs are disabled or the top of TX_FIFO when the
FIFOs are enabled.
Setting this bit enables interrupts on Receiver High-
Data-Level, or RX_FIFO Time-Out events (EIR Bits 3-0
are 0100 or 1100. See Table 6-3 on page 141).
6.5.2
Interrupt Enable Register (IER)
0: Disable Receiver High-Data-Level and RX_FIFO
Time-Out interrupts (Default).
This register controls the enabling of various interrupts.
Some interrupts are common to all operating modes of the
module, while others are mode specific. Bits 4 to 7 can be
set in Extended mode only. They are cleared in Non-Ex-
tended mode. The bits of the Interrupt Enable Register
(IER) are defined differently, depending on operating the
module in Extended or Non-Extended mode.
1: Enable Receiver High-Data-Level and RX_FIFO
Time-Out interrupts.
Bit 1 - Transmitter Low-Data-Level Interrupt Enable
(TXLDL_IE)
The following sections describe the bits in this register for
each of these modes.
Setting this bit enables interrupts on Transmitter Low
Data-Level-events (EIR Bits 3-0 are 0010. See Table
6-3 on page 141).
The reset mode for the IER is the Non-Extended UART
mode.
0: Disable Transmitter Low-Data-Level Interrupts (De-
fault).
When edge-sensitive interrupt triggers are employed, user is
advised to clear all IER bits immediately upon entering the in-
terrupt service routine and to re-enable them prior to exiting
(or alternatively, to disable CPU interrupts and re-enable pri-
or to exiting). This will guarantee proper interrupt triggering in
the interrupt controller in case one or more interrupt events
occur during execution of the interrupt routine.
1: Enable Transmitter Low-Data-Level Interrupts.
Bit 2 - Line Status Interrupt Enable (LS_IE)
Setting this bit enables interrupts on Line Status events.
(EIR Bits 3-0 are 0110. See Table 6-3 on page 141).
0: Disable Line Status Interrupts (LS_EV) (Default).
1: Enable Line Status Interrupts (LS_EV).
If the LSR, MSR or EIR registers are to be polled, interrupt
sources which are identified by self-clearing bits should
have their corresponding IER bits set to 0, to prevent spuri-
ous pulses on the interrupt output pin.
Bit 3 - Modem Status Interrupt Enable (MS_IE)
Setting this bit enables the interrupts on Modem Status
events. (EIR Bits 3-0 are 0000. See Table 6-3 on page
141).
If an interrupt source must be disabled, the CPU can do so
by clearing the corresponding bit in the IER register. How-
ever, if an interrupt event occurs just before the correspond-
ing enable bit in the IER register is cleared, a spurious
interrupt may be generated. To avoid this problem, the
clearing of any IER bit should be done during execution of
the interrupt service routine. If the interrupt controller is pro-
grammed for level-sensitive interrupts, the clearing of IER
bits can also be performed outside the interrupt service rou-
tine, but with the CPU interrupt disabled.
0 - Disable Modem Status Interrupts (MS_EV) (De-
fault).
1: Enable Modem Status Interrupts (MS_EV).
Bits 7-4- Reserved
These bits are reserved.
Interrupt Enable Register (IER), in the Non-Extended
Mode
Upon reset, the IER supports the Non-Extended mode. See
the bitmap of the Interrupt Enable Register in these modes.
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Enhanced Serial Port - UART1 (Logical Device 3)
Interrupt Enable Register (IER), in the Extended Mode
6.5.3
Event Identification Register (EIR)
The Event Identification Register (EIR) and the FIFO
Control Register (FCR) (see next register description)
share the same address. The EIR is accessed during CPU
read cycles while the FCR is accessed during CPU write cy-
cles.The Event Identification Register (EIR) indicates the in-
terrupt source. The function of this register changes
according to the selected mode of operation.
See the bitmap of the Interrupt Enable Register in these
mode.
IER in Extended Mode
7
0
6
0
5
0
4
3
2
0
1
0
Interrupt Enable
Register (IER)
0
0
0
0
Reset
Bank 0,
Event Identification Register (EIR), Non-Extended Mode
Required
Offset 01h
When Extended mode is not selected (EXT_SL bit in
EXCR1 register is set to 0), this register is the same as in
the 16550.
RXHDL_IE
TXLDL_IE
LS_IE
MS_IE
Reserved
TXEMP_IE
Reserved
Reserved
In a Non-Extended UART mode, this module prioritizes in-
terrupts into four levels. The EIR indicates the highest level
of interrupt that is pending. The encoding of these interrupts
is shown in Table 6-3 on page 141.
Non-Extended Modes, Read Cycles
Event Identification
Register (EIR)
Bank 0,
7
0
6
0
5
0
4
3
2
0
1
0
Bit 0 - Receiver High-Data-Level Interrupt Enable
(RXHDL_IE)
0
0
0
1
Reset
Offset 02h
0
0
Required
Setting this bit enables interrupts when the RX_FIFO is
equal to or above the RX_FIFO threshold level, or an
RX_FIFO time out occurs.
IPF - Interrupt Pending
IPR0 - Interrupt Priority 0
IPR1 - Interrupt Priority 1
RXFT - RX_FIFO Time-Out
Reserved
Reserved
FEN0 - FIFOs Enabled
FEN1 - FIFOs Enabled
0: Disable Receiver Data Ready interrupt. (Default)
1: Enable Receiver Data Ready interrupt.
Bit 1 - Transmitter Low-Data-Level Interrupt Enable
(TXLDL_IE)
Setting this bit enables interrupts when the TX_FIFO is
below the threshold level or the Transmitter Holding
Register is empty.
Bit 0 - Interrupt Pending Flag (IPF)
0: There is an interrupt pending.
1: No interrupt pending. (Default)
0: Disable Transmitter Low-Data-Level Interrupts (De-
fault).
1: Enable Transmitter Low-Data-Level Interrupts.
Bits 2,1 - Interrupt Priority 1,0 (IPR1,0)
Bit 2 - Line Status Interrupt Enable (LS_IE)
When bit 0 (IPF) is 0, these bits indicate the pending in-
terrupt with the highest priority. See Table 6-3 on page
141.
Setting this bit enables interrupts on Line Status events.
0: Disable Line Status Interrupts (LS_EV) (Default)
1: Enable Line Status Interrupts (LS_EV).
Default value is 00.
Bit 3 - Modem Status Interrupt Enable (MS_IE)
Bit 3 - RX_FIFO Time-Out (RXFT)
Setting this bit enables the interrupts on Modem Status
events.
In the 16450 mode, this bit is always 0. In the 16550
mode (FIFOs enabled), this bit is set to 1 when an
RX_FIFO read time-out occurred and the associated in-
terrupt is currently the highest priority pending interrupt.
0: Disable Modem Status Interrupts (MS_EV) (Default)
1: Enable Modem Status Interrupts (MS_EV).
Bits 5,4 - Reserved
Read/Write 0.
Bit 4 - Reserved
Reserved.
Bit 7,6 - FIFOs Enabled (FEN1,0)
Bit 5 - Transmitter Empty Interrupt Enable (TXEMP_IE)
0: No FIFO enabled. (Default)
Setting this bit enables interrupt generation if the trans-
mitter and TX_FIFO become empty.
1: FIFOs are enabled (bit 0 of FCR is set to 1).
0: Disable Transmitter Empty interrupts (Default)
1: Enable Transmitter Empty interrupts.
Bits 7,6 - Reserved
Reserved.
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Enhanced Serial Port - UART1 (Logical Device 3)
TABLE 6-3. Non-Extended Mode Interrupt Priorities
Interrupt Set and Reset Functions
EIR Bits
3 2 1 0
Priority
Level
Interrupt Type
Interrupt Source
Interrupt Reset Control
0 0 0 1
0 1 1 0
None
None
−
−
Highest
Line Status
Parity error, framing error, data overrun Read Line Status Register (LSR).
or break event
0 1 0 0
1 1 0 0
Second
Second
Receiver High Receiver Holding Register (RXD) full, or Reading the RXD or, RX_FIFO level
Data Level
Event
RX_FIFO level equal to or above
threshold.
drops below threshold.
RX_FIFO Time- At least one character is in the
Reading the RXD port.
Out
RX_FIFO, and no character has been
input to or read from the RX_FIFO for 4
character times.
0 0 1 0
0 0 0 0
Third
Transmitter Low Transmitter Holding Register or
Reading the EIR Register if this
interrupt is currently the highest
priority pending interrupt, or writing
into the TXD port.
Data Level
Event
TX_FIFO empty.
Fourth
Modem Status Any transition on CTS, DSR or DCD or a Reading the Modem Status Register
low to high transition on RI.
(MSR).
Event Identification Register (EIR), Extended Mode
Bit 2 - Line Status Event (LS_EV) or Transmitter Halted
Event (TXHLT_EV)
In Extended mode, each of the previously prioritized and
encoded interrupt sources is broken down into individual
bits. Each bit in this register acts as an interrupt pending
flag, and is set to 1 when the corresponding event occurred
or is pending, regardless of the IER register bit setting.
This bit is set to 1 when a receiver error or break condi-
tion is reported.
When FIFOs are enabled, the Parity Error(PE), Frame
Error(FE) and Break(BRK) conditions are only reported
when the associated character reaches the bottom of
the RX_FIFO. An Overrun Error (OE) is reported as
soon as it occurs.
Extended Mode, Read Cycles
Event Identification
Register (EIR)
Bank 0,
7
0
6
0
5
0
4
3
2
0
1
0
Bit 3 - Modem Status Event (MS_EV)
0
0
0
1
Reset
In UART mode this bit is set to 1 when any of the 0 to 3
bits in the MSR register is set to 1.
Offset 02h
Required
RXHDL_EV
Bit 4 - Reserved
Read/Write 0.
TXLDL_EV
LS_EV or TXHLT_EV
MS_EV
Reserved
TXEMP-EV
Reserved
Reserved
Bit 5 - Transmitter Empty (TXEMP_EV)
This bit is the same as bit 6 of the LSR register. It is set
to 1 when the transmitter is empty.
Bits 7,6 - Reserved
Read/Write 0.
Bit 0 - Receiver High-Data-Level Event (RXHDL_EV)
When FIFOs are disabled, this bit is set to 1 when a
character is in the Receiver Holding Register.
When FIFOs are enabled, this bit is set to 1 when the
RX_FIFO is above threshold or an RX_FIFO time-out
has occurred.
Bit 1 - Transmitter Low-Data-Level Event (TXLDL_EV)
When FIFOs are disabled, this bit is set to 1 when the
Transmitter Holding Register is empty.
When FIFOs are enabled, this bit is set to 1 when the
TX_FIFO is below the threshold level.
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Enhanced Serial Port - UART1 (Logical Device 3)
6.5.4
FIFO Control Register (FCR)
TABLE 6-5. RX_FIFO Level Selection
RXFTH (Bits 5,4) RX_FIF0 Threshold
The FIFO Control Register (FCR) is write only. It is used to
enable the FIFOs, clear the FIFOs and set the interrupt
thresholds levels for the reception and transmission FIFOs.
00(Default)
1
4
01
10
11
Write Cycles
8
7
0
6
0
5
0
4
3
2
0
1
0
FIFO Control
Register (FCR)
Bank 0,
14
0
0
0
0
Reset
0
Offset 02h
Required
6.5.5
Line Control Register (LCR) and Bank
Selection Register (BSR)
FIFO_EN
The Line Control Register (LCR) and the Bank Select
Register (BSR) (see the next register) share the same ad-
dress.
RXSR
TXSR
Reserved
TXFTH0
TXFTH1
RXFTH0
RXFTH1
The Line Control Register (LCR) selects the communica-
tions format for data transfers.
Upon reset, all bits are set to 0.
Reading the register at this address location returns the
content of the BSR. The content of LCR may be read from
the Shadow of Line Control Register (SH_LCR) register in
bank 3 (See Section 6.8.2 on page 151). During a write op-
eration to this register at this address location, the setting of
bit 7 (Bank Select Enable, BKSE) determines whether LCR
or BSR is to be accessed, as follows:
Bit 0 - FIFO Enable (FIFO_EN)
When set to 1 enables both the Transmision and Recep-
tion FIFOs. Resetting this bit clears both FIFOs.
Bit 1 - Receiver Soft Reset (RXSR)
●
Writing a 1 to this bit generates a receiver soft reset,
which clears the RX_FIFO and the receiver logic. This
bit is automatically cleared by the hardware.
If bit 7 is 0, the write affects both LCR and BSR.
●
If bit 7 is 1, the write affects only BSR, and LCR remains
unchanged. This prevents the communications format
from being spuriously affected when a bank other than
0 or 1 is accessed.
Bit 2 - Transmitter Soft Reset (TXSR)
Writing a 1 to this bit generates a transmitter soft reset,
which clears the TX_FIFO and the transmitter logic. This
bit is automatically cleared by the hardware.
Upon reset, all bits are set to 0.
Line Control Register (LCR)
Bit 3 - Reserved
Read/Write 0.
Line Control
Register (LCR)
All Banks,
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
0
Reset
Bits 5,4 - TX_FIFO Threshold Level (TXFTH1,0)
Offset 03h
In Non-Extended modes, these bits have no effect.
Required
In Extended modes, these bits select the TX_FIFO in-
terrupt threshold level. An interrupt is generated when
the level of the data in the TX_FIFO drops below the en-
coded threshold.
WLS0
WLS1
STB
PEN
EPS
STKP
SBRK
BKSE
TABLE 6-4. TX_FIFO Level Selection
TXFTH (Bits 5,4) TX_FIF0 Threshold
00(Default)
1
3
01
10
11
Bits 1,0 - Character Length Select (WLS1,0)
9
These bits specify the number of data bits in each trans-
mitted or received serial character. Table 6-6 shows
how to encode these bits.
13
Bits 7,6 - RX_FIFO Threshold Level (RXFTH1,0)
TABLE 6-6. Word Length Select Encoding
These bits select the RX_FIFO interrupt threshold level.
An interrupt is generated when the level of the data in
the RX_FIFO is equal to or above the encoded thresh-
old.
WLS1
WLS0
Character Length
0
0
1
1
0
1
0
1
5 (Default)
6
7
8
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Enhanced Serial Port - UART1 (Logical Device 3)
1: This register functions as the Bank Select Register
Bits 2 - Number of Stop Bits (STB)
(BSR).
This bit specifies the number of stop bits transmitted
with each serial character.
6.5.6
Bank Selection Register (BSR)
0: One stop bit is generated. (Default)
1: If the data length is set to 5-bits via bits 1,0
(WLS1,0), 1.5 stop bits are generated. For 6, 7 or 8
bit word lengths, two stop bits are transmitted. The
receiver checks for one stop bit only, regardless of
the number of stop bits selected.
Bank Selection
Register (BSR)
All Banks,
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
0
Reset
Offset 03h
Required
Bit 3 - Parity Enable (PEN)
This bit enable the parity bit See Table 6-7 on page 143.
The parity enable bit is used to produce an even or odd
number of 1s when the data bits and parity bit are
summed, as an error detection device.
Bank Selection
0: No parity bit is used. (Default)
1: A parity bit is generated by the transmitter and
checked by the receiver.
BKSE-Bank Selection Enable
The Bank Selection Register (BSR) selects which register
bank is to be accessed next.
Bit 4 - Even Parity Select (EPS)
When Parity is enabled (PEN is 1), this bit, together with
bit 5 (STKP), controls the parity bit as shown in Table
6-7.
About accessing this register see the description of bit 7 of
the LCR Register.
0: If parity is enabled, an odd number of logic 1s are
transmitted or checked in the data word bits and
parity bit. (Default)
Bits 6-0 - Bank Selection
When bit 7 is set to 1, bits 6-0 of BSR select the bank,
as shown in Table 6-8.
1: If parity is enabled, an even number of logic 1s are
transmitted or checked.
Bit 7 - Bank Selection Enable (BKSE)
0: Bank 0 is selected.
Bit 5 - Stick Parity (STKP)
1: Bits 6-0 specify the selected bank.
When Parity is enabled (PEN is 1), this bit, together with
bit 4 (EPS), controls the parity bit as show in Table 6-7.
TABLE 6-8. Bank Selection Encoding
TABLE 6-7. Bit Settings for Parity Control
BSR Bits
Bank
LCR
PEN
EPS
STKP
Selected Parity Bit
Selected
7
6
5
4
3
2
1
0
0
1
1
1
1
x
0
1
0
1
x
0
0
1
1
None
Odd
0
1
1
1
1
1
x
0
1
1
1
1
x
x
x
x
1
1
x
x
x
x
0
0
x
x
x
x
0
0
x
x
x
x
0
1
x
x
1
x
0
0
x
x
x
1
0
0
0
1
1
1
2
3
LCR is writ-
ten
Even
Logic 1
Logic 0
LCR is not
written
Bit 6 - Set Break (SBRK)
This bit enables or disables a break. During the break,
the transmitter can be used as a character timer to ac-
curately establish the break duration.
6.5.7
Modem/Mode Control Register (MCR)
This register controls the interface with the modem or data
communications set, and the device operational mode
when the device is in the Extended mode. The register
function differs for Extended and Non-Extended modes.
This bit acts only on the transmitter front-end and has no
effect on the rest of the transmitter logic.
When set to 1 the SOUT pin is forced to a logic 0 state.
To avoid transmission of erroneous characters as a re-
sult of the break, use the following procedure to set
SBRK:
1. Wait for the transmitter to be empty. (TXEMP = 1).
2. Set SBRK to 1.
3. Wait for the transmitter to be empty, and clear SBRK
when normal transmission must be restored.
Bit 7 - Bank Select Enable (BKSE)
0: This register functions as the Line Control Register
(LCR).
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Enhanced Serial Port - UART1 (Logical Device 3)
Modem/Mode Control Register (MCR), Non-Extended
Mode
Extended Mode
Non-Extended UART mode
7
0
6
0
5
0
4
3
2
0
1
0
Modem Control
Register (MCR)
Bank 0,
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
0
Reset
Modem Control
Register (MCR)
Bank 0,
0
0
0
0
Reset
0
0
0
0
Offset 04h
Required
0
0
0
Offset 04h
Required
DTR
RTS
Reserved
TX_DFR
DTR
RTS
RILP
ISEN or DCDLP
LOOP
Reserved
Reserved
Bit 0 - Data Terminal Ready (DTR)
This bit controls the DTR signal output. When set to1,
DTR is driven low. When loopback is enabled (LOOP is
set), this bit internally drives both DSR and RI.
Bit 0 - Data Terminal Ready (DTR)
This bit controls the DTR signal output. When set to 1,
DTR is driven low. When loopback is enabled (LOOP is
set to 1), this bit internally drives DSR.
Bit 1 - Request To Send (RTS)
This bit controls the RTS signal output. When set to1,
RTS is driven low. When loopback is enabled (LOOP is
set), this bit internally drives both CTS and DCD.
Bit 1 - Request To Send (RTS)
This bit controls the RTS signal output. When set to 1,
drives RTS low. When loopback is enabled (LOOP is
set), this bit drives CTS, internally.
Bit 2 - Reserved
Read/Write 0.
Bit 2 - Loopback Interrupt Request (RILP)
When loopback is enabled, this bit internally drives RI.
Otherwise it is unused.
Bit 3 - Transmission Deferral (TX_DFR)
For a detailed description of the Transmission Deferral
see “Fallback from a Non-Extended mode can be dis-
abled by setting the LOCK bit in register EXCR2. When
LOCK is set to 1 and the UART is in a Non-Extended
mode, two scratch registers overlaid with LBGD(L) and
LBGD(H) are enabled. Any attempted CPU access of
LBGD(L) and LBGD(H) accesses the scratch registers,
and the baud rate setting is not affected. This feature al-
lows existing legacy programs to run faster than 115.2
Kbps.” on page 138.
Bit 3 - Interrupt Signal Enable (ISEN) or Loopback DCD
(DCDLP)
In normal operation (standard 16450 or 16550) mode,
this bit controls the interrupt signal and must be set to 1
in order to enable the interrupt request signal.
When loopback is enabled, the interrupt output signal is
always enabled, and this bit internally drives DCD.
New programs should always keep this bit set to 1 dur-
ing normal operation. The interrupt signal should be
controlled through the Plug-n-Play logic.
0: No transmission deferral enabled. (Default)
1: Transmission deferral enabled.
This bit is effective only if the Transmission FIFOs is en-
abled.
Bit 4 - Loopback Enable (LOOP)
When this bit is set to 1, it enables loopback. This bit ac-
cesses the same internal register as bit 4 of the EXCR1
register. (see “Bit 4 - Loopback Enable (LOOP)” on page
149 for more information on the Loopback mode).
Bits 7- 4 - Reserved
Read/Write 0.
0: Loopback disabled. (Default)
1: Loopback enabled.
6.5.8
Line Status Register (LSR)
This register provides status information concerning the
data transfer. They are cleared when one of the following
events occurs:
Bits 7-5 - Reserved
Read/Write 0.
●
.
●
Modem/Mode Control Register (MCR), Extended Mode
The receiver is soft-reset.
●
In Extended mode the interrupt output signal is always en-
abled, and loopback can be enabled by setting bit 4 of the
EXCR1 register.
The LSR register is read.
Upon reset this register assumes the value of 0x60h.
The bit definitions change depending upon the operation
mode of the module.
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Enhanced Serial Port - UART1 (Logical Device 3)
Bits 4 through 1 of the LSR are the error conditions that gen-
After a framing error is detected, the receiver will try to
erate a Receiver Line Status interrupt whenever any of the
corresponding conditions are detected and that interrupt is
enabled.
resynchronize.
If the bit following the erroneous stop bit is 0, the receiv-
er assumes it to be a valid start bit and shifts in the new
character. If that bit is a 1, the receiver enters the idle
state and awaits the next start bit.
The LSR is intended for read operations only. Writing to the
LSR is not permitted
This bit is cleared upon read.
7
0
6
1
5
1
4
3
2
0
1
0
Line Status
Register (LSR)
Bank 0,
Bit 4 - Break Event Detected (BRK)
0
0
0
0
Reset
This bit is set to 1 when a break event is detected (i.e.
when a sequence of logic 0 bits, equal or longer than a
full character transmission, is received). If the FIFOs are
enabled, the break condition is associated with the par-
ticular character in the RX_FIFO to which it applies. In
this case, the BRK bit is set when the character reaches
the bottom of the RX_FIFO.
Offset 05h
Required
RXDA
OE
PE
FE
When a break event occurs, only one zero character is
transferred to the Receiver Holding Register or to the
RX_FIFO.
BRK
TXRDY
TXEMP
ER_INF
The next character transfer takes place after at least
one logic 1 bit is received followed by a valid start bit.
This bit is cleared upon read.
Bit 0 - Receiver Data Available (RXDA)
Set to 1 when the Receiver Holding Register is full.
Bit 5 - Transmitter Ready (TXRDY)
If the FIFOs are enabled, this bit is set when at least one
character is in the RX_FIFO.
This bit is set to 1 when the Transmitter Holding Regis-
ter or the TX_FIFO is empty.
Cleared when the CPU reads all the data in the Holding
Register or in the RX_FIFO.
It is cleared when a data character is written to the TXD
register.
Bit 1 - Overrun Error (OE)
Bit 6 - Transmitter Empty (TXEMP)
This bit is set to 1 as soon as an overrun condition is de-
tected by the receiver.
This bit is set to 1 when the Transmitter Holding Regis-
ter or the TX_FIFO is empty, and the transmitter front-
end is idle.
Cleared upon read.
With FIFOs Disabled:
Bit 7 - Error in RX_FIFO (ER_INF)
An overrun occurs when a new character is completely
received into the receiver front-end section and the CPU
has not yet read the previous character in the receiver
holding register. The new character is discarded, and
the receiver holding register is not affected.
This bit is set to a 1 if there is at least 1 framing error,
parity error or break indication in the RX_FIFO.
This bit is always 0 in the 16450 mode.
This bit is cleared upon read.
With FIFOs Enabled:
6.5.9
Modem Status Register (MSR)
An overrun occurs when a new character is completely
received into the receiver front-end section and the
RX_FIFO is full. The new character is discarded, and
the RX_FIFO is not affected.
The function of this register depends on the selected oper-
ational mode. When a UART mode is selected, this register
provides the current-state as well as state-change informa-
tion of the status lines from the modem or data transmission
module.
Bit 2 - Parity Error (PE)
This bit is set to 1 if the received data character does not
have the correct parity, even or odd as selected by the
parity control bits of the LCR register.
When loopback is enabled, the MSR register works similar-
ly except that its status input signals are internally driven by
appropriate bits in the MCR register since the modem input
lines are internally disconnected. Refer to at the MCR (see
page 143) and to the LOOP & ETDLBK bits at the EXCR1
(see page 149) for more information.
If the FIFOs are enabled, this error is associated with
the particular character in the FIFO that it applies to.
This error is revealed to the CPU when its associated
character is at the bottom of the RX_FIFO.
A description of the various bits of the MSR register, with
Loopback disabled and UART Mode selected, is provided
below.
This bit is cleared upon read.
Bit 3 - Framing Error (FE)
When bits 0, 1, 2 or 3 is set to 1, a Modem Status Event
(MS_EV) is generated if the MS_IE bit is enabled in the IER
This bit is set to 1 when the received data character
does not have a valid stop bit (i.e., the stop bit following
the last data bit or parity bit is a 0).
Bits 0 to 3 are set to 0 as a result of any of the following
events:
If the FIFOs are enabled, this Framing Error is associat-
ed with the particular character in the FIFO that it ap-
plies to. This error is revealed to the CPU when its
associated character is at the bottom of the RX_FIFO.
●
Hardware reset occurs.
●
The MSR register is read.
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Enhanced Serial Port - UART1 (Logical Device 3)
In the reset state, bits 4 through 7 are indeterminate as they
reflect their corresponding input signals.
Non-Extended Modes
7
6
5
4
3
2
1
0
Note: The modem status lines can be used as general
purpose inputs. They have no effect on the trans-
mitter or receiver operation.
Scratchpad Register
(SCR)
Reset
Bank 0,
Offset 07h
Required
7
6
5
4
3
2
0
1
0
Modem Status
Register (MSR)
Bank 0,
X
X
X
X
0
0
0
Reset
Offset 06h
Required
DCTS
Scratch Data
DDSR
TERI
DDCD
CTS
DSR
6.5.11 Auxiliary Status and Control Register (ASCR)
This register shares a common address with the previous
one (SCR).
RI
DCD
This register is accessed when the Extended mode of op-
eration is selected. The definition of the bits in this case is
dependent upon the mode selected in the MCR register,
bits 7 through 5. This register is cleared upon hardware re-
set Bits 2 and 6 are cleared when the transmitter is “soft re-
set”. Bits 0,1,4 and 5 are cleared when the receiver is “soft
reset”.
Bit 0 - Delta Clear to Send (DCTS)
Set to 1, when the CTS input signal changes state.
This bit is cleared upon read.
Bit 1 - Delta Data Set Ready (DDSR)
Set to 1, when the DSR input signal changes state.
This bit is cleared upon read
Extended Modes
7
0
6
0
5
0
4
3
2
0
1
0
Auxiliary Status
Register (ASCR)
Bank 0,
Bit 2 - Trailing Edge Ring Indicate (TERI)
0
0
0
0
Reset
Set to 1, when the RI input signal changes state from
low to high.
0
Offset 07h
0
0
0
0
0
0
Required
This bit is cleared upon read
RXF_TOUT
Bit 3 - Delta Data Carrier Detect (DDCD)
Set to 1, when the DCD input signal changes state.
1: DCD signal state changed.
Reserved
Bit 4 - Clear To Send (CTS)
This bit returns the inverse of the CTS input signal.
Bit 5 - Data Set Ready (DSR)
Bit 0 - RX_FIFO Time-Out (RXF_TOUT)
This bit returns the inverse of the DSR input signal.
This bit is read only and set to 1 when an RX_FIFO tim-
eout occurs. It is cleared when a character is read from
the RX_FIFO.
Bit 6 - Ring Indicate (RI)
This bit returns the inverse of the RI input signal.
Bits 7 - 1 -Reserved
Read/Write 0.
Bit 7 - Data Carrier Detect (DCD)
This bit returns the inverse of the DCD input signal.
6.6 BANK 1 – THE LEGACY BAUD GENERATOR
DIVISOR PORTS
6.5.10 Scratchpad Register (SPR)
This register shares a common address with the ASCR
Register.
This register bank contains two registers as the Baud Gen-
erator Divisor Port, and a bank select register.
In Non-Extended mode, this is a scratch register (as in the
The Legacy Baud Generator Divisor (LBGD) port provides
an alternate path to the Baud Divisor Generator register.
This bank is implemented to maintain compatibility with
16550 standard and to support existing legacy software
packages. In case of using legacy software, the addresses
0 and 1 are shared with the data ports RXD/TXD (see page
138). The selection between them is controlled by the value
of the BKSE bit (LCR bit 7 page 142).
16550) for temporary data storage.
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146
Enhanced Serial Port - UART1 (Logical Device 3)
TABLE 6-9. Bank 1 Register Set
TABLE 6-10. Bits Cleared On Fallback
Register
Name
UART Mode & LOCK bit before Fallback
Extended Non-Extended Non-Extended
Offset
Description
Register
00h
LBGD(L)
Legacy Baud Generator
Divisor Port (Low Byte)
Mode
Mode
Mode
LOCK = x
LOCK = 0
LOCK = 1
01h
LBGD(H)
Legacy Baud Generator
Divisor Port (High Byte)
MCR
2 to 7
none
5 and 7
0 to 5
none
none
none
EXCR1 0, 5 and 7
EXCR2 0 to 5
02h
03h
Reserved
LCR/
BSR
Line Control /
Bank Select Register
.
04h - 07h
Reserved
Legacy Baud Generator Divisor
7
6
5
4
3
2
1
0
In addition, a fallback mechanism maintains this compatibil-
ity by forcing the UART to revert to 16550 mode if 16550
software addresses the module after a different mode was
set. Since setting the baud rate divisor values is a neces-
sary initialization of the 16550, setting the divisor values in
bank 1 forces the UART to enter 16550 mode. (This is
called fallback.)
Low Byte port
(LBGD(L))
Bank 1,
Reset
Required
Offset 00h
To enable other modes to program their desired baud rates
without activating this fallback mechanism, the baud rate di-
visor register in bank 2 should be used.
Least Significant Byte
of Baud Generator
6.6.1
Legacy Baud Generator Divisor Ports (LBGD(L)
and LBGD(H)),
The programmable baud rates in the Non-Extended mode
are achieved by dividing a 24 MHz clock by a prescale value
of 13, 1.625 or 1. This prescale value is selected by the
PRESL field of EXCR2 (see page 149). This clock is subdi-
vided by the two baud rate generator divisor buffers, which
output a clock at 16 times the desired baud rate (this clock is
the BOUT clock). This clock is used by I/O circuitry, and after
a last division by 16 produces the output baud rate.
.
Legacy Baud Generator Divisor
7
6
5
4
3
2
1
0
High Byte port
(LBGD(H))
Bank 1,
Reset
Offset 01h
Required
Divisor values between 1 and 216-1 can be used. (Zero is
forbidden). The baud rate generator divisor must be loaded
during initialization to ensure proper operation of the baud
rate generator. Upon loading either part of it, the baud rate
generator counter is immediately loaded. Table 6-12 on
page 148 shows typical baud divisors. After reset the divisor
register contents are indeterminate.
Most Significant Byte
of Baud Generator
Any access to the LBGD(L) or LBGD(H) ports causes a re-
set to the default Non-Extended mode, i.e., 16550 mode
(See “AUTOMATIC FALLBACK TO A NON-EXTENDED
UART MODE” on page 138).To access a Baud Generator
Divisor when in the Extended mode, use the port pair in
bank 2 (BGD on page 148).
6.6.2
Line Control Register (LCR) and Bank Select
Register (BSR)
These registers are the same as the registers at offset 03h
in bank 0.
Table 6-10 shows the bits which are cleared when Fallback
occurs during Extended or Non-Extended modes.
If the UART is in Non-Extended mode and the LOCK bit is
1, the content of the divisor (BGD) ports will not be affected
and no other action is taken.
When programming the baud rate, the new divisor is loaded
upon writing into LBGD(L) and LBGD(H). After reset, the
contents of these registers are indeterminate.
Divisor values between 1 and 216-1 can be used. (Zero is
forbidden.) Table 6-12 shows typical baud rate divisors.
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147
Enhanced Serial Port - UART1 (Logical Device 3)
6.7 BANK 2 – EXTENDED CONTROL AND STATUS
6.7.1
Baud Generator Divisor Ports, LSB (BGD(L))
and MSB (BGD(H))
REGISTERS
Bank 2 contains two alternate Baud rate Generator Divisor
ports and the Extended Control Registers (EXCR1 and
EXCR2).
These ports perform the same function as the Legacy Baud
Divisor Ports in Bank 1 and are accessed identically to
them, but do not change the operation mode of the module
when accessed. Refer to Section 6.6.1 on page 147 for
more detail.
TABLE 6-11. Bank 2 Register Set
Use these ports to set the baud rate when operating in Ex-
tended mode to avoid fallback to a Non-Extended operation
mode, i.e., 16550 compatible.When programming the baud
rate, writing to BGDH causes the baud rate to change im-
mediately.
Register
Name
Offset
Description
00h
BGD(L)
Baud Generator Divisor Port (Low
byte)
01h
BGD(H)
Baud Generator Divisor Port (High
byte)
Baud Generator Divisor
7
6
x
5
x
4
3
2
1
0
Low Byte Port
(BGD(L))
02h
EXCR1
Extended Control Register 1
x
x
x
x
x
x
Reset
03h LCR/BSR Line Control/ Bank Select Register
Bank 2,
Required
Offset 00h
04h
05h
06h
07h
EXCR2
Extended Control Register 2
Reserved
TXFLV
RXFLV
TX_FIFO Level
RX_FIFO Level
Least Significant Byte
of Baud Generator
TABLE 6-12. Baud Generator Divisor settings
13 1.625
Prescaler Value
1
Baud
Divisor
% Error
Divisor
% Error
Divisor
% Error
50
75
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
8
0.16%
0.16%
0.19%
0.10%
0.16%
0.16%
0.16%
0.16%
0.16%
0.53%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
---
18461
12307
8391
6863
6153
3076
1538
769
512
461
384
256
192
128
96
0.00%
0.01%
0.01%
0.00%
0.01%
0.03%
0.03%
0.03%
0.16%
0.12%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
---
30000
20000
13636
11150
10000
5000
2500
1250
833
750
625
416
312
208
156
104
78
0.00%
0.00%
0.00%
0.02%
0.00%
0.00%
0.00%
0.00%
0.04%
0.00%
0.00%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
0.16%
---
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
14400
19200
28800
38400
57600
115200
230400
460800
750000
921600
1500000
64
6
48
4
32
52
3
24
39
2
16
26
1
8
13
---
4
---
---
---
2
---
---
---
---
---
2
0.00%
---
---
---
1
0.16%
---
---
---
---
---
1
0.00%
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148
Enhanced Serial Port - UART1 (Logical Device 3)
2. UART and infrared receiver serial input signals are
disconnected. The internal receiver input signals are
connected to the corresponding internal transmitter
output signals.
Baud Generator Divisor
0
High Byte Port
7
6
x
5
x
4
3
2
1
(BGD(H))
Bank 2,
x
x
x
x
x
x
Reset
3. The UART transmitter serial output is forced high
and the infrared transmitter serial output is forced
low, unless the ETDLBK bit is set to 1. In which case
they function normally.
Required
Offset 01h
4. The modem status input pins (DSR, CTS, RI and
DCD) are disconnected. The internal modem status
signals, are driven by the lower bits of the MCR reg-
ister.
Most Significant Byte
of Baud Generator
Bit 5 - Enable Transmitter During Loopback (ETDLBK)
When this bit is set to 1, the transmitter serial output is
enabled and functions normally when loopback is en-
abled.
6.7.2
Extended Control Register 1 (EXCR1)
Use this register to control module operation in the Extend-
ed mode. Upon reset all bits are set to 0.
Bit 6 - Reserved
Read/Write 0.
Extended Control and
7
0
6
0
5
0
4
3
2
0
1
0
Bit 7 - Baud Generator Test (BTEST)
Status Register 1
0
0
0
0
Reset
(EXCR1)
When set to 1, this bit routes the Baud Generator to the
DTR pin for testing purposes.
Bank 2,
Offset 02h
1
0
0
0
Required
6.7.3
Line Control Register (LCR) and Bank Select
Register (BSR)
EXT_SL
These registers are the same as the registers at offset 03h
in bank 0.
Reserved
LOOP
ETDLBK
Reserved
BTEST
6.7.4
Extended Control and Status Register 2
(EXCR2)
This register configures the Prescaler and controls the
Baud Divisor Register Lock.
Bit 0 - Extended Mode Select (EXT_SL)
Upon reset all bits are set to 0.
When set to 1, the Extended mode is selected.
Extended Control and
Status Register 2
7
0
6
0
5
0
4
3
2
0
1
0
Bits 3 - 1 - Reserved
Read/Write 0.
0
0
0
0
Reset
(EXCR2)
Bank 2,
Offset 04h
0
0
0
0
0
Required
Bit 4 - Loopback Enable (LOOP)
During loopback, the transmitter output is connected in-
ternally to the receiver input, to enable system self-test
of serial communications. In addition to the data signal,
all additional signals within the UART are interconnect-
ed to enable real transmission and reception using the
UART mechanisms.
Reserved
PRESL0
PRESL1
Reserved
LOCK
When this bit is set to 1, loopback is selected. This bit
accesses the same internal register as bit 4 in the MCR
register, when the UART is in a Non-Extended mode.
Loopback behaves similarly in both Non-Extended and
Extended modes.
Bits 3 - 0 - Reserved
Read/Write 0.
When Extended mode is selected, the DTR bit in the
MCR register internally drives both DSR and RI, and the
RTS bit drives CTS and DCD.
Bits 5,4 - Prescaler Select
During loopback, the following actions occur:
The prescaler divides the 24 MHz input clock frequency
to provide the clock for the Baud Generator. (See Table
6-13).
1. The transmitter and receiver interrupts are fully op-
erational. The Modem Status Interrupts are also fully
operational, but the interrupt sources are now the
lower bits of the MCR register.
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149
Enhanced Serial Port - UART1 (Logical Device 3)
TABLE 6-13. Prescaler Select
6.7.7
RX_FIFO Current Level Register (RXFLV)
This read-only register returns the number of bytes in the
RX_FIFO. It can be used for software debugging.
Bit 5
Bit 4
Prescaler Value
0
0
1
1
0
1
0
1
13
1.625
Reserved
1.0
Extended Modes
7
0
6
0
5
0
4
3
2
0
1
0
Current Level
0
0
0
0
Reset
Register (RXFLV)
0
0
0
Bank 2,
Offset 07h
Required
Bit 6 - Reserved
Read/Write 0.
RFL0
RFL1
Bit 7 - Baud Divisor Register Lock (LOCK)
RFL2
RFL3
RFL4
When set to 1, accesses to the Baud Generator Divisor
Register through LBGD(L) and LBGD(H) as well as fall-
back are disabled from non-extended mode.
In this case two scratchpad registers overlaid with LB-
GD(L) and LBGD(H) are enabled, and any attempted
CPU access of the Baud Generator Divisor Register
through LBGD(L) and LBGD(H) will access the scratch-
pad registers instead. This bit must be set to 0 when ex-
tended mode is selected.
Reserved
Bits 4-0 - Number of Bytes in RX_FIFO (RFL(4-0))
These bits specify the number of bytes in the RX_FIFO.
Bits 7,6 - Reserved
Read/Write 0.
6.7.5
Reserved Register
Upon reset, all bits in Bank 2 register with offset 05h are set
to 0.
Note: The contents of TXFLV and RXFLV are not frozen
during CPU reads. Therefore, invalid data could be re-
turned if the CPU reads these registers during normal
transmitter and receiver operation. To obtain correct da-
ta, the software should perform three consecutive reads
and then take the data from the second read, if first and
second read yield the same result, or from the third
read, if first and second read yield different results.
Bits 7-0 - Reserved
Read/write 0.
6.7.6
TX_FIFO Current Level Register (TXFLV)
This read-only register returns the number of bytes in the
TX_FIFO. It can be used to facilitate programmed I/O
modes during recovery from transmitter underrun in one of
the fast infrared modes.
6.8 BANK 3 – MODULE REVISION ID AND SHADOW
REGISTERS
Bank 3 contains the Module Revision ID register which
identifies the revision of the module, shadow registers for
monitoring various registers whose contents are modified
by being read, and status and control registers for handling
the flow control.
Extended Modes
TX_FIFO
7
0
6
0
5
0
4
3
2
0
1
0
Current Level
Register (TXFLV)
Bank 2,
0
0
0
0
Reset
TABLE 6-14. Bank 3 Register Set
0
0
0
Required
Offset 06h
Register
Name
TFL0
TFL1
Offset
Description
TFL2
TFL3
TFL4
00h
01h
MRID
Module Revision ID Register
SH_LCR
Shadow of LCR Register
(Read Only)
02h
03h
SH_FCR Shadow of FIFO Control Register
(Read Only)
Reserved
LCR/
BSR
Line Control Register/
Bank Select Register
Bits 4-0 - Number of Bytes in TX_FIFO (TFL(4-0))
These bits specify the number of bytes in the TX_FIFO.
04h-07h
Reserved
Bits 7,6 - Reserved
Read/Write 0.
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Enhanced Serial Port - UART1 (Logical Device 3)
6.8.1
Module Revision ID Register (MRID)
6.8.3
Shadow of FIFO Control Register (SH_FCR)
This read-only register identifies the revision of the module.
When read, it returns the module ID and revision level. This
module returns the code 2xh, where x indicates the revision
number.
This read-only register returns the contents of the FCR reg-
ister in bank 0.
Shadow of
FIFO Control Register
7
0
6
0
5
0
4
3
2
0
1
0
(SH_FCR)
Bank 3,
Offset 02h
0
0
0
0
Reset
7
0
6
0
5
1
4
3
2
1
0
Module Revision ID
Register
0
x
x
x
x
Reset
Required
(MRID)
Required
Bank 3,
FIFO_EN
Offset 00h
RXSR
TXSR
Reserved
TXFTH0
TXFHT1
RXFTH0
RXFTH1
Revision ID(RID 3-0)
Module ID(MID 7-4)
See “FIFO Control Register (FCR)” on page 142 for bit de-
scriptions.
Bits 3-0 - Revision ID (MID3-0)
6.8.4
Line Control Register (LCR) and Bank Select
Register (BSR)
The value in these bits identifies the revision level.
These registers are the same as the registers at offset 03h
in bank 0.
Bits 7-4 - Module ID (MID7-4)
The value in these bits identifies the module type.
6.9 UART1 REGISTER BITMAPS
6.8.2
Shadow of Line Control Register (SH_LCR)
This register returns the value of the LCR register. The LCR
register is written into when a byte value according to Table
6-8 on page 143, is written to the LCR/BSR registers loca-
tion (at offset 03h) from any bank.
Read Cycles
Receiver Data
Register (RXD)
Bank 0,
7
6
5
4
3
2
1
0
Reset
Offset 00h
Required
Shadow of
7
0
6
0
5
0
4
3
2
0
1
0
Line Control Register
(SH_LCR)
0
0
0
0
Reset
Bank 3,
Offset 01h
Required
WLS0
Received Data
WLS1
STB
PEN
EPS
STKP
SBRK
BKSE
Write Cycles
Transmitter Data
Register (TXD)
Bank 0,
7
6
5
4
3
2
1
0
Reset
Required
See “Line Control Register (LCR)” on page 142 for bit de-
scriptions.
Offset 00h
Transmitted Data
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Enhanced Serial Port - UART1 (Logical Device 3)
Extended Mode
Line Control
Register (LCR)
All Banks,
7
0
6
0
5
0
4
3
2
0
1
0
7
0
6
0
5
0
4
3
2
0
1
0
Interrupt Enable
Register (IER)
Bank 0,
0
0
0
0
0
0
0
0
Reset
Reset
Offset 03h
0
0
Offset 01h
Required
Required
WLS0
RXHDL_IE
TXLDL_IE
LS_IE or TXUR_IE
MS_IE
Reserved
WLS1
STB
PEN
EPS
STKP
SBRK
BKSE
TXEMP_I
E
Reserved
Non-Extended Modes, Read Cycles
Bank Selection
Register (BSR)
All Banks,
7
0
6
0
5
0
4
3
2
0
1
0
Event Identification
Register (EIR)
Bank 0,
7
6
5
0
4
3
2
0
1
0
0
0
0
0
Reset
0
0
0
0
0
1
Reset
Offset 03h
Required
Offset 02h
0
0
Required
IPF - Interrupt Pending
IPR0 - Interrupt Priority 0
IPR1 - Interrupt Priority 1
RXFT - RX_FIFO Time-Out
Reserved
Bank Selected
FEN0 - FIFO Enabled
FEN1 - FIFO Enabled
BKSE-Bank Selection Enable
Extended Mode, Read Cycles
Non-Extended Mode
Event Identification
7
0
6
0
5
0
4
3
2
0
1
0
7
0
6
0
5
0
4
3
2
1
0
Modem Control
Register (MCR)
Bank 0,
Register (EIR)
Bank 0,
0
0
0
1
Reset
0
0
0
0
0
Reset
Offset 02h
0
0
Required
0
0
0
Required
Offset 04h
RXHDL_EV
DTR
TXLDL_EV
LS_EV or TXHLT_EV
MS_EV
Reserved
TXEMP-EV
RTS
RILP
ISEN or DCDLP
LOOP
Reserved
Reserved
Extended Mode
Write Cycles
7
0
6
0
5
0
4
3
2
1
0
7
0
6
0
5
0
4
3
2
0
1
0
FIFO Control
Register (FCR)
Bank 0,
Modem Control
Register (MCR)
Bank 0,
0
0
0
0
0
Reset
0
0
0
0
Reset
0
Offset 02h
0
0
0
0
Required
Offset 04h
Required
FIFO_EN
DTR
RXSR
TXSR
Reserved
TXFTH0
TXFTH1
RXFTH0
RXFTH1
RTS
Reserved
TX_DFR
Reserved
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152
Enhanced Serial Port - UART1 (Logical Device 3)
Legacy Baud Generator Divisor
Non-Extended Mode
7
6
5
4
3
2
1
0
Low Byte Register
7
0
6
1
5
1
4
3
2
0
1
0
Line Status
Register (LSR)
Bank 0,
(LBGD(L)
Bank 1,
Offset 00h
Reset
0
0
0
0
Reset
Required
Offset 05h
Required
RXDA
OE
PE
FE
BRK
Least Significant Byte
of Baud Generator
TXRDY
TXEMP
ER_INF
Legacy Baud Generator Divisor
7
6
5
4
3
2
0
1
0
0
Modem Status
Register (MSR)
Bank 0,
7
6
5
4
3
2
1
0
High Byte Register
(LBGD(H))
X
X
X
X
0
0
Reset
Reset
Bank 1,
Offset 06h
Required
Offset 01h
Required
DCTS
DDSR
TERI
DDCD
CTS
DSR
Most Significant Byte
of Baud Generator
RI
DCD
Non-Extended Mode
Baud Generator Divisor
Low Byte Register
7
6
x
5
x
4
3
2
1
0
7
6
5
4
3
2
1
0
Scratch Register
(SCR)
(BGD(L))
x
x
x
x
x
x
Reset
Reset
Bank 2,
Offset 00h
Bank 0,
Required
Offset 07h
Required
Least Significant Byte
of Baud Generator
Scratch Data
Baud Generator Divisor
High Byte Register
(BGD(H))
Extended Mode
7
6
x
5
x
4
3
2
1
0
7
6
5
0
4
3
2
0
1
0
Auxiliary Status
Register (ASCR)
Bank 0,
x
x
x
x
x
x
Reset
Bank 2,
0
0
0
0
0
0
Reset
Offset 01h
Required
0
Offset 07h
Required
RXF_TOUT
Most Significant Byte
of Baud Generator
Reserved
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Enhanced Serial Port - UART1 (Logical Device 3)
Extended Control and
7
0
6
0
5
1
4
3
2
1
0
7
0
6
0
5
0
4
3
2
0
1
0
Module Revision ID
Register
Status Register 1
0
x
x
x
x
Reset
0
0
0
0
Reset
(EXCR1)
(MRID)
Bank 2,
Offset 02h
Required
1
0
0
0
Required
Bank 3
Offset 00h
EXT_SL
Revision ID(RID 3-0)
Reserved
LOOP
ETDLBK
Reserved
BTEST
Module ID(MID 7-4)
Extended Control and
Status Register 2
Shadow of
7
0
6
0
5
0
4
3
2
0
1
0
7
0
6
0
5
0
4
3
2
0
1
0
Line Control Register
0
0
0
0
Reset
(SH_LCR)
Bank 3,
0
0
0
0
0
Reset
(EXCR2)
Bank 2,
Required
0
0
0
0
Required
Offset 04h
Offset 01h
WLS0
WLS1
STB
PEN
EPS
STKP
SBRK
BKSE
Reserved
PRESL0
PRESL1
Reserved
LOCK
IrDA or Consumer-IR Modes
Shadow of
FIFO Control Register
(SH_FCR)
7
0
6
0
5
0
4
3
2
0
1
0
TX_FIFO
Current Level
Register (TXFLV)
Bank 2,
7
0
6
0
5
0
4
3
2
0
1
0
0
0
0
0
Reset
0
0
0
0
Reset
Bank 3,
Offset 02h
0
Required
0
0
0
Required
Offset 06h
FIFO_EN
TFL0
TFL1
TFL2
TFL3
TFL4
RXFR
TXFR
Reserved
TXFTH0
TXFHT1
RXFTH0
RXFTH1
Reserved
IrDA or Consumer-IR Modes
RX_FIFO
Current Level
Register (RXFLV)
7
0
6
5
4
3
2
0
1
0
0
0
0
0
0
0
Reset
0
0
0
Bank 2,
Offset 07h
Required
RFL0
RFL1
RFL2
RFL3
RFL4
Reserved
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Power Management (Logical Device 4)
7.2.2
Power Management Data Register
7.0 Power Management
(Logical Device 4)
This read/write register contains the data in the register
pointed to by the Power Management Index register at the
base address.
7.1 POWER MANAGEMENT OPTIONS
The Power Management logical device provides configura-
tion options. Registers in this logical device enable activa-
tion of other logical devices, and set signal characteristics
for certain I/O pins. (See Section 7.2 "THE POWER MAN-
AGEMENT REGISTERS".)
7
0
6
0
5
0
4
3
2
0
1
0
Power Management
Data Register,
0
0
0
0
Reset
Base Address
+ 01h
Required
7.2 THE POWER MANAGEMENT REGISTERS
Seventeen Power Management register control, activate
and monitor all activity of the power Management Logical
device.
Access to these registers is achieved by the use of two reg-
isters mapped in the PC87309 address space. The Power
Management registers are accessed via the Power Man-
agement Index and Data registers, which are located at
base address and base address + 01h, respectively. The
base address is indicated by the Base Address registers at
indexes 60h and 61h of Logical Device 4, respectively. See
TABLE 2-15 "Power Management Configuration Registers
- Logical Device 4" on page 27. TABLE 7-1 "The Power
Management Registers" lists these registers.
Data in the Indicated Power
Management Register
7.2.3
Function Enable Register 1 (FER1)
The bits of this register enable or disable activity of Logic
devices within the PC87309.
A set bit enables activation of the corresponding logical de-
vice via its Active register at index 30h.
A cleared bit disables the corresponding logical device re-
gardless of the value in its Active register. Bit 0 of the Active
register of a logical device is ignored when the correspond-
ing FER1 bit is cleared.
TABLE 7-1. The Power Management Registers
Index Symbol
Description
Type
Hard reset sets this read/write register to FFh.
Base+0
Base+1
Power Management Index Register R/W
Power Management Data Register R/W
7
0
6
1
5
1
4
3
2
0
1
0
Function Enable
Register 1 (FER1),
Index 00h
1
1
0
1
Reset
00h
01h
FER1
Function Enable Register 1
Reserved
R/W
R/W
R/W
0
0
0
Required
02h PMC1
03h
Power Management Control 1
Reserved
KBC Function Enable
Reserved
FDC Function Enable
Parallel Port Function Enable
UART2 and Infrared Function Enable
UART1 Function Enable
Reserved
04h PMC3
Power Management Control 3
Reserved
05h-
07h
7.2.1
Power Management Index Register
This read/write register points to one of the Power Manage-
ment registers. Bits 7 through 3 are read only and return
00000 when read.
Bit 0 - KBC Function Enable
0: Disabled.
It is reset by hardware to 00h. The data in the indicated reg-
ister is accessed via the Power Management Data register
at the base address + 01h.
1: Enabled. (Default)
Bit 1 - Reserved
Bit 2 - Reserved
7
0
6
0
5
0
4
3
2
0
1
0
Power Management
Index Register,
0
0
0
0
Reset
Bit 3 - FDC Function Enable
0: Disabled.
Base Address
+00h
0
0
0
0
0
Required
1: Enabled. (Default)
Bit 4 - Parallel Port Function Enable
0: Disabled.
Index of a Power
Management Register
1: Enabled. (Default).
Bit 5 - UART2 and Infrared Function Enable
0: Disabled.
Read Only
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Power Management (Logical Device 4)
See Section 2.8 "SUPERI/O UART1 CONFIGURA-
1: Enabled. (Default).
TION REGISTER (LOGICAL DEVICE 3)" on page 32.
Bit 6 - UART1 Function Enable
0: Disabled.
1: UART1 signals are in TRI-STATE.
Bit 7 - Reserved
Reserved.
1: Enabled. (Default).
Bit 7 - Reserved
7.2.5
Power Management Control 3 Register (PMC3)
7.2.4
Power Management Control Register (PMC1)
This register enables and monitors functions and devices.
Hard reset initializes this register to 0Eh.
The bits of this register place the signals of the correspond-
ing inactive logical device in TRI-STATE (except IRQ and
DMA pins) when set to “1”,regardless of the value of bit 0 of
the corresponding logical device register at index F0h.
7
0
6
0
5
0
4
3
2
1
1
0
Power Management
Control 3 Register
0
1
1
0
Reset
A cleared bit has no effect. In this case, the TRI-STATE sta-
tus of signals is controlled by bit 0 of the corresponding log-
ical device register at index F0h.
(PMC3)
Required
Index 04h
This is an OR function between PMC1 and the register at in-
dex F0h of the corresponding logical device.
Reserved
Parallel Port Clock Enable
UART2 Clock Enable
UART1 Clock Enable
Hard reset clears this read/write register to 00h.
7
0
6
0
5
0
4
3
2
0
1
0
Power Management
Reserved
UART2 Busy Indicator
UART1 Busy Indicator
0
0
0
0
Reset
Control 1 Register
(PMC1)
Required
Index 02h
Bit 0 - Power Management Timer CLock Enable
Reserved
0: The clock is disabled.
The PM Timer registers (see Fixed ACPI registers)
are not accessible. Reads are ignored.
The TMR_STS and the TMR_EN bits (in PM1
Event registers) are read-only bits. Read returns 0.
FDC TRI-STATE Control
Parallel Port TRI-STATE Control
UART2 and Infrared TRI-STATE Control
UART1 TRI-STATE Control
Reserved
1: The clock is enabled.
The PM Timer registers (see Fixed ACPI registers)
are accessible.
Bits 2-0 - Reserved
The TMR_STS and the TMR_EN bits (in PM1
Event registers) are functional.
Bit 3 - FDC TRI-STATE Control
Bit 1 - Parallel Port Clock Enable
0: No effect. TRI-STATE controlled by bit 0 of the Su-
perI/O FDC Configuration register. (Default)
This bit is ANDed with bit 1 of the SuperI/O Parallel Port
Configuration register at index F0h of Logical Device 4.
If either bit is cleared to 0, the clock is disabled. Both bits
must be set to 1 to enable the clock.
See Section 2.5.1 "SuperI/O FDC Configuration
Register" on page 30.
1: FDC signals are in TRI-STATE.
0: The clock is disabled.
1: If bit 1 of the SuperI/O Parallel Port Configuration
register is set to 1, the clock is enabled. (Default)
Bit 4 - Parallel Port TRI-STATE Control
0: No effect. TRI-STATE controlled by bit 0 of the Su-
perI/O Parallel Port Configuration register. (Default)
Bit 2 - UART2 Clock Enable
See Section 2.6 "SUPERI/O PARALLEL PORT
CONFIGURATION REGISTER (LOGICAL DEVICE
1)" on page 30.
This bit is ANDed with bit 1 of the SuperI/O UART2 Con-
figuration register at index F0h of Logical Device 2. If ei-
ther bit is cleared to 0, the clock is disabled. Both bits
must be set to 1 to enable the clock.
1: Parallel Port signals are in TRI-STATE.
0: The clock is disabled.
Bit 5 - UART2 and Infrared TRI-STATE Control
1: If bit 1 of the SuperI/O UART2 Configuration regis-
ter is set to 1, the clock is enabled. (Default)
0: No effect. TRI-STATE controlled by bit 0 of the Su-
perI/O UART2 Configuration register. (Default)
See “Bit 0 - TRI-STATE Control for UART2 signals”
on page 31.
1: UART2 signals are in TRI-STATE.
Bit 6 - UART1 TRI-STATE Control
0: No effect. TRI-STATE controlled by bit 0 of the Su-
perI/O UART1 Configuration register. (Default)
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Power Management (Logical Device 4)
Bit 3 - UART1 Clock Enable
This bit is ANDed with bit 1 of the SuperI/O UART1 Con-
figuration register at index F0h of Logical Device 3. If, ei-
ther bit is cleared to 0, the clock is disabled. Both bits
must be set to 1 to enable the clock.
7
0
6
1
5
1
4
3
2
0
1
0
Function Enable
Register 1 (FER1),
Index 00h
1
1
0
1
Reset
0
0
0
Required
0: The clock is disabled.
1: If bit 1 of the SuperI/O UART1 Configuration regis-
ter is set to 1, the clock is enabled. (Default)
KBC Function Enable
Reserved
FDC Function Enable
Parallel Port Function Enable
UART2 and Infrared Function Enable
UART1 Function Enable
Reserved
Bits 5,4 - Reserved
Bit 6 - UART2 Busy Indicator
When set to 1, this read-only bit indicates the UART2 is
busy. It is also accessed via the SuperI/O UART2 Con-
figuration register at index F0h of Logical Device 2. See
Section 2.7 on page 31.
Bit 7 - UART1 Busy Indicator
When set to 1, this read-only bit indicates the UART1 is
busy. It is also accessed via the SuperI/O
UART1Configuration register at index F0h of Logical
Device 3. See Section 2.8 on page 32.
7
0
6
0
5
0
4
3
2
0
1
0
Power Management
0
0
0
0
Reset
Control 1 Register
(PMC1)
Required
Index 02h
7.3 POWER MANAGEMENT REGISTER BITMAPS
Reserved
7
0
6
0
5
0
4
3
2
0
1
0
Power Management
Index Register,
FDC TRI-STATE Control
Parallel Port TRI-STATE Control
UART2 and Infrared TRI-STATE Control
UART1 TRI-STATE Control
Reserved
0
0
0
0
Reset
Base Address
+00h
0
0
0
Required
Index of a Power
Management Register
7
0
6
0
5
0
4
3
2
1
1
0
Power Management
Control 3 Register
0
1
1
0
Reset
(PMC3)
Required
Index 04h
Read Only
PM Timer Clock Enable
Parallel Port Clock Enable
UART2 Clock Enable
UART1 Clock Enable
7
0
6
0
5
0
4
3
2
0
1
0
Power Management
Data Register,
0
0
0
0
Reset
Base Address
+ 01h
Required
Reserved
UART2 Busy Indicator
UART1 Busy Indicator
Data in the Indicated Power
Management Register
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Mouse and Keyboard Controller (KBC) (Logical Devices 5 and 6)
8.1 SYSTEM ARCHITECTURE
8.0 Mouse and Keyboard Controller
The KBC is a general purpose microcontroller, with an 8-bit
internal data bus. See FIGURE FIGURE 8-1 "KBC System
Functional Block Diagram". It includes these functional
blocks:
(KBC) (Logical Devices 5 and 6)
The Keyboard Controller (KBC) is a functionally indepen-
dent programmable device controller. It is implemented
physically as a single hardware module on the PC87309
multi-I/O chip and houses two separate logical devices: a
mouse controller (Logical Device 5) and a keyboard control-
ler (Logical Device 6).
Serial Open-collector Drivers: Four open-collector bi-di-
rectional serial lines enable serial data exchange with
the external devices (keyboard and mouse) using the
PS/2 protocol.
The KBC accepts user input from the keyboard or mouse,
and transfers this input to the host PC via the common
PC87309-PC interface.
Program ROM: 2 Kbytes of ROM store program machine
code in non-erasable memory. The code is copied to
this ROM during manufacture, from customer-supplied
code.
The KBC is functionally equivalent to the industry standard
8042A keyboard controller, which may serve as a detailed
technical reference for the KBC.
Data RAM: A 256-byte data RAM enables run-time inter-
nal data storage, and includes an 8-level stack and 16
8-bit registers.
The KBC is delivered preprogrammed with customer-sup-
plied code. KBC firmware code is identical to 8042 code,
and to code of the keyboard controller of the PC87323VUL
chip. The PC87323VUL is a recommended development
platform for the KBC since it uses identical code and in-
cludes internal program RAM that enables software devel-
opment.
Timer/Counter: An internal 8-bit timer/counter can count
external events or pre-divided system clock pulses. An
internal time-out interrupt may be generated by this de-
vice.
I/O Ports: Two 8-bit ports (Port 1 and Port 2) serve various
I/O functions. Some are for general purpose use, others
are utilized by the KBC firmware.
Program
Address
Data
RAM
256 x 8
Program
ROM
(including
registers
and stack)
8-Bit
CPU
2 K x 8
TEST1
8-Bit Internal Bus
Timer
Overflow
8-Bit Timer
or Counter
DBBOUT
STATUS DBBIN
I/O PORT 1
8-Bit
I/O Port 2
8-Bit
P24
IBF
P25
P11,10
P27, P26, P23, P22
Serial Open-Collector
Drivers
TEST0
P21-20
A2
D7-0
RD WR
P12
To PnP
Interrupt Matrix KBDAT KBCLK MDAT MCLK
PC87309 Interface
I/O Interface
FIGURE 8-1. KBC System Functional Block Diagram
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Mouse and Keyboard Controller (KBC) (Logical Devices 5 and 6)
8.2 FUNCTIONAL OVERVIEW
abled by KBC firmware. Both are disabled by a hard reset.
These two interrupts only affect the execution flow of the
KBC firmware, and have no connection with the external in-
terrupts requested by this logical device.
The KBC supports two external devices — a keyboard and
a mouse. Each device communicates with the KBC via two
bidirectional serial signals. Five additional external general-
purpose I/O signals are provided.
The KBC can generate two external interrupt requests.
These request signals are controlled by the KBC firmware
which generates them by manipulating I/O port signals. See
Section 8.3.2 "Interrupt Request Signals".
KBC operation involves three signal interfaces:
●
External I/O interface
●
The PC87309 supports the KBC and handles interactions
with the PC chip set. In addition to data transfer, these inter-
actions include KBC configuration, activation and status
monitoring. The PC87309 interconnects with the host via
one interface that is shared by all chip devices
Internal KBC - PC87309 interface
●
PC87309 - PC chip set interface.
These system interfaces are shown in FIGURE FIGURE
8-2 "System Interfaces".
The KBC clock is generated from the main clock of the chip,
which may come from an external clock source or from the
internal frequency multiplier. (See Section 8.3 "DEVICE
CONFIGURATION" and FIGURE 8-5 "Timing Generation
and Timer Circuit" on page 161.) The KBC clock rate is con-
figured by the SIO Configuration Registers.
The KBC uses two data registers (for input and output) and
a status register to communicate with the PC87309 central
system. Data exchange between these units may be based
on programmed I/O or interrupt-driven.
The KBC has two internal interrupts: the Input Buffer Full
(IBF) interrupt and Timer Overflow interrupt (see FIGURE
8-1 "KBC System Functional Block Diagram" on page 158).
These two interrupts can be independently enabled or dis-
PC87309
SA15-0
A15-0
KBC Device
P12
STATUS
XD7-0
D7-0
P20
P21
DBBIN
DBBOUT
KBCLK
P26
AEN
Keyboard Clock
PC
TEST0
Chip Set
KBDAT
P27
P10
RD
Keyboard Data
MCLK
WR
MR
P23
Mouse Clock
TEST1
MDAT
P22
P11
KBC IRQ
Mouse Data
P24
Plug and
Play
IRQn
Mouse IRQ P25
Matrix
FIGURE 8-2. System Interfaces
8.3.2 Interrupt Request Signals
The KBC IRQ and Mouse IRQ interrupt request signals are
identical to (or functions of) the P24 and P25 signals of the
8042. These interrupt request signals are routed internally
to the Plug and Play interrupt Matrix and may be routed to
user-programmable IRQ pins. Each logical device is inde-
pendently controlled.
8.3 DEVICE CONFIGURATION
The KBC hardware contains two logical devices—the mouse
(Logical Device 5) and the keyboard (Logical Device 6).
8.3.1
I/O Address Space
The KBC has two I/O addresses and one IRQ line (KBC
IRQ) and can operate without the companion mouse.
The Interrupt Select registers (index 70h for each logical de-
vice) select the IRQ pin to which the corresponding interrupt
request is routed. The interrupt may also be disabled by not
routing its request signal to any IRQ pin.
The mouse cannot operate without the KBC device. It has
one IRQ line (mouse IRQ) but has no I/O address. It utilizes
the KBC I/O addresses.
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Mouse and Keyboard Controller (KBC) (Logical Devices 5 and 6)
Bit 0 of the Interrupt Type registers (index 71h for each log-
FIGURE FIGURE 8-3 "Interrupt Request Logic" illustrates
the internal interrupt request logic.Refer to FIGURE 8-4 "In-
struction Timing" for a timing diagram.
ical device) determines whether the interrupts are passed
(bit 0 = 0) or latched (bit 0 = 1). If bit 0 = 0, interrupt request
signals (P24 and P25) are passed directly to the selected
IRQ pin. If bit 0 = 1, interrupt request signals that become
active are latched on their rising edge, and held until read
from the KBC output buffer (port 60h).
Interrupt
Polarity
(0 = Invert)
Interrupt
Type
(1 = Latch)
Plug and
Play Matrix
“1”
0
PR
0
D
Q
1
MUX
From KBC IRQ
CLK
1
MUX
CLR
KBC IRQ Feedback
Interrupt Enable
Port 60
Read
RD
AEN
Address
Decoder
A15-0
Interrupt
Polarity
(0 = Invert)
Interrupt
Type
(1 = Latch)
Plug and
Play Matrix
MR
“1”
0
PR
0
D
Q
1
MUX
From Mouse IRQ
CLK
CLR
1
MUX
Mouse IRQ Feedback
Interrupt Enable
Port 60
Read
Address
Decoder
RD
AEN
A15-0
MR
FIGURE 8-3. Interrupt Request Logic
S1
S2
S3
S4
S5
S1
1 Instruction Cycle = 15 Clock Cycles
KBC CLK
FIGURE 8-4. Instruction Timing
Note: The EN FLAGS command (for routing OBF and IBF onto P24 and P25 in the 8042) causes unpredictable results and
should not be issued
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Mouse and Keyboard Controller (KBC) (Logical Devices 5 and 6)
External
48 MHz
Clock
CLKIN
Frequency
Select
÷ 2
÷
2 or 3
KBC Clock
3-State
Counter
Stop
32-Bit
Timer
Prescaler
8-Bit Timer
or Counter
Overflow
Flag
5-Cycle
Counter
Timer
Counter
External Event Input
TEST1
Interrupt
(MCLK)
FIGURE 8-5. Timing Generation and Timer Circuit
8.4 EXTERNAL I/O INTERFACES
8.3.3
KBC Clock
The KBC clock frequency is selected by the SuperI/O KBC
Configuration Register at index F0h of Logical Device 6 to
be either 8, 12 or 16 MHz.
The PC chip set interfaces with the PC87309 as illustrated
in FIGURE 8-2 "System Interfaces" on page 159.
All data transactions between the KBC and the PC chip set
are handled by the PC87309.
For details regarding the configuration of each device, refer
to TABLES 2-17 "KBC Configuration Registers for Key-
board - Logical Device 6" and 2-16 "KBC Configuration
Registers for Mouse - Logical Device 5" on page 27.
The PC87309 decodes all I/O device chip-select functions
from the address bus. The KBC chip-select codes are, tra-
ditionally, 60h or 64h, as described in TABLE 8-1 "System
Interface Operations" on page 163. (These addresses are
user-programmable.)
8.3.4
Timer or Event Counter
The keyboard controller includes an 8-bit counter, which
can be used as a timer or an event counter, as selected by
the firmware.
The external interface includes two sets of signals: the key-
board and mouse interface signals, and the general-pur-
pose I/O signals.
Timer Operation
8.4.1
Keyboard and Mouse Interface
When the internal clock is chosen as the counter input, the
counter functions as a timer. The clock fed to the timer con-
sists of the KBC instruction cycle clock, divided by 32. (See
FIGURES 8-4 "Instruction Timing" on page 160 and FIG-
URE 8-5 "Timing Generation and Timer Circuit".) The divi-
sor is reset only by a hardware reset or when the timer is
started by an STRT T instruction.
Four serial I/O signals interface with the external keyboard
and mouse. These signals are driven by open-collector driv-
ers with signals derived from two I/O ports residing on the
internal bus. Each output can drive 16 mA, making them
suitable for driving the keyboard and mouse cables. The
signals are named KBCLK, KBDAT, MCLK and MDAT, and
they are the logical complements of P26, P27, P23 and
P22, respectively.
Event Counter Operation
TEST0 and TEST1 are dedicated test pins, internally con-
nected to KBCLK and MCLK, respectively, as shown in FIG-
URES 8-1 "KBC System Functional Block Diagram" on
page 158 and 8-2 "System Interfaces" on page 159. These
pins may be used as logical conditions for conditional jump
instructions, which directly check the logical levels at the
pins.
When the clock input of the counter is switched to the exter-
nal input (MCLK), it becomes an event counter. The falling
edge of the signal on the MCLK pin causes the counter to
increment. Timer Overflow Flag and Timer interrupt operate
as in the timer mode.
KBDAT and MDAT are connected to pins P10 and P11, re-
spectively.
MCLK also provides input to the event counter.
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Mouse and Keyboard Controller (KBC) (Logical Devices 5 and 6)
General Purpose I/O Signals During output, a 1 written to output is strongly pulled up for
8.4.2
the duration of a (short) write pulse, and thereafter main-
tained by a high impedance “weak” active pull-up (imple-
mented by a degenerated transistor employed as a
switchable pull-up resistor). A series resistor to those port
lines used for input is recommended to limit the surge cur-
rent during the strong pull-up. See FIGURE FIGURE 8-7
"Current Limiting Resistor".
The P12, P20 and P21 general purpose I/O signals inter-
face to two I/O ports (port1 and port2). P12 is mapped to
port 1 and P20 and P21 are mapped to port 2.
P12 does not exist in the default configuration of Two-UART
mode see “Wake Up Options” on page 19. In this mode,
P12 input is connected implicitly to the port output. It may be
optionally select on either IRRX or MTR1, in which case it is
open drain and not quasi-bidirectional as described below.
If a 1 is asserted, an externally applied signal may pull down
the output. Therefore, input from this quasi-bidirectional cir-
cuit can be correctly read if preceded by a 1 written to output.
P12 is driven by quasi-bidirectional drivers. (See FIGURE
FIGURE 8-6 "Quasi-Bidirectional Driver".) These signals
are called quasi-bidirectional because the output buffer
cannot be turned off (even when the I/O signal is used for
input).
P20 and P21 are driven by open-drain drivers.
When the KBC is reset, all port data bits are initialized to 1.
ORL, ANL
+VCC
MR
Q1
Q2
Q3
P
Q
D
PORT
F/F
PAD
Q
Port
Write
IN
Internal Bus
FIGURE 8-6. Quasi-Bidirectional Driver
R
Port Pin
Port Pin
R: current limiting resistor
100 – 500Ω
A small-value series current limiting
resistor is recommended when
port pins are used for input.
PC87309
R
100 – 500Ω
FIGURE 8-7. Current Limiting Resistor
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Mouse and Keyboard Controller (KBC) (Logical Devices 5 and 6)
8.5 INTERNAL KBC - PC87309 INTERFACE
8.5.3
The KBC STATUS Register
The KBC interfaces internally with the PC87309 via three
registers: an input (DBBIN), output (DBBOUT) and status
(STATUS) register. See FIGURE 8-1 "KBC System Func-
tional Block Diagram" on page 158 and TABLE 8-1 "Sys-
tem Interface Operations".
The STATUS register holds information regarding the sys-
tem interface status.The bitmap below shows the bit defini-
tion of this register. This register is controlled by the KBC
firmware and hardware, and is read-only for the system.
TABLE 8-1. System Interface Operations
KBC Status Register
Offset 64h
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset
Read Only
Default
RD WR
Operation
Addresses
60h
Read DBBOUT
OBF Output Buffer Full
IBF Input Buffer Full
F0 General Purpose Flag
0
1
0
1
1
0
1
0
Write DBBIN, F1 Clear (Data)
Read STATUS
60h
F1 Command or Data Flag
64h
Write DBBIN, F1 Set (Command)
General Purpose
Flags
64h
TABLE 8-1 "System Interface Operations" illustrates the
use of address line A2 to differentiate between data and
commands. The device is selected by chip identification of
default address 60h (when A2 is 0) or 64h (when A2 is 1).
After reset, these addresses can be changed by software.
Bit 0 - OBF, Output Buffer Full
A 1 indicates that data has been written into the DB-
BOUT register by the KBC. It is cleared by a system
read operation from DBBOUT.
8.5.1
The KBC DBBOUT Register, Offset 60h,
Read Only
Bit 1 - IBF, Input Buffer Full
When a write operation is performed by the host system,
this bit is set to 1, which may be set up to trigger the IBF
interrupt. Upon executing an IN A, DBB instruction, it is
cleared.
The DBBOUT register transfers data from the keyboard
controller to the PC87309. It is written to by the keyboard
controller and read by the PC87309 for transfer to the PC.
The PC may be notified of the need to read data from the
KBC by an interrupt request or by polling the Output Buffer
Full (OBF) bit (bit 0 of the KBC STATUS register described
in Section 8.5.3 "The KBC STATUS Register").
Bit 2 - F0, General Purpose Flag
A general purpose flag that can be cleared or toggled by
the keyboard controller firmware.
8.5.2
The KBC DBBIN Register, Offset 60h (F1 Clear)
or 64h (F1 Set), Write Only
Bit 3 - F1, Command/Data Flag
This flag holds the state of address line A2 while a write
operation is performed by the host system. It distin-
guishes between commands and data from the host
system. In this device, a write with A2 = 1 (hence F1 =
1) is defined as a command, and A2 = 0 (hence F1 = 0)
is data.
The DBBIN register transfers data from the PC87309 sys-
tem to the keyboard controller. (This transaction is transpar-
ent to the user, who should program the device as if direct
access to the registers were in effect.)
When data is received in this manner, an Input Buffer Full
(IBF) internal interrupt may be generated in the KBC, to deal
with this data. Alternatively, reception of data in this manner
can be detected by the KBC polling the Input Buffer Full bit
(IBF, bit 1 of the KBC STATUS register).
Bits 7-4, General Purpose Flags
These flags may be modified by KBC firmware.
8.6 INSTRUCTION TIMING
The KBC clock is first divided by 3 to generate the state tim-
ing, then by 5 to generate the instruction timing. Thus each
instruction cycle consists of five states and 15 clock cycles.
Most keyboard controller instructions require only one in-
struction cycle, while some require two cycles. Refer to the
8042 or PC87323VUL instruction set for details.
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Interrupt and DMA Mapping
Only the UART1 and UART2 may map more than one logi-
9.0 Interrupt and DMA Mapping
cal device to any IRQ signal. Other devices may not do so.
The standard Plug and Play configuration registers map
IRQs and DMA channels for the PC87309. See TABLES
2-7 "Plug and Play (PnP) Interrupt Configuration Registers"
and 2-8 "Plug and Play (PnP) DMA Configuration Regis-
ters" on page 24.
An IRQ signal is in TRI-STATE when any of the following
conditions is true:
●
No logical device is mapped to the IRQ signal.
●
The logical device mapped to the IRQ signal is inactive.
9.1 IRQ MAPPING
●
The logical device mapped to the IRQ signal floats its
IRQ signal.
The PC87309 allows connection of some logical devices to
the seven IRQ signals.
9.2 DMA MAPPING
The polarity of an IRQ signal is controlled by bit 1 of the In-
terrupt Type registers (index 71h) of each logical device.
The same bit also controls selection of push-pull or open-
drain IRQ output. High polarity implies push-pull output.
Low polarity implies open-drain output with strong pull-up
for a short time, followed by weak pull-up.
Although the PC87309 allows some logical devices to be
connected to the three 8-bit DMA channels, it is illegal to
map two logical devices to the same pair of DMA signals.
A DRQ signal is in TRI-STATE and the DACK input signal
is blocked to 1 when any of the following conditions is true:
The IRQ input signals of the KBC or mouse, and of the par-
allel port are not affected by this bit, i.e., bit 1 at index 71h
of each logical device. This bit affects only the output buffer,
not the input buffer.
●
No logical device is mapped to the DMA channel.
●
The logical device mapped to the DMA channel is inactive.
●
The logical device mapped to the DMA channel floats its
DRQ signal.
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Device Specifications
10.0 Device Specifications
10.1 GENERAL DC ELECTRICAL CHARACTERISTICS
10.1.1 Recommended Operating Conditions
Symbol Parameter
Min
4.5
0
Typ
Max Unit
VDD
TA
5.0
5.5
V
Supply Voltage
+70
°C
Operating Temperature
10.1.2 Absolute Maximum Ratings
Absolute maximum ratings are values beyond which damage to the device may occur. Unless otherwise specified, all volt-
ages are relative to ground.
Symbol Parameter
Conditions
Min
Max
Unit
V
VDD
VI
−0.5
6.5
Supply Voltage
−0.5 VDD + 0.5
−0.5 VDD + 0.5
V
Input Voltage
VO
V
Output Voltage
TSTG
PD
−65
+165
1
°C
W
°C
Storage Temperature
Power Dissipation
TL
Lead Temperature Soldering (10 sec)
+260
CZAP = 100 pF
RZAP = 1.5 KΩ1
ESD Tolerance
1500
V
1. Value based on test complying with RAI-5-048-RA human body model ESD testing.
10.1.3 Capacitance
Symbol Parameter
Min
Typ
5
Max Unit
CIN
CIN1
CIO
CO
7
10
12
8
pF
pF
pF
pF
Input Pin Capacitance
Clock Input Capacitance
I/O Pin Capacitance
8
10
6
Output Pin Capacitance
TA = 25°C, f = 1 MHz
10.1.4 Power Consumption under Recommended Operating Conditions
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VIL = 0.5 V
VIH = 2.4 V
No Load
VDD Average Main Supply
Current
ICC
32
50
mA
mA
VIL = VSS
VIH = VDD
No Load
VDD Quiescent Main Supply
Current in Low Power Mode
ICCSB
1.3
1.7
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Device Specifications
10.2 DC CHARACTERISTICS OF PINS, BY GROUP
The following tables list the DC characteristics of all device pins described in Section 1.2. The pin list preceeding each table
lists the device pins to which the table applies.
10.2.1 Group 1
Pin List:
A11-0, AEN, CLKIN, CTS2,1, DACK3-1, DCD2,1, DSKCHG, DSR2,1, ID3-0, INDEX, IORD, IOWR, MR, RDATA, RI2,1,
SIN2,1, TC, TRK0, WP
All Group 1 pins are back-drive protected.
Symbol Parameter
Conditions
Min
Max
Unit
V
1
VIH
VIL
2.0
VDD
0.8
10
Input High Voltage
Input Low Voltage
−0.51
V
VIN = VDD
VIN = VSS
µA
µA
mV
IIL
Input Leakage Current
Input Hysteresis
−10
VH
250
1. Not tested. Guaranteed by design.
10.2.2 Group 2
Pin List:
BUSY, PE, SLCT, WAIT
Output from SLCT, PE and BUSY is open-drain in all SPP modes, except in SPP Compatible mode when the setup mode
is ECP-based FIFO and bit 4 of the Control2 parallel port register is 1. (See TABLE 4-1 "Parallel Port Mode Selection" on
page 80.) Otherwise, output from these signals is level 2. External 4.7 KΩ pull-up resistors should be used.
PE is in Group 2 only if bit 2 of PP Confg0 Register is “0” (see Section 4.5.19 "PP Confg0 Register" on page 94).
All group 2 pins are back-drive protected.
Symbol Parameter
Conditions
Min
Max
Unit
V
1
VIH
VIL
2.0
VDD
0.8
Input High Voltage
Input Low Voltage
−0.51
V
VIN = VDD
VIN = VSS
120
−10
µA
µA
IIL
Input Leakage Current
1. Not tested. Guaranteed by design.
10.2.3 Group 3
Pin List:
ACK, ERR, PE
Output from ACK and ERR is open-drain in all SPP modes, except in SPP Compatible mode when the setup mode is ECP-
based FIFO and bit 4 of the Control2 parallel port register is 1. (See TABLE 4-1 "Parallel Port Mode Selection" on page 80.)
Otherwise, output from these signals is level 2.
External 4.7 KΩ pull-up resistors should be used.
PE is in Group 3 only if bit 2 of PP Confg0 Register is “1” (see Section 4.5.19 "PP Confg0 Register" on page 94).
All group 3 pins are back-drive protected.
Symbol Parameter
Conditions
Min
Max
Unit
V
1
VIH
VIL
2.0
VDD
0.8
Input High Voltage
Input Low Voltage
−0.51
V
VIN = VDD
VIN = VSS
10
µA
µA
IIL
Input Leakage Current
−120
1. Not tested. Guaranteed by design.
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Device Specifications
10.2.4 Group 4
Pin List:
BADDR1,0, CFG0
These are CMOS input pins.
Symbol Parameter
Conditions
Min
Max
Unit
V
1
VIH
2.5
VDD
200
−10
Input High Voltage
During Reset: VIN = VDD
VIN = VSS
µA
µA
IIL
Input Leakage Current
1. Not tested. Guaranteed by design.
10.2.5 Group 5
Pin List:
D7-0
Input
Conditions
Symbol Parameter
Min
Max
Unit
1
VIH
VIL
2.0
VDD
0.8
10
V
V
Input High Voltage
Input Low Voltage
−0.51
VIN = VDD
VIN = VSS
µA
µA
mV
IIL
Input Leakage Current
Hysteresis
−10
VH
250
1. Not tested. Guaranteed by design.
Output
Symbol Parameter
Conditions
IOH = −15 mA
IOL = 24 mA
Min
2.4
Max
Unit
V
VOH
VOL
Output High Voltage
Output Low Voltage
0.4
V
10.2.6 Group 6
Pin List:
KBCLK, KBDAT, MCLK, MDAT
Output from these signals is open-drain and cannot be forced high.
Input
Symbol Parameter
Conditions
Min
Max
Unit
1
VIH
VIL
2.0
VDD
0.8
10
V
V
Input High Voltage
Input Low Voltage
−0.51
VIN = VDD
VIN = VSS
µA
µA
mV
IIL
Input Leakage Current
Hysteresis
−10
VH
250
1. Not tested. Guaranteed by design.
Output
Symbol Parameter
VOL
Conditions
Min
Max
Unit
IOL = 16 mA
0.4
V
Output Low Voltage
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Device Specifications
10.2.7 Group 7
Pin List:
P12, P20, P21
Input
Symbol Parameter
Conditions
Min
Max
Unit
V
1
VIH
VIL
2.0
VDD
0.8
10
Input High Voltage
Input Low Voltage
−0.51
V
VIN = VDD
µA
µA
mV
IIL
Input Leakage Current
Hysteresis
VIN = VSS
−10
VH
250
1. Not tested. Guaranteed by design.
Output
Symbol Parameter
Conditions
IOH = −14 mA1
IOL = 14 mA
Min
2.4
Max
Unit
V
VOH
VOL
Output High Voltage
Output Low Voltage
0.4
V
1. IOH is driven for 10 nsec after the low-to-high transition, on pins P12.
10.2.8 Group 8
Pin List:
AFD, ASTRB, DSTRB, INIT, SLIN, STB, WRITE
These pins are back-drive protected.
Input
Conditions
Symbol Parameter
Min
Max
Unit
1
VIH
VIL
2.0
VDD
0.8
10
V
V
Input High Voltage
Input Low Voltage
−0.51
VIN = VDD
VIN = VSS
µA
µA
mV
IIL
Input Leakage Current
Hysteresis
−10
VH
250
1. Not tested. Guaranteed by design.
Output
Symbol Parameter
Conditions
IOH = −2 mA
IOL = 2 mA
Min
2.4
Max
Unit
V
Output High Voltage1
Output Low Voltage
VOH
VOL
0.4
V
1. Output from STB, AFD, INIT, SLIN is open-drain in all SPP modes, except in SPP
Compatible mode when the setup mode is ECP-based (FIFO). (See TABLE 4-1 "Par-
allel Port Mode Selection" on page 80.) Otherwise, output from these signals is Level
2. External 4.7 KΩ pull-up resistors should be used.
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Device Specifications
10.2.9 Group 9
Pin List:
PD7-0
These pins are back-drive protected.
Input
Symbol Parameter
Conditions
Min
Max
Unit
V
1
VIH
VIL
2.0
VDD
0.8
10
Input High Voltage
Input Low Voltage
−0.51
V
VIN = VDD
µA
µA
mV
IIL
Input Leakage Current
Hysteresis
VIN = VSS
−10
VH
250
1. Not tested. Guaranteed by design.
Output
Symbol Parameter
Conditions
IOH = −14 mA
IOL = 14mA
Min
2.4
Max
Unit
V
Output High Voltage1
Output Low Voltage
VOH
VOL
0.4
V
1. Output from PD7-0 is open-drain in all SPP modes, except in SPP Compatible mode
when the setup mode is ECP-based (FIFO) and bit 4 of the Control2 parallel port reg-
ister is 1. (See TABLE 4-1 "Parallel Port Mode Selection" on page 80.) Otherwise,
output from these signals is Level 2. External 4.7 KΩ pull-up resistors should be used.
10.2.10 Group 10
Pin List:
IRQ1,3,4,5,6,7,12.
Symbol Parameter
Conditions
IOH = −15 mA
IOL = 24 mA
Min
Max
Unit
V
VOH
VOL
2.4
Output High Voltage
Output Low Voltage
0.4
V
10.2.11 Group 11
Pin List:
DENSEL, DIR, DR1,0, HDSEL, MTR1,0, STEP, WDATA, WGATE
Symbol Parameter
Conditions
Min
Max
Unit
V
VOH
VOL
IOH = −4 mA
2.4
Output High Voltage
Output Low Voltage1
IOL = 40 mA
0.4
V
1. Not 100% tested. Guaranteed by characterization.
10.2.12 Group 12
Pin List:
BOUT2,1, DTR2,1, IRSL2-0, RTS2,1, SOUT2,1, IRTX
Symbol Parameter
Conditions
IOH = −6 mA
IOL = 12 mA
Min
Max
Unit
V
VOH
VOL
2.4
Output High Voltage
Output Low Voltage
0.4
V
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Device Specifications
10.2.13 Group 13
Pin List:
DRQ3-1
Symbol Parameter
Conditions
IOH = −15 mA
IOL = 24 mA
Min
Max
Unit
V
VOH
VOL
2.4
Output High Voltage
Output Low Voltage
0.4
V
10.2.14 Group 14
Pin List:
DRATE0
Symbol Parameter
Conditions
IOH = −6 mA
IOL = 12 mA
Min
Max
Unit
V
VOH
VOL
2.4
Output High Voltage
Output Low Voltage
0.4
V
10.2.15 Group 15
Pin List:
IOCHRDY
Symbol Parameter
Conditions
IOH = −15 mA
IOL = 24 mA
Min
Max
Unit
V
VOH
VOL
2.4
Output High Voltage
Output Low Voltage
0.4
V
10.2.16 Group 18
Pin List:
IRRX2,1
These pins are back-drive protected.
Symbol Parameter
Conditions
Min
Max
Unit
V
1
VIH
VIL
2.0
VDD
0.8
10
Input High Voltage
Input Low Voltage
−0.51
V
VIN = VDD
VIN = VSS
µA
µA
mV
IIL
Input Leakage Current
Input Hysteresis
−10
VH
250
1. Not tested. Guaranteed by design.
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Device Specifications
10.3 AC ELECTRICAL CHARACTERISTICS
10.3.1 AC Test Conditions
Load Circuit (Notes 1, 2, 3)
AC Testing Input, Output Waveform
VDD
S1
2.4
0.4
2.0
0.8
2.0
0.8
0.1 µf
Test Points
RL
Device
Input
Output
Under
Test
CL
FIGURE 10-1. AC Test Conditions, TA = 0 °C to 70 °C, VDD = 5.0 V ±10%
Notes:
1. CL = 100 pF, includes jig and scope capacitance.
2. S1 = Open for push-pull output pins.
S1 = VDD for high impedance to active low and active low to high impedance measurements.
S1 = GND for high impedance to active high and active high to high impedance measurements.
RL = 1.0KΩ for µP interface pins.
3. For the FDC open-drive interface pins, S1 = VDD and RL = 150Ω.
10.3.2 Clock Timing
Symbol Parameter
Min
8.4
Max
Unit
nsec
nsec
nsec
Clock High Pulse Width1
Clock Low Pulse Width1
Clock Period1
tCH
tCL
tCP
8.4
20.6
21
1. Not tested. Guaranteed by design.
tCH
tCP
CLKIN
tCL
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Device Specifications
10.3.3 Microprocessor Interface Timing
Symbol Parameter
Min
18
18
0
Max
Unit
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
tAR
Valid Address to Read Active
tAW
tDH
Valid Address to Write Active
Data Hold
tDS
18
13
10
0
Data Setup
Read to Floating Data Bus1
tHZ
25
tPS
Port Setup
tRA
Address Hold from Inactive Read
Read Cycle Update1
45
60
10
tRCU
tRD
tRDH
tRI
Read Strobe Width
Read Data Hold
55
55
Read Strobe to Clear IRQ6
Active Read to Valid Data
Address Hold from Inactive Write
tRVD
tWA
tWCU
tWI
0
Write Cycle Update1
45
55
60
Write Strobe to Clear IRQ6
Write Data to Port Update
Write Strobe Width
tWO
tWR
tWRR
60
80
RD low after WR high1
1
123
RC
Read Cycle = tAR + tRD + tRCU
1
123
nsec
WC
Write Cycle = tAW + tWR + tWC
1. Not tested. Guaranteed by design.
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Device Specifications
Read
AEN
A11-0,
DACK
Valid
Valid
RC
tAR
tRD
tRCU
RD
tRA
OR
tRVD
WR
Valid Data
tRDH
tHZ
D7-0
tPS
PD7-0, ERR,
PE, SLCT, ACK,
BUSY
IRQ
tRI
Write
AEN
A11-0,
DACK
Valid
Valid
WC
tAW
tWR
tWCU
WR
tWA
OR
RD
Valid Data
tDS
D7-0
tDH
SLIN, INIT, STB,
PD7-0, AFD
Previous State
tWI
tWO
IRQ
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Device Specifications
Read After Write Operation to All Registers and RAM
AEN
or CS
A11-0
WR
RD
tWRR
D7-0
(Input)
10.3.4 Baud Output Timing
Symbol
Parameter
Conditions
Min
Max
Unit
N
Baud Divisor
Baud Output Positive Edge Delay1
1
65535
56
nsec
nsec
tBHD
CLK = 24 MHz/2, 100 pF load
CLK = 24 MHz/2, 100 pF load
Baud Output Negative Edge Delay1
56
nsec
tBLD
1. Not tested. Guaranteed by design.
N
CLK
tBLD
BAUD OUT
(÷1)
tBHD
tBLD
BAUD OUT
(÷2)
tBHD
tBHD
tBLD
BAUD OUT
(÷3)
tBLD
tBHD
BAUD OUT
(÷N, N > 3)
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Device Specifications
10.3.5 Transmitter Timing
Symbol
tHR
Parameter
Min
Max
40
55
24
24
8
Unit
nsec
Delay from WR (WR THR) to Reset IRQ
Delay from RD (RD IIR) to Reset IRQ (THRE)
Delay from Initial IRQ Reset to Transmit Start1
tIR
nsec
tIRS
tSI
8
Baud Output Cycles
Baud Output Cycles
Baud Output Cycles
Delay from Initial Write to IRQ1
16
Delay from Start Bit to IRQ (THRE)1
tSTI
1. Not tested. Guaranteed by design.
Serial
START
DATA (5-8)
PARITY STOP (1-2) START
Out
(SOUT)
tIRS
tSTI
Interrupt
(THRE)
tHR
tHR
tSI
WR
(WR THR)
Note 1
tIR
RD
(RD IIR)
Note 2
Notes:
1. See write cycle timing in Section 10.3.3 on page 172.
2. See read cycle timing in Section 10.3.3 on page 172.
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Device Specifications
10.3.6 Receiver Timing
Symbol Parameter
Min
Max
78
78
78
55
41
2
Unit
tRAI1
tRAI2
tRAI3
tRINT
tSCD
tSINT
nsec
Delay from Active Edge of RD to Reset IRQ
nsec
Delay from Active Edge of RD to Reset IRQ
Delay from Active Edge of RD to Reset IRQ
Delay from Inactive Edge of RD (RD LSR) to Reset IRQ
Delay from RCLK to Sample Time1
nsec
nsec
nsec
Delay from Stop bit to Set Interrupt2
Baud Output Cycles
1. This is internal timing and is therefore not tested.
2. Not tested. Guaranteed by design.
Standard Mode
RCLK
tSCD
8 CLKS
Sample
CLK
DATA (5-8)
STOP
SIN
Sample Clock
RDR
Interrupt
tRAI1
tSINT
LSI
Interrupt
tRINT
RD
(RD RBR)
ACTIVE
RD
ACTIVE
(RD LSR)
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Device Specifications
FIFO Mode
Data (5-8)
Stop
SIN
(FIFO at
or above
Trigger
Level)
Sample Clock
Trigger
Level
Interrupt
Note
tSINT
(FIFO
Below
Trigger
Level)
tRAI2
LSI
Interrupt
tRINT
RD
(RD LSR)
Active
RD
(RD RBR)
Active
Note:
If SCR0 = 1, then tSINT = 3 RCLKs. For a time-out interrupt, tSINT = 8 RCLKs.
Time-Out Mode
SIN
Stop
Sample Clock
(FIFO at
or above
Trigger
Level)
Time-Out or
Trigger Level
Interrupt
Note
tSINT
(FIFO
Below
Trigger
Level)
tRAI3
Top Byte of FIFO
tRINT
LSI Interrupt
tSINT
RD
Active
(RD LSR)
RD
(RD RBR)
Active
Active
Previous Byte
Read From FIFO
Note:
If SCR0 = 1, then tSINT = 3 RCLKs. For a time-out interrupt, tSINT = 8 RCLKs
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Device Specifications
10.3.7 UART, Sharp-IR, SIR and Consumer Remote Control Timing
Symbol Parameter
Conditions
Transmitter
Receiver
Min
Max
Unit
nsec
nsec
nsec
nsec
nsec
nsec
tBTN − 251
tBTN − 2%
tCWN − 252
tBTN + 25
tBTN + 2%
tCWN + 25
tBT
Single Bit Time in UART and Sharp-IR
Modulation Signal Pulse Width in
Sharp-IR and Consumer Remote
Control
Transmitter
Receiver
tCMW
500
tCPN − 253
tCPN + 25
Transmitter
Receiver
Modulation Signal Period in Sharp-IR
and Consumer Remote Control
tCMP
4
4
tMMIN
tMMAX
(3/16) x tBTN + 151
Transmitter,
Variable
(3/16) x tBTN − 151
nsec
tSPW
SIR Signal Pulse Width
Transmitter,
Fixed
1.48
1.78
µsec
µsec
Receiver
Transmitter
Receiver
1
± 0.87%
± 2.0%
± 2.5%
± 6.5%
SIR Data Rate Tolerance.
% of Nominal Data Rate.
SDRT
Transmitter
Receiver
SIR Leading Edge Jitter.
% of Nominal Bit Duration.
tSJT
1. tBTN is the nominal bit time in UART, Sharp-IR, SIR and Consumer Remote Control modes. It is deter-
mined by the setting of the Baud Generator Divisor registers.
2. tCWN is the nominal pulse width of the modulation signal for Sharp-IR and Consumer Remote Control
modes. It is determined by the MCPW field (bits 7-5) of the IRTXMC register at bank 7, offset 01h, and
the TXHSC bit (bit 2) of the RCCFG register at bank 7, offset 02h.
3. tCPN is the nominal period of the modulation signal for Sharp-IR and Consumer Remote Control modes. It
is determined by the MCFR field (bits 4-0) of the IRTXMC register at offset 01h and the TXHSC bit (bit 2)
of the RCCFG register at offset 02h.
4. tMMIN and tMMAX define the time range within which the period of the incoming subcarrier signal has to fall
in order for the signal to be accepted by the receiver. These time values are determined by the content of
register IRRXDC at bank 7, offset 00h and the setting of the RXHSC bit (bit 5) of the RCCFG register at
bank 7, offset 02h.
t
BT
UART
t
t
CMP
CMW
Sharp-IR
Consumer Remote Control
t
SPW
SIR
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Device Specifications
10.3.8 IRSLn Write Timing
Parameter
Symbol
Min
Max
Unit
tWOD
60
nsec
IRSLn Output Delay from Write Inactive
WR
tWOD
IRSLn
10.3.9 Modem Control Timing
Symbol
tHL
Parameter
Min
10
Max
Unit
nsec
nsec
nsec
nsec
nsec
RI2,1 High to Low Transition
RI2,1 Low to High Transition
tLH
10
tMDO
tRIM
40
78
40
Delay from WR (WR MCR) to Output
Delay to Reset IRQ from RD (RD MSR)
Delay to Set IRQ from Modem Input
tSIM
WR
(WR MCR)
Note 1
tMDO
tMDO
RTS, DTR
CTS, DSR, DCD
INTERRUPT
tSIM
tRIM
tSIM
tRIM
tSIM
RD
(RD MSR)
Note 2
tLH
tHL
RI
Notes:
1. See write cycle timing, Section 10.3.3 on page 172.
2. See read cycle timing, Section 10.3.3 on page 172.
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Device Specifications
10.3.10 FDC DMA Timing
Symbol Parameter
Min
25
Max
Unit
nsec
nsec
nsec
nsec
tKI
DACK Inactive Pulse Width
tKK
tKQ
tQK
tQP
tQQ
tQR
tQW
DACK Active Pulse Width
65
DACK Active Edge to DRQ Inactive
DRQ to DACK Active Edge
65
10
1
8 x tDRP
300
DRQ Period (Except Non-Burst DMA)
DRQ Inactive Non-Burst Pulse Width
DRQ to RD, WR Active
4002
nsec
nsec
15
1 3
1 3
DRQ to End of RD, WR (DRQ Service Time)
(8 x tDRP) − (16 x tICP
)
tQT
tRQ
tTQ
tTT
DRQ to TC Active (DRQ Service Time)
(8 x tDRP) − (16 x tICP
)
4
RD, WR Active Edge to DRQ Inactive
65
75
nsec
nsec
nsec
TC Active Edge to DRQ Inactive
TC Active Pulse Width
50
1. tDRP and tICP are defined in TABLE "" on page 171.
2. Only in case of pending DRQ.
3. Values shown are with the FIFO disabled, or with FIFO enabled and THRESH = 0. For nonzero values
of THRESH, add (THRESH x 8 x tDRP) to the values shown.
4. The active edge of RD or WR and TC is recognized only when DACK is active.
tQP
tQQ
DRQ
tQK
tKQ
tKK
DACK
tKI
tQW
RD, WR
tQR
tQT
tRQ
tTQ
TC
tTT
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180
Device Specifications
10.3.11 ECP DMA Timing
Symbol
tKIP
Parameter
Min
25
Max
65 + (6 x 32 x tCP
4003
Unit
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
DACK Inactive Pulse Width
DACK Active Pulse Width
tKKP
tKQP
tQKP
tQPP
tQQP
tQRP
tRQP
tTQP
tTT
65
DACK Active Edge to DRQ Inactive1 2
DRQ to DACK Active Edge
DRQ Period
)
10
330
300
15
DRQ Inactive Non-Burst Pulse Width
DRQ to RD, WR Active
RD, WR Active Edge to DRQ Inactive4
TC Active Edge to DRQ Inactive
TC Active Pulse Width
65
75
50
1. One DMA transaction takes six clock cycles.
2. tCP is defined in Section 10.3.2 on page 171.
3. Only in case of pending DRQ.
4. The active edge of RD or WR and TC is recognized only when DACK is active.
tQPP
tQQP
DRQ
tQKP
tKQP
tKKP
DACK
tKIP
RD, WR
tQRP
tRQP
tTQP
TC
tTT
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181
Device Specifications
10.3.12 UART2 DMA Timing
Symbol Parameter
Min
Max
Unit
tACH
tACS
tDCH
AEN Hold from RD, WR Inactive
5
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
AEN Signal Setup
15
0
DACK Hold from RD, WR Inactive
DACK Signal Setup
tDCS
tDSW
tRQS
15
60
RD, WR Pulse Width
1000
60
DRQ Inactive from RD, WR Active
TC Hold from RD, WR Inactive
TC Signal Setup
tTCH
tTCS
2
60
DRQ
AEN
tACH
tDCS
tDCH
DACK
tDSW
RD, WR
TC
tACS
tRQ
tTCS
tTCH
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182
Device Specifications
10.3.13 Reset Timing
Symbol Parameter
Min
Max
Unit
µsec
nsec
Reset Width1
tRW
100
Reset to Control Inactive2
tSRC
300
1. The software reset pulse width is 100 nsec.
2. Not tested. Guaranteed by design.
tRW
MR
tSRC
DRQ,
INT,
WGATE
(Note)
Note:
In PC-AT mode, the DRQ and IRQ signals of the FDC are in TRI-STATE after time tSRC
.
10.3.14 FDC - Write Data Timing
Symbol Parameter
Min
750
Max
Unit
µsec
µsec
HDSEL Hold from WGATE Inactive1
HDSEL Setup to WGATE Active1
tHDH
tHDS
100
See tDRP tICP
tWDW Values below
tWDW
Write Data Pulse Width
1. Not tested. Guaranteed by design.
HDSEL
WGATE
WDATA
tHDS
tHDH
tWDW
t
DRP tICP tWDW Values
tICP Nominal
tDRP
tICP
tWDW
tWDW Minimum
Data Rate
Unit
nsec
nsec
nsec
nsec
1
125
2 x tICP
2 x tICP
2 x tICP
2 x tICP
1 Mbps
500 Kbps
300 Kbps
250 Kbps
1000
2000
3333
4000
250
250
375
500
6 x tCP
6 x tCP
1
125
208
250
1
1
10 x tCP
12 x tCP
1. tCP is the Clock Period defined in Section 10.3.2 "Clock Timing" on page 171.
www.national.com
183
Device Specifications
10.3.15 FDC - Drive Control Timing
Symbol Parameter
Min
Max
Unit
nsec
µsec
nsec
msec
µsec
msec
tDRV
tDST
tIW
110
DR1,0 and MTR1,0 from End of WR
DIR Setup to STEP Active1
6
100
tSTR
8
Index Pulse Width
tSTD
tSTP
tSTR
DIR Hold from STEP Inactive
STEP Active High Pulse Width
STEP Rate Time (See TABLE 3-25.)
1
1. Not tested. Guaranteed by design.
WR
tDRV
tDRV
DR1,0
MTR1,0
DIR
tDST
tSTD
STEP
tSTP
tSTR
INDEX
tIW
10.3.16 FDC - Read Data Timing
Symbol Parameter
tRDW
Min
Max
Unit
50
nsec
Read Data Pulse Width
RDATA
tRDW
www.national.com
184
Device Specifications
10.3.17 Standard Parallel Port Timing
Symbol Parameter
Conditions
Typ
Max
Unit
These times are system dependent and are
therefore not tested.
500
nsec
tPDH
tPDS
Port Data Hold
Port Data Setup
These times are system dependent and are
therefore not tested.
500
nsec
tPILa
tPILia
tPIHa
tPIHia
tPIz
33
33
33
33
33
nsec
nsec
nsec
nsec
nsec
nsec
Port Active Low Interrupt, Active
Port Active Low Interrupt, Inactive
Port Active High Interrupt, Active
Port Active High Interrupt, Inactive
Port Active High Interrupt, TRISTATE
These times are system dependent and are
therefore not tested.
500
tSW
Strobe Width
Compatible Mode
ACK
IRQ
tPILa
tPILia
Extended Mode
ACK
IRQ
tPIHia
tPIz
tPIHa
tPIHa
(TRI-STATE)
RD STR
WR CTR4 = 0
Typical Data Exchange
BUSY
ACK
tPDH
tPDS
PD7-0
tSW
STB
www.national.com
185
Device Specifications
10.3.18 Enhanced Parallel Port 1.7 Timing
Symbol
tWW17
Parameter
Min
Max
45
Unit
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
WRITE Active or Inactive from WR Active or Inactive
DSTRB or ASTRB Active or Inactive from WR or RD Active or Inactive1
DSTRB or ASTRB Active after WRITE Becomes Active
PD7-0 Hold after WRITE Becomes Inactive
IOCHRDY Active or Inactive after WAIT Becomes Active or Inactive
PD7-0 Valid after WRITE Becomes Active2
tWST17
45
tWEST17
tWPD17h
tHRW17
tWPDS17
tEPDW17
tEPD17h
tZWS17a
tZWS17h
0
50
40
15
80
0
PD7-0 Valid Width
PD7-0 Hold after DSTRB or ASTRB Becomes Inactive
ZWS Valid after WR or RD Active
45
0
ZWS Hold after WR or RD Inactive
1. The PC87309 design guarantees that WRITE will not change from low to high before DSTRB, or
ASTRB, goes from low to high.
2. D7-0 is stable 15 nsec before WR becomes active.
WR
tZWS17h
RD
tZWS17a
tZWS17h
ZWS
tZWS17a
D7-0
Valid
tWW17
tWW17
WRITE
tWST17
tWEST17
tWST17
tWST17
DSTRB
or
ASTRB
tWST17
tEPD17h
PD7-0
Valid
tEPDW17
tWPDS17
tHRW17
tWPD17h
WAIT
tHRW17
tHRW17
IOCHRDY
www.national.com
186
Device Specifications
10.3.19 Enhanced Parallel Port 1.9 Timing
Symbol
tWW119a
tWW19ia
tWST19a
tWST19ia
tWEST19
tWPD19h
tHRW19
Parameter
Min
Max
45
Unit
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
nsec
WRITE Active from WR Active or WAIT Low1
WRITE Inactive from WAIT Low
45
DSTRB or ASTRB Active from WR or RD Active or WAIT Low1 2
DSTRB or ASTRB Inactive from WR or RD High
DSTRB or ASTRB Active after WRITE Active
PD7-0 Hold after WRITE Inactive
65
45
10
0
40
15
IOCHRDY Active after WR or RD Active or Inactive after WAIT High
PD7-0 Valid after WRITE Active3
tWPDS19
tEPDW19
tEPD19h
tZWS19a
tZWS19h
80
0
PD7-0 Valid Width
PD7-0 Hold after DSTRB or ASTRB Inactive
ZWS Valid after WR or RD Active
45
0
ZWS Hold after WR or RD Inactive
1. When WAIT is low, tWST19a and tWW19a are measured after WR or RD becomes active; else
WST19a and tWW19a are measured after WAIT becomes low.
t
2. The PC87307VUL design guarantees that WRITE will not change from low to high before
DSTRB, or ASTRB, goes from low to high.
3. D7-0 is stable 15 nsec before WR becomes active.
WR
RD
tWW19a
{Note a}
tZWS19h
tZWS19a
tZWS19h
ZWS
tZWS19a
Valid
D7-0
tWW19a
tWST19ia
WRITE
tWST19a
{Note a}
tWST19a
tWST19ia
{Note a}
DSTRB
or
ASTRB
tEPD19h
tWPD19h
tWST19a
tWST19a
tWEST19
Valid
PD7-0
tEPDW19
tWW19ia
tWPDS19
WAIT
tHRW19
tHRW19
tHRW19
tHRW19
IOCHRDY
www.national.com
187
Device Specifications
10.3.20 Extended Capabilities Port (ECP) Timing
Forward
Parameter
Symbol
tECDSF
Min
0
Max
Unit
nsec
nsec
nsec
sec
Data Setup before STB Active
Data Hold after BUSY Inactive
BUSY Active after STB Active
STB Inactive after BUSY Active
BUSY Inactive after STB Active
STB Active after BUSY Inactive
tECDHF
tECLHF
tECHHF
tECHLF
tECLLF
0
75
0
1
0
35
msec
nsec
0
tECDHF
PD7-0
AFD
tECDSF
STB
tECLLF
tECHLF
tECLHF
BUSY
tECHHF
Backward
Parameter
Symbol
Min
0
Max
Unit
nsec
nsec
nsec
sec
tECDSB
tECDHB
tECLHB
tECHHB
tECHLB
tECLLB
Data Setup before ACK Active
Data Hold after AFD Active
AFD Inactive after ACK Active
ACK Inactive after AFD Inactive
AFD Active after ACK Inactive
ACK Active after AFD Active
0
75
0
1
0
35
msec
nsec
0
tECDHB
PD7-0
BUSY
tECDSB
ACK
AFD
tECLLB
tECLHB
tECHLB
tECHHB
www.national.com
188
Glossary
DFIFO
Glossary
ECP Data FIFO in Extended Capabilities Port
(ECP) mode 011.
ADDR
Address Register of the Parallel Port in EPP
modes.
DID
DIR
Device ID register for the UARTs.
AFIFO
ASCR
Address FIFO for the Parallel Port in Extended Ca-
pabilities Port (ECP) mode 011.
Digital Input Register of the Floppy Disk Controller
(FDC) for read operations.
DOR
DSR
Auxiliary Status and Control Register for the
UART2 in Extended operation modes.
Digital Output Register of the Floppy Disk Control-
ler (FDC).
ASK-IR
Amplitude Shift Keying Infrared.
BGD(H) and BGD(L)
Baud rate Generator Divisor buffer (High and Low
Two expressions:
1. Data rate Select Register of the Floppy Disk Con-
troller (FDC) for write operations.
bytes) for the UARTs.
2. The Data Status Register of the Parallel Port in Ex-
tended Capabilities Port (ECP) modes.
BSR
DTR
Bank Selection Register for the UARTs, when en-
abled, i.e., when bit 7 of this register is 1.
Data Register of the Parallel Port in SPP or EPP
modes.
CCR
EAR
Configuration Control Register of the Floppy Disk
Controller (FDC) for write operations.
Extended Auxiliary Register of the Parallel Port in
Extended Capabilities Port (ECP) modes.
CFIFO
ECP
ECR
Parallel port data FIFO in Extended Capabilities
Port (ECP) mode 010.
Extended Capabilities Port.
CNFGA and CNFGB
Configuration registers A and B for the Parallel Port
in Extended Capabilities Port (ECP) mode 111.
Confg0
Extended Control Register for the Parallel Port in
Extended Capabilities Port (ECP) modes.
EDR
EIR
See PP Confg0.
Extended Data Register for the Parallel Port in ex-
tended Capabilities Port (ECP) modes.
Consumer Remote Control Mode
This IR mode supports all four protocols currently
used in remote-controlled home entertainment
equipment. Also called TV-Remote mode.
Two expressions:
1. Extended Index Register of the Parallel Port Ex-
tended Capabilities Port (ECP) modes.
Control0, Control2 and Control4
Internal configuration registers of the Parallel Port
in Extended Capabilities Port (ECP) modes.
2. Event Identification Register for the UARTs for read
cycles.
CSN
Extended UART Operation Mode
Card Select Number register - an 8-bit register with
a unique value that identifies an ISA card when us-
ing PnP protocol.
This UART operation mode supports standard
16450 and 16550A UART operations plus addition-
al interrupts and DMA features.
CTR
EPP
Control Register of the Parallel Port in SPP modes.
DASK-IR
Enhanced Parallel Port.
EXCR1 and EXCR2
Digital Amplitude Shift Keying Infrared.
DATA0, DATA1, DATA2 and DATA3
Data Registers of the Parallel Port in EPP modes.
DATAR
Extended Control Registers 1 and 2 for the UARTs.
FCR
The FIFO Control Register for the UARTs.
FDC
Data Register for the Parallel Port in Extended Ca-
pability Port (ECP) modes 000 and 001.
Floppy Disk Controller.
FDD
DCR
Floppy Disk Drive.
FER1 and FER2
Data Control Register for the Parallel Port in Ex-
tended Capabilities Port (ECP) modes.
Function Enable Registers of the Power Manage-
ment.
Device
Any circuit that performs a specific function, such
as a Parallel Port.
www.national.com
189
Glossary
Full-IR mode
In this mode, the PC87309 decodes address lines
Plug and Play
A design philosophy and a set of specifications that
A0-A10, and UART2 is a fully featured UART with
IR. The mode is configured during reset, via CFG0
strap pin.
describe hardware and software changes to the PC
and its peripherals that automatically identify and
arbitrate resource requirements among all devices
and buses on the system. Plug and Play is abbrevi-
ated as PnP.
IER
IR
The Interrupt Enable Register for the UARTs.
Infrared.
PM
Power Management.
IRCFG1, IRCFG3 and IRCFG4
PME
Infrared module Configuration registers for UART2.
IRCR1, IRCR2 and IRCR3
Power Management Event.
Infrared Module Control Registers 1, 2 and 3 for
UART2.
PMC1, PMC2 and PMC3
Power Management Control registers.
IrDA
PnP
Infrared Data Association.
Plug and Play.
PnP Mode
In this mode, the interrupts, the DMA channels and
IRRXDC
Infrared Receiver Demodulator Control register for
the UART2. (Logical Device 2, bank 7, offset 00h.)
the base address of the FDC, UARTs, KBC, GPIO
and the Parallel Port of the PC87309 are fully Plug
and Play.
IRTXMC
Infrared Transmitter Modulator Control register for
UART2.
PP Confg0
LBGD(H) and LBGD(L)
Internal configuration register of the Parallel Port in
Extended Capabilities Port (ECP) modes.
Legacy Baud rate Generator Divisor port (High and
Low bytes) for the UARTs.
Precompensation
LCR
Also called write precompensation, is a way of pre-
conditioning the WDATA output signal to adjust for
the effects of bit shift on the data as it is written to
the disk surface.
Link Control Register for the UARTs.
Legacy
Usually refers to older devices or systems that are
not Plug and Play compatible.
RBR
Receiver Buffer Register for the UARTs read opera-
tions.
Legacy Mode
In this mode, the interrupts and the base addresses
of the FDC, UARTs, KBC and the Parallel Port of
the PC87309 are configured as in earlier SuperI/O
chips.
RCCFG
Consumer Remote Control Configuration register
for UART2.
LFSR
RLC
RLE
The Linear Feedback Shift Register. This register is
used to prepare the chip for operation in Plug and
Play (PnP) mode.
Run Length Count byte for parallel ports.
Run Length Expander for parallel ports.
Reception FIFO Level for the UARTs.
System Control Interrupt.
LSR
RXFLV
SCI
Link Status Register for the UARTs.
MCR
Modem Control Register for the UARTs.
MSR
SCR
Two expressions:
Scratch Register for the UARTs.
1. Main Status Register of the FDC.
2. Modem Status Register for the UARTs.
Non-Extended UART Operation Modes
SH_FCR
Shadow of the FIFO Control Register (FCR) for the
UARTs.
SH_LCR
These UART operation modes support only UART
operations that are standard for 15450 or 16550A
devices.
Shadow of the Line Control Register (LCR) for the
UARTs for read operations.
PIO
Sharp IR Mode
Programmable Input/Output.
P_MDR
In this mode, the PC87309 supports a Sharp Infra-
red interface.
Pipeline Mode Register for the UARTs.
www.national.com
190
Glossary
SIR
Serial Infrared mode.
SIR_PW
SIR Pulse Width control for UART2.
SPP
The Standard Parallel Port configuration of the Par-
allel Port device supports the Compatible SPP
mode and the Extended PP mode.
SRA and SRB
Status Registers A and B of the FDC.
ST0, ST1, ST2 and ST3
Status registers 0, 1, 2 and 3 of the FDC.
STR
Status Register of the Parallel Port in SPP modes.
Tape Drive Register of the FDC.
TDR
TFIFO
Test FIFO for the Parallel Port in Extended Capabil-
ities Port (ECP) mode 110.
TV-Remote Mode
See Consumer Remote Control mode.
Two-UART mode
In this mode, the PC87309 decodes address lines
A0-A11. UART2 provides a 16550 UART with
SIN2/SOUT2 interface signals only or a partially IR
support with IRRX and IRTX signals only. The
mode is configured during reset, via CFG0 strap
pin.
TXFLV
Transmission FIFO Level for the UARTs.
www.national.com
191
- February 1998
Physical Dimensions
All dimensions are in millimeters
Plastic Quad Flatpack (PQFP), EIAJ
Order Number PC87309VLJ
NS Package Number VLJ100A
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1. Life support devices or systems are devices or
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2. A critical component is any component of a life support
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Products > Personal Computing > ISA Super I/O > PC87309
Product Folder
PC87309
SuperI/O Plug and Play Compatible Chip in Compact 100-Pin VLJ Packaging
Parametric Table
Generic P/N 87309
Contents
Primary Application
Operating Voltage
Compliance
Desktop
5 V
l
l
Datasheet
Package Availability, Models, Samples
& Pricing
PC97
NA
Fan Speed Control and Monitor
MIDI Port
No
Game Port
No
System Hardware Monitoring: Temp.
No
System Hardware Monitoring: Voltage No
Datasheet
Size
Title
(in
Kbytes)
Date
22-
May-
98
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Compatible Chip in Compact 100-Pin VLJ
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Package Availability, Models, Samples & Pricing
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Samples
&
Electronic
Orders
Package
Models
Std
Pack
Size
Part
Number
P
M
Status
#
pins
$US
each
Type
SPICE
IBIS
N/A
N/A
Quantity
PC87309- evaluation
IBW/EB board
PC87309- evaluation
Full
production
N/A
N/A
.
.
N/A
N/A
Full
production
ICK/EB
board
[logo
tray ©(M
1K+ $3.7500 of
66 MEG
.
PC87309-
IBW/VLJ
Full
production
Order Parts
PQFP 100
N/A pc87309.ibs
N/A pc87309.ibs
©
PC87
[logo
tray ©(M
.
PC87309-
ICK/VLJ
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production
Order Parts
PQFP 100
1K+ $3.7500 of
66
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P
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SI9137LG
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SI9122E
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