WED7P128ATA8004C25 [WEDC]
32MB to 4GB Flash Card; 32MB到4GB闪存卡
| 型号： | WED7P128ATA8004C25 |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 32MB to 4GB Flash Card |
| 文件： | 总10页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WED7PxxxATA80xxC25
White Electronic Designs
32MB to 4GB Flash Card
FEATURES
DESCRIPTION
ꢀ
ATA compatibility
The WED7PxxxATA80xxC25 series ATA card is an ATA
interface flash memory card based on flash technology.
The ATA card is constructed with a flash disk controller
chip and NAND-type flash memory device. Operates
from a single 5-Volt or 3.3-Volt power source. The card
is available in ATA type-2 form factor from 32MB to 4GB
unformatted capacity. Being able to emulate IDE hard disk
drives, WEDC’sATAcard is a perfect choice for solid-state
mass-storage in industrial applications.
ꢀ
Supports 3 variations of mode access
• I/O Card Mode
• Memory Card Mode
• True- IDE Mode
ꢀ
ꢀ
+5.5V / +3.0V single power supply.
Internal Error Correction Logic
• Data Interleave to 2 for each 256 Bytes.
* This product is subject to change without notice.
• Error Correction of 1 Byte random error per 128
Bytes of data.
• Automatic on-the-fly, in-buffer error correction.
ꢀ
ꢀ
Compatible with all PC Card Service and Socket
Service.
Integrated PC Card attribute memory of 256
Bytes(CIS).
ꢀ
ꢀ
ꢀ
4 PC Card function register support.
Supports Host-side Write Protect.
Automatic wake up from power-down on host reset
or command write.
ꢀ
ꢀ
Sector data transfers without microprocessor
intervention.
Operation Environment
• Temperature — 0°C ~ 65°C
• Humidity — 8% ~ 95%
PRODUCT TYPES
Card Density
32MB
64MB
128MB
256MB
512MB
1024MB
2048MB
4096MB
Model No.
7P032ATA80xxC25
7P064ATA80xxC25
7P128ATA80xxC25
7P256ATA80xxC25
7P512ATA80xxC25
7P1G0ATA80xxC25
7P2G0ATA80xxC25
7P4G0ATA80xxC25
xx = Housing
03 = WEDC logo
04 = No logo
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED7PxxxATA80xxC25
White Electronic Designs
BLOCK DIAGRAM
D0 to D15
BVD2/1SPKR/DASP#
A0 to A10
Data Bus
FAD [7:0]/FBD[7:0]
CE1#, CE2#
OE#, ATASEL#
WE#
Control Signal
FCE/7..01
Flash
Memory
IORD#
IOWR#
REG#
Controller
RESET/RESET#
CSEL#
RDY/BSY#/IREQ#/INTRQ
WP/IOIS16#
INPACK#
BVD1/STSCHG#/PDIAG#
WAIT#/IORDY
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED7PxxxATA80xxC25
White Electronic Designs
PIN ASSIGNMENTS AND PIN TYPE
Memory card mode
I/O Card Mode
Signal Name I/O
True IDE Mode
Memory card mode
I/O Card Mode
Signal Name I/O
True IDE Mode
Pin # Signal Name
I/O
Signal Name
GND
D3
I/O
Pin # Signal Name
I/O
–
Signal Name
GND
CD1#
D11
I/O
1
GND
D3
GND
D3
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
GND
CD1#
D11
GND
CD1#
D11
–
O
I/O
I/O
I/O
I/O
I
–
O
I/O
I/O
I/O
I/O
I
2
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
I/O
I/O
I/O
I
O
I/O
I/O
I/O
I/O
I
3
D4
D4
D4
4
D5
D5
D5
D12
D12
D12
5
D6
D6
D6
D13
D13
D13
6
D7
D7
D7
D14
D14
D14
7
CE1#
A10
OE#
N.C.
A9
CE1#
A10
OE#
N.C.
A9
CE1#
A10
ATASEL#
N.C.
A9
D15
D15
D15
8
I
I
I
CE2#
VS1
I
CE2#
VS1
I
CE2#
VS1
I
9
I
I
I
O
I
O
I
O
I
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
–
–
–
IORD#
IOWR#
NC
IORD#
IOWR#
NC
IORD#
IOWR#
NC
I
I
I
I
I
I
A8
I
A8
I
A8
I
–
–
–
N.C.
N.C.
WE#
RDY/BSY
Vcc
N.C.
N.C.
N.C.
N.C.
A7
–
N.C.
N.C.
WE#
IREQ#
Vcc
N.C.
N.C.
N.C.
N.C.
A7
–
N.C.
N.C.
WE#
INTRQ
Vcc
–
NC
–
NC
–
NC
–
–
–
–
NC
–
NC
–
NC
–
I
I
I
NC
–
NC
–
NC
–
O
O
O
NC
–
NC
–
NC
–
Vcc
–
Vcc
–
Vcc
–
–
–
N.C.
N.C.
N.C.
N.C.
A7
–
NC
–
NC
–
NC
–
–
–
–
NC
–
NC
–
NC
–
–
–
–
NC
–
NC
–
NC
–
–
–
–
NC
–
NC
–
NC
–
I
I
I
CSEL#
VS2
I
CSEL#
VS2
I
CSEL#
VS2
I
A6
I
A6
I
A6
I
O
I
O
I
O
I
A5
I
I
A5
I
I
A5
I
I
RESET
Wait#
INPACK#
REG#
BVD2
BVD1
D8
RESET
Wait#
INPACK#
REG#
SPKR#
STSCHG#
D8
RESET#
IORDY
INPACK#
REG#
DASP
PDIAG#
D8
A4
A4
A4
O
O
I
O
O
I
O
O
I
A3
I
A3
I
A3
I
A2
I
A2
I
A2
I
A1
I
A1
I
A1
I
I/O
I/O
I/O
I/O
O
O
–
I/O
I/O
I/O
I/O
O
O
–
I/O
I/O
I/O
I/O
O
O
–
A0
I
A0
I
A0
I
D0
I/O
I/O
I/O
O
–
D0
I/O
I/O
I/O
O
–
D0
I/O
I/O
I/O
O
–
D1
D1
D1
D9
D9
D9
D2
D2
D2
D10
D10
D10
WP
GND
IOIS16#
GND
IOIS16#
GND
CD2#
GND
CD2#
GND
CD2#
GND
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED7PxxxATA80xxC25
White Electronic Designs
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATING
Symbol
VCC
VIN
VOUT
TSTG
Parameter
Power supply
Input voltage
Rating
Units
V
V
V
°C
-0.3 to 6.0
-0.3 to VCC+0.3
-0.3 to VCC+0.3
-40 to 125
Output voltage
Storage temperature
DC CHARACTERISTICS:
I) Recommended Operating Conditions:
Symbol
VCC
VIN
Parameter
Power supply
Input voltage
Min.
3.0
0
Max.
Units
V
V
5.5
VCC
65
TOPR
Operating temperature
-20
°C
II) General DC Characteristics:
Symbol
IIL
IIH
IOZ
CIN
Parameter
Input low current
Conditions
no pull up/down
no pull up/down
Min
-1
-1
-10
4
Typ
Max
1
1
10
pF
pF
pF
Units
µA
µA
Input high current
Tri-state leakage current
Input capacitance
Output capacitance
Bi-direction capacitance
µA
COUT
CBID
4
4
III) DC Electrical Characteristics:
Symbol
VIL
Parameter
Input low voltage
Min
Typ
Max
0.3VCC
Units
V
VIH
Input high voltage
0.7VCC
V
VIL
VIH
VOL
VOH
RI
Schmitt input low voltage
Schmitt input high voltage
Output low voltage
Output high voltage
Input pull up/down resistance
1.22
2.08
V
V
V
V
0.4
1
2.3
75
kΩ
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED7PxxxATA80xxC25
White Electronic Designs
AC CHARACTERISTICS:
Attribute Memory Read Timing Specification
Attribute Memory access time is defined as 300ns. Detailed timing specs are shown in Table below.
300 ns
Speed Version
Item
Read Cycle Time
Symbol
tc(R)
IEEE Symbol
tAVAV
Min ns.
300
Max ns.
Address Access Time
ta(A)
tAVQV
tELQV
tGLQV
tEHQZ
tGHQZ
tAVGL
tELQNZ
tGLQNZ
tAXQX
300
300
150
100
100
Card Enable Access Time
Output Enable Access Time
Output Disable Time from CE
Output Disable Time from OE
Address Setup Time
Output Enable Time from CE
Output Enable Time from OE
Data Valid from Address Change
ta(CE)
ta(OE)
tdis(CE)
tdis(OE)
tsu(A)
ten(CE)
ten(OE)
tv(A)
30
5
5
0
Note: All times are in nanoseconds. The CE# signal or both the OE# signal and the WE# signal must be de-asserted between consecutive cycle operations.
Configuration Register (Attribute Memory) Write Timing Specification
The Card Configuration write access time is defined as 250ns. Detailed timing specifications are shown in Table below.
Speed Version
250 ns
Item
Write Cycle Time
Symbol
tc(W)
tw(WE)
tsu(A)
trec(WE)
tsu(D-WEH)
th(D)
IEEE Symbol
tAVAV
Min ns
250
150
30
30
80
Max ns
Write Pulse Width
Address Setup Time
Write Recovery Time
Data Setup Time for WE
Data Hold Time
tWLWH
tAVWL
tWMAX
tDVWH
tWMDX
30
Note: All times are in nanoseconds.
Common Memory Read Timing Specification
Item
Symbol
ta(OE)
tdis(OE)
tsu(A)
th(A)
tsu(CE)
th(CE)
tv(WT-OE)
tv(WT)
tw(WT)
IEEE Symbol
tGLQV
Min ns.
Max ns.
125
100
Output Enable Access Time
Output Disable Time from OE
Address Setup Time
Address Hold Time
CE Setup before OE
CE Hold following OE
Wait Delay Falling from OE
Data Setup for Wait Release
Wait Width Time
tGHQZ
tAVGL
tGHAX
tELGL
30
20
0
tGHEH
20
tGLWTV
tQVWTH
tWTLWTH
35
0
350 (3000 for CF+)
Note: The maximum load on -WAIT# is 1 LSTTL with 50pF total load. All times are in nanoseconds. The WAIT# signal may be ignored if the OE# cycle to cycle time is greater than
the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA specification of 12ps but is
intentionally less in this specification.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED7PxxxATA80xxC25
White Electronic Designs
AC CHARACTERISTICS (cont'd):
I/O Input (Read) Timing Specification
Item
Symbol
td(IORD)
IEEE Symbol
tIGLQV
Min ns.
Max ns.
100
Data Delay after IORD
Data Hold following IORD
IORD Width Time
Address Setup before IORD
Address Hold following IORD
CE Setup before IORD
CE Hold following IORD
REG Setup before IORD
REG Hold following IORD
INPACK Delay Falling from IORD
INPACK Delay Rising from IORD
IOIS16 Delay Falling from Address
IOIS16 Delay Rising from Address
Wait Delay Falling from IORD
Data Delay from Wait Rising
Wait Width Time
th(IORD)
tw(IORD)
tsuA(IORD)
thA(IORD)
tIGHQX
tIGLIGH
tAVIGL
tIGHAX
tELIGL
0
165
70
20
5
20
5
0
tsuCE(IORD)
thCE(IORD)
tsuREG(IORD)
thREG(IORD)
tdfINPACK(IORD)
tdrINPACK(IORD)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
tdWT(IORD)
td(WT)
tIGHEH
tRGLIGL
tIGHRGH
tIGLIAL
tIGHIAH
tAVISL
0
45
45
35
35
35
0
tAVISH
tIGLWTL
tWTHQV
tWTLWTH
tw(WT)
350 (3000 for CF+)
Note: Maximum load on WAIT#, INPACK# and I0IS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT# high to IORD# high is Onsec, but
minimum IORD# width must still be met. Wait Width time meets PCMCIA specification of 12ps but is intentionally less in this spec.
I/O Output (Write) Timing Specification
Item
Symbol
tsu(IOWR)
th(IOWR)
tw(IOWR)
tsuA(IOWR)
thA(IOWR)
tsuCE(IOWR)
thCE(IOWR)
tsuREG(IOWR)
thREG(IOWR)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
tdWT(IOWR)
tdrIOWR(WT)
tw(WT)
IEEE Symbol
tDVIWH
Min ns.
Max ns.
Data Setup before IOWR
Data Hold following IOWR
IOWR Width Time
60
30
165
70
20
5
20
5
0
tIWHDX
tIWLIWH
tAVIWL
tIWHAX
tELIWL
Address Setup before IOWR
Address Hold following IOWR
CE Setup before IOWR
CE Hold following IOWR
REG Setup before IOWR
REG Hold following IOWR
IOIS16 Delay Falling from Address
IOIS16 Delay Rising from Address
Wait Delay Falling from IOWR
IOWR high from Wait high
Wait Width Time
tIWHEH
tRGLIWL
tIWHRGH
tAVISL
35
35
35
tAVISH
tIWLWTL
tWTJIWH
tWTLWTH
0
350 (3000for CF+)
Note: The maximum load on WAIT#, INPACK#, and I0IS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT# high to IOWR# high is Onsec,
but minimum IOWR# width must still be met. The Wait Width time meets the PCMCIA specification of 12ps but is intentionally less in this specification.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED7PxxxATA80xxC25
White Electronic Designs
AC CHARACTERISTICS (cont'd):
True IDE Mode I/O Input (Read) Timing Specification
Item
Symbol
td(IORD)
th(IORD)
tw(IORD)
tsuA(IORD)
thA(IORD)
tsuCE(IORD)
thCE(IORD)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
IEEE Symbol
tIGLQV
Min ns.
Max ns.
100
Data Delay after IORD
Data Hold following IORD
IORD Width Time
Address Setup before IORD
Address Hold following IORD
CE Setup before IORD
CE Hold following IORD
I0IS16 Delay Falling from Address
I0IS16 Delay Rising from Address
tIGHQX
tIGLIGH
tAVIGL
tIGHAX
tELIGL
tIGHEH
tAVISL
tAVISH
0
165
70
20
5
20
35
35
Note: The maximum load on I0IS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT# high to IORD# high is 0 nsec, but minimum IORD# width
must still be met.
True IDE Mode I/O Output (Write) Timing Specification
Item
Symbol
tsu(IOWR)
th(IOWR)
tw(IOWR)
tsuA(IOWR)
thA(IOWR)
tsuCE(IOWR)
thCE(IOWR)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
IEEE Symbol
tDVIWH
tIWHDX
tIWLIWH
tAVIWL
Min ns.
60
30
165
70
20
Max ns.
Data Setup before IOWR
Data Hold following IOWR
IOWR Width Time
Address Setup before IOWR
Address Hold following IOWR
CE Setup before IOWR
CE Hold following IOWR
I0IS16 Delay Falling from Address
I0IS16 Delay Rising from Address
tIWHAX
tELIWL
tIWHEH
tAVISL
tAVISH
5
20
35
35
Note: The maximum load on I0IS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT# high to IOWR# high is 0 nsec, but minimum IOWR#
width must still be met.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED7PxxxATA80xxC25
White Electronic Designs
PACKAGE DIMENSIONS
Type II
1.6mm 0.05
85.6mm 0.20
(0.063”)
3.0mm MIN
(0.118”)
(3.370”)
1.0mm 0.05
(0.039”)
54.0mm 0.10
(2.126”)
Substrate area
1.0mm 0.05
(0.039”)
10.0mm MIN
(0.400”)
5.0mm T1
(0.197”)
Interconnect area
3.3mm 0.10
(0.129”)
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED7PxxxATA80xxC25
White Electronic Designs
PART NUMBERING GUIDE
WED 7P xxx ATA 80 xx C 25
WEDC
Flash
Memory Size
ATA Flash
Commercial Flash
Housing:
03 = WEDC Logo
04 = Blank Housing
Commercial Temp
Speed
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WED7PxxxATA80xxC25
White Electronic Designs
Document Title
32MB to 4GB Flash Card
Revision History
Rev #
History
Release Date Status
Rev 0
Initial Release
March 2005
Final
Rev 1
1.1 Added "ED" to part marking
July 2005
Final
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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