WE128K32N-200G2TCA [WEDC]
128Kx32 EEPROM MODULE, SMD 5962-94585; 128Kx32 EEPROM模块， SMD 5962-94585
| 型号： | WE128K32N-200G2TCA |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 128Kx32 EEPROM MODULE, SMD 5962-94585 |
| 文件： | 总14页 (文件大小：621K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WE128K32-XXX
White Electronic Designs
128Kx32 EEPROM MODULE, SMD 5962-94585
FEATURES
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Page Write Cycle Time: 10ms Max
ꢀ
Access Times of 120**, 140, 150, 200, 250, 300ns
Packaging:
Data Polling for End of Write Detection
Hardware and Software Data Protection
TTL Compatible Inputs and Outputs
5 Volt Power Supply
ꢀ
• 66-pin, PGA Type, 27.3mm (1.075") square,
Hermetic Ceramic HIP (Package 400)
• 68 lead, 22.4mm sq. CQFP (G2T), 4.57mm
(0.180") high, (Package 509)
Built-in Decoupling Caps and Multiple Ground Pins
for Low Noise Operation
ꢀ
Organized as 128Kx32; User Configurable as
256Kx16 or 512Kx8
ꢀ
Weight
ꢀ
ꢀ
ꢀ
Write Endurance 10,000 Cycles
WE128K32-XG2TX - 8 grams typical
WE128K32-XH1X - 13 grams typical
Data Retention Ten Years Minimum (at +25°C)
Commercial, Industrial and Military Temperature
Ranges
** 120ns not available for SMD product
ꢀ
ꢀ
Low Power CMOS
*This product is subject to change without notice.
Automatic Page Write Operation
FIGURE 1 – PIN CONFIGURATION FOR
WE128K32N-XH1X
Pin Description
Top View
I/O0-31
A0-16
WE1-4#
CS1-4#
OE#
Data Input/Output
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
1
12
23
34
45
56
I/O8
I/O9
I/O10
A13
WE2#
CS2#
GND
I/O11
A10
I/O15
I/O14
I/O13
I/O12
OE#
NC
I/O24
I/O25
I/O26
A6
VCC
CS4#
WE4#
I/O27
A3
I/O31
I/O30
I/O29
I/O28
A0
VCC
GND
NC
Not Connected
A14
A7
A15
A11
NC
A4
A1
Block Diagram
A16
A12
WE1#
I/O7
A8
A5
A2
WE1
#
CS1
#
WE2
#
CS2
#
WE3
#
CS3
#
WE4 # CS4#
NC
VCC
A9
WE3#
CS3#
GND
I/O19
I/O23
I/O22
I/O21
I/O20
OE#
A
0-16
I/O0
I/O1
I/O2
CS1#
NC
I/O6
I/O16
I/O17
I/O18
128K x 8
128K x 8
128K x 8
128K x 8
I/O5
I/O3
I/O4
8
8
8
8
11
22
33
44
55
66
I/O16-23
I/O24-31
I/O0-7
I/O8-15
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 10
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE128K32-XXX
White Electronic Designs
FIGURE 3 – PIN CONFIGURATION FOR WE128K32-XG2TX
Top View
Pin Description
I/O0-31
Data Input/Output
Address Inputs
Write Enable
Chip Selects
Output Enable
Power Supply
Ground
9
8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
A0-16
WE1-4#
CS1-4#
OE#
VCC
GND
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
1
2
3
4
5
6
7
I/O16
I/O17
I/O18
I/O19
I/O20
I/O21
I/O22
I/O23
GND
I/O24
I/O25
I/O26
I/O27
I/O28
I/O29
I/O30
I/O31
GND
Not Connected
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Block Diagram
WE
1
#
CS
1
#
WE
2
#
CS
2
#
WE
3
#
CS
3
#
4 4
WE # CS #
OE#
A
0-16
128K x 8
128K x 8
128K x 8
128K x 8
8
8
8
8
I/O16-23
I/O24-31
I/O0-7
I/O8-15
The WEDC 68 lead CQFP
fills the same fit and function
as the JEDEC 68 lead CQFJ
or 68 PLCC. But it has the
TCE and lead inspection
advantage of the CQFP
form.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 10
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE128K32-XXX
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
Parameter
Symbol
TA
TSTG
VG
Unit
°C
°C
V
CS#
H
L
L
X
OE#
X
L
H
H
WE#
X
H
L
X
Mode
Standby
Read
Write
Out Disable
Write
Data I/O
High Z
Data Out
Operating Temperature
Storage Temperature
Signal Voltage Relative to GND
Voltage on OE# and A9
-55 to +125
-65 to +150
-0.6 to + 6.25
-0.6 to +13.5
Data In
High Z/Data Out
V
NOTE:
X
X
X
L
H
X
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Inhibit
CAPACITANCE
TA = +25°C
Parameter
OE# capacitance
WE1-4# capacitance
HIP (PGA)
Symbol
COE
CWE
Conditions
VIN = 0 V, f = 1.0 MHz 50 pF
VIN = 0 V, f = 1.0 MHz
Max Unit
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
VCC
VIH
Min
4.5
2.0
-0.5
-55
-40
Max
5.5
Unit
V
pF
Supply Voltage
20
20
Input High Voltage
Input Low Voltage
Operating Temp. (Mil.)
Operating Temp. (Ind.)
VCC + 0.3
+0.8
+125
+85
V
V
°C
°C
CQFP G2T
VIL
TA
TA
CS1-4# capacitance
Data I/O capacitance
Address input capacitance
CCS
CI/O
CAD
VIN = 0 V, f = 1.0 MHz 20 pF
VI/O = 0 V, f = 1.0 MHz 20 pF
VIN = 0 V, f = 1.0 MHz 50 pF
This parameter is guaranteed by design but not tested.
DC CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Symbol
ILI
ILOx32
ICCx32
ISB
VOL
VOH
Conditions
Min
Max
10
10
250
2.5
0.45
Unit
µA
µA
mA
mA
V
Input Leakage Current
Output Leakage Current
Operating Supply Current (x32)
Standby Current
Output Low Voltage
Output High Voltage
VCC = 5.5, VIN = GND to VCC
CS# = VIH, OE# = VIH, VOUT = GND to VCC
CS# = VIL, OE# = VIH, f = 5MHz
CS# = VIH, OE# = VIH, f = 5MHz
IOL = 2.1mA, VCC = 4.5V
IOH = -400µA, VCC = 4.5V
2.4
V
NOTE: DC test conditions: VIH = VCC -0.3V, VIL = 0.3V
FIGURE 3
AC TEST CONDITIONS
AC Test Circuit
I
OL
Parameter
Typ
Unit
V
Current Source
Input Pulse Levels
VIL = 0, VIH = 3.0
Input Rise and Fall
5
1.5
1.5
ns
V
V
Input and Output Reference Level
Output Timing Reference Level
Notes: VZ is programmable from -2V to +7V.
V
~ 1.5V
~
z
D.U.T
= 50 pf
Bipolar Supply
C
eff
I
OL & IOH programmable from 0 to 16mA.
Tester Impedance Z0 = 75Ω.
Z is typically the midpoint of VOH and VOL
OL & IOH are adjusted to simulate a typical resistive load circuit.
ATE tester includes jig capacitance.
V
I
.
I
OH
Current Source
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 10
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE128K32-XXX
White Electronic Designs
AC WRITE CHARACTERISTICS
WRITE
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
A write cycle is initiated when OE# is high and a low pulse
is on WE# or CS# with CS# or WE# low. The address
is latched on the falling edge of CS# or WE# whichever
occurs last. The data is latched by the rising edge of CS#
or WE#, whichever occurs first. A byte write operation will
automatically continue to completion.
Write Cycle Parameter
Symbol Min
Max
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time, TYP = 6ms
Address Set-up Time
tWC
10
tAS
tWP
tCS
0
100
0
Write Pulse Width (WE# or CS#)
Chip Select Set-up Time
Address Hold Time
tAH
100
10
0
Data Hold Time
tDH
write cycle timing
Chip Select Hold Time
Data Set-up Time
tCSH
tDS
Figures 5 and 6 show the write cycle timing relationships.
Awrite cycle begins with address application, write enable
and chip select. Chip select is accomplished by placing
the CS# line low. Write enable consists of setting the WE#
line low. The write cycle begins when the last of either CS#
or WE# goes low.
50
0
Output Enable Set-up Time
Output Enable Hold Time
Write Pulse Width High
tOES
tOEH
tWPH
0
50
The WE# line transition from high to low also initiates
an internal 150 µsec delay timer to permit page mode
operation. Each subsequent WE# transition from high to
low that occurs before the completion of the 150 µsec time
out will restart the timer from zero. The operation of the
timer is the same as a retriggerable one-shot.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 10
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE128K32-XXX
White Electronic Designs
FIGURE 5 – WRITE WAVEFORMS WE# CONTROLLED
tWC
OE#
tOEH
t OES
ADDRESS
CS1-4#
tCSH
tAS
tCS
t AH
WE1-4#
tWP
t WPH
t DH
tDS
DATA IN
FIGURE 6 – WRITE WAVEFORMS CS# CONTROLLED
tWC
OE#
tOEH
t OES
ADDRESS
WE1 - 4#
CS1 - 4#
tCSH
tAS
tCS
tAH
tWP
t WPH
t DH
tDS
DATA IN
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 10
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE128K32-XXX
White Electronic Designs
READ
The WE128K32-XXX stores data at the memory location
determined by the address pins. When CS# and OE# are
low and WE# is high, this data is present on the outputs.
When CS# and OE# are high, the outputs are in a high
impedance state. This two line control prevents bus
contention.
AC READ CHARACTERISTICS
VCC = 5.0V, GND = 0V, -55°C ≤ TA ≤ +125°C
-120 -140 -150
Min Max Min Max Min Max Min Max Min Max Min Max
-200
-250
-300
Read Cycle Parameter
Symbol
Unit
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Hold from Add. Change, OE# or CS#
Output Enable to Output Valid
Chip Select or OE# to High Z Output
tRC
tACC
tACS
tOH
tOE
tDF
120
140
150
200
250
300
ns
ns
ns
ns
ns
ns
120
120
140
140
150
150
200
200
250
250
300
300
0
0
0
0
0
0
0
0
0
0
0
0
50
60
55
70
55
70
55
70
85
70
85
70
FIGURE 7 – READ WAVEFORMS
t RC
ADDRESS VALID
ADDRESS
CS#
OE#
tACS
tOE
tDF
tACC
HIGH Z
t OH
OUTPUT
VALID
OUTPUT
Notes:
OE# may be delayed up to tACS - tOE after the falling edge of CS# without impact
on tOE or by tACC - tOE after an address change without impact on tACC.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 10
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE128K32-XXX
White Electronic Designs
DATA POLLING CHARACTERISTICS
DATA POLLING
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
The WE128K32-XXX offers a data polling feature which
allows a faster method of writing to the device. Figure 8
shows the timing diagram for this function. During a byte
or page write cycle, an attempted read of the last byte
written will result in the complement of the written data
on D7 (for each chip.) Once the write cycle has been
completed, true data is valid on all outputs and the next
cycle may begin. Data polling may begin at any time during
the write cycle.
Parameter
Symbol
tDH
tOEH
tOE
Min
10
10
Max
Unit
ns
ns
ns
ns
Data Hold Time
OE# Hold Time
OE# To Output Valid
Write Recovery Time
55
tWR
0
FIGURE 8 – DATA POLLING WAVEFORMS
WE1-4#
CS1-4#
OE#
tOEH
tOE
tDH
I/O7
HIGH Z
tWR
ADDRESS
TOGGLE BUT CHARACTERISTICS(1)
TOGGLE BIT: In addition to DATA# Polling another method for determining the end of
a write cycle is provided. During the write operation, successive attempts to read data
from the device will result in I/O6 toggling between one and zero. Once the write has
completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may
begin at any time during the write cycle.
Symbol Parameter
Min
Max
Units
ns
tDH
tOEH
tOE
Data Hold Time
10
OE# Hold Time
10
ns
OE# to Output Delay
OE# High Pulse
ns
tOEHP
tWR
150
0
ns
Write Recovery Time
ns
WE#
CS#
tOEH
OE#
tDH
tOE
HIGH Z
I/O6 (2)
tWR
NOTE:
1. Toggling either OE# or CS# or both OE# and CS# will operate toggle bit.
2. Beginning and ending state of I/O6 will vary
3. Any address location may be used but the address should not vary.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 10
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE128K32-XXX
White Electronic Designs
PAGE WRITE CHARACTERISTICS
PAGE WRITE OPERATION
(VCC = 5.0V, VSS = 0V, TA = -55°C to +125°C)
The WE128K32-XXX has a page write operation that
allows one to 128 bytes of data to be written into the device
and consecutively loads during the internal programming
period. Successive bytes may be loaded in the same
manner after the first data byte has been loaded. An
internal timer begins a time out operation at each write
cycle. If another write cycle is completed within 150µs
or less, a new time out period begins. Each write cycle
restarts the delay period. The write cycles can be continued
as long as the interval is less than the time out period.
Page Mode Write Characteristics
Parameter
Write Cycle Time, TYP = 6ms
Address Set-up Time
Address Hold Time (1)
Data Set-up Time
Data Hold Time
Write Pulse Width
Byte Load Cycle Time
Write Pulse Width High
1. Page address must remain valid for duration of write cycle.
Symbol
Unit
Min
Max
10
tWC
tAS
tAH
tDS
tDH
tWP
tBLC
tWPH
ms
ns
ns
ns
ns
ns
µs
ns
0
100
50
10
100
150
The usual procedure is to increment the least significant
address lines from A0 through A6 at each write cycle. In
this manner a page of up to 128 bytes can be loaded in
to the EEPROM in a burst mode before beginning the
relatively long interval programming cycle.
50
After the 150µs time out is completed, the EEPROM
begins an internal write cycle. During this cycle the entire
page of bytes will be written at the same time. The internal
programming cycle is the same regardless of the number
of bytes accessed.
FIGURE 9 – PAGE MODE WRITE WAVEFORMS
OE#
CS#
WE#
ADDRESS
DATA
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 10
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE128K32-XXX
White Electronic Designs
FIGURE 10 – SOFTWARE BLOCK DATA PROTECTION ENABLE ALGORITHM(1)
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA A0
WRITES ENABLED(2)
TO
ADDRESS 5555
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
ENTER DATA
PROTECT STATE
LAST ADDRESS
NOTES:
1. Data Format: D7 - D0 (Hex);
Address Format: A16 - A0 (Hex).
2. Write Protect state will be activated at end of write even if no other data is loaded.
3. Write Protect state will be deactivated at end of write period even if no other data is loaded.
4. 1 to 128 bytes of data to be loaded.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 10
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE128K32-XXX
White Electronic Designs
FIGURE 10 –
SOFTWARE DATA PROTECTION
SOFTWARE BLOCK DATA PROTECTION
A software write protection feature may be enabled
or disabled by the user. When shipped by White
Microelectronics, the WE-128K32-XXX has the feature
disabled. Write access to the device is unrestricted.
DISABLE ALGORITHM(1)
To enable software write protection, the user writes three
access code bytes to three special internal locations.
Once write protection has been enabled, each write to the
EEPROM must use the same three byte write sequence
to permit writing. After setting software data protection,
any attempt to write to the device without the three-byte
command sequence will start the internal write timers. No
data will be written to the device, however, for the duration
of tWC. The write protection feature can be disabled by
a six byte write sequence of specific data to specific
locations. Power transitions will not reset the software
write protection.
LOAD DATA AA
TO
ADDRESS 5555
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 80
TO
ADDRESS 5555
LOAD DATA AA
TO
ADDRESS 5555
Each 128K byte block of the EEPROM has independent
write protection. One or more blocks may be enabled and
the rest disabled in any combination. The software write
protection guards against inadvertent writes during power
transitions, or unauthorized modification using a PROM
programmer.
LOAD DATA 55
TO
ADDRESS 2AAA
LOAD DATA 20
TO
ADDRESS 5555
EXIT DATA
PROTECT STATE(3)
HARDWARE DATA PROTECTION
These features protect against inadvertent writes to the
WE128K32-XXX. These are included to improve reliability
during normal operation:
LOAD DATA XX
TO
ANY ADDRESS(4)
LOAD LAST BYTE
TO
LAST ADDRESS
a)
VCC power on delay
As VCC climbs past 3.8V typical the device will wait
5msec typical before allowing write cycles.
b)
VCC sense
While below 3.8V typical write cycles are inhibited.
c) Write inhibiting
Holding OE# low and either CS# or WE# high
inhibits write cycles.
d) Noise filter
NOTES:
Pulses of <8ns (typ) on WE# or CS# will not initiate
a write cycle.
1. Data Format: D7 - D0 (Hex);
Address Format: A16 - A0 (Hex).
2. Write Protect state will be activated at end of write even if
no other data is loaded.
3. Write Protect state will be deactivated at end of write
period even if no other data is loaded.
4. 1 to 128 bytes of data may be loaded.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 10
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE128K32-XXX
White Electronic Designs
PACKAGE 400: 66 PIN, PGA TYPE, CERAMIC HEX-IN-LINE PACKAGE, HIP (H1)
4.60 (0.181)
MAX
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 10
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE128K32-XXX
White Electronic Designs
PACKAGE 509: 68 LEAD, CERAMIC QUAD FLAT PACK, CQFP (G2T)
ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 10
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE128K32-XXX
White Electronic Designs
FIGURE 12 – ALTERNATE PIN CONFIGURATION FOR WE128K32NP-XH1X
Top View Pin Description
I/O0-31
A0-16
WE1-4#
CS1-4#
OE#
VCC
GND
NC
Data Inputs/Outputs
Address Inputs
Write Enables
Chip Selects
Output Enable
Power Supply
Ground
1
12
23
34
45
56
I/O
8
9
WE
2
#
I/O15
I/O24
I/O25
I/O26
V
CS
WE
CC
I/O31
I/O30
I/O29
I/O28
I/O
CS
2
#
I/O14
I/O13
I/O12
OE#
NC
4
4
#
#
I/O10
GND
I/O11
A14
A16
A11
A0
A7
I/O27
A
A
A
V
10
A
12
A
A
A
4
5
5
A1
A2
A3
Not Connected
9
NC
Block Diagram
WE
1
#
CS
1
#
WE
2
#
CS
2
#
WE
3
#
CS
3
#
4 4
WE # CS #
15
CC
WE1
#
A13
OE#
A
0-16
NC
I/O
I/O
I/O
I/O
7
A
8
WE
3
3
#
#
I/O23
I/O22
I/O21
I/O20
128K x 8
128K x 8
128K x 8
128K x 8
I/O
I/O
I/O
0
CS
NC
I/O
1
#
6
I/O16
I/O17
I/O18
CS
1
2
5
4
GND
I/O19
8
8
8
8
3
I/O16-23
I/O24-31
I/O0-7
I/O8-15
11
22
33
44
55
66
ORDERING INFORMATION
W E 128K32 X - XXX X X X
LEAD FINISH:
Blank = Gold plated leads
A = Solder dip leads
DEVICE GRADE:
Q = Compliant
M = Military Screened
I = Industrial
C = Commercial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
PACKAGE TYPE:
H1 = 1.075" sq. Ceramic Hex In-line Package, HIP (Package 400*)
G2T = 22.4mm Ceramic Quad Flat Pack, Low Profile CQFP (Package 509)
ACCESS TIME (ns)
IMPROVEMENT MARK
N = No Connect at pins 8, 21, 28, and 39 in HIP for upgrade
P = Alternate Pin Configuration for HIP package
ORGANIZATION 128K x 32
User Configurable as 256K x 16 or 512K x 8
EEPROM
WHITE ELECTRONIC DESIGNS CORP.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 10
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WE128K32-XXX
White Electronic Designs
DEVICE TYPE
SPEED
PACKAGE
SMD NO.
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
300ns
250ns
200ns
150ns
140ns
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
66 pin HIP (H1)
5962-94585 01H5X
5962-94585 02H5X
5962-94585 03H5X
5962-94585 04H5X
5962-94585 05H5X
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
300ns
250ns
200ns
150ns
140ns
66 pin HIP (H1, P type pinout)
66 pin HIP (H1, P type pinout)
66 pin HIP (H1, P type pinout)
66 pin HIP (H1, P type pinout)
66 pin HIP (H1, P type pinout)
5962-94585 01H6X
5962-94585 02H6X
5962-94585 03H6X
5962-94585 04H6X
5962-94585 05H6X
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
128K x 32 EEPROM Module
300ns
250ns
200ns
150ns
140ns
68 lead CQFP/J (G2T)
68 lead CQFP/J (G2T)
68 lead CQFP/J (G2T)
68 lead CQFP/J (G2T)
68 lead CQFP/J (G2T)
5962-94585 01HMX
5962-94585 02HMX
5962-94585 03HMX
5962-94585 04HMX
5962-94585 05HMX
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
March 2006
Rev. 10
14
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
相关型号：
©2020 ICPDF网 联系我们和版权申明