W7N1G16VH2SBI [WEDC]
Flash Memory Drive, IDE Compatible, CMOS, PBGA224, 27 X 22 MM, 2.60 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-224;
| 型号： | W7N1G16VH2SBI |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | Flash Memory Drive, IDE Compatible, CMOS, PBGA224, 27 X 22 MM, 2.60 MM HEIGHT, 1.27 MM PITCH, PLASTIC, BGA-224 数据传输 PC 驱动 外围集成电路 驱动器 |
| 文件： | 总13页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W7NxxxVHxxBISx
White Electronic Designs
ADVANCED*
Secure Embedded SLC NAND SSD PBGA
FEATURES
Built in ATA/PCMCIA 2.1, and compact flash 3.0
Storage Capacities:
4GBYTE and 8GBYTE**
Environment conditions:
interface capability
•
Hardware & software triggered security erase that
meets:***
•
•
Operating temperature: -40°C to 85°C
Storage temperature: -55°C to 125°C
•
•
•
•
•
NISPOM DoD 5220.22-M
NSA - 130-2
SLC Flash
Airforce AFSSI - 5020
Army AR380-19
•
•
3.3V single power supply
256 Bytes of attribute memory
Navy NAVSO P-5234-26
Power consumption
Page read operation
•
•
3.3V ± 10%
Page Program time: 200μs (Typ)
Block erase time: 1.5ms (Typ)
Program/Erase lockout during transition
Active mode: Read, Write, Erase operation:
95 mA (Typ), 150 (Max)
•
•
Sleep mode: 10 mA (Typ); TBD mA (Max)
Secure erase: 85 mA (Max) (4GB)
Data transfer rate: Up to 66MB/s UDMA mode 4
Up to 25MB/s PIO mode 6 or
MDMA mode 4
Interface modes
Sustained read: Up to 45 MBytes/s
•
•
•
PC card memory mode
Sustained write: Up to 30 MBytes/s with interleaving
Random read: Up to 35 MBytes/s
PC card I/O mode
True IDE mode
Random write: Up to 6 MBytes/s
Less than 1 Error in 1014 bits read
MTBF > 4,000,000 hours
DESCRIPTION
High shock & vibration tolerance
W/E Endurance: 4,000,000 write/erase cycles
High performance
The W7NxxxVHxxBISx series embedded SLC NAND
SSD PBGA is based on flash technology. This product is
constructed with 32bit RISC base controller and SLC NAND
flash memory devices. They operate from a single 3.3 volt
power supply. Capacity ranges from 4GB to 8GB**.
•
•
•
•
Interface Transfer speed in PIO mode 6
Typical write: 30 MBytes/s in ATA PIO mode 6
Typical read: 45 MBytes/s in ATA PIO mode 6
* This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
** 8GB capacity is TBD.
On card ECC up to 4 Bytes per 512 Byte data
sector
Dimensions:
*** This feature will not be available for sample production
•
27mm x 22mm x 2.60mm
Highly resistant to data corruption due to power loss
Single device connector free solution for embedded
environments
TABLE 1
Item
Size
4GB
Performance
Sophisticated wear leveling firmware
W7N2G16VHxxBISx
W7N4G16VHxxBISx
Enhanced reliability with a 1.27mm pitch; eutectic
tin-lead solder ball
3.0 to 3.60
8GB**
Same form, fit and functionality as W7NxxxVHxxBI
with the following exceptions: M9 = EXTPWR and
L11 = EXTTRIG for secure erase
November 2009
Rev. 1
© 2010 White Electronic Designs Corp. All rights reserved
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NxxxVHxxBISx
White Electronic Designs
ADVANCED*
FIGURE 1 – 224 PBGA PIN CONFIGURATION – TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A
B
C
D
E
F
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
IOCS16#
(IOIS16#)
(WP)
PDIAG#
(STSCHG#)
(BVD1)
IORDY
(WAIT#)
DMACK#
(REG#)
GND
GND
VCC
VCC
VCC
GND
CSEL#
GND
D00
D09
D01
D04
VCC
GND
GND
D10
D15
VCC
VCC
VCC
GND
GND
NC
DASP#
(SPKR#)
(BVD2)
DMARQ
(INPACK#)
CS1#
(CE2#)
CS0#
(CE1#)
WE#
IOWR#
GND
GND
GND
A05
IORD#
D14
GND
D07
D12
D03
D13
D02
NC
INTRQ
(IREQ#)
(READY)
ATASEL#
(OE#)
NC
VCC
NC
D08
GND
GND
VCC
NC
NC
GND
GND
GND
A10
A09
A08
NC
G
H
J
RESET#
(RESET)
NC
GND
A02
A01
A04
NC
NC
GND
GND
NC
A03
A00
GND
NC
D05
D11
K
L
A06
D06
EXTTRIG
GND
NC
A07
EXTPWR
NC
M
N
P
R
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NOTE: Pin assignemts are identical to the W7NxxxVHxxBI standard embedded SLC NAND SSD BGA except for M9 - EXTPWR and L11 - EXTTRIG.
November 2009
Rev. 1
© 2010 White Electronic Designs Corp. All rights reserved
2
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NxxxVHxxBISx
White Electronic Designs
ADVANCED
WN7xxxVHxxBISx Secure
NAND SSD PBGA Features:
1. Secure Erase: A hardware or software triggered erase 5. The W7NxxxVHxxBISx will initiate a Secure Erase:
which will erase all internal customer data, including
a. by a logic low level applied to the EXTTRIG pin
data which may have been left in blocks which have
for >50ms. The EXTTRIG pin must be high for
been set aside because of wear leveling or blocks which
>200ms on power-up before arming to allow a
have been declared bad by the flash controller. This
Secure Erase command from this source. The
Secure Erase will be completed within 10 (Typ) sec
EXTTRIG pin has an internal 4.7K pull-up resistor
of initiation.
to 3.3V, and is de-bounced, so a momentary
2. Power Loss: Once a Secure Erase has been initiated,
if power is lost, then the Secure Erase will complete
the next time power is restored.
contact to ground or an open-drain output can
also be used.
b. by the receipt of a serial “Secure Erase” command
on the EXTTRIG pin. The serial "Secure Erase"
command uses Manchester like encoding on this
single signal line.
3. EXTPWR: An external power pin is provided to which
a backup power supply can be connected. If VCC is
removed from the BGA, the part will continue to operate
from the backup power supply. If a battery or capacitor
based temporary power source is attached, a Secure
Erase could be completed even after the main power
on VCC is lost. For the 4GB W7N2G16VH1SBISx,
a maximum of 85 mA is needed for ~10 sec during
Secure Erase.
c. Additonal data available on secure app. note:
4. Security Erase: The following Security Erase protocol
standards will be supported as options. The customer
may select one of these standard protocols to be
included:
a. NISPOM DoD 5220.22-M
b. NSA-130-2
c. Air Force AFSSI-5020
d. Army AR380-19
e. Navy NAVSO P-5239-26
Upon initiation of a Secure Erase, the simple erase
discussed in item 1 above will be completed first, then
the erase protocol which has been specified by the
customer will commence. This allows the data to be
purged quickly for an emergency situation, and also
allows the data to be erased to the specified protocol
in a longer time frame.
November 2009
Rev. 1
© 2010 White Electronic Designs Corp. All rights reserved
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NxxxVHxxBISx
White Electronic Designs
ADVANCED
ENVIRONMENTAL CHARACTERIZATION
Item
Performance
Temperature Cycle
Humidity
JEDEC - JESD STD A104 Temp condition N (-40°C to 85 °C) and soak mode 3; 200 cycles
MIL-STD 810F, Method 507.4, Paragraph 4.5.2 - 10 day test per figure 507.4-1, 10 day test
MIL-STD 810F, Method 514.5, procedure 1, category 24, 1 hour per axis
Vibration
MIL-STD 810F, Method 516.5, procedure1, non-operational, 40g, SRS functional shock for ground equipment, three (3)
shock per axis (positive or negative).
Shock
JEDEC- JESD22-B, 104-A, test condition B,1500 g pulse, 0.5 msec
Altitude
MIL-STD 810F, Method 500.4, procedure II, modified to 80,000 ft and non operation 1 hr test duration at altitude
PRODUCT RELIABILITY
Item
Value
MTBF (@ 25°C)
Data reliability
Endurance
TBD
< 1 Non-Recoverable Error in 1014 Bits Read
TBD
PRODUCT PERFORMANCE
Item
Performance (PIO mode 6 true IDE)
45MBYTES/s
Read Transfer Rate (Typical)
Write Transfer Rate (Typical)
30MBYTES/s
Controller Overhead
(Command to DRQ)
1ms typical, 5ms (max)
ABSOLUTE MAXIMUM RATINGS
Symbol
TA
Parameter
Min
-40
Max
+85
Unit
C
Operating Free-Air Temperature
Storage Temperature
TSTG
VG
-40
+105
VCC +0.5
4.0
C
Signal Voltage Relative to GND
Supply Voltage
-0.5
-0.5
V
VCC
V
CURRENT CONSUMPTION FOR SECURE ERASE
Symbol
ICC
Parameter
Temp
Max
TBD
10
Unit
mA
mA
mA
85°C
ICC
Supply Current
25°C
ICC
-40°C
TBD
November 2009
Rev. 1
© 2010 White Electronic Designs Corp. All rights reserved
4
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NxxxVHxxBISx
White Electronic Designs
ADVANCED
DC ELECTRICAL CHARACTERISTICS
Symbol
VCC
VIL
Parameter
Min
3.0
-0.3
2.0
—
Max
3.6
Units
Notes
Supply Voltage Range
Input LOW Voltage
Input HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Operating Current, VCC = 3.3V
Sleep Mode
V
V
V
V
V
+0.8
—
—
VIH
VCC+0.3
0.45
VOL
at 4mA
-1mA
VOH
ICC
2.4
—
—
—
—
TBD
165
±10
±10
mA
mA
μA
μA
—
—
—
—
Operating
ILI
Input Leakage Current
Output Leakage Current
ILO
CI,O
Input/Output Capacitance
—
10
pF
—
ATTRIBUTE MEMORY READ AND WRITE AC CHARACTERISTICS
3.3 V ±0.3V
Symbol
tcR
Parameter
Min
250
—
—
—
—
—
5
Max
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
ta(A)
Address Access Time
250
250
125
100
100
—
ta(CE)
ta(OE)
tdis(CE)
tdis(OE)
ten(CE)
ten(OE)
tv(A)
Card Enable Access Time
Output Enable Access Time
Output Disable time from CE#
Output Disable time from OE#
Output Enable time from CE#
Output Enable time from OE#
Data valid time from address change
Address Setup Time
5
—
0
—
tsu(A)
th(A)
30
20
0
—
Address Hold Time
—
tsu(CE)
th(CE)
tcW
Card Enable Setup Time
Card Enable Hold Time
Write Cycle Time
—
20
250
—
—
tw(WE)
tsu(A-WEH)
tsu(CE-WEH)
tsu(D-WEH)
th(D)
Write Pulse TIme
150
30
30
80
30
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address setup time for WE#
Card Enable setup time for WE#
Data setup time for WE#
—
—
Data hold time
—
tdis(WE)
Output disable time from WE#
Output enable time from WE#
Output Enable setup time for WE#
Output Enable hold time from WE#
100
—
ten(WE)
5
tsu(OE-WE)
th(OE-WE)
10
10
—
—
November 2009
Rev. 1
© 2010 White Electronic Designs Corp. All rights reserved
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NxxxVHxxBISx
White Electronic Designs
ADVANCED
COMMON MEMORY READ AND WRITE AC CHARACTERISTICS
Symbol
tcR
Parameter
Min
80
—
—
—
—
—
5
Max
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
ta(A)
Address Access Time
55
55
45
45
45
—
ta(CE)
ta(OE)
tdis(CE)
tdis(OE)
ten(CE)
ten(OE)
tV(A)
Card Enable Access Time
Output Enable Access Time
Output Disable time from CE#
Output Disable time from OE#
Output Enable time from CE#
Output Enable time from OE#
Data valid time from address change
Address Setup Time
5
—
0
—
tsu(A)
th(A)
10
10
0
—
Address Hold Time
—
tsu(CE)
th(CE)
tcW
Card Enable Setup Time
Card Enable Hold Time
Write Cycle Time
—
10
80
—
—
tw(WE)
tsu(A-WEH)
tsu(CE-WEH)
tsu(D-WEH)
th(D)
Write Pulse TIme
55
10
0
—
—
—
—
—
—
45
—
—
—
ns
ns
ns
ns
ns
—
ns
ns
ns
ns
Address setup time for WE#
Card Enable setup time for WE#
Data setup time for WE#
30
10
15
—
5
Data hold time
trec(WE)
Data record time from WE#
Output disable time from WE#
Output enable time from WE#
Output Enable setup time for WE#
Output Enable hold time from WE#
tdis(WE)
ten(WE)
tsu(OE-WE)
th(OE-WE)
10
10
November 2009
Rev. 1
© 2010 White Electronic Designs Corp. All rights reserved
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NxxxVHxxBISx
White Electronic Designs
ADVANCED
I/O ACCESS READ AND WRITE AC CHARACTERISTIC
Symbol
td(IORD)
Parameter
Min
Max
45
—
—
—
—
—
—
—
—
45
45
35
35
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Delay after IORD#
—
5
th(IORD)
Data Hold following IORD#
IORD# pulse width
tw(IORD)
55
15
10
5
tsuA(IORD)
thA(IORD)
Address setup time for IORD#
Address hold time for IORD#
Card Enable setup time for IORD#
Card Enable hold time from IORD#
REG setup time for IORD#
REG Hold time from IORD#
INPACK delay falling from IORD#
INPACK delay rising from IORD#
IOIS16 delay falling from address
IOIS16 delay rising from address
Data setup time for IOWR#
Data hold time from IOWR#
IOWR# pulse width
tsuCE(IORD)
thCE(IORD)
tsuREG(IORD)
thREG(IORD)
tdflNP(IORD)
tdrlNP(IORD)
tdflO16(IORD)
tdrlO16(IORD)
tsu(IOWR)
10
5
0
0
—
—
—
15
5
th(IOWR)
tw(IOWR)
55
15
tsuA(IOWR)
Address setup time for IOWR#
thA(IOWR)
tsuCE(IOWR)
thCE(IOWR)
Address hold time from IOWR#
Card Enable setup time for IOWR#
Card Enable hold time from IOWR#
10
5
—
—
—
—
—
ns
ns
ns
ns
ns
10
5
tsuREG(IOWR) REG setup time for IOWR#
thREG(IOWR)
REG hold tme from IOWR#
0
November 2009
Rev. 1
© 2010 White Electronic Designs Corp. All rights reserved
7
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NxxxVHxxBISx
White Electronic Designs
ADVANCED
TRUE-IDE PIO MODE READ AND WRITE CHARACTERISTICS
Symbol
Parameter
Min
80
10
10
55
20
10
5
Max
—
—
—
—
—
—
—
20
—
—
Units
ns
t0
t1
Cycle time
Address setup time for IORD#/IOWR#
Address hold time from IORD#/IOWR#
IORD#/IOWR# pulse width
ns
t9
ns
t2
ns
t2i
t5
IORD#/IOWR# recovery time
Data setup time for IORD#
ns
ns
t6
Data setup time for IORD#
ns
t6z
t3
Output disable time from IORD#
Data setup time for IOWR#
—
15
5
ns
ns
t4
Data hold following IOWR#
ns
TRUE-IDE MDMA MODE READ AND WRITE CHARACTERISTICS
Symbol
Parameter
Min
80
55
—
5
Max
—
—
45
—
—
—
—
—
—
35
—
—
25
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tO
tD
tE
tF
tG
tH
tI
Cycle time
IORD#/IOWR# pulse width
IORD# data access
Data hold following IORD#
Data setup time for IORD#/IOWR#
Data hold following IOWR#
10
5
DMACK# setup time for IORD#/IOWR#
DMACK# hold following IORD#/IOWR#
IORD#/IOWR# recovery time
0
tJ
5
t
KR, tKW
20
—
5
tLR, tLW
IORD#/IOWR# to DMARQ delay
CS0#, CS1# setup for IORD#/IOWR#
CS0#, CS1# hold following IORD#/IOWR#
Output disable time from DMACK#
tM
tN
tZ
10
—
TRUE-IDE IDMA MODE READ AND WRITE CHARACTERISTICS
The interface timing in the True-IDE UDMA modes is not only depending on the interface hardware, but also on the
correct setup of the UDMA registers in the firmware, according to the UDMA transfer mode selected by the host. With
a correct register setup, the interface timing complies to the UDMA Mode 0 to Mode 4 timing specifications of the CF
Specification Revision 4.1, and to the UDMA Mode 0 to Mode 4 timing specifications of the ATA/ATAPI-6 Standard.
November 2009
Rev. 1
© 2010 White Electronic Designs Corp. All rights reserved
8
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NxxxVHxxBISx
White Electronic Designs
ADVANCED
PIN ASSIGNMENTS & PIN TYPE
TBD
TBD
Pin Number
A02-A15
B01-B15
C01-C15
D01-D03
D04
Signal Name
Pin Type
No Connect
No Connect
No Connect
No Connect
Ground
Ground
Pin Number
H08
Signal Name
GND
GND
D07
Pin Type
Ground
Ground
I/O
I/O
Power
No Connect
No Connect
NC
NC
NC
NC
GND
H09
H10
H11
H12
H13-H15
J01-J03
J04
J05
J06
J07
J08
J09
J10
J11
J12
J13-J15
K01-K03
K04
D04
VCC
NC
D05
D06
D07
D08
GND
IOCS16# (IOIS16#) (WP)
IORDY (WAIT#)
DMACK# (REG#)
CSEL#
O
O
I
NC
RESET# (RESET)
NC
I
No Connect
Ground
Ground
Ground
Power
I/O
Power
Power
D09
I
GND
GND
GND
VCC
D12
VCC
VCC
NC
NC
NC
PDIAG# (STSCHG#)
(BVD1)
D10
I/O
D11
D12
D13-D15
E01-E03
E04
GND
GND
NC
NC
Ground
Ground
No Connect
No Connect
Ground
I/O
No Connect
No Connect
No Connect
GND
E05
E06
DASP# (SPKR#) (BVD2)
DMARQ (INPACK#)
O
K05
A03
I
E07
WE#
I
K06
A02
I
E08
CS1# (CE2#)
I
K07
A05
I
E09
CS0# (CE1#)
I
K08
A10
I
E10
IORD#
I
K09
D05
I/O
E11
D00
I/O
K10
K11
K12
K13-K15
L01-L03
L04
L05
L06
D03
D11
VCC
NC
NC
GND
A00
A01
A06
I/O
I/O
Power
No Connect
No Connect
Ground
E12
GND
NC
NC
VCC
Ground
No Connect
No Connect
Power
No Connect
O
E13-E15
F01-F03
F04
F05
F06
F07
F08
F09
F10
NC
INTRQ (IREQ#) (READY)
I
I
I
I
IOWR#
ATASEL# (OE#)
D08
I
I
L07
L08
I/O
I/O
A09
D14
L09
D06
I/O
F11
D09
I/O
L10
D13
I/O
F12
D10
I/O
L11
L12
L13-L15
M01-M03
M04
M05
M06
M07
M08
EXTTRIG
GND
NC
I/O
F13-F15
G01-G03
G04
G05
G06
G07
G08
G09
G10
NC
NC
VCC
VCC
No Connect
No Connect
Power
Power
No Connect
Ground
Ground
Ground
Ground
I/O
Ground
No Connect
No Connect
Ground
Ground
I
NC
GND
GND
A04
A07
A08
NC
GND
GND
GND
GND
D01
I
I
M09
M10
EXTPWR
D02
Power
I/O
G11
G12
D15
I/O
M11
M12
M13-M15
N01-N15
P01-P15
R01-R15
GND
GND
NC
NC
NC
Ground
Ground
No Connect
No Connect
No Connect
No Connect
G13-G15
H01-H03
H04
H05
H06
NC
NC
VCC
NC
NC
GND
No Connect
No Connect
Power
No Connect
No Connect
Ground
NC
H07
November 2009
Rev. 1
© 2010 White Electronic Designs Corp. All rights reserved
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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NxxxVHxxBISx
White Electronic Designs
ADVANCED
SIGNAL DESCRIPTION
Signal Name
Dir.
I,U
I
Description
CS0# (CE1#)
Card Enable 1
CS1# (CE2#)
Card Enable 2
DMACK# (REG#)
WE#
DMA Acknowledge (Attribute Memory or I/O Enable)
Memory Write Enable
ATASEL# (OE#)
IOWR# (STOP)
IORD#
True-IDE Mode select (Output Enable)
I/O Write Enable (Terminate ultra DMA data burst)
I/O Read Enable
I,U
CSEL#
True-IDE Master/Slave select
RESET# (RESET)
A10..A00
Reset signal. This pin includes an input filter that filters pulses shorter than about 40 ns.
Address Bus. Unused pins may be left open, or connected to GND.
Data Bus
I/O
O,U
D15..D00
DMARQ (INPACK#)
INTRQ (IREQ#) (READY)
PDIAG# (STSCHG#) (BVDI)
DASP# (SPKR#)(BVD2)
IORDY (WAIT#)
IOCS16# (IOIS16#) (WP)
EXTTRIG
DMA Acknowledge (Input Acknowledge)
Interrupt Request (Interrupt Request) (Ready/Busy signal )
True-IDE DIAG (Status Change ) (Unsupported)
True-IDE DASP (Unsupported) (Unsupported)
I/O Ready (UDMA DDMARDY#, DSTROBE) (Wait)
Word Data Transfer (I/O is 16 bit signal ) (Write Protect)
External Secure Erase Trigger Input
I/O,U
O
I, U
EXTPWR
PWR
External Backup Power Input
TYPICAL SERIES TERMINATION FOR ULTRA DMA
Signal
Host Termination
22 ohm
Device Termination
82 ohm
IORD# (HDMARDY#, HSTROBE)
IOWR# (STOP)
CS0#, CS1#
22 ohm
82 ohm
33 ohm
82 ohm
A00, A01, A02
DMACK#
33 ohm
82 ohm
22 ohm
82 ohm
D00 through D15
DMARQ
33 ohm
33 ohm
82 ohm
22 ohm
INTRQ
82 ohm
22 ohm
IORDY (DDMARDY#, DSTROBE)
RESET#
82 ohm
22 ohm
33 ohm
82 ohm
Note: Host Interface Terminator Resistors are at the discretion of the user, but are required for all Ultra DMA modes according to the ATA/ATAPI-6 Specification and the CFA
CompactFlash Specification 4.1. Only those signals needing termination are listed in this table. If a signal is not listed, series termination is not needed for operation in an Ultra
DMA mode. The actual termination values should be selected to compensate for transceiver and trace impedance to match the characteristic cable or board trace impedance.
November 2009
Rev. 1
© 2010 White Electronic Designs Corp. All rights reserved
10
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NxxxVHxxBISx
White Electronic Designs
ADVANCED
PACKAGE DIMENSIONS
BOTTOM VIEW
224x Ø 0.84 (0.033) MAX
15 14 13 12 11 10 9
8
7
6
5
4
3
2 1
A
B
C
D
E
F
G
H
J
22.1 (0.87) MAX
17.78 BSC
K
L
M
N
P
1.27 (.050)
TYP
R
0.69 (0.027)
TYP
1.27 (.050)
TYP
2.11 (.083)
TYP
4.61
(.181)
TYP
2.86 (0.113)
MAX
17.78
BSC
27.01 (1.07)
MAX
ALL DIMENSIONS ARE IN MILLIMETERS (PARENTHESES FOR INCHES)
November 2009
Rev. 1
© 2010 White Electronic Designs Corp. All rights reserved
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NxxxVHxxBISx
White Electronic Designs
ADVANCED
Part Numbering Guide
W 7N xxx V H X x B I S x
WEDC:
Flash, SLC - NAND:
Memory Capacity:
512M16 = 1G Byte
1G16 = 2G Byte
2G16 = 4G Byte
4G16 = 8G Byte**
Voltage:
3.3V
Controller/Manufacturer:
ROCKV3
Controller/Firmware revision number:
1, 2, 3...
Memory Mfg.:
S = Samsung
Package Type:
B = 224 Pin BGA
Temperature:
I = Industrial (-40°C - +85°C)
Secure
Blank = Default
A = NISPOM DoD 5220.22-M
B = NSA-130-2
C = Airforce AFSSI-5020v
D = Army AR380-19
E = Navy NAVSO P-5239-26
* For help selecting the proper and most current part number for your application please contact your local sales representative.
Example:
Part number for
4GBYTE: W7N2G16VH1SBISA
November 2009
Rev. 1
© 2010 White Electronic Designs Corp. All rights reserved
12
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
W7NxxxVHxxBISx
White Electronic Designs
ADVANCED
Document Title
Secure Embedded SLC NAND SSD PBGA
Revision History
Rev #
History
Release Date Status
Rev 0
Initial Release
October 2009
Advanced
Rev 1
Changes (2, 3, 11)
1.1 Correct spelling of "pin."
1.2 Correct spelling of "serial" and "encoding."
1.3 Change dimensions to "MAX" for "width and height."
November 2009
Rev. 1
© 2010 White Electronic Designs Corp. All rights reserved
13
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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