EDI88128CDXCB [WEDC]
128Kx8 Monolithic SRAM, SMD 5962-89598; 128Kx8单片SRAM ， SMD 5962-89598
| 型号： | EDI88128CDXCB |
| 厂家： | 
WHITE ELECTRONIC DESIGNS CORPORATION |
| 描述： | 128Kx8 Monolithic SRAM, SMD 5962-89598 |
| 文件： | 总9页 (文件大小：464K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EDI88128CS
White Electronic Designs
128Kx8 Monolithic SRAM, SMD 5962-89598
FEATURES
• 32 pad Ceramic LCC (Package 141)
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Access Times of 15*, 17, 20, 25, 35, 45, 55ns
CS# and OE# Functions for Bus Control
2V Data Retention (EDI88128LPS)
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
• 32 lead Ceramic Flatpack (Package 142)
ꢀ
Single +5V ( 10ꢀ) Supply OperationThe
EDI88128CS is a high speed, high performance,
128Kx8 megabit density Monolithic CMOS Static
RAM.
Organized as 128Kx8
The device has eight bi-directional input-output lines to
provide simultaneous access to all bits in a word. An
automatic power down feature permits the on-chip circuitry
to enter a very low standby mode and be brought back into
operation at a speed equal to the address access time.
Commercial, Industrial and Military Temperature
Ranges
ꢀ
Thru-hole and Surface Mount Packages JEDEC
Pinout
ALowPowerversionwith2VDataRetention(EDI88128LPS)
is also available for battery back-up opperation. Military
product is available compliant to MIL-PRF-38535.
• 32 pin Ceramic DIP, 400 mil (Package 102)
• 32 pin Ceramic DIP, 600 mil (Package 9)
• 32 lead Ceramic ZIP (Package 100)
• 32 lead Ceramic SOJ (Package 140)
* 15ns access time is advanced information, contact factory for availability.
This product is subject to change without notice.
FIGURE 1 – PIN CONFIGURATION
PIN DESCRIPTION
32 DIP
32 SOJ
32 LCC
32 FLATPACK
TOP VIEW
I/O0-7
A0-16
WE#
CS#
OE#
VCC
VSS
NC
Data Inputs/Outputs
Address Inputs
Write Enable
32 ZIP
TOP VIEW
Chip Select
Output Enable
Power (+5V 10ꢀ%
Ground
NC
A16
A14
A12
A7
1
2
3
4
5
6
7
8
9
NC
A16
A14
A12
A7
1
2
3
4
5
6
7
8
9
32 VCC
V
CC
A15
NC
31 A15
30 NC
29 WE#
28 A13
27 A8
WE#
Not Connected
10 A13
12 A8
A6 11
A6
A5 13
A4 15
A3 17
A2 19
A1 21
A0 23
I/O0 25
I/O1 27
I/O2 29
A5
26 A9
14 A9
A4
25 A11
24 OE#
23 A10
22 CS#
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
16 A11
18 OE#
20 A10
22 CS#
24 I/O7
26 I/O6
28 I/O5
30 I/O4
32 I/O3
A3
A2 10
A1 11
BLOCK DIAGRAM
A0 12
I/O0 13
I/O1 14
I/O2 15
Memory Array
VSS 31
V
SS 16
Address
Buffer
Address
Decoder
I/O
Circuits
A
0-16
I/O0-7
WE#
CS#
OE#
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2000
Rev. 10
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88128CS
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
TRUTH TABLE
Parameter
Unit
V
OE# CS# WE#
Mode
Standby
Output Deselect
Read
Output
High Z
High Z
Data Out
Data In
Power
Icc2, Icc3
Icc1
Icc1
Icc1
Voltage on any pin relative to VSS
Operating Temperature TA (Ambient%
Commercial
Industrial
Military
Storage Temperature, Plastic
Power Dissipation
Output Current
Junction Temperature, TJ
NOTE:
-0.5 to 7.0
X
H
L
H
L
L
L
X
H
H
L
0 to +70
-40 to +85
-55 to +125
-65 to +150
1.5
°C
°C
°C
°C
W
X
Write
Recommended Operating Conditions
Parameter
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
20
175
mA
°C
Symbol
VCC
VSS
VIH
VIL
Min
4.5
0
2.2
-0.3
Typ
5.0
0
—
—
Max
5.5
0
Unit
V
V
Stress greater than those listed under "Absolute Maximum Ratings" may cause
VCC +0.5
+0.8
V
V
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
TA = +25°C
Parameter
Symbol
Condition
Max
Unit
CSOJ,
LLC
ZIP, DIP,
Flatpack
Address Lines
Data Lines
CI
CO
VIN = VCC or VSS, f = 1.0MHz
VOUT = VCC or VSS, f = 1.0MHz 14
12
pF
pF
These parameters are sampled, not 100ꢀ tested.
DC CHARACTERISTICS
VCC = 5.0V, -55°C ≤ TA ≤ +125°C
Symbol Conditions
Parameter
Input Leakage Current
Output Leakage Current
Min
—
—
Typ
—
—
Max
5
10
Units
µA
µA
ILI
VIN = 0V to VCC
VI/O = 0V to VCC
ILO
(15-17ns%
(20ns%
—
—
—
—
—
300
225
200
25
60
mA
mA
mA
mA
mA
Operating Power Supply Current
Icc1
Icc2
WE#, CS# = VIL, II/O = 0mA, CS2 = VIH
CS# ≥ VIH, VIN ≤ VIH or ≥ VIL
(25-55ns%
(17-55ns%
(15ns%
Standby (TTL% Power Supply Current
CS (17-55ns%
CS (15ns%
LPS
—
—
—
—
2.4
3
10
15
5
0.4
—
mA
mA
mA
V
CS# ≥ VCC -0.2V
Full Standby Power Supply Current
Icc3
—
—
—
—
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
Output Low Voltage
Output High Voltage
VOL
VOH
IOL = 8.0mA
IOH = -4.0mA
V
NOTE: DC test conditions : VIL = 0.3V, VIH = VCC -0.3V
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2000
Rev. 10
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88128CS
White Electronic Designs
AC CHARACTERISTICS – READ CYCLE (15 to 20ns)
VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C
Parameter
Units
Symbol
15ns*
17ns
20ns
JEDEC
Alt.
tRC
tAA
tACS
tCLZ
tCHZ
tOH
Min
15
Max
Min
17
Max
Min
20
Max
Read Cycle Time
Address Access Time
Chip Enable Access Time
tAVAV
tAVQV
tELQV
tELQX
tEHQZ
tAVQX
tGLQV
tGLQX
tGHQZ
tELICCH
tEHICCL
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
15
17
17
20
20
Chip Enable to Output in Low Z (1%
Chip Disable to Output in High Z (1%
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1%
Output Disable to Output in High Z(1%
Chip Enable to Power Up (1%
Chip Enable to Power Down (1%
3
0
0
0
3
0
0
0
3
0
0
0
8
6
8
6
10
8
tOE
tOLZ
tOHZ
tPU
6
6
8
tPD
15
17
20
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – READ CYCLE (25 to 55ns)
VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C
Symbol
25ns
35ns
45ns
55ns
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1%
Chip Disable to Output in High Z (1%
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1%
Output Disable to Output in High Z(1%
Chip Enable to Power Up (1%
Chip Enable to Power Down (1%
JEDEC
Alt.
tRC
tAA
tACS
tCLZ
tCHZ
tOH
Min
25
Max
Min
35
Max
Min
45
Max
Min
55
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
tAVAV
tAVQV
tELQV
tELQX
tEHQZ
tAVQX
tGLQV
tGLQX
tGHQZ
tELICCH
tEHICCL
25
25
35
35
45
45
55
55
3
0
0
0
3
0
0
0
3
0
0
0
3
0
0
0
12
10
10
25
20
15
15
35
20
20
20
45
20
25
20
55
tOE
tOLZ
tOHZ
tPU
ns
ns
ns
tPD
1. This parameter is guaranteed by design but not tested.
AC TEST CONDITIONS
Figure 1
Figure 2
Vcc
Vcc
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
VSS to 3.0V
5ns
1.5V
Figure 1
480Ω
480Ω
5pF
Q
Q
NOTE: For tEHQZ, tGHQZ and tWLQZ, CL = 5pF Figure 2
30pF
255Ω
255Ω
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2000
Rev. 10
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88128CS
White Electronic Designs
AC CHARACTERISTICS – WRITE CYCLE (15 to 20ns)
VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C
Symbol
15ns*
17ns
20ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Units
Write Cycle Time
Chip Enable to End of Write
tAVAV
tWC
15
17
20
ns
tELWH
tCW
12
13
15
ns
tELEH
tAVWL
tAVEL
tAVWH
tAVEH
tWLWH
tWLEH
tWHAX
tEHAX
tWHDX
tCW
12
13
15
ns
Address Setup Time
Address Valid to End of Write
Write Pulse Width
tAS
tAS
0
0
0
0
0
0
ns
ns
tAW
12
13
15
ns
tAW
12
13
15
ns
tWP
tWP
12
12
13
13
15
15
ns
ns
Write Recovery Time
Data Hold Time
tWR
0
0
0
ns
tWR
0
0
0
ns
tDH
tDH
0
0
0
0
0
0
ns
ns
tEHDX
Write to Output in High Z (1%
Data to Write Time
tWLQZ
tWHZ
0
7
0
8
0
8
ns
tDVWH
tDW
7
8
10
ns
tDVEH
tDW
7
8
10
ns
Output Active from End of Write (1%
tWHQX
tWLZ
3
3
3
ns
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – WRITE CYCLE (25 to 55ns)
VCC = 5.0V, Vss = 0V, -55°C ≤ TA ≤ +125°C
Symbol
25ns
35ns
45ns
55ns
Max
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Min
Units
Write Cycle Time
Chip Enable to End of Write
tAVAV
tWC
25
35
45
55
ns
tE1LWH
tCW
20
25
35
45
ns
tELEH
tAVWL
tAVEL
tAVWH
tAVEH
tWLWH
tWLEH
tWHAX
tEHAX
tWHDX
tCW
20
25
35
45
ns
Address Setup Time
Address Valid to End of Write
Write Pulse Width
tAS
tAS
0
0
0
0
0
0
0
0
ns
ns
tAW
20
25
35
45
ns
tAW
20
25
35
45
ns
tWP
tWP
20
20
30
30
30
30
35
35
ns
ns
Write Recovery Time
Data Hold Time
tWR
0
0
5
5
ns
tWR
0
0
5
5
ns
tDH
tDH
0
0
0
0
0
0
0
0
ns
ns
tEHDX
Write to Output in High Z (1%
Data to Write Time
tWLQZ
tWHZ
0
10
0
13
0
15
0
20
ns
tDVWH
tDW
15
20
20
25
ns
tDVEH
tDW
15
20
20
25
ns
Output Active from End of Write (1%
tWHQX
tWLZ
3
3
3
3
ns
1. This parameter is guaranteed by design but not tested.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2000
Rev. 10
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88128CS
White Electronic Designs
FIGURE 2 – TIMING WAVEFORM - READ CYCLE
tAVAV
ADDRESS
CS#
tAVQV
tAVAV
ADDRESS
DATA I/O
ADDRESS 1
ADDRESS 2
tELQV
tELQX
tELICCH
tEHQZ
tEHICCL
tAVQV
tAVQX
Icc
DATA 1
DATA 2
OE#
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
tGLQV
tGLQX
tGHQZ
DATA I/O
READ CYCLE 2 (WE# HIGH)
FIGURE 3 – WRITE CYCLE - WE# CONTROLLED
tAVAV
ADDRESS
tAVWH
tWHAX
tELWH
CS#
tAVWL
tWLWH
WE#
tDVWH
tWHDX
DATA IN
DATA VALID
tWLQZ
tWHQX
HIGH Z
DATA OUT
WRITE CYCLE 1, WE# CONTROLLED
FIGURE 4 – WRITE CYCLE - CS# CONTROLLED
tAVAV
ADDRESS
tAVEH
tEHAX
tELEH
CS#
tAVEL
tWLEH
WE#
tDVEH
tEHDX
DATA IN
DATA VALID
HIGH Z
WRITE CYCLE 2, CS# CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
DATA OUT
February 2000
Rev. 10
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88128CS
White Electronic Designs
DATA RETENTION CHARACTERISTICS (EDI88128LPA only)
-55°C ≤ TA ≤ +125°C
Characteristic
Low Power Version only
Sym
Conditions
Min
Typ
Max
Units
Data Retention Voltage
Data Retention Quiescent Current
VCC
ICCDR
VCC = 2.0V
CS# ≥ VCC -0.2V
2
–
–
0.5
–
2
V
mA
Chip Disable to Data Retention Time (1%
Operation Recovery Time (1%
TCDR
TR
VIN ≥ VCC -0.2V
or VIN ≤ 0.2V
0
TAVAV
–
–
–
–
ns
ns
*
NOTE:
1. Parameter guaranteed by design, but not tested.
* Read Cycle Time
FIGURE 5 – DATA RETENTION - CS# CONTROLLED
Data Retention Mode
4.5V
4.5V
Vcc
VCC
tCDR
tR
CS#
CS# = VCC -0.2V
DATA RETENTION, CS# CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2000
Rev. 10
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88128CS
White Electronic Designs
PACKAGE 9: 32 PIN SIDEBRAZED CERAMIC DIP (600mils wide)
1.616
1.584
0.620
0.600
0.060
0.040
Pin 1 Indicator
0.200
0.125
0.155
0.115
0.600
NOM
0.020
0.016
0.100
TYP
0.061
0.017
15 x 0.100 = 1.500
ALL DIMENSIONS ARE IN INCHES
PACKAGE 100: 32 LEAD CERAMIC ZIP
1.65 MAX
0.125
MAX
0.500
MAX
0.040
0.020
0.155
0.125
0.100
NOM
0.050
0.040
MIN
31 x 0.050 = 1.550
ALL DIMENSIONS ARE IN INCHES
PACKAGE 102: 32 PIN SIDEBRAZED CERAMIC DIP (400mils wide)
1.616
1.584
0.420
0.400
0.060
0.040
Pin 1 Indicator
0.175
0.125
0.155
0.115
0.020
0.016
0.100
TYP
0.400
NOM
0.061
0.017
15 x 0.100 = 1.500
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2000
Rev. 10
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88128CS
White Electronic Designs
PACKAGE 140: 32 LEAD CERAMIC SOJ
0.010
0.006
0.019
0.015
0.840
0.820
0.050
TYP
0.444
0.430
0.379
0.155
0.106
ALL DIMENSIONS ARE IN INCHES
PACKAGE 141: 32 PAD CERAMIC LCC
0.096
0.080
0.028
0.022
0.840
0.820
0.050
TYP
0.405
0.395
ALL DIMENSIONS ARE IN INCHES
PACKAGE 142: 32 PIN CERAMIC FLATPACK
0.830
0.810
0.007
0.370
0.003
0.250
1.00 REF
0.290
0.270
0.420
0.400
0.040
0.030
Pin 1
0.019
0.015
0.045
0.020
0.116
0.100
0.050
TYP
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2000
Rev. 10
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
EDI88128CS
White Electronic Designs
ORDERING INFORMATION
EDI 8 8 128 CS X X X
WHITE ELECTRONIC DESIGNS
SRAM
ORGANIZATION, 128Kx8
TECHNOLOGY:
CS = CMOS Standard Power
LPS = Low Power
ACCESS TIME (ns)
PACKAGE TYPE:
C = 32 lead Sidebrazed DIP, 600 mil (Package 9)
F = 32 lead Ceramic Flatpack (Package 142)
L = 32 pad Ceramic LCC (Package 141)
N = 32 lead Ceramic SOJ (Package 140)
T = 32 lead Sidebrazed DIP, 400 mil (Package 102)
Z = 32 lead Ceramic ZIP (Package 100)
DEVICE GRADE:
B = MIL-STD-883 Compliant
M= Military Screened
I = Industrial
C = Commercial
-55°C to +125°C
-40°C to +85°C
0°C to +70°C
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
February 2000
Rev. 10
9
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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