SVPL1209SG [VPT]
SPACE QUALIFIED POINT OF LOAD CONVERTERS;
| 型号： | SVPL1209SG |
| 厂家： | 
VPT, Inc. |
| 描述： | SPACE QUALIFIED POINT OF LOAD CONVERTERS |
| 文件： | 总17页 (文件大小：1438K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
.
SVPL1209SG SERIES
SPACE QUALIFIED POINT OF LOAD CONVERTERS
Models Available
Input: 3.1 V to 13.2 V
9 A output
Qualified to MIL-PRF-38534 Class H and Class K
SVPL Series DC-DC Converter
1.0 DESCRIPTION
1.2 SPACE LEVEL CHARACTERIZATIONS
The SVPL Series of space qualified point-of-load DC-DC
converters is specifically designed for the harsh radiation
environment of space applications. Performance is guaranteed
through the use of hardened semiconductor components and
analysis. The SVPL Series has been characterized for Total
Ionizing Dose (TID) performance including Enhanced Low Dose
Rate Sensitivity (ELDRS) and for Single Event Effects (SEE) per
VPT’s DLA-approved Radiation Hardness Assurance (RHA) plan
per MIL-PRF-38534, Appendix G, Level R.
• Total Ionizing Dose Performance
• High Dose Rate [50-300 rad(Si)/s] ≥ 100 krad(Si)
• Low Dose Rate [<10 mrad(Si)/s] ≥ 100 krad(Si)
• Single Event Effects Performance
• SEL, SEB, and SEGR LETTH ≥ 85 MeV-cm2/mg
• SEFI Threshold LETTH ≥ 42 MeV-cm2/mg
• SEFI X-section (LETEFF = 85 MeV-cm2/mg) ≤ 1.18x10-7 cm2
• SET fully characterized for cross section and magnitude
• Operation from -55 °C to +125 °C
• Worst-case analysis, stress, radiation, reliability reports available
The SVPL1209SG is based on the Intersil ISL70003ASEH
radiation-hardened monolithic buck regulator. It is designed to
operate from nominal bus voltages from 3.3 V to 12 V. The
SVPL1209SG supplies low voltages at 9 A with high efficiency
and fast transient response, making it an ideal choice to supply
point-of-load applications such as high performance space
processors.
1.3 MANUFACTURING AND COMPLIANCE
• Qualified to MIL-PRF-38534 Class H and Class K,
DLA SMD # 5962-17232
• MIL-PRF-38534 element evaluated components
• Manufactured in a MIL-PRF-38534 Class H and Class K facility
• MIL-STD-883
• ISO-9001
1.1 FEATURES
1.4 PACKAGING
• Operates from 3.1 – 13.2 V input
• Adjustable Output from 0.8 – 5 V
• Up to 9 Amps Output
• High Efficiency, up to 93%
• High Power Density, up to 132 W/in3
• Output Enable Control
• Low Output Noise
• Over Current Protection
• Synchronizable to an external clock
• Low-profile: 1.110” x 1.110” x 0.276”
• Max weight: 22 g
• Precision seam-welded hermetic metal case
• Standard gullwing or optional straight-lead versions available
1.5 SIMILAR PRODUCTS AND ACCESSORIES
• SVPL3R306SG 6 A space qualified point of load DC-DC converter
• SVPL3R312SG 12 A space qualified point of load DC-DC converter
• SVGA0510SG 10 A space qualified point of load DC-DC converter
• SVGA0515SG 15 A space qualified point of load DC-DC converter
• Custom versions available
• Space qualified isolated DC-DC converters, 6 - 100 W
Products and reports described in this datasheet are subject to all export license restrictions and regulations which may include but are not limited to ITAR
(International Traffic in Arms Regulations) and the Export Administration and Foreign Assets Control Regulations. Further restrictions may apply. Contact VPT
sales for details. VPT, its logo and tagline are registered trademarks in the U.S. Patent and Trademark Office. All other names, product names and trade names
may be trademarks or registered trademarks of their respective holders.
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SVPL1209SG Series
2.0 DIAGRAMS
2.1 BLOCK DIAGRAM
2.2 CONNECTION DIAGRAMS
1.
2.
Rtrim should be connected directly across pins 11 and 12 as close as possible to the SVPL.
AGND should be connected to GND close to the SVPL. Voltage difference between the AGND and the GND pins greater than 0.3 V may result in regulation error
and/or damage to the SVPL.
3.
4.
5.
6.
If not using EN and VIN ≤ 5.15 V, pin 7 can be connected directly to VIN. For VIN > 5.15 V, pin 7 can be pulled up toward VIN through a 49.9 kΩ - 100 kΩ resistor.
If not synchronizing converters, connect pin 9 to GND.
If not using PGOOD, leave pin 10 open.
Rcomp and Ccomp are optional components that can be used to optimize the SVPL transient response.
3.0 SPECIFICATIONS
3.1 ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings
1
-0.3 V to 16 V
Operating Temperature (Full Load):
-55 °C to +125 °C
VIN, PGOOD :
2
-0.3 V to 5.15 V or to VIN + 0.3 V
Storage Temperature:
-65 °C to +150 °C
270 °C
EN, UVLO, SYNC :
AGND:
-0.3 V to 0.3 V
1 B
Lead Solder Temperature (10 seconds):
Solder Reflow Temperature (30 seconds):
ESD Rating per MIL-PRF-38534:
220 °C
1. VIN and PGOOD limited to 13.7 V for operation in a heavy ion environment at LET ≥ 85 MeV-cm2/mg and Tcase = 125 °C. Derate VIN ≤ 12.5 V to comply with
MIL-HDBK-1547.
2. EN, UVLO, and SYNC must be limited to 5.15 V or to VIN + 0.3 V, whichever is lower. EN can be pulled up toward voltages higher than 5.15 V through a 49.9 kΩ - 100 kΩ
resistor.
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SVPL1209SG Series
1
3.2 PERFORMANCE SPECIFICATIONS
Tcase = -55 °C to +125 °C, Vin = 3.3 V ± 1% or 5 V ± 1% or 12 V ± 1%, Full Load, Unless Otherwise Specified
SVPL1209SG
Parameter
Conditions
Min
Typ
Max
Units
INPUT
2
3.1
-
13.2
7
7
7
60
V
Voltage
Current
EN = GND, Vin = 3.3 V
EN = GND, Vin = 5 V
EN = GND, Vin = 12 V
Vin = 3.3 V, No Load
Vin = 5 V, No Load
Vin = 12 V, No Load
UVLO Reference Voltage
UVLO Sink Current
-
-
-
-
-
1.3
2
4
40
50
90
0.6
12
mA
mA
mA
mA
mA
mA
V
75
-
125
0.65
15.1
2
0.55
8.9
Undervoltage Lockout
µA
OUTPUT STATIC
Voltage
Tcase = 25 °C
Tcase = -55 °C to +125 °C
-1.0
-1.5
0
-
-
-
-
-
+1.0
+1.5
45
%Vout
%Vout
W
3
Power
4
Tcase = -55 °C to +95 °C
Tcase = +125 °C
0
0
9
6
Current
A
Vin = 3.3 V, Vout = 1.8 V,
20 Hz to 10 MHz
Vin = 5 V, Vout = 3.3 V,
20 Hz to 10 MHz
Vin = 12 V, Vout = 5 V,
20 Hz to 10 MHz
Ripple Voltage
-
-
-
30
35
85
60
60
mVpp
mVpp
mVpp
120
Load Regulation
Load Fault Dissipation
OUTPUT DYNAMIC
Load Step, Half to Full Load, Vin = 5 V,
-0.6
-
0.03
-
+0.6
6
%Vout
W
Vin = 12 V, Vout = 5 V
Output Transient
-
-
75
140
300
mV
µs
5
Vout = 3.3 V
150
Recovery
Turn-On
Delay
-
-
6
0
10
15
ms
(Vin = 0 to 3.3 V or 5 V or 12 V, EN = Vin)
Overshoot
mVpk
FUNCTION
2
EN Input High Voltage
EN Input Low Voltage
2.1
-
-
-
-
-
V
Enable (EN)
0.7
580
V
2
420
kHz
SYNC Frequency Range
GENERAL
Efficiency
Vin = 5 V, Vout = 3.3 V
81
-
87
-
-
%
2
Vout ≤ 1.2 V
5000
Capacitive Load
µF
6000
Vout
575
22
Vout ≥ 1.2 V
-
-
Switching Frequency
Weight
MTBF (MIL-HDBK-217F)
425
-
-
500
-
5.77
kHz
g
MHr
Standard package option
SF @ Tcase = 55 °C
-
6
POST-RAD END-OF-LIFE LIMITS
OUTPUT Voltage
Switching Frequency
Tcase = -55 °C to +125 °C
-3.0
420
-
-
+3.0
580
%Vout
kHz
1. Performance specifications are guaranteed with 100 µF from VIN to GND.
2. Verified by qualification testing.
3. Dependent on output voltage.
4. Output current is rated to 9 A for Tcase ≤ 95 °C. From 95 °C to 125 °C, derate linearly from 9 A to 6 A.
5. Time for output voltage to settle within 1% of steady-state value.
6. End-of-Life performance includes aging and radiation degradation and is within standard limits except where noted.
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SVPL1209SG Series
4.0 PERFORMANCE CURVES
4.1.1 SVPL1209SG Efficiency (Typical, 25 °C, Vin = 3.3 V)
4.1.2 SVPL1209SG Efficiency (Typical, 25 °C, Vin = 5 V)
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SVPL1209SG Series
4.0 PERFORMANCE CURVES (CONTINUED)
4.1.1 SVPL1209SG Efficiency (Typical, 25 °C, Vin = 12 V)
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SVPL1209SG Series
5.0 MECHANICAL OUTLINES AND PINOUT
Standard Gullwing Package Option:
1. Tolerances are +0.005” unless otherwise stated
2. Case temperature is measured on the center of the baseplate surface
3. Materials: Case (Steel, gold over nickel plated); Cover (Steel, nickel plated); Pin (Copper-cored alloy 52, gold over nickel plated, 63/37 SnPb solder dipped);
Pin Seals (Glass)
Pin Function
Pin Function
Pin Function
Pin Function
1
2
3
4
5
VIN
6
GND
11
12
13
14
15
AGND
16
17
18
19
20
GND
VIN
7
EN
TRIM
VOUT
VOUT
VOUT
VOUT
VIN
8
UVLO
SYNC
PGOOD
+SENSE
GND
GND
GND
9
10
GND
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SVPL1209SG Series
5.0 MECHANICAL OUTLINES AND PINOUT (CONTINUED)
Optional Straight-Lead Package:
1. Tolerances are +0.005” unless otherwise stated
2. Case temperature is measured on the center of the baseplate surface
3. Materials: Case (Steel, gold over nickel plated); Cover (Steel, nickel plated); Pin (Copper-cored alloy 52, gold over nickel plated); Pin Seals (Glass)
4. Pins may have exposed nickel plating (not base metal) beyond the ceramic tie bars due to the plating process. No nickel plating is exposed between the tie bar and case.
Pin Function
Pin Function
Pin Function
Pin Function
1
2
3
4
5
VIN
6
GND
11
12
13
14
15
AGND
16
17
18
19
20
GND
VIN
7
EN
TRIM
VOUT
VOUT
VOUT
VOUT
VIN
8
UVLO
SYNC
PGOOD
+SENSE
GND
GND
GND
9
10
GND
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SVPL1209SG Series
6.0 TECHNICAL NOTES
Please note that many of these functions are also demonstrated in detail on the VPT website in the
form of technical video labs.
6.1 GENERAL INFORMATION
6.1.1 Topology Description
The SVPL1209SG is a non-isolated, fixed-frequency, radiation-hardened, synchronous buck
converter based on the Intersil ISL70003ASEH. It is optimized for low voltage point-of-load (POL) applications. The SVPL1209SG
operates from a 3.1 to 13.2 V input and provides a stepped-down, precisely regulated, programmable output voltage at high efficiency.
6.1.2 Source Impedance
The impedance of the input source can interact with the POL converter and impact performance. High source impedance is often
caused by a long input cable or other components added in series with the input. In some cases, additional input capacitance will be
needed to stabilize the system.
6.1.3 Case Connection
The SVPL1209SG case is connected to GND at a single point inside of the package.
6.2 FUNCTION DESCRIPTIONS
6.2.1 Enable (EN)
The EN pin accepts TTL/CMOS logic input as described in the Performance Specifications table. When EN is pulled low, the converter
is disabled and the supply current drops to typical values between 1.3 – 4 mA, depending on the input voltage. The internal power
MOSFETs will be turned off, and the SVPL1209SG power stage will be in a high-impedance state. When the EN pin voltage exceeds
its logic rising threshold, the SVPL1209SG monitors the UVLO pin voltage before initiating soft-start. The EN pin should not be driven
higher than 5.15 V. If the EN signaling voltage is higher than 5.15 V, use a 49.9 kΩ – 100 kΩ resistor in series with the EN pin. If
ON/OFF capability is not required and Vin ≤ 5.15 V, EN can be connected directly to Vin. If Vin > 5.15 V, EN can be pulled up toward
Vin through a 49.9 kΩ – 100 kΩ current limiting resistor.
6.2.3 Power Good (PGOOD)
PGOOD is an open-drain output. It is pulled to GND when the output voltage is outside a ±11% regulation window. When the output
voltage is within ±11% of its set point, PGOOD will be released and can be pulled up through a resistor to any voltage from 0 V to 13.2
V. The external pull-up resistor should have a nominal value in the range of 1 kΩ to 10 kΩ. PGOOD should be bypassed to GND with a
10nF ceramic capacitor to mitigate SEE.
6.2.2 Synchronization (SYNC)
The SVPL1209SG can be synchronized to an external clock with a frequency range of 500 kHz ±15%. During start-up, the converter
will use its internal oscillator. Once soft-start is complete and PGOOD is released, the converter will synchronize to the external clock
signal. This allows the SVPL1209SG to be the power source to the external clock components without the requirement that a clock
signal be present at the SYNC pin before start-up. The clock signal’s low level must be less than 0.7 V and its high level must be
between 2.1 V and 5.15 V to guarantee proper synchronization. The clock signal’s duty cycle should be between 40 to 60%. If not
synchronizing converters, connect SYNC to GND.
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SVPL1209SG Series
6.2.4 Adjusting the Output Voltage (TRIM)
The output voltage of the converter is set with an external trim resistor connected from the TRIM pin to the AGND pin. Use the
equations or table below to choose the trim resistor value. Trim resistor tolerance of 0.1% is recommended to achieve an accurate
output voltage. The default output voltage with the TRIM pin left open is 0.8 V.
SVPL1209SG
+Vout (V)
0.8
Rtrim (Ω)
Open
58.6k
28.6k
13.6k
7.17k
4.60k
3.60k
2.13k
1.60k
1.33k
1.00k
475
0.9
1.0
6000
푅푇ꢂꢁ푀
=
− 1400
+ 0.8
1.2
푉푂푈푇 − 0.8
1.5
1.8
2.0
6000
2.5
푉푂푈푇
=
2.8
푅푇ꢂꢁ푀 + 1400
3.0
3.3
4.0
5.0
28.6
6.2.5 Output Capacitors
Output capacitors for point-of-load (POL) DC/DC converters should be chosen to meet output voltage ripple and transient requirements.
Meeting the transient response requirement is accomplished by making the output impedance of the converter sufficiently small. Given
the high control bandwidth of POL converters like the SVPL series, the peak output impedance is typically dominated by the equivalent
series resistance (ESR) of the bulk output capacitance. Therefore, the output capacitors should be chosen to set a certain maximum
total ESR. The total ESR is the parallel combination of the internal bulk capacitor’s ESR and that of the added capacitors. Given the
output voltage transient requirement, maximum load step, and the ESR of each bulk capacitor that will be added, the number of added
capacitors needed is calculated with the following equations:
Parameter Definition
Max VOUT transient allowed
Max load current step
ΔVOUT
ΔIOUT
∆푉푂푈푇
∆퐼푂푈푇
퐸푆푅푇푂푇퐴퐿
=
=
Total combined parallel ESR, including internal
and added capacitors
ESRTOTAL
ESRADDED
퐸푆푅푇푂푇퐴퐿 ∗ 퐸푆푅ꢁ푁푇ꢀꢂ푁퐴퐿
퐸푆푅ꢁ푁푇ꢀꢂ푁퐴퐿 − 퐸푆푅푇푂푇퐴퐿
퐸푆푅퐴퐷퐷ꢀ퐷
Combined parallel ESR of the added capacitors
ESR of the internal bulk capacitor
퐸푆푅ꢀ퐴퐶퐻
ESRINTERNAL
(43.7mΩ max under worst-case conditions)
ꢃ =
퐸푆푅퐴퐷퐷ꢀ퐷
ESR of each of the added capacitors
Number of added capacitors
ESREACH
N
Make sure that the added capacitance does not violate the maximum allowed output capacitance using the following equation:
6000µ퐹
ꢄ푂푈푇ꢅ푀퐴푋
=
푉푂푈푇
For example, assume that VOUT is 1.5 V, the maximum output transient allowed is 37.5mV, and the load step is 4.5 A. Assume the
output capacitors being used are 330 µF and have a maximum ESR of 50 mΩ each.
∆푉푂푈푇
∆퐼푂푈푇
37.5푚푉
4.5ꢆ
퐸푆푅푇푂푇퐴퐿
=
=
= 8.33푚훺
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SVPL1209SG Series
퐸푆푅푇푂푇퐴퐿 ∗ 퐸푆푅ꢁ푁푇ꢀꢂ푁퐴퐿
퐸푆푅ꢁ푁푇ꢀꢂ푁퐴퐿 − 퐸푆푅푇푂푇퐴퐿
8.33푚훺 ∗ 43.7푚훺
43.7푚훺 − 8.33푚훺
퐸푆푅퐴퐷퐷ꢀ퐷
=
=
= 10.30푚훺
퐸푆푅ꢀ퐴퐶퐻
50푚훺
ꢃ =
=
= 4.85 → 푢푠푒 5 표푢푡푝푢푡 푐푎푝푎푐푖푡표푟푠
퐸푆푅퐴퐷퐷ꢀ퐷 10.30푚훺
6000µ퐹 6000µ퐹
ꢄ푂푈푇ꢅ푀퐴푋
=
=
= 4000µ퐹
푉푂푈푇
1.5
In the example, 5x 330 µF/50 mΩ capacitors are needed. This is a total capacitance of 1650 µF, which is well below the 4000 µF
maximum allowed.
The output voltage ripple can be evaluated through simulation using the circuit below. This circuit incorporates worst-case conditions
that include the effects of component tolerances, temperature extremes (-55 °C to 125 °C), radiation (100 krad), and aging (10 year
mission). Note that the resistor shown in series with the inductor includes the resistance of the inductor and ISL70003A power FETs.
The pulsed voltage source should have a peak voltage equal to the input voltage and the minimum switching frequency (420 kHz) to
evaluate the worst-case ripple. The duty cycle should be adjusted to attain the correct output voltage.
6.2.6 Input Capacitors
A minimum input capacitance of 100 µF should be added between VIN and GND to maintain the input voltage during transient
conditions. The SVPL1209SG has been designed with internal ceramic input capacitors to minimize the voltage stresses on its power
MOSFETs. These ceramic capacitors also reduce the current stress in the user-added input capacitors. For 100 µF or greater
capacitors, the RMS currents of the added capacitors will be determined primarily by their combined ESR. The curves below estimate
the total RMS current in the added input capacitors for different VOUT/VIN ratios. Worst-case conditions for load current, internal
capacitance, and switching frequency are used. To verify the capacitors will have sufficient margin, the RMS current ratings of the
added capacitors can be compared to the appropriate curve. If the application VOUT/VIN ratio is between two curves, use the curve with
higher RMS current to be conservative. If multiple capacitors are added, then the RMS current will divide between them. If the
maximum application load current is less than the SVPL1209SG maximum of 9 A, then the RMS current will be reduced proportionally.
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SVPL1209SG Series
For example, let us assume Vin = 5 V, Vout = 1.8 V, max Iout = 5 A, and maximum temperature = 85 °C. Also, assume the capacitor
being considered is a 150 µF capacitor with an ESR of 30 mΩ at 85 °C and the worst-case minimum switching frequency of 420 kHz.
Assume the capacitor’s RMS current rating is 2.7 A at 85 °C. First, determine the Vout/Vin ratio:
푉
1.8푉
5푉
ꢇꢈꢉ
=
= 0.36
푉
ꢊ푛
The ratio lies between the 0.3 and 0.4 curves. Use the Vout/Vin = 0.4 curve, as it has higher RMS current and gives a more
conservative estimate. At 30 mΩ, the 0.4 curve indicates an RMS current of 2.65 A. The RMS current for this application is found as:
ꢆ푝푝푙푖푐푎푡푖표ꢍ max 퐼ꢇꢈꢉ
푆푉푃ꢎ max 퐼ꢇꢈꢉ
5ꢆ
) = 2.65 ( ) = 1.47ꢆ
9ꢆ
퐼ꢂ푀ꢋ_퐶ꢁ푁 = 퐼ꢂ푀ꢋ_퐶푈ꢂꢌꢀ
(
The RMS current in the added input capacitors is 1.47 A, which is 54% of the 2.7 A current rating. The power dissipated in the capacitor
will be about 30% of its power rating (0.542 = 0.30).
6.3 PROTECTION FEATURES
6.3.1 Input Undervoltage Lockout
The SVPL1209SG Series provides input undervoltage lockout (UVLO) protection. For input voltages below the turn-on voltage, the
converter will remain off. The internal power MOSFETs will be turned off, and the SVPL1209SG power stage will be in a
high-impedance state. When the input voltage exceeds the turn-on voltage, the converter will soft-start. For input voltages above the
UVLO turn-off voltage but below the operating range of the converter, the converter may reach its maximum duty cycle and the output
may be out of regulation. The figure below demonstrates the UVLO circuit. Note that it is referenced to AGND.
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SVPL1209SG Series
Initially, the input voltage (VIN) is below the turn-on threshold (VUVLO_ON) and the IUVLO current sink is active. IUVLO is only active when
the voltage at the UVLO pin is less than the UVLO reference voltage, VR. As VIN rises, the UVLO turn-on threshold is calculated as:
푅ꢏ
푉푈ꢌ퐿푂_푂푁 = 푉ꢂ ∙ [1 + ] + 퐼푈ꢌ퐿푂 ∙ 푅ꢏ
푅ꢐ
After VIN reaches VUVLO_ON, IUVLO turns off. With the part enabled and IUVLO off, the converter will shut down if VIN falls below the UVLO
turn-off threshold (VUVLO_OFF):
푅ꢏ
푉푈ꢌ퐿푂_푂ꢑꢑ = 푉ꢂ ∙ [1 +
]
푅ꢐ
The undervoltage lockout circuit hysteresis is:
푉푈ꢌ퐿푂_퐻푌ꢋ = 푉푈ꢌ퐿푂_푂푁 − 푉푈ꢌ퐿푂_푂ꢑꢑ = 퐼푈ꢌ퐿푂 ∙ 푅ꢏ
R1 and R2 are chosen to set the desired thresholds and hysteresis. Typical and extreme values of VR and IUVLO are provided in section
3.2. The UVLO pin should be bypassed to AGND with a 10nF capacitor to mitigate SEE.
6.3.2 Output Soft-Start
The SVPL1209SG Series utilizes an output soft-start function to ramp the output in a controlled manner, eliminating output voltage
overshoot and limiting inrush current at turn on. A voltage mode soft-start ensures the output waveform remains consistent regardless
of changes in the load current. The output rise time is approximately 4 ms. The soft-start function is active whether the module is turned
on with an application of input voltage or from driving EN high. The turn-on delay time is specified from the application of input voltage
(or application of EN) until the output reaches 90% of its final value.
6.3.3 Output Short Circuit Protection
The SVPL1209SG Series provides hiccup-mode output short-circuit protection. When a sustained high peak current is detected, the
converter will shut down. After a delay, the converter will attempt a soft-start. This sequence will continue until the fault is removed,
allowing the converter to soft-start and resume normal operation.
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SVPL1209SG Series
6.4 THERMAL CONSIDERATIONS
The SVPL1209SG output current rating versus case temperature is illustrated in the figure below. It is rated at 9 A for case
temperatures up to 95 °C. From 95 °C to 125 °C, derate linearly from 9 A to 6 A. From 125 °C to 135 °C, derate linearly to 0 A. The
case temperature of the converter is specified on the baseplate of the converter. The converter is designed to be conduction-cooled,
with the baseplate mounted to a heat sink, chassis, PCB, or other thermal surface. The internal power-dissipating components are
mounted to the baseplate of the converter and all heat flow is through the baseplate. The lid of the converter does not provide a good
thermal path.
The maximum temperature rise from junction to case is 20 °C at 9 A output and 15 °C at 6 A output.
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SVPL1209SG Series
6.5 VPT RHA PLAN AND APPROACH
VPT takes a conservative approach to radiation testing to ensure product performance during space travel. VPT’s DLA approved
Radiation Hardness Assurance (RHA) plan documents VPT’s processes and procedures for guaranteeing the performance of VPT
products under various environmental conditions in space, including TID, SEE, and ELDRS.
Documents Available
Details
The radiation environments covered by this overview include: total ionizing dose (TID), which
includes enhanced low dose rate sensitivity (ELDRS); displacement damage (DD); and single
event effects (SEE).
DLA approved Radiation Hardness Assurance (RHA) Plan Summary
Worst-Case Analysis Report
Stress Report
Detailed worst-case analysis guarantees circuit performance post radiation and end of life.
Individual component stress analysis and deratings are included as part of the WCA report.
An overview report on the component level RLAT and characterization testing for TID and DD
as well as the hybrid level characterizations for TID and SEE response.
Radiation Test Summary Report
Reliability Report
MTBF report based on MIL-HDBK-217 reliability calculations.
Component temperature rise analysis and measurement results.
Thermal Analysis Report
Test Definition
VPT’s Approach
Total Ionizing Dose (TID). A measure of the energy absorbed in the
semiconductor components from the naturally occurring sources of
radiation (protons, electrons, photons). This results in the slow
degradation of semiconductor performance specifications. TID is tested
by exposing components to gamma radiation from a Cobalt-60 source.
Designed for 100 krad(Si). Sensitive semiconductor components undergo RLAT to 100
krad(Si) per MIL-STD-883 Method 1019. Converters are characterized to 100 krad(Si).
Enhanced Low Dose Rate Sensitivity (ELDRS): Many linear-bipolar
integrated circuits show enhanced parameter degradation when exposed
at low dose rates close to those seen in a space environment as
compared to the high dose rates (50-300 rad(Si)/s) that components were
traditionally tested at for TID degradation. MIL-STD-883 Method 1019
gives guidance for characterizing components for ELDRS. Components
that exhibit ELDRS are tested for TID at a rate below 0.01 rad(Si)/s.
All bipolar linear ICs are verified to be ELDRS free in accordance with MIL-STD-883 test
method 1019 section 3.13
Single Event Effects (SEE). Single high energy protons and heavy ions
can deposit sufficient energy in a semiconductor component, causing a
range of effects. SEEs include single event latchups (SELs), single event
gate ruptures (SEGRs), single event transients (SETs), single event
functional interrupts (SEFIs) and single event burnouts (SEBs).
Converters are characterized for catastrophic events (SEL, SEB, SEGR) as well as functional
interrupts (SEFI) under heavy ion exposure to LET = 85 MeV-cm2/mg. Converters are also
characterized for cross section and magnitude of output transients (SET) for at least 3
different LET levels.
Displacement Damage (DD) is caused by protons and neutrons. Particles
displace atoms in the bulk silicon crystal structure. DD leads to a
darkening of optics and gradual degradation of performance. DD is tested
at the component level with a neutron source.
Optoisolators are not used. The sensitive semiconductor component is characterized by the
manufacturer for DD performance to 1x1012 n/cm2.
Radiation Lot Acceptance Testing (RLAT): Semiconductor wafer lots are
exposed to TID or neutron radiation on a sample basis. If the parameter
degradation for the tested samples is within the predetermined
acceptance limits, then the lot can be used in radiation hardened
converters.
Sensitive semiconductor component undergoes RLAT for TID.
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SVPL1209SG Series
7.0 ENVIRONMENTAL SCREENING
100% tested per MIL-STD-883 as referenced to MIL-PRF-38534.
Contact sales for more information concerning additional environmental screening and testing options. VPT Inc. reserves the right to
ship higher screened or SMD products to meet orders for lower screening levels at our sole discretion unless specifically forbidden by
customer contract.
/EM
/H+
/K
(Engineering Model)
Non-QML1,6
MIL-STD-883 Test
Method, Condition
Test
(Class H + PIND)
(Class K)
Non-Destructive
Bond Pull
2
2
TM2023
●
●
●
●
●
TM2010, TM2017, TM2032
(MIL-STD-750, TM2072,
TM2073)
Internal Visual
●
●
TM1010, Condition C
-65 °C to 150 °C, Ambient
Temperature
Cycling
●
●
Constant
Acceleration
TM2001, 3000g, Y1
Direction
●
●
●
3
2
TM2020, Condition A
25 °C
PIND
●
Pre Burn-In
Electrical
TM1015, 320 hrs.,
125 °C, Case Typ
●
TM1015, 160 hrs.,
125 °C, Case Typ
Burn-In
●
●
24 hrs., 125 °C, Case Typ
●
●
MIL-PRF-38534, Group A
Subgroups 1-6
●
4
-55 °C, 25 °C, 125 °C
Final Electrical
MIL-PRF-38534, Group A
Subgroups 1 and 4
25 °C
TM1014, Fine Leak,
Condition A2 or B1
●
●
●
●
Hermeticity
(Seal)
TM1014, Gross Leak,
Condition C1 or B2
Gross Leak, Dip (1x10-3)
●
●
5
TM2012
●
●
Radiography
External Visual
TM2009
●
1. Non-QML products may not meet all requirements of MIL-PRF-38534
2. Not required per MIL-PRF-38534. Test performed for additional product quality assurance
3. PIND test Certificate of Compliance included in product shipment
4. 100% R&R testing with all test data included in product shipment
5. Radiographic test Certificate of Compliance and film(s) or data CD included in product shipment
6. Engineering models utilize only the screening specified and are not considered compliant for flight use
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SVPL1209SG Series
8.0 STANDARD MICROCIRCUIT DRAWING (SMD) NUMBERS
Standard Microcircuit SVPL1209SG Series
Drawing Number Similar Part Number
5962R1723201HYC
5962R1723201HXA
5962R1723201KYC
5962R1723201KXA
SVPL1209SGN/H+
SVPL1209SG/H+-E
SVPL1209SGN/K
SVPL1209SG/K-E
Do not use the SVPL1209SG Series similar part number for SMD product acquisition. It is listed for reference only. For exact
specifications of the SMD product, refer to the SMD drawing. SMDs can be downloaded from the DLA Land and Maritime (Previously
known as DSCC) website at https://landandmaritimeapps.dla.mil/programs/defaultapps.asp. The SMD numbers listed above represents
the Federal Stock Class, Device Type, Device Class Designator, Case Outline, Lead Finish and RHA Designator (where applicable).
Please reference the SMD for other screening levels, lead finishes, and radiation levels. All SMD products are marked with a “Q” on the
cover as specified by the QML certification mark requirement of MIL-PRF-38534.
9.0 ORDERING INFORMATION
SVPL
12
09
S
G
/K
-
E
1
2
3
4
5
6
7
8
(1)
Product
Series
(2)
Nominal
Input
(3)
Output
Current
(4)
Number
of
(5)
Package
Option
(6)
(7)
(8)
Package Lead Screening Code1,2,3
Option4
Additional
Screening Code4
Voltage
Outputs
SVPL
12 12 Volts
09 9 Amps
S
Single
G
Gullwing
None
N
Formed
Straight
/EM Engineering Model
/H+ Class H + PIND
/K Class K
E
Solder Dipped
Contact Sales for
additional options
1
2
Contact the VPT Sales Department for availability of Class H (/H) or Class K (/K) qualified products
VPT Inc. reserves the right to ship higher screened or SMD products to meet lower screened orders at our sole discretion unless specifically forbidden by customer
contract
3
Engineering models utilize only the standard screening specified and are not considered compliant for flight use. These models are intended for low volume engineering
characterization only and have no guarantee regarding operation in a radiation environment. The customer must place the following statement on each line item of their
purchase order(s) for /EM units when ordering engineering models:
“(Customer Name) acknowledges that the /EM unit listed in this line item is not permitted for flight use and will be used for Engineering characterization only.”
4
When selecting Package Lead Option “Formed”, Additional Screening Code “-E” (solder dipped leads) must also be applied. When selecting Package Lead Option
“Straight”, Additional Screening Code “-E” should not be applied.
Please contact your sales representative or the VPT Inc. Sales Department for more information concerning additional environmental
screening and testing, different input voltage, output voltage, power requirements, source inspection, and/or special element evaluation
for space or other higher quality applications.
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SVPL1209SG Series
10.0 CONTACT INFORMATION
To request a quotation or place orders please contact your sales representative or the VPT, Inc. Sales Department at:
Phone:
Fax:
(425) 353-3010
(425) 353-4030
E-mail:
vptsales@vptpower.com
All information contained in this datasheet is believed to be accurate, however, no responsibility is assumed for possible errors or
omissions. The products or specifications contained herein are subject to change without notice.
11.0 ADDITIONAL INFORMATION
Visit the VPT website for additional technical resources, including:
Product Catalogs
Application Notes and White Papers
Technical Video Labs
Additional Products For Avionics/Military,
Hi-Rel COTS, and Space Applications
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