VS-P105KW [VISHAY]
Silicon Controlled Rectifier,;
| 型号： | VS-P105KW |
| 厂家： | 
VISHAY |
| 描述： | Silicon Controlled Rectifier, |
| 文件： | 总8页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VS-P100 Series
Vishay Semiconductors
www.vishay.com
Power Modules,
Passivated Assembled Circuit Elements, 25 A
FEATURES
• Glass passivated junctions for greater reliability
• Electrically isolated base plate
• Available up to 1200 VRRM/VDRM
• High dynamic characteristics
• Wide choice of circuit configurations
• Simplified mechanical design and assembly
• UL E78996 approved
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
PACE-PAK (D-19)
DESCRIPTION
PRODUCT SUMMARY
The VS-P100 series of integrated power circuits consists of
power thyristors and power diodes configured in a single
package. With its isolating base plate, mechanical designs
are greatly simplified giving advantages of cost reduction
and reduced size.
IO
25 A
Type
Modules - Thyristor, Standard
PACE-PAK (D-19)
Package
Single phase, hybrid bridge common cathode,
Single phase, hybrid bridge doubler connection,
Single phase, all SCR bridge
Circuit
Applications include power supplies, control circuits and
battery chargers.
MAJOR RATINGS AND CHARACTERISTICS
SYMBOL
CHARACTERISTICS
VALUES
25
UNITS
IO
85 °C
A
50 Hz
60 Hz
50 Hz
60 Hz
357
ITSM
A
375
637
I2t
A2s
580
I2t
6365
A2s
V
VDRM, VRRM
400 to 1200
2500
VISOL
TJ
V
Range
-40 to 125
-40 to 125
°C
°C
TStg
ELECTRICAL SPECIFICATIONS
VOLTAGE RATINGS
VRRM/VDRM, MAXIMUM
V
RSM, MAXIMUM
I
RRM MAXIMUM
REPETITIVE PEAK REVERSE AND
NON-REPETITIVE PEAK
TYPE NUMBER
AT TJ MAXIMUM
mA
PEAK OFF-STATE VOLTAGE
V
REVERSE VOLTAGE
V
VS-P101, VS-P121, VS-P131
VS-P102, VS-P122, VS-P132
VS-P103, VS-P123, VS-P133
VS-P103, VS-P124, VS-P134
VS-P105, VS-P125, VS-P135
400
600
500
700
800
900
10
1000
1200
1100
1300
Revision: 27-Mar-14
Document Number: 93754
1
For technical questions within your region: DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VS-P100 Series
Vishay Semiconductors
www.vishay.com
ON-STATE CONDUCTION
PARAMETER
SYMBOL
TEST CONDITIONS
VALUES
25
UNITS
A
Maximum DC output current at case
temperature
IO
Full bridge
85
°C
t = 10 ms
t = 8.3 ms
t = 10 ms
t = 8.3 ms
t = 10 ms
t = 8.3 ms
t = 10 ms
t = 8.3 ms
357
375
300
315
637
580
450
410
No voltage
reapplied
Maximum peak, one-cycle non-repetitive
on-state or forward current
ITSM
IFSM
,
A
100 % VRRM
reapplied
Sinusoidal half wave,
initial TJ = TJ maximum
No voltage
reapplied
Maximum I2t for fusing
I2t
A2s
100 % VRRM
reapplied
t = 0.1 ms to 10 ms, no voltage reapplied
I2t for time tx = I2t · tx
Maximum I2t for fusing
I2t
VT(TO)
rt1
6365
0.82
12
A2s
V
Maximum value of threshold voltage
TJ = 125 °C
Maximum level value of on-state slope
resistance
2
TJ = 125 °C, average power = VT(TO) x IT(AV) + rt + (IT(RMS)
)
m
Maximum on-state voltage drop
Maximum forward voltage drop
VTM
VFM
ITM = x IT(AV)
TJ = 25 °C
TJ = 25 °C
1.35
1.35
V
V
IFM = x IF(AV)
Maximum non-repetitive rate of rise of
turned-on current
TJ = 125 °C from 0.67 VDRM
dI/dt
200
A/μs
mA
I
TM = x IT(AV), Ig = 500 mA, tr < 0.5 μs, tp > 6 μs
Maximum holding current
Maximum latching current
IH
IL
TJ = 25 °C anode supply = 6 V, resistive load, gate open
TJ = 25 °C anode supply = 6 V, resistive load
130
250
BLOCKING
PARAMETER
SYMBOL
TEST CONDITIONS
VALUES
UNITS
Maximum critical rate of rise of off-state
voltage
dV/dt
TJ = 125 °C, exponential to 0.67 VDRM gate open
200
V/μs
Maximum peak reverse and off-state
leakage current at VRRM, VDRM
IRRM
IDRM
,
TJ = 125 °C, gate open circuit
TJ = 25 °C
10
mA
μA
V
Maximum peak reverse leakage current
IRRM
100
50 Hz, circuit to base, all terminals shorted,
TJ = 25 °C, t = 1 s
RMS isolation voltage
VISOL
2500
TRIGGERING
PARAMETER
SYMBOL
PGM
TEST CONDITIONS
VALUES
UNITS
Maximum peak gate power
Maximum average gate power
Maximum peak gate current
Maximum peak negative gate voltage
8
2
W
PG(AV)
IGM
2
A
V
-VGM
10
3
TJ = - 40 °C
TJ = 25 °C
Maximum gate voltage required to trigger
Maximum gate current required to trigger
VGT
2
V
TJ = 125 °C
1
Anode supply =
6 V resistive load
TJ = - 40 °C
90
60
35
0.2
2
IGT
TJ = 25 °C
mA
TJ = 125 °C
Maximum gate voltage that will not trigger
Maximum gate current that will not trigger
VGD
IGD
V
TJ = 125 °C, rated VDRM applied
mA
Revision: 27-Mar-14
Document Number: 93754
2
For technical questions within your region: DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VS-P100 Series
Vishay Semiconductors
www.vishay.com
THERMAL AND MECHANICAL SPECIFICATIONS
PARAMETER
SYMBOL
TEST CONDITIONS
VALUES
UNITS
Maximum junction operating
and storage temperature range
TJ, TStg
-40 to 125
°C
Maximum thermal resistance,
RthJC
RthCS
DC operation
Mounting surface, smooth and greased
2.24
0.10
junction to case per junction
K/W
Maximum thermal resistance,
case to heatsink
Mounting torque, base to heatsink (1)
4
Nm
g
58
2.0
Approximate weight
oz.
Case style
PACE-PAK (D-19)
Note
(1)
A mounting compound is recommended and the torque should be checked after a period of 3 hours to allow for the spread of the compound
60
50
40
30
20
10
0
60
50
40
30
20
10
0
+
-
~
180°
(sine)
TJ = 125 °C
20
25
0
25
50
75
100
125
0
5
10
15
93754_01a
Total Output Current (A)
93754_01b
Maximum Allowable
Ambient Temperature (°C)
Fig. 1 - Current Ratings Nomogram (1 Module Per Heatsink)
20
15
DC
180°
180°
120°
90°
60°
30°
15
10
5
120°
90°
60°
30°
10
5
RMS limit
RMS limit
Ø
Ø
Conduction period
Conduction angle
TJ = 125 °C
Per junction
TJ = 125 °C
Per junction
0
0
0
5
10
15
0
5
10
15
20
93754_02
Average On-State Current (A)
Fig. 2 - On-State Power Loss Characteristics
93754_03
Average On-State Current (A)
Fig. 3 - On-State Power Loss Characteristics
Revision: 27-Mar-14
Document Number: 93754
3
For technical questions within your region: DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VS-P100 Series
Vishay Semiconductors
www.vishay.com
130
120
110
100
90
350
300
250
200
150
At any rated load condition and with
rated VRRM applied following surge.
Initial TJ = 125 °C
Fully turned-on
at 60 Hz 0.0083 s
at 50 Hz 0.0100 s
180°
(Rect.)
180°
(Sine)
80
Per junction
Per module
5
70
0
10
15
20
25
30
1
10
100
Number of Equal Amplitude Half
93754_04
Total Output Current (A)
93754_06
Cycle Current Pulses (N)
Fig. 4 - Current Ratings Characteristics
Fig. 6 - Maximum Non-Repetitive Surge Current
1000
100
10
400
Maximum non-repetitive surge current
versus pulse train duration. Control of
conduction may not be maintained.
Initial TJ = 125 °C
TJ = 25 °C
350
TJ = 125 °C
No voltage reapplied
Rated VRRM reapplied
300
250
200
150
100
Per junction
Per junction
1
0
1
2
3
4
5
6
0.01
0.1
1
Instantaneous On-State Voltage (V)
93754_05
Pulse Train Duration (s)
93754_07
Fig. 5 - On-State Voltage Drop Characteristics
Fig. 7 - Maximum Non-Repetitive Surge Current
10
Steady state value
RthJC = 2.24 K/W
(DC operation)
1
0.1
Per junction
0.01
0.0001
0.001
0.01
0.1
1
10
93754_08
Square Wave Pulse Duration (s)
Fig. 8 - Thermal Impedance ZthJC Characteristics
Revision: 27-Mar-14
Document Number: 93754
4
For technical questions within your region: DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VS-P100 Series
Vishay Semiconductors
www.vishay.com
100
(1) PGM = 10 W, tp = 5 ms
(2) PGM = 20 W, tp = 25 ms
(3) PGM = 50 W, tp = 1 ms
(4) PGM = 100 W, tp = 500 μs
Rectangular gate pulse
(a) Recommended load line for
rated dI/dt: 10 V, 20 Ω, tr ≤ 1 μs
(b) Recommended load line for
rated dI/dt: 10 V, 65 Ω, tr ≤ 1 μs
(a)
10
(b)
1
(1)
(2)
(3)
(4)
VGD
Frequency limited by PG(AV)
IGD
0.1
0.001
0.01
0.1
1
10
100
93754_09
Instantaneous Gate Current (A)
Fig. 9 - Gate Characteristics
ORDERING INFORMATION TABLE
Device code
VS-
P
1
0
2
K
W
1
2
3
4
5
6
7
1
2
3
-
-
-
Vishay Semiconductors product
Module type
Current rating
1 = 25 A DC (P100 Series)
4 = 40 A DC (P400 Series)
-
-
Circuit configuration
4
5
0 = Single Phase, Hybrid Bridge Common Cathode
2 = Single Phase, Hybrid Bridge Doubler Connection
3 = Single Phase, all SCR Bridge
Voltage code
1 = 400 V
2 = 600 V
3 = 800 V
4 = 1000 V
5 = 1200 V
6
7
-
-
K = Optional Voltage Suppression
W = Optional Freewheeling Diode
Revision: 27-Mar-14
Document Number: 93754
5
For technical questions within your region: DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
VS-P100 Series
Vishay Semiconductors
www.vishay.com
CIRCUIT CONFIGURATION
CIRCUIT
CONFIGURATION
CODE
CIRCUIT DESCRIPTION
SCHEMATIC DIAGRAM
TERMINAL POSITIONS
G1
AC1
AC2
AC1 G1
AC2 G2
-
Single phase, hybrid bridge
common cathode
0
2
3
+
G2
(-)
(+)
G1
G2
AC2
AC1
AC1 G1
AC2 G2
-
Single phase, hybrid bridge
doubler connection
+
(-)
(+)
G3
G1
AC1
AC2
AC2 G2
G1 G4
AC1 G3
-
Single phase, all SCR bridge
+
G4 G2
(-)
(+)
CODING (1)
WITH BOTH
VOLTAGE SUPPRESSION
AND FREEWHEELING
DIODE
CIRCUIT
CONFIGURATION
CODE
WITH
FREEWHEELING
DIODE
BASIC
SERIES
WITH VOLTAGE
SUPPRESSION
CIRCUIT DESCRIPTION
Single phase, hybrid bridge
common cathode
P10.
P10.K
0
P10.W
P10.KW
Single phase, hybrid bridge
doubler connection
P12.
P13.
P12.K
P13.K
2
3
-
-
-
-
Single phase, all SCR bridge
Note
(1)
To complete code refer to Voltage Ratings table, i.e.: For 600 V P10.W complete code is P102W
LINKS TO RELATED DOCUMENTS
Dimensions
www.vishay.com/doc?95335
Revision: 27-Mar-14
Document Number: 93754
6
For technical questions within your region: DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Outline Dimensions
Vishay Semiconductors
D-19 PACE-PAK
DIMENSIONS in millimeters (inches)
0.9 x 45°
(0.035 x 45°)
Ø 1.65 (0.06)
12.7 (0.50) 12.7 (0.50)
4.6 (0.18)
25 (0.98) MAX.
15.5 (0.61)
MAX.
2.5 (0.10)
MAX.
63.5 (2.50)
45 (1.77)
Fast-on 6.35 x 0.8 (0.25 x 0.03)
23.2 (0.91)
32.5 (1.28) MAX.
5.2 (0.20)
33.8 (1.33)
48.7 (1.91)
Document Number: 95335
Revision: 24-Jul-08
For technical questions, contact: indmodules@vishay.com
www.vishay.com
1
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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
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Revision: 02-Oct-12
Document Number: 91000
1
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