IRFR1N60ATRRPBF [VISHAY]
Power MOSFET; 功率MOSFET型号: | IRFR1N60ATRRPBF |
厂家: | VISHAY |
描述: | Power MOSFET |
文件: | 总8页 (文件大小:156K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A
Vishay Siliconix
Power MOSFET
FEATURES
• Low Gate Charge Qg Results in Simple Drive
Requirement
PRODUCT SUMMARY
VDS (V)
DS(on) (Max.) (Ω)
Qg (Max.) (nC)
600
Available
R
VGS = 10 V
7.0
RoHS*
• Improved Gate, Avalanche and Dynamic dV/dt
Ruggedness
14
2.7
COMPLIANT
Q
Q
gs (nC)
gd (nC)
8.1
• Fully Characterized Capacitance and Avalanche Voltage
and Current
Configuration
Single
• Lead (Pb)-free Available
D
APPLICATIONS
DPAK
IPAK
(TO-252)
(TO-251)
• Switch Mode Power Supply (SMPS)
• Uninterruptible Power Supply
• Power Factor Correction
G
TYPICAL SMPS TOPOLOGIES
S
• Low Power Single Transistor Flyback
N-Channel MOSFET
ORDERING INFORMATION
Package
DPAK (TO-252)
IRFR1N60APbF
SiHFR1N60A-E3
IRFR1N60A
DPAK (TO-252)
IRFR1N60ATRLPbFa
SiHFR1N60ATL-E3a
DPAK (TO-252)
IRFR1N60ATRPbFa
SiHFR1N60AT-E3a
IRFR1N60ATRa
SiHFR1N60ATa
DPAK (TO-252)
IRFR1N60ATRRPbFa IRFU1N60APbF
SiHFR1N60ATR-E3a
IPAK (TO-251)
Lead (Pb)-free
SiHFU1N60A-E3
IRFU1N60A
-
-
-
-
SnPb
SiHFR1N60A
SiHFU1N60A
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
600
UNIT
Drain-Source Voltage
Gate-Source Voltage
VDS
V
VGS
30
TC = 25 °C
C = 100 °C
1.4
Continuous Drain Current
VGS at 10 V
ID
T
0.89
5.6
A
Pulsed Drain Currenta
IDM
Linear Derating Factor
0.28
93
W/°C
mJ
A
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
Repetitive Avalanche Energya
EAS
IAR
1.4
EAR
3.6
mJ
W
Maximum Power Dissipation
TC = 25 °C
PD
36
Peak Diode Recovery dV/dtc
dV/dt
TJ, Tstg
3.8
V/ns
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
- 55 to + 150
300d
°C
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Starting TJ = 25 °C, L = 95 mH, RG = 25 Ω, IAS = 1.4 A (see fig. 12).
c. ISD ≤ 1.4 A, dI/dt ≤ 180 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91267
S-81367-Rev. A, 21-Jul-08
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1
IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
UNIT
Maximum Junction-to-Ambient
RthJA
-
110
Maximum Junction-to-Ambient
(PCB Mount)a
RthJA
RthJC
-
-
50
°C/W
Maximum Junction-to-Case (Drain)
3.5
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
Gate-Source Threshold Voltage
Gate-Source Leakage
VDS
VGS(th)
IGSS
VGS = 0 V, ID = 250 µA
VDS = VGS, ID = 250 µA
600
-
-
-
-
-
-
-
-
V
2.0
4.0
100
25
250
7.0
-
VGS
VDS = 600 V, VGS = 0 V
DS = 480 V, VGS = 0 V, TJ = 150 °C
VGS = 10 V
ID = 0.84 Ab
VDS = 50 V, ID = 0.84 A
=
30 V
-
nA
µA
-
Zero Gate Voltage Drain Current
IDSS
V
-
-
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
RDS(on)
gfs
Ω
0.88
S
Input Capacitance
Ciss
Coss
Crss
-
-
-
-
-
-
-
-
-
-
-
-
-
229
32.6
2.4
320
11.5
130
-
-
VGS = 0 V,
DS = 25 V,
f = 1.0 MHz, see fig. 5
Output Capacitance
V
-
Reverse Transfer Capacitance
-
pF
VDS = 1.0 V, f = 1.0 MHz
-
Output Capacitance
Coss
V
GS = 0 V
V
DS = 480 V, f = 1.0 MHz
VDS = 0 V to 480 Vc
-
-
Effective Output Capacitance
Total Gate Charge
Coss eff.
Qg
14
2.7
8.1
-
ID = 1.4 A, VDS = 400 V,
see fig. 6 and 13b
Gate-Source Charge
Gate-Drain Charge
Qgs
Qgd
td(on)
tr
V
GS = 10 V
-
nC
ns
-
Turn-On Delay Time
Rise Time
9.8
14
-
V
DD = 250 V, ID = 1.4 A,
R
G = 2.15 Ω, RD = 178 Ω, see fig. 10b
Turn-Off Delay Time
Fall Time
td(off)
tf
18
-
20
-
Drain-Source Body Diode Characteristics
D
MOSFET symbol
showing the
Continuous Source-Drain Diode Current
Pulsed Diode Forward Currenta
IS
-
-
-
-
1.4
5.6
A
G
integral reverse
p - n junction diode
ISM
S
Body Diode Voltage
VSD
trr
TJ = 25 °C, IS = 1.4 A, VGS = 0 Vb
-
-
-
-
1.6
440
760
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
290
510
ns
µC
TJ = 25 °C, IF = 1.4 A, dI/dt = 100 A/µsb
Qrr
ton
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS
.
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Document Number: 91267
S-81367-Rev. A, 21-Jul-08
IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
10
10
VGS
15V
TOP
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
°
T = 150 C
J
1
1
°
T = 25 C
J
0.1
0.01
4.5V
20μs PULSE WIDTH
V
= 100V
DS
20μs PULSE WIDTH
°
T = 25 C
J
0.1
0.1
1
10
100
4.0
5.0
6.0
7.0 8.0
9.0
V
, Drain-to-Source Voltage (V)
V
, Gate-to-Source Voltage (V)
DS
GS
Fig. 3 - Typical Transfer Characteristics
Fig. 1 - Typical Output Characteristics
10
3.0
VGS
1.4A
=
I
D
TOP
15V
10V
8.0V
7.0V
2.5
2.0
1.5
1.0
0.5
0.0
6.0V
5.5V
5.0V
BOTTOM 4.5V
1
4.5V
20μs PULSE WIDTH
T = 150 C
V
=10V
°
GS
J
0.1
-60 -40 -20
0
20 40 60 80 100 120 140 160
°
1
10
100
T , Junction Temperature ( C)
V
, Drain-to-Source Voltage (V)
J
DS
Fig. 2 - Typical Output Characteristics
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 91267
S-81367-Rev. A, 21-Jul-08
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3
IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A
Vishay Siliconix
10000
10
V
C
C
C
= 0V,
f = 1MHz
GS
iss
rss
oss
= C + C
,
C
SHORTED
gs
gd
ds
= C
gd
= C + C
ds
gd
1000
100
10
°
T = 150 C
J
C
iss
1
C
oss
°
T = 25 C
J
C
rss
V
= 0 V
GS
1
0.1
A
0.4
0.6
0.8
1.0
1.2
1
10
100
1000
V
,Source-to-Drain Voltage (V)
V
, Drain-to-Source Voltage (V)
SD
DS
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
20
100
I
D
= 1.4A
OPERATION IN THIS AREA LIMITED
V
V
V
= 480V
= 300V
= 120V
BY R
DS
DS
DS
DS(on)
16
12
8
10
10us
100us
1
1ms
4
°
T = 25 C
J
C
°
T = 150 C
FOR TEST CIRCUIT
SEE FIGURE 13
10ms
1000
Single Pulse
0.1
0
10
100
10000
0
2
4
6
8
10
12
14
V
, Drain-to-Source Voltage (V)
Q , Total Gate Charge (nC)
DS
Fig. 8 - Maximum Safe Operating Area
G
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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Document Number: 91267
S-81367-Rev. A, 21-Jul-08
IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A
Vishay Siliconix
RD
VDS
1.6
1.2
0.8
0.4
0.0
VGS
D.U.T.
RG
+
V
-
DD
10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
VDS
90 %
25
50
75
100
125
°
150
10 %
VGS
T , Case Temperature ( C)
C
td(on) tr
td(off) tf
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
10
D = 0.50
1
0.20
0.10
0.05
0.02
P
2
DM
SINGLE PULSE
0.01
0.1
t
(THERMAL RESPONSE)
1
t
2
Notes:
1. Duty factor D =
t / t
1
2. Peak T =P
x Z
+ T
C
J
DM
thJC
0.01
0.00001
0.0001
0.001
0.01
0.1
1
t , Rectangular Pulse Duration (sec)
1
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
15 V
tp
Driver
L
VDS
D.U.T
IAS
RG
+
-
V
A
DD
IAS
20 V
0.01 Ω
tp
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
Document Number: 91267
S-81367-Rev. A, 21-Jul-08
www.vishay.com
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IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A
Vishay Siliconix
200
770
I
D
TOP
0.65A
0.9A
160
120
80
40
0
BOTTOM 1.4A
750
730
710
690
670
A
0.0
0.4
0.8
1.2
1.6
25
50
75
100
125
150
I
, Avalanche Current (A)
°
av
Starting T , Junction Temperature ( C)
J
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 12d - Basic Gate Charge Waveform
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
QGD
+
-
VDS
D.U.T.
VG
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Maximum Avalanche Energy vs. Drain Current
Fig. 13b - Gate Charge Test Circuit
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Document Number: 91267
S-81367-Rev. A, 21-Jul-08
IRFR1N60A, IRFU1N60A, SiHFR1N60A, SiHFU1N60A
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
Circuit layout considerations
• Low stray inductance
• Ground plane
D.U.T
• Low leakage inductance
current transformer
-
+
-
-
+
RG
• dV/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by duty factor "D"
• D.U.T. - device under test
VDD
Driver gate drive
P.W.
P.W.
Period
Period
D =
V
= 10 V*
GS
D.U.T. I waveform
SD
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. V waveform
DS
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Body diode forward drop
Ripple ≤ 5 %
Inductor current
I
SD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91267.
Document Number: 91267
S-81367-Rev. A, 21-Jul-08
www.vishay.com
7
Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
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Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000
Revision: 18-Jul-08
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1
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