IRFL210 [VISHAY]
Power MOSFET; 功率MOSFET
| 型号： | IRFL210 |
| 厂家： | 
VISHAY |
| 描述： | Power MOSFET |
| 文件： | 总8页 (文件大小：1069K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IRFL210, SiHFL210
Vishay Siliconix
Power MOSFET
FEATURES
• Surface Mount
PRODUCT SUMMARY
VDS (V)
200
Available
• Available in Tape and Reel
• Dynamic dV/dt Rating
R
DS(on) (Ω)
VGS = 10 V
1.5
RoHS*
Qg (Max.) (nC)
8.2
1.8
COMPLIANT
• Repetitive Avalanche Rated
• Fast Switching
Q
Q
gs (nC)
gd (nC)
4.5
Configuration
Single
• Ease of Paralleling
D
• Simple Drive Requirements
• Lead (Pb)-free Available
SOT-223
DESCRIPTION
G
Third generation Power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
S
The SOT-223 package is designed for surface-mounting
using vapor phase, infrared, or wave soldering techniques.
Its unique package design allows for easy automatic
pick-and-place as with other SOT or SOIC packages but has
the added advantage of improved thermal performace due to
an enlarged tab for heatsinking. Power dissipation of greater
than 1.25 W is possible in a typical surface mount
application.
N-Channel MOSFET
ORDERING INFORMATION
Package
SOT-223
SOT-223
IRFL210PbF
SiHFL210-E3
IRFL210
IRFL210TRPbFa
SiHFL210T-E3a
IRFL210TRa
SiHFL210Ta
Lead (Pb)-free
SnPb
SiHFL210
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
200
20
UNIT
Drain-Source Voltage
Gate-Source Voltage
VDS
V
VGS
TC = 25 °C
TC =100°C
0.96
0.6
Continuous Drain Current
VGS at 10 V
ID
A
Pulsed Drain Currenta
IDM
7.7
Linear Derating Factor
0.025
0.017
50
W/°C
Linear Derating Factor (PCB Mount)e
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
Repetitive Avalanche Energya
EAS
IAR
mJ
A
0.96
0.31
EAR
mJ
* Pb containing terminations are not RoHS compliant, exemptions may apply
Document Number: 91193
S-81377-Rev. A, 30-Jun-08
www.vishay.com
1
IRFL210, SiHFL210
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
LIMIT
3.1
UNIT
W
Maximum Power Dissipation
TC = 25 °C
PD
Maximum Power Dissipation (PCB Mount)e
Peak Diode Recovery dV/dtc
TA = 25 °C
2.0
dV/dt
5.0
V/ns
°C
Operating Junction and Storage Temperature Range
Soldering Recommendations (Peak Temperature)
TJ, Tstg
- 55 to + 150
300d
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = 50 V, starting TJ = 25 °C, L = 81 mH, RG = 25 Ω, IAS = 0.96 A (see fig. 12).
c. ISD ≤ 3.3 A, dI/dt ≤ 70 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
40
UNIT
°C/W
Maximum Junction-to-Ambient
(PCB Mount)a
RthJA
-
-
-
-
Maximum Junction-to-Case (Drain)
RthJC
60
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Gate-Source Leakage
VDS
ΔVDS/TJ
VGS(th)
IGSS
VGS = 0 V, ID = 250 µA
Reference to 25 °C, ID = 1 mA
VDS = VGS, ID = 250 µA
200
-
-
V
V/°C
V
-
0.30
-
2.0
-
-
-
-
-
-
4.0
100
25
250
1.5
-
VGS
=
20 V
-
nA
VDS = 200 V, VGS = 0 V
-
Zero Gate Voltage Drain Current
IDSS
µA
V
DS = 160 V, VGS = 0 V, TJ = 125 °C
-
-
Drain-Source On-State Resistance
Forward Transconductance
Dynamic
RDS(on)
gfs
VGS = 10 V
ID = 0.58 Ab
Ω
VDS = 50 V, ID = 0.58 A
0.51
S
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Ciss
Coss
Crss
Qg
-
-
-
-
-
-
-
-
-
-
140
53
15
-
-
VGS = 0 V,
DS = 25 V,
f = 1.0 MHz, see fig. 5
V
-
pF
nC
-
8.2
1.8
4.5
-
ID = 3.3 A, VDS = 160 V,
see fig. 6 and 13b
Qgs
Qgd
td(on)
tr
V
GS = 10 V
-
-
8.2
17
14
8.9
-
V
DD = 100 V, ID = 3.3 A,
ns
R
G = 24 Ω, RD = 30 Ω, see fig. 10b
Turn-Off Delay Time
Fall Time
td(off)
tf
-
-
D
Between lead,
Internal Drain Inductance
Internal Source Inductance
LD
LS
-
-
4.0
6.0
-
-
6 mm (0.25") from
package and center of
die contact
nH
G
S
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2
Document Number: 91193
S-81377-Rev. A, 30-Jun-08
IRFL210, SiHFL210
Vishay Siliconix
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Drain-Source Body Diode Characteristics
D
MOSFET symbol
Continuous Source-Drain Diode Current
Pulsed Diode Forward Currenta
IS
-
-
-
-
0.96
7.7
showing the
integral reverse
p - n junction diode
A
G
ISM
S
Body Diode Voltage
VSD
trr
TJ = 25 °C, IS = 0.96 A, VGS = 0 Vb
-
-
-
-
2.0
310
1.4
V
Body Diode Reverse Recovery Time
Body Diode Reverse Recovery Charge
Forward Turn-On Time
150
0.60
ns
µC
TJ = 25 °C, IF = 3.3 A, dI/dt = 100 A/µsb
Qrr
ton
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
101
VGS
Top
15 V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
4.5 V
100
10-1
10-2
150 °C
100
25 °C
Bottom
10-1
4.5 V
20 µs Pulse Width
DS = 50 V
20 µs Pulse Width
V
TC = 25 °C
4
5
6
7
8
9
10
100
101
10-1
91193_03
VGS
, Gate-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
91193_01
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 3 - Typical Transfer Characteristics
3.5
3.0
VGS
15 V
10 V
ID = 3.3 A
GS = 10 V
Top
V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
4.5 V
2.5
2.0
1.5
100
4.5 V
Bottom
10-1
1.0
0.5
20 µs Pulse Width
TC = 150 °C
0.0
100
101
10-1
- 60 - 40 - 20
0
20 40 60 80 100 120 140 160
VDS
, Drain-to-Source Voltage (V)
91193_02
91193_04
TJ, Junction Temperature (°C)
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 91193
S-81377-Rev. A, 30-Jun-08
www.vishay.com
3
IRFL210, SiHFL210
Vishay Siliconix
300
VGS = 0 V, f = 1 MHz
iss = Cgs + Cgd, Cds Shorted
101
C
250
200
150
100
50
Crss = Cgd
Coss = Cds + Cgd
Ciss
150 °C
100
25 °C
Coss
Crss
VGS = 0 V
1.6 2.0
0
10-1
100
101
0.4
0.8
1.2
VDS
,
Drain-to-Source Voltage (V)
91193_05
VSD, Source-to-Drain Voltage (V)
91193_07
Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
102
20
ID = 3.3 A
Operation in this area limited
5
by RDS(on)
V
DS = 160 V
16
12
8
2
V
DS = 100 V
10
V
DS = 40 V
5
100 µs
2
1
1 ms
5
4
TC = 25 °C
TJ = 150 °C
Single Pulse
10 ms
2
For test circuit
see figure 13
0.1
0
5
2
5
2
2
5
103
102
1
10
0
2
4
6
8
10
VDS, Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
91193_08
QG, Total Gate Charge (nC)
91193_06
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
www.vishay.com
4
Document Number: 91193
S-81377-Rev. A, 30-Jun-08
IRFL210, SiHFL210
Vishay Siliconix
RD
VDS
VGS
D.U.T.
RG
+
-
1.0
V
DD
10 V
0.8
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
0.6
0.4
0.2
0.0
Fig. 10a - Switching Time Test Circuit
VDS
90 %
25
50
75
100
125
150
10 %
VGS
TC, Case Temperature (°C)
91193_09
td(on) tr
td(off) tf
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
102
0 - 0.5
10
0.2
0.1
0.05
1
0.02
0.01
PDM
Single Pulse
t1
(Thermal Response)
0.1
t2
Notes:
1. Duty Factor, D = t1/t2
2. Peak Tj = PDM x ZthJC + TC
10-2
10-5
10-4
10-3
10-2
0.1
1
10
103
102
t1, Rectangular Pulse Duration (S)
91193_11
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
Document Number: 91193
S-81377-Rev. A, 30-Jun-08
www.vishay.com
5
IRFL210, SiHFL210
Vishay Siliconix
L
VDS
VDS
Vary tp to obtain
required IAS
tp
VDD
D.U.T
IAS
RG
+
-
VDD
VDS
10 V
0.01 Ω
tp
IAS
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12a - Unclamped Inductive Test Circuit
120
ID
Top
0.43 A
0.61 A
100
80
60
40
20
Bottom 0.90 A
VDD = 50 V
0
125
25
75
100
150
50
Starting T , Junction Temperature (°C)
91193_12C
J
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
QGD
+
-
VDS
D.U.T.
VG
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
Fig. 13b - Gate Charge Test Circuit
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6
Document Number: 91193
S-81377-Rev. A, 30-Jun-08
IRFL210, SiHFL210
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
+
Circuit layout considerations
• Low stray inductance
• Ground plane
D.U.T
• Low leakage inductance
current transformer
-
+
-
-
+
RG
• dV/dt controlled by RG
+
-
• Driver same type as D.U.T.
• ISD controlled by duty factor "D"
• D.U.T. - device under test
VDD
Driver gate drive
P.W.
P.W.
Period
Period
D =
V
= 10 V*
GS
D.U.T. I waveform
SD
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. V waveform
DS
Diode recovery
dV/dt
V
DD
Re-applied
voltage
Body diode forward drop
Ripple ≤ 5 %
Inductor current
I
SD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see http://www.vishay.com/ppg?91193.
Document Number: 91193
S-81377-Rev. A, 30-Jun-08
www.vishay.com
7
Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf
(collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein
or in any other disclosure relating to any product.
Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any
information provided herein to the maximum extent permitted by law. The product specifications do not expand or
otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed
therein, which apply to these products.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this
document or by any conduct of Vishay.
The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless
otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such
applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting
from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding
products designed for such applications.
Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000
Revision: 18-Jul-08
www.vishay.com
1
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INFINEON
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