DG485DJ [VISHAY]
Octal Analog Switch Array; 八通道模拟开关阵列
| 型号： | DG485DJ |
| 厂家： | 
VISHAY |
| 描述： | Octal Analog Switch Array |
| 文件： | 总11页 (文件大小：107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DG485
Vishay Siliconix
Octal Analog Switch Array
FEATURES
BENEFITS
APPLICATIONS
D Low On-Resistance: 55 W
D Rail-to-Rail Analog Input Range
D Serial Interface
D Low Signal Distortion
D Audio Switching and Routing
D Devices Can Be Chained for System D Audio Teleconferencing
Expansion
D Data Acquisition and Industrial
D Reduced Board Space
D Reduced Switch Errors
Process Control
D Low-Power—PD: 35 nW
D TTL and CMOS Compatible
D Battery Powered Remote Systems
D Reduced Power Supply
D Automotive, Avionics and ATE
D Any Combination of 8 SPST to the
Requirements
Systems
Output
D Simple Interfacing
D Summing Amplifiers
D High Speed—tON: 170 ns
DESCRIPTION
The DG485 is an analog switch array consisting of eight SPST
switches connected to a common output. This device may be
used as an 8-channel multiplexer in serial control applications.
Any, all or none of the eight switches may be closed at any
serial output (DOUT) allow daisy chaining of multiple arrays for
large systems.
W
given time. Combining low on-resistance (rDS(on) 55 , typ.)
Built on the Vishay Siliconix high voltage silicon gate process
the DG485 has a wide 44-V power supply voltage rating. An
epitaxial layer prevents latchup.
and fast switching (tON: 170 ns, typ.), the DG485 is ideally
suited for data acquisition, process control, communication,
and avionic applications.
Eachchannelconductsequallywellineitherdirectionwhenon
and blocks up to rail-to-rail voltages when off.
Control data is input serially into the shift register with each
clock pulse. The shift register contents can be latched-in (via
LD) at any point into an octal latch which in turn controls all
switches. RS resets the shift register, forcing all latch inputs to
a low condition (all switches off). The serial input (DIN) and
For additional information please refer to application note
AN204.
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
PLCC and LCC
Dual-In-Line
LD
RS
GND
D
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
3
2
1
20 19
V
S
S
S
S
L
4
3
S
S
S
S
4
5
6
7
8
18
17
16
15
14
D
S
4
3
2
1
S
5
5
S
6
S
S
S
2
1
6
S
S
7
7
V+
8
Shift Register/Latches
10 11 12 13
V+
8
9
D
IN
V–
Shift Register
Latches
CLK
D
OUT
Top View
Top View
Document Number: 70065
S-52433—Rev. E, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-1
DG485
Vishay Siliconix
TRUTH TABLES AND ORDERING INFORMATION
TRUTH TABLEĊDUALĆINĆLINE PACKAGE
TRUTH TABLEĊPLCC
&
LCC PACKAGES
RS
1
CLK*
DIN
0
D1
0
Dn
LD*
Dn
0
Ln
0
SWn
D
OFF
ON
n-1
n-1
1
1
1
D
1
1
1
0
X
X
D
D
n
(No Change)
0
D
L
n
(No Change)
1
n
X
0
*LD Input Level Triggered
*CLK Input Edge Triggered
ORDERING INFORMATION
Temp Range
Package
Part Number
18-Pin Plastic DIP
20-Pin PLCC
LCC-20
DG485DJ
–40 to 85_C
DG485DN
–55 to 125_C
DG485AZ/883
ABSOLUTE MAXIMUM RATINGS
b
Voltages Referenced to V–
Power Dissipation (Package)
c
18-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW
20-Pin PLCC, LCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 mW
V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V
d
GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V
a
Digital Inputs V , V . . . . . . . . . . . . . . . . . . . . . . . . . . (V–) –2 V to (V+) + 2 V
S
D
or 30 mA, whichever occurs first
Notes:
a. Signals on S , D or IN exceeding V+ or V– will be clamped by internal
X
X
X
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Current, S or D (Pulsed 1 ms, 10% duty cycle) . . . . . . . . . . . . . . . . . . 100 mA
diodes. Limit forward diode current to maximum current ratings.
b. All leads soldered or welded to PC board.
c. Derate 6 mW/_C above 75_C.
Storage Temperature
(AZ Suffix) . . . . . . . . . . . . . . . . . . –65 to 150_C
(DJ, DN Suffix) . . . . . . . . . . . . . . –65 to 125_C
d. Derate 10 mW/_C above 75_C.
Document Number: 70065
S-52433—Rev. E, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-2
DG485
Vishay Siliconix
a
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
A Suffix
–55 to 125_C
D Suffix
–40 to 85_C
V+ = 15 V, V– = –15 V
f
Parameter
Symbol
Tempb Typc
Mind Maxd Mind Maxd Unit
V
L
= 5 V, V = 2.4 V, 0.8 V
IN
Analog Switch
e
Analog Signal Range
V
Full
–15
15
–15
15
V
ANALOG
Drain-Source
On-Resistance
V+ = 13.5 V, V– = –13.5 V
= –5 mA, V = "10 V
Room
Full
55
85
125
85
125
r
W
DS(on)
I
S
D
Delta Drain-Source
On-Resistance
Dr
Room
6
%
DS(on)
S(off)
g
Room
Full
0.01
–1
–20
1
20
–1
–10
1
10
I
Switch Off
Leakage Current
V+ = 16.5 V, V– = –16.5 V
V = #15.5 V, V = "15.5 V
D
S
Room
Full
0.1
–10
–200
10
200
–10
–50
10
50
I
D(off)
nA
V" = "16.5 V V = V = "15.5 V
Room
Full
0.11
–20
–500
20
500
–20
–50
20
50
S
D
One Switch At A Time
Channel On
Leakage Current
I
D(on)
V" = "16.5 V, V = V = "15.5 V
S
D
Room
0.2
All Switches On
Input
mA
Input Current
I
V
Under Test = 0.8 V
IN
All Other = 2.4 V
Room
Full
–0.0001
0.0001
–1
–5
1
5
–1
–5
1
5
IL
with V Low
IN
Input Current
V
IN
Under Test = 2.4 V
All Other = 0.8 V
Room
Full
–1
–5
1
5
–1
–5
1
5
I
IH
with V High
IN
Serial Data Output
Output Voltage
V
I
= 1.6 mA, V+ = 4.5 V
Full
Full
0.25
4.4
0.4
0.4
OL
O
with V Low – D
IN
OUT
V
Output Voltage
I
O
= –80 mA, V+ = 16.5 V
V
OH
2.7
2.7
with V High – D
V
L
= 4.75 V
IN
OUT
Dynamic Characteristics
V
= "10 V
Room
Full
170
150
200
275
200
275
S
Turn-On Time
t
ON
See Figures 1, 8
V
S
= "10 V
Room
Full
200
275
200
276
Turn-Off Time
t
OFF
See Figures 2, 3, 8
Room
Full
40
60
40
60
Data Setup Time
Data Hold Time
LOAD Hold Time
RESET Hold Time
t
DS
DH
See Figures 4, 8
Room
Full
40
60
40
60
t
ns
Room
Full
100
150
100
150
t
LH
Room
Full
100
150
100
150
t
RH
See Figures 5, 8
RESET " to CLOCK "
Room
Full
40
60
40
60
t
DRC
Delay
V
= 0 V, C = 1,000 pF
L
Any One Channel
S
Charge Injection
Q
Room
Room
Room
17
–75
10
pC
dB
R
L
= 50 W, C = 5 pF, f = 1 MHz
L
e
Off Isolation
OIRR
See Figure 9
Maximum
Clock Frequency
f
MHz
CLK
Document Number: 70065
S-52433—Rev. E, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-3
V
IN
mA
DG485
Vishay Siliconix
a
SPECIFICATIONS
Test Conditions
Unless Otherwise Specified
A Suffix
–55 to 125_C
D Suffix
–40 to 85_C
V+ = 15 V, V– = –15 V
f
Parameter
Symbol
Tempb Typc
Mind Maxd Mind Maxd Unit
V
L
= 5 V, V = 2.4 V, 0.8 V
IN
Dynamic Characteristics (Cont’d)
Source Off
Capacitance
C
Room
Room
Room
7
S(off)
D(off)
e
V
= 0 V, R
= 0 W, f = 1 MHz
gen
gen
e
Drain Off Capacitance
C
43
53
pF
V
= 0 V, R
= 0 W, f = 1 MHz One
gen
gen
Channel On
e
On-State Capacitance
C
D(on)
V
= 0 V, R
= 0 W, f = 1 MHz All Chan-
gen
gen
Room
122
nels On
Power Supplies
Positive Supply
Current
Room
Full
0.001
–0.001
0.001
3
10
3
10
I+
I–
Negative Supply
Current
Room
Full
–3
–10
–3
–10
V+ = 16.5 V, V– = –16.5 V
= 0 or 5 V, V = 5.25 V
L
Room
Full
3
10
3
10
D
OUT
Open
Logic Supply Current
I
L
Room
Full
–0.001
–3
–10
–3
–10
Ground Current
Notes:
I
GND
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f.
V
IN
= input voltage to perform proper function.
r
MAX – r
DS(on)
DS(on)
AVE
g.
For each V
:
Dr
+
ǒ
MINǓ
D
DS(on)
r
DS(on)
TYPICAL CHARACTERISTICS (_2C5 UNLESS NOTED)
Supply Currents vs. Temperature
r vs. V and Power Supply Voltage
DS(on) D
1 mA
160
V+ = 15 V
V– = –15 V
V
I
= 5 V
= –5 mA
L
S
140
120
100
80
100 nA
10 nA
1 nA
V
L
= 5 V
I
L
I
POS
"5 V
I
NEG
"8 V
100 pA
10 pA
60
"10 V
I
GND
40
"12 V
1 pA
"20 V
20
"15 V
0.1 pA
0
–50 –30 –10 10
30
50
70
90 110 130
–20
–15 –10
–5
0
5
10
15
20
Temperature (_C)
V – Drain Voltage (V)
D
Document Number: 70065
S-52433—Rev. E, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-4
DG485
Vishay Siliconix
TYPICAL CHARACTERISTICS (_2C5 UNLESS NOTED)
r
400
vs. V and Unipolar Power Supply Voltage
r
vs. V and Temperature
DS(on) D
DS(on)
D
100
90
V– = 0 V
350
300
250
200
150
100
50
V
= 5 V
= –5 mA
L
I
S
80
70
60
50
40
V+ = 5 V
125_C
25_C
8 V
30
20
10
0
10 V
V+ = 15 V
V– = –15 V
= 5 V
= –5 mA
–55_C
12 V
15 V
20 V
V
I
L
S
0
0
–15
5
2
4
6
8
10 12 14 16 18 20
–15
–10
–5
0
5
10
15
V
– Drain Voltage (V)
V – Drain Voltage (V)
D
D
Channel On/Off Leakage Currents
vs. Analog Voltage
Channel On/Off Leakage Currents
vs. Temperature
1 mA
100 nA
10 nA
1 nA
60
40
V+ = 15 V
V– = –15 V
= 5 V
V+ = 15 V
V– = –15 V
V
V
V
L
S
= 5 V
L
or V = – 14 V
D
20
I
S(off)
0
I
I
S(off)
100 pA
10 pA
1 pA
D(on)
I
D(off)
–20
–40
–60
–80
I
D(on)
I
D(off)
0.1 pA
0.01 pA
–10
–5
0
5
10
15
–50 –30 –10 10
30
50
70
90 110 130
V
D
or V – Drain or Source Voltage (V)
S
Temperature (_C)
Switching Threshold
vs. Power Supply Voltage and V
RF Characteristics
L
–140
–120
3.0
2.5
5 V
V
L
= 7 V
6 V
–100
–80
–60
–40
–20
0
2.0
1.5
1.0
0.5
X
TALK
OIRR
4 V
V+ = 15 V
V– = –15 V
V
= 5 V
L
See Figures 9, 10
0
6
7
8
9
10 11 12 13 14 15
1 k
10 k
100 k
f – Frequency (Hz)
1 M
10 M
V+ Supply (V)
Document Number: 70065
S-52433—Rev. E, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-5
DG485
Vishay Siliconix
TYPICAL CHARACTERISTICS (_2C5 UNLESS NOTED)
Supply Currents vs. Switching Frequency
Source/Drain On Capacitance vs. Analog Voltage
180
10 mA
V+ = 15 V
V– = –15 V
V+ = 15 V
V– = –15 V
= 5 V
160
140
120
100
80
V
V
= 5 V
1 mA
L
V
L
= 3 V
IN
I
n
I
L
C
D(on)
100 mA
10 mA
1 mA
(All Channels On)
I
p
100 nA
C
D(on)
60
(Channel 1 On Only)
10
40
10 nA
100
1 k
10 k
f – Frequency (Hz)
100 k
1 M
–15
–10
–5
0
5
15
V
– Analog Voltage (V)
ANALOG
Source/Drain Off Capacitance
vs. Analog Voltage
Charge Injection vs. Analog Voltage
55
45
35
25
15
5
70
60
50
40
30
20
10
V+ = 15 V
V– = –15 V
V+ = 15 V
V– = –15 V
= 5 V
V
C
= 5 V
= 1 nF
V
L
L
L
C
D(off)
C
S(off)
0
–5
–15
–10
–5
0
5
10
15
–15
–10
–5
V – Source Voltage (V)
S
0
5
10
15
V
– Analog Voltage (V)
ANALOG
TIMING DIAGRAMS
3 V
3 V
50%
50%
LD 0 V
LD 0 V
V
S
V
S
90%
90%
0 V
0 V
V
D
V
D
Repeat for All Channels
from LD
Repeat for All Channels
t
t
OFF
ON
FIGURE 1.
t
from LD
FIGURE 2. t
OFF
ON
3 V
0 V
50%
RS
V
S
90%
0 V
V
D
t
OFF
FIGURE 3.
t
from RS
OFF
Document Number: 70065
S-52433—Rev. E, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-6
DG485
Vishay Siliconix
TIMING DIAGRAMS
50%
CLOCK
50%
DATA
t
DH
t
DS
FIGURE 4. Data Setup and Hold Time
CLOCK
RS
LOAD
t
LH
t
t
DRC
RH
FIGURE 5. Timing Relationships
RS
D
IN
CLK
LD
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
D
OUT
S
1
– S and D are expected output with the drain connected high. The sources require pull-down of 1 kW.
OUT
8
FIGURE 6.
Document Number: 70065
S-52433—Rev. E, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-7
DG485
Vishay Siliconix
SCHEMATIC DIAGRAM (TYPICAL CHANNEL)
V+
S
S
V
L
1
V+
RS
RS
D
1
8
Level
Shift/
Drive
Octal
Latch
D
n
D
IN
Shift
Register
V–
V+
CLK
D
8
CLK
LD
D
D
OUT
V+
LD
V–
GND
FIGURE 7.
Document Number: 70065
S-52433—Rev. E, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-8
DG485
Vishay Siliconix
TEST CIRCUITS
+15 V
V+
+5 V
50 W
S
S
S
1
2
3
V
L
50 W
V
S
S
S
1
2
V
O
D
50 W
50 W
50 W
35 pF
D
1 kW
DG485
S
S
7
DG485
50 W
8
CLK
LD
D
IN
RS
V–
S
8
GND
–15 V
FIGURE 8. Switching Time Test Circuit
FIGURE 9. Adjacent Input Crosstalk
TEST CIRCUITS
50 W
S
1
50 W
V
O
DG485
50 W
S
2
50 W
50 W
S
8
FIGURE 10. Off Isolation
Document Number: 70065
S-52433—Rev. E, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-9
DG485
Vishay Siliconix
APPLICATIONS
f= for CLK and LD inputs of the same frequency.
The recommended phase delay of LD from CLK is
CLK
LD
½ t
LOGIC
to t
:
LOGIC
t
:
80 ns at 25_C
V+ = 15 V
V– = –15 V
GND = 0 V
f
LOGIC(MIN)
150 ns at 125_C
t
t
LOGIC
LOGIC
FIGURE 11.
C
C
1
DG485
V
REF
2
D
IN
DG485
R
R
1
IN
IN
R
R
1
IN
2
CLK
R
F
R
0
R
1
R
2
R
7
2
IN
V
OUT
–
+
–
+
FIGURE 13. Serial DAC Circuit
FIGURE 12. Multi-Function Circuit Provides Input Selection,
Gain Ranging and Filtering with One DG485
Document Number: 70065
S-52433—Rev. E, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-10
DG485
Vishay Siliconix
APPLICATIONS
R
F
R
V
1
V
–
+
OUT
+
–
R
V
2
C
H
R
V
8
DG485
DG485
FIGURE 14. Summing Node Mixer
FIGURE 15. Multiplexing, Sampling Application
S
1
S
2
S
8
DG485
D
Switch Array
Octal Latch
8085
D
IN
D
OUT
To Next
Switch
Array
SOD
ALE
S/R
RS
LD
CLK
Data Bus
8212
(8)
Decoder
8205
Address Bus
(8)
WR
R/S
FIGURE 16. Direct Serial Interface (8085)
Document Number: 70065
S-52433—Rev. E, 06-Sep-99
www.vishay.com S FaxBack 408-970-5600
5-11
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