CRCW06030000Z0EA [VISHAY]
5 V, 3 A Current-Mode Constant On-Time Synchronous Buck Regulator; 5 V ， 3 A电流模式恒定导通时间同步降压稳压器
| 型号： | CRCW06030000Z0EA |
| 厂家： | 
VISHAY |
| 描述： | 5 V, 3 A Current-Mode Constant On-Time Synchronous Buck Regulator |
| 文件： | 总19页 (文件大小：715K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SiP12107
Vishay Siliconix
www.vishay.com
5 V, 3 A Current-Mode Constant On-Time
Synchronous Buck Regulator
DESCRIPTION
FEATURES
• Halogen-free According to IEC 61249-2-21
Definition
• 2.8 V to 5.5 V input voltage
The SiP12107 is a high frequency current-mode constant
on-time (CM-COT) synchronous buck regulator with
integrated high-side and low-side power MOSFETs. Its
power stage is capable of supplying 3 A continuous current
at 4 MHz switching frequency. This regulator produces an
adjustable output voltage down to 0.6 V from 2.8 V to 5.5 V
input rail to accommodate a variety of applications,
including computing, consumer electronics, telecom, and
industrial.
• Adjustable output voltage down to 0.6 V
• 3 A continuous output current
• Programmable switching frequency up to 4 MHz
• 95 % peak efficiency
• Supports all ceramic capacitors No external ESR required
• Ultrafast transient response
SiP12107’s CM-COT architecture delivers ultra-fast
transient response with minimum output capacitance and
tight ripple regulation at very light load. No ESR or external
ESR network is required for loop stability purpose. The
device also incorporates a power saving scheme that
significantly increases light load efficiency.
• Selectable power saving mode or force current mode
•
1 % accuracy
• Pulse-by-pulse current limit
• Scalable with SiP12108 - 5A
• Fully protected with OTP, SCP, UVP, OVP
• PGood Indicator
The regulator integrates a full protection feature set,
including output overvoltage protection (OVP), output under
voltage protection (UVP) and thermal shutdown (OTP). It
also has UVLO for input rail and internal soft-start ramp.
• Compliant to RoHS Directive 2011/65/EU
APPLICATIONS
The SiP12107 is available in lead (Pb)-free power enhanced
MLP-16L package in 3 mm x 3 mm dimension.
• Notebook computers
• Desktop PCs and servers
• Handheld devices
• POLs for telecom
• Consumer electronics
• Industrial and automation
TYPICAL APPLICATION CIRCUIT AND PACKAGE OPTIONS
PWR_SAVE_MODE
ENABLE
POWER GOOD
PGD
EN AUTO
LX
VOUT
INPUT = 2.8 V to 5.5 V
VIN
VOUT
VFB
AVIN
PGND
GMO
RON
AGND
Fig. 1 - Typical Application Circuit for SiP12107
S12-0412-Rev. B, 20-Feb-12
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SiP12107
Vishay Siliconix
www.vishay.com
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL PARAMETER
CONDITIONS
Reference to PGND
Reference to AGND
Reference to PGND
LIMIT
- 0.3 to 6
UNIT
VIN
AVIN
LX
- 0.3 to 6
- 0.3 to 6
V
A
GND to PGND
- 0.3 to + 0.3
- 0.3 to AVIN + 0.3
All Logic Inputs
Reference to AGND
TEMPERATURE
Max. Operating Junction Temperature
Storage Temperature
150
°C
- 65 to 150
POWER DISSIPATION
Junction to Ambient Thermal Impedance
36.3
°C/W
W
(RthJA
)
Ambient Temperature = 25 °C
Ambient Temperature = 100 °C
3.4
1.3
Maximum Power Dissipation
ESD PROTECTION
HBM
2
kV
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
ELECTRICAL PARAMETER
MINIMUM
TYPICAL
MAXIMUM
5.5
UNIT
V
VIN
2.8
2.8
- 1
-
AVIN
-
5.5
LX
-
5.5
VOUT
0.6
-
0.85 x VIN
Ambient Temperature
- 40 to 85
°C
S12-0412-Rev. B, 20-Feb-12
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SiP12107
Vishay Siliconix
www.vishay.com
ELECTRICAL SPECIFICATIONS
TEST CONDITION UNLESS OTHERWISE
SPECIFIED
VIN = AVIN = 3.3 V, TA = - 40 °C to 85 °C
LIMITS
UNIT
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
POWER SUPPLY
Power Input Voltage Range
Bias Input Voltage Range
VIN
2.8
2.8
-
-
5.5
5.5
V
AVIN
Device switching, IO = 0 A,
Input Current
IVIN_NOLOAD
-
1000
-
Ron = 100 k, AUTO = Low
μA
Shutdown Current
IVIN_SHDN
AVIN, UVLO
UVLOHYS
EN = 0 V
-
-
-
6
12
-
AVIN UVLO Threshold
AVIN UVLO Hysteresis
PWM CONTROLLER
AVIN rising edge
2.55
300
V
-
mV
TA = 0 °C to + 70 °C
0.594
0.600
0.600
2
0.606
Feedback Reference
VFB
V
TA = - 40 °C to + 85 °C
0.591
0.609
VFB Input Bias Current
-
-
200
nA
Transconductance
1
-
-
-
4
-
-
-
mS
COMP Source Current
COMP Sink Current
Switching Frequency Range
Minimum On-Time
-
50
μA
MHz
ns
-
50
Guaranted by design
Guaranted by design
0.2
-
-
50
Minimum Off-Time
VOUT = 1.2 V, RON = 100 k
-
120
1.5
Soft Start Time
-
ms
INTEGRATED MOSFETS
High-Side On Resistance
Low-Side On Resistance
FAULT PROTECTIONS
Over Current Limit
-
-
56
33
-
-
VIN = 3.3 V
m
Inductor valley current
-
-
-
-
-
4.5
20
-
-
-
-
-
A
Output OVP Threshold
Output UVP Threshold
VFB with respect to 0.6 V reference
%
- 25
160
35
Rising temperature
Hysteresis
Over Temperature Protection
POWER GOOD
°C
%
V
FB rising above 0.6 V reference
-
-
-
-
20
- 10
30
6
-
-
-
-
Power Good Output Threshold
VFB falling below 0.6 V reference
Power Good On Resistance
Power Good Delay Time
ENABLE THRESHOLD
Logic High Level
μs
1.5
-
-
-
-
V
Logic Low Level
0.4
S12-0412-Rev. B, 20-Feb-12
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SiP12107
Vishay Siliconix
www.vishay.com
FUNCTIONAL BLOCK DIAGRAM
7
2
6
5
3
1,16
VIN
AVIN
PGOOD
EN
GMO
AUTO
AGND
8
OTP
VIN
0.6 V
REFERENCE
UVLO
SOFT
START
VIN
LX
+
ANTI-XCOND
CONTROL
CONTROL
LOGIC
SECTION
11,12,13
+ OTA
+
-
ON-TIME
GENERATOR
9
-
VIN
VFB
PWM COMPARATOR
I-V
Converter
Isense
ZCD
OCP
PGND
RON
4
14,15
-
+
VOUT
UV Comparator
OV Comparator
0.45 V
10
Current
Mirror
+
-
VFB
0.72 V
Isense
PAD
Fig. 2 - SiP12107 Functional Block Diagram
ORDERING INFORMATION
MARKING
(LINE 2: P/N)
PART NUMBER
PACKAGE
SIP12107DMP-T1-GE3
SIP12107DB
QFN33-16L
2107
Reference Board
P/N
AA
W11B
Format:
Line 1: Dot
Line 2: P/N
Line 2: Siliconix Logo + ESD Symbol
Line 3: Factory Code + Year Code + Work Week Code + Lot Code
S12-0412-Rev. B, 20-Feb-12
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PIN CONFIGURATION
16 15 14 13
VIN
AVIN
EN
LX
1
2
3
4
12
11
10
9
LX
VOUT
VFB
RON
7
8
5
6
MLPQ 3 x 3 - 16L
Fig. 3 - SiP12107 Pin Configuration (Top View)
PIN CONFIGURATION
PIN NUMBER
NAME
FUNCTION
1
2
VIN
Input supply voltage for power MOS. VIN = 2.8 V to 5.5 V
AVIN
EN
Input supply voltage for internal circuitry. AVIN = 2.8 V to 5.5 V
Enable pin. Enable > 1.5 V
3
4
RON
AUTO
PGD
GMO
AGND
VFB
An external resistor between RON and GND sets the switching on time.
Sets switching mode AUTO to AVIN = PWM, AUTO to GND = light load mode
Power good output. Open drain.
5
6
7
Connect to an external RC network for loop compensation and droop function
Analog ground
8
9
Feedback voltage. 0.6 V (typ.)
10
11
12
13
14
15
16
VOUT
LX
VOUT, output voltage sense connection
Switching output, inductor connection point
Switching output, inductor connection point
Switching output, inductor connection point
Power ground
LX
LX
PGND
PGND
VIN
Power ground
Input supply voltage for power MOS. VIN = 2.8 V to 5.5 V
S12-0412-Rev. B, 20-Feb-12
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SiP12107
Vishay Siliconix
www.vishay.com
ELECTRICAL CHARACTERISTICS (VIN = 3.3 V, L = 1 μH, C = 3 x 22 μF, fSW = 1.2 MHz unless noted otherwise)
1.2 V PWM
1.8 V PWM
Efficiency vs. IOUT (PSM)
Efficiency vs. IOUT (PWM)
Load Regulation: % of VOUT vs. IOUT (PSM)
Load Regulation: % of VOUT vs. IOUT (PWM)
1.2 V PWM
1.8 V PWM
Line Regulation 1.2 VOUT Nominal 0 A Load (PSM)
Line Regulation 1.2 VOUT at 3 A Load (PWM)
S12-0412-Rev. B, 20-Feb-12
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SiP12107
Vishay Siliconix
www.vishay.com
FSW Variation vs. IOUT (PSM)
FSW Variation vs. IOUT (PWM)
CH1: VOUT 20 mV/Div
CH2: LX 2 V/Div
CH1: VOUT 20 mV/Div
CH2: LX 2 V/Div
Output Ripple PSM: 0 A Load
Output Ripple PSM: 0 A Load
Output Ripple PWM: 0 A Load
Output Ripple PWM: 3 A Load
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SiP12107
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VIN = 2 V/div
VOUT = 1 V/div
P
GOOD = 2 V/div
LX = 2 V/div
VIN = 2 V/div
VOUT = 1 V/div
PGOOD = 2 V/div
LX = 2 V/div
Startup PSM: 0 A Load
Startup PSM: 3 A Load
Startup PWM: 0 A Load
Shutdown PSM: 0 A Load
VIN = 2 V/div
VOUT = 1 V/div
P
GOOD = 2 V/div
LX = 2 V/div
VIN = 2 V/div
VOUT = 1 V/div
PGOOD = 2 V/div
LX = 2 V/div
Shutdown PSM: 3 A Load
VIN = 2 V/div
VOUT = 1 V/div
P
GOOD = 2 V/div
LX = 2 V/div
VIN = 2 V/div
VOUT = 1 V/div
PGOOD = 2 V/div
LX = 2 V/div
Shutdown PWM: 0 A Load
S12-0412-Rev. B, 20-Feb-12
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SiP12107
Vishay Siliconix
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VIN = 2 V/div
VOUT = 1 V/div
P
GOOD = 2 V/div
LX = 2 V/div
VIN = 2 V/div
VOUT = 1 V/div
PGOOD = 2 V/div
LX = 2 V/div
Startup PWM: 3 A Load
Shutdown PWM: 3 A Load
VOUT = 100 mV/div
ILOAD = 1 A/div
LX = 2 V/div
VOUT = 100 mV/div
ILOAD = 1 A/div
LX = 2 V/div
Load Step PSM: 0 A to 1.5 A Load (undershoot)
Load Step PSM 0 A to 1.5 A Load (overshoot)
VOUT = 200 mV/div
VOUT = 200 mV/div
ILOAD = 5 A/div
LX = 2 V/div
I
LOAD = 5 A/div
LX = 2 V/div
Load Step PSM: 0 A to 3 A Load (undershoot)
Load Step PSM: 0 A to 3 A Load (overshoot)
S12-0412-Rev. B, 20-Feb-12
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SiP12107
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VOUT = 50 mV/div
LOAD = 2 A/div
LX = 2 V/div
VOUT = 50 mV/div
ILOAD = 2 A/div
LX = 2 V/div
I
Load Step PWM: 0 A to 1.5 A Load (undershoot)
Load Step PWM 0 A to 1.5 A Load (overshoot)
VOUT = 100 mV/div
ILOAD = 5 A/div
LX = 2 V/div
VOUT = 100 mV/div
ILOAD = 5 A/div
LX = 2 V/div
Load Step PWM: 0 A to 3 A Load (undershoot)
Load Step PWM 0 A to 3 A Load (overshoot)
S12-0412-Rev. B, 20-Feb-12
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SiP12107
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OPERATIONAL DESCRIPTION
Device Overview
Power Stage
SiP12107 is a high-efficiency monolithic synchronous buck
regulator capable of delivering up to 3 A continuous current.
The device has programmable switching frequency up to
4 MHz. The control scheme is based on current-mode
constant-on-time architecture, which delivers fast transient
response and minimizes external components. Thanks to
the internal current ramp information, no high-ESR output
bulk or virtual ESR network is required for the loop stability.
This device also incorporates Power-Saving feature by
enabling diode emulation mode and frequency foldback as
load decrease.
SiP12107 integrates a high-performance power stage with
a ~ 64 m p-channel MOSFET and a ~ 33 m n-channel
MOSFET. The MOSFETs are optimized to achieve 95 %
efficiency at 2 MHz switching frequency.
The power input voltage (VIN) can go up to 5.5 V and down
as low as 2.8 V for the power conversion. The logic bias
voltage (AVIN) ranges from 2.8 V to 5.5 V.
PWM Control Mechanism
SiP12107 employs a state-of-the-art current-mode COT
control mechanism. During steady-state operation, output
voltage is compared with internal reference (0.6 V typ.) and
the amplified error signal (VCOMP) is generated on the COMP
pin. In the meantime, inductor valley current is sensed, and
its slope (Isense) is converted into a voltage signal (Vcurrent) to
SiP12107 has a full set of protection and monitoring
features:
- Over current protection in pulse-by-pulse mode
- Output over voltage protection
be compared with VCOMP. Once Vcurrent is lower than VCOMP
,
a single shot on-time is generated for a fixed time
programmed by the external RON. Figure 4 illustrates the
basic block diagram for CM-COT architecture and figure 5
demonstrates the basic operational principle:
- Output under voltage protection with device latch
- Over temperature protection with hysteresis
- Dedicated enable pin for easy power sequencing
- Power Good open drain output
This device is available in MLPQ 3 x 3-16L package to
deliver high power density and minimize PCB area.
RON
Bandgap
VOUT
VOUT
Vref
HG
+
OTA
-
Control
VIN
ON-TIME
Generator
Logic &
MOSFET
Driver
VIN
LG
Vcomp
+
-
HG
+
Vcurrent
PWM
COMPARATOR
Current
Mirror
Isense I-AMP
-
LS FET
LG
Fig. 4 - CM-COT Block Diagram
S12-0412-Rev. B, 20-Feb-12
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SiP12107
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Vcurrent
vcomp
Fixed ON-time
PWM
Fig. 5 - CM-COT Operational Principle
The following equation illustrates the relationship between
on-time, VIN, VOUT and RON value:
Once on-time is set, the pseudo constant frequency is then
determined by the following equation:
VOUT
VOUT
TON = RON x K x
, where K = 9.6 x 10-12 a constant set internally
D
VIN
1
VIN
¼ sw =
=
=
TON
VOUT
VIN
R
ON x K
x RON x K
Loop Stability and Compensator Design
Due to the nature of current mode control, a simple RC network (type II compensator) is required between COMP and AGND for
loop stability and transient response purpose. General concept of this loop design is to introduce a single zero through the
compensator to determine the crossover frequency of overall close loop system.
The overall loop can be broken down into following segments.
Output feedback divider transfer function Hfb:
Rfb2
-----------------------------
=
Hfb
Rfb1 x Rfb2
Voltage compensator transfer function GCOMP (s):
GCOMP (s) =
RO x 1 + sCCOMPRCOMP
-------------------------------------------------------------------------
gm
1 + sROCCOMP
Modulator transfer function Hmod (s):
Rload x 1 + sCORESR
1
----------------------------------- -------------------------------------------------------------
Hmod (s) =
x
AV1 x RDS(on)
1 + sCORload
The complete loop transfer function is given by:
Rfb2 RO x 1 + sCCOMPRCOMP
Rload x 1 + sCORESR
1
----------------------------- -------------------------------------------------------------------------
----------------------------------- -------------------------------------------------------------
Hmod (s) =
x
gm x
x
Rfb1 x Rfb2
1 + sROCCOMP
AV1 x RDS(on)
1 + sCORload
When:
CCOMP = Compensation capacitor
RCOMP = Compensation resistor
RDS(on) = LS switch resistance
Rfb1
Rfb2
RO
= Feedback resistor connect to LX
= Feedback resistor connect to ground
= Output impedance of error amplifier = 20 M
= Voltage to current gain = 3
gm
Rload = Load resistance
CO = Output capacitor
= Error amplifier transconductance
AV1
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SiP12107
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Power-Saving Mode Operation
To further improve efficiency at light-load condition,
SiP12107 provides a set of innovative implementations to
eliminate LS recirculating current and switching losses. The
internal Zero Crossing Detector (ZCD) monitors LX node
voltage to determine when inductor current starts to flow
negatively. In power saving mode (PSM), as soon as
inductor valley current crosses zero, the device first deploys
diode emulation mode by turning off LS FET. If load further
decreases, switching frequency is further reduced
proportional to load condition to save switching losses while
keeping output ripple within tolerance. The switching
frequency is set by the controller to maintain regulation. At
zero load this frequency can go as low as hundreds of Hz.
Whenever fixed frequency PWM operation is required over
the entire load span, power saving mode feature can be
disabled by connecting AUTO pin to VIN or AVIN.
OUTPUT MONITORING AND PROTECTION FEATURES
Output Over-Current Protection (OCP)
SiP12107 has pulse-by-pulse over-current limit control. The
inductor valley current is monitored during LS FET turn-on
period through RDS(on) sensing. After a pre-defined time, the
valley current is compared with internal threshold (5 A typ.)
to determine the threshold for OCP. If monitored current is
higher than threshold, HS turn-on pulse is skipped and LS
FET is kept on until the valley current returns below OCP
limit.
In the severe over-current condition, pulse-by-pulse current
limit eventually triggers output under-voltage protection
(UVP), which latches the device off to prevent catastrophic
thermal-related failure. UVP is described in the next section.
OCP is enabled immediately after AVIN passes UVLO level.
Figure 6 illustrates the OCP operation.
OCPthreshold
Iload
Iinductor
GH
Skipped GH Pulse
Fig. 6 - Over-Current Protection Illustration
Output Under-Voltage Protection (UVP)
Over-Temperature Protection (OTP)
UVP is implemented by monitoring output through VFB pin.
Once the voltage level at VFB is below 0.45 V for more than
20 μs, then UVP event is recognized and both HS and LS
MOSFETs are turned off. UVP latches the device off until
either AVIN or EN is recycled.
SiP12017 has internal thermal monitor block that turns off
both HS and LS FETs when junction temperature is above
160 °C (typ.). A hysteresis of 30 °C is implemented, so when
junction temperature drops below 130 °C, the device
restarts by initiating the soft-start sequence again.
UVP is only active after the completion of soft-start
sequence.
Soft Startup
SiP12107 deploys an internally regulated soft-start
sequence to realize a monotonic startup ramp without any
output overshoot. Once AVIN is above UVLO level (2.55 V
typ.). Both the reference and VOUT will ramp up slowly to
regulation in 1 ms (typ.) with the reference going from 0 V to
0.6 V and VOUT rising monotonically to the programmed
output voltage.
Output Over-Voltage Protection (OVP)
For OVP implementation, output is monitored through FB
pin. After soft-start, if the voltage level at FB is above 20 %
(typ.), OVP is triggered with HS FET turning off and LS FET
turning on immediately to discharge the output. Normal
operation is resumed once FB voltage drops back to 0.6 V.
During soft-start period, OCP is activated. OVP and
short-circuit protection are not active until soft-start is
complete.
OVP is active immediately after AVIN passes UVLO level.
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Pre-bias Startup
Power Good (PG)
In case of pre-bias startup, output is monitored through FB
pin. If the sensed voltage on FB is higher than the internal
reference ramp value, control logic prevents HS and LS FET
from switching to avoid negative output voltage spike and
excessive current sinking through LS FET.
SiP12107’s Power Good is an open-drain output. Pull PG
pin high up to 5 V through a 10K resistor to use this signal.
Power Good window is shown in the below diagram. If
voltage level on FB pin is out of this window, PG signal is
de-asserted by pulling down to GND.
VFB_Rising_Vth_OV
(Typ. = 0.725 V)
VFB_Falling_Vth_OV
(Typ. = 0.675V)
Vref (0.6V)
VFB_Rising_Vth_UV
(Typ. = 0.575V)
VFB_Falling_Vth_UV
(Typ. = 0.525V)
VFB
Pull-high
PG
Pull-low
Fig. 7 - PG Window and Timing Diagram
DESIGN PROCEDURE
The design process of the SiP12107 is quite straight
forward. Only few passive components such as output
capacitors, inductor and Ron resistor need to be selected.
Setting Switching Frequency
Selection of the switching frequency requires making a
trade-off between the size and cost of the external filter
components (inductor and output capacitor) and the power
conversion efficiency. The desired switching frequency,
1 MHz was chosen based on optimizing efficiency while
maintaining a small footprint and minimizing component
cost.
The following paragraph describes the selection procedure
for these peripheral components for a given operating
conditions.
In the next example the following definitions apply:
V
V
INmax.: the highest specified input voltage
In order to set the design for 1 MHz switching frequency,
(RON) resistor which determines the on-time (indirectly
setting the frequency) needs to be calculated using the
following equation.
INmin.: the minimum effective input voltage subject to
voltage drops due to connectors, fuses, switches,
and PCB traces
There are two values of load current to evaluate - continuous
load current and peak load current.
1
1
---------------------
--------------------------------------------------------
RON
=
=
105 k
1 x 106 x 9.6 x 10-12
FSW x K
Continuous load current relates to thermal stress
considerations which drive the selection of the inductor and
input capacitors.
Peak load current determines instantaneous component
stresses and filtering requirements such as inductor
saturation, output capacitors, and design of the current limit
circuit.
The following specifications are used in this design:
• VIN = 3.3 V 10 %
• VOUT = 1.2 V 1 %
• FSW = 1 MHz
• Load = 3 A maximum
S12-0412-Rev. B, 20-Feb-12
Document Number: 63395
14
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiP12107
Vishay Siliconix
www.vishay.com
INDUCTOR SELECTION
In order to determine the inductance, the ripple current must
first be defined. Cost, PCB size, output ripple, and efficiency
are all used in the selection process. Low inductor values
result in smaller size and allow faster transient performance
but create higher ripple current which can reduce efficiency.
Higher inductor values will reduce the ripple current while
compromising the efficiency (higher DCR) and transient
response.
Assuming a peak voltage VPEAK of 1.3 V (100 mV rise upon
load release), and a 3 A load release, the required
capacitance is shown by the next equation.
1 μH x (3 A + 0.5 x (81 A))2
COUTmin.
=
= 46.37 μF
(1.3 V)2 - (1.2 V)2
If the load release is relatively slow, the output capacitance
can be reduced. Using MLCC ceramic capacitors we will
use 3 x 22 μF or 66 μF as the total output capacitance.
The ripple current will also set the boundary for power-save
operation. The switcher will typically enter power-save
mode when the load current decreases to 1/2 of the ripple
current. For example, if ripple current is 1 A then power-save
operation will typically start at loads approaching 0.5 A.
Alternatively, if ripple current is set at 40 % of maximum load
current, then power-save will start for loads less than
~ 20 % of maximum current.
STABILITY CONSIDERATIONS
Using the output capacitance as a starting point for
compensation values. Then, taking Bode plots and transient
response measurements we can fine tune the compensation
values.
Setting the ripple current 20 % to 50 % of the maximum load
current provides an optimal trade-off of the areas mentioned
above.
Setting the crossover frequency to 1/5 of the switching
frequency:
F0 = Fsw/5 = 1 MHz/5 = 200 kHz
Setting the compensation zero at 1/5 to 1/10 the crossover
frequency for the phase boost:
The equation for determining inductance is shown next.
Example
In this example, the inductor ripple current is set equal to
30 % of the maximum load current. Thus ripple current will
be 30 % x 3 A or 0.9 A. To find the minimum inductance
needed, use the VIN and TON values that correspond to
VINmax.
F0
5
1
FZ
=
=
2π x RC x CC
Setting CC = 1 nF and solve for RC
5
5
TON
RC
=
=
= 4K
----------
L = VIN - VOUT x
2π x CC x F0
2π x 1 nF x 200K
i
Plugging numbers into the above equation we get
330 x 10-9
SWITCHING FREQUENCY VARIATIONS
s
--------------------------------
L = 3.63 V - 1.2 V x
= 0.891 μH
The switching frequency variation in COT can be mainly
attributed to the increase in conduction losses as the load
increases. The on time is “ideally constant” so the controller
must account for losses by reducing the off time which
increases the overall duty cycle. Hence the FSW will tend to
increase with load.
0.9 A
A slightly larger value of 1 μH is selected which is a standard
value. This will decrease the maximum ripple current by
10 %. Note that the inductor must be rated for the maximum
DC load current plus 1/2 of the ripple current. The actual
ripple current using the chosen 1 μH inductor comes out to
be.
In power save mode (PSM) the IC will run in pulse skip mode
at light loads. As the load increases the FSW will increase
until it reaches the nominal set FSW. This transition occurs
approximately when the load reaches to 20 % of the full load
current.
330 ns
1 μH
-----------------
i = 3.63 V - 1.2 V x
= 0.8 A
Output Capacitance Calculation
The output capacitance is usually chosen to meet transient
requirements. A worst-case load release, from maximum
load to no load at the exact moment when inductor current
is at the peak, determines the required capacitance. If the
load release is instantaneous (load changes from maximum
to zero in < 1/FSW μs), the output capacitor must absorb all
the inductor’s stored energy. This will approximately cause
a peak voltage on the capacitor according to the following
equation.
2
1
2
--
L x IOUT
+
x I
RIPPLEmax.
-------------------------------------------------------------------------
COUTmin.
=
Vpeak2 - VOUT2
S12-0412-Rev. B, 20-Feb-12
Document Number: 63395
15
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiP12107
Vishay Siliconix
www.vishay.com
Fig. 8 - Reference Board Schematic
16
S12-0412-Rev. B, 20-Feb-12
Document Number: 63395
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiP12107
Vishay Siliconix
www.vishay.com
BILL OF MATERIALS
ITEM QTY.
REFERENCE
PART
22 μF
DNP
220 μF
0.1 μF
22 μF
DNP
10 μF
0.1 μF
68 pF
0.1 μF
68 pF
2.2 μF
DNP
1 nF
VOLTAGE
16 V
50 V
25 V
50 V
6.3 V
6.3 V
16 V
50 V
50 V
50 V
50 V
10 V
50 V
50 V
-
PCB FOOTPRINT
SM/C_1210
SM/C_0603
594D-R TYPE
SM/C_0603
SM/C_1210
SM/C_1210
SM/C_1206
SM/C_0402
SM/C_0603
SM/C_0402
SM/C_0402
SM/C_0603
SM/C_0402
SM/C_0402
IHLP2525
PART NUMBER
MANUFACTURER
1
4
1
2
3
3
3
2
1
1
1
1
1
1
1
1
1
1
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C1, C2, C3, C4
GRM32ER71C226ME18L
-
Murata
-
2
C5
3
C7, C13
594D227X0016R2T
VJ0603Y104KXACW1BC
GCM32ER70J476KE19L
-
Vishay
Vishay
Murata
-
4
C8, C19, C21
5
C9, C10, C11
6
C12, C29, C30
7
C14, C20
C15
C16
C17
C18
C23
C26
C27
L1
C1206C106K4RACTU
VJ0603Y104KXACW1BC
VJ0402A680JNAAJ
VJ0402Y104KXACW1BC
VJ0402A680JNAAJ
GRM188R71A225KE15D
-
Taiyo Yuden
Vishay
Vishay
Vishay
Vishay
Murata
-
8
9
10
11
12
13
14
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
VJ0402Y102KXACW1BC
IHLP2525DZER1R0M01
Si4812BDY
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
Vishay
-
1μH
Q1
-
30 V
200 V
50 V
50 V
50 V
50 V
-
SO-8
R1
3R01
100K
100
C_2512
CRCW25123R01FKTA
CRCW0603100KFKEA
TNPW0402100RBEED
CRCW06035K11FKEA
CRCW04020000FKTA
CRCW06035K11FKEA
TNPW0402100RBEED
CRCW060310K0FKEA
CRCW0603100KFKEA
CRCW06032K00FKEA
-
R2, R3, R5, R9
R6
SM/C_0603
SM/C_0402
SM/C_0603
SM/C_0402
SM/C_0603
SM/C_0603
SM/C_0603
SM/C_0603
SM/C_0603
SM/C_0805
SM/C_0603
SM/C_0402
QFN3X3_16 L
PROBE PIN
PROBE PIN
Power connector
Power connector
PROBE PIN
Power connector
Power connector
Control PIN
Control PIN
Probe PIN
R7
5K11
0R
R8
R10
R11
R12
R14
R42
R43
R44
R45
U1
5K11
100
50 V
50 V
50 V
50 V
-
Vishay
Vishay
Vishay
Vishay
10K
100K
2K
DNP
0R
50 V
50 V
-
CRCW06030000Z0EA
CRCW04020000FKTA
SiP12107
Vishay
Vishay
0R
-
Vishay
J1
VIN
PK007-015
Lecroy
J2
LX
PK007-015
Lecroy
J3
VIN
575-6
Keystone
Keystone
Lecroy
J4
VOUT
VOUT
VIN_GND
VO_GND
EN
575-6
J5
PK007-015
J6
575-6
Keystone
Keystone
Keystone
Keystone
Keystone
Keystone
Lecroy
J7
575-6
J8
1573-3
J9
MODE
PGD
Step_I_Sense
LDT
1573-3
J10
J11
J12
J13
J14
1573-3
Probe PIN
1573-3
SMA test connector
Test point
PK007-015
CH2
1573-3
Keystone
Keystone
CH1
Test point
1573-3
S12-0412-Rev. B, 20-Feb-12
Document Number: 63395
17
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
SiP12107
Vishay Siliconix
www.vishay.com
PCB LAYOUT OF REFERENCE BOARD
Fig. 9 - Top Layer
Fig. 11 - Bottom Layer
Fig. 10 - Inner Layer1
Fig. 12 - Inner Layer2
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?63395.
S12-0412-Rev. B, 20-Feb-12
Document Number: 63395
18
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Legal Disclaimer Notice
www.vishay.com
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
disclosure relating to any product.
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the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all
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Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical
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product with the properties described in the product specification is suitable for use in a particular application. Parameters
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All
operating parameters, including typical parameters, must be validated for each customer application by the customer’s
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including but not limited to the warranty expressed therein.
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining
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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
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Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
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Revision: 02-Oct-12
Document Number: 91000
1
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