AN501 [VISHAY]
The DG535/536 Wideband Multiplexers Suit a Wide Variety of Applications; 该DG535 / 536宽带多路复用器套装适用于各种应用
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| 厂家： | 
VISHAY |
| 描述： | The DG535/536 Wideband Multiplexers Suit a Wide Variety of Applications |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AN501
Vishay Siliconix
The DG535/536 Wideband Multiplexers
Suit a Wide Variety of Applications
Introduction
S PCM routing networks
S ATE systems
S High-channel-density multiplexing or demultiplexing systems
S High-speed multiplexing systems
Analog switch IC’s traditionally have found limited use in
applications involving high-frequency analog or digital signals.
Degradation of switch performance and intolerable signal
cross-talk between channels has undoubtedly forced many
designers to use bulky electromechanical switches or costly
discrete designs.
S Low-level signal multiplexing
At best, analog switch ICs configured in L or T arrangement could
be adopted. However, increased board space and layout
complexity became major problems in configuring systems with
high channel density.
Product Description
A functional block diagram of the DG535/536 is shown in
Figure 1 and the switch configuration is shown in Figure 2. The
device is fabricated using self-isolated, silicon-gate D/CMOS
technology. This process enables the logic interface and driver
circuitry, the gating and latching stages, and the switching
elements to be combined in a monolithic structure.
The DG535/536 are compact 16-channel, single-ended
multiplexer ICs, primarily designed as a cost-effective solution to
video and wideband switching problems. Other applications that
benefit from the devices’ superior performance characteristics
are:
Ease of design for large switching matrices and interface with
microprocessors is accomplished with comprehensive logic
gating and latching functions available on the chip.
S Digital switching
S Audio Switching
V+
GND
S
1
SW
SW
3
1
S
1
S
2
SW
2
D
S
8
S
9
SW
4
S
S
‘T’ Switch
Configuration
8
D
9
SW
5
S
16
S
15
S
16
DIS
Decoders/Drivers
Gating
Logic
Latches
1st Level
2nd Level
A
3
A
2
A A
1 0
ST
CS
EN CS
FIGURE 1. DG535/536 Functional Block Diagram
FIGURE 2. Switch Configuration
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The DG536 is housed in a small, 44-pin J-lead package, thus
minimizing board size requirements. The DG535 is packaged in
a 28-pin DIP. Chip select pins (CS and CS) permit easy stacking
of devices for multi-channel multiplexing systems (see
Applications Section, Figure 19).
Two-Level Switching
The two-level switching system of the DG535/536 (SW4 and
SW5) works out of phase, effectively isolating half of the switch
outputs from the drain (output) of the multiplexer. These series
switches serve several functions:
They provide an extra stage of off-isolation.
An additional feature, a DIS pin, is an open drain terminal with the
source tied to the device substrate. The DIS terminal represents
a high impedance to the substrate (normally ground) when the
DG535/536 is disabled and a low impedance to ground when the
DG535/536 is enabled. This output can be used to indicate which
device in a large matrix has been enabled (see Figure 13), or it
can be used to switch off circuitry following the multiplexer stages.
They reduce the drain output capacitance significantly and
increase the multiplexing transition speed.
They reduce the off-leakage current, which reduces the offset
voltage that develops from the total off-leakage current flowing
through the load resistance and/or switch on-resistance. This
enables lower analog signal levels to be handled accurately.
Silicon Gate
Minimizing Parasitic Effects
Polysilicon is used as the transistor gate material for the
DG535/536, as opposed to more conventional metal-gate
designs. This technology minimizes the charge coupling of the
control-logic signals to the switch output due to the self-aligning
properties of the process. Metal-gate technology relies on
photolithographically aligning the gate metal with the channel
diffusions, resulting in greater overlap tolerances.
The insertion loss and bandwidth of the switch are improved with
DMOS transistors that offer a low on-resistance and low intrinsic
capacitance (see Vishay Siliconix SD5000 data sheet). On the
DG536 channel-to-channel crosstalk is minimized by physically
separating each input channel with a GND pin which extends to
the device substrate. This, in conjunction with careful PC board
layout (see Figure 6), can yield channel-to-channel crosstalk
figures better than –92 dB at 5 MHz.
As shown in Figure 3, a PN junction exists between the p-type
substrate and the n-type channel diffusions. This junction should
not become forward biased by the analog signal going more
negative than the substrate potential (normally ground).
Further ac performance benefits are obtained through the
n-channel DMOS transistor T configurations (Figure 2). This
maximizes the off-isolation, since SW2 provides a shunt path to
ground for any signals fed through the parasitic capacitance
associated with SW1. SW3 (working in phase with SW1) provides
an extra stage of off-isolation and prevents the shunt switch
(SW2) from affecting consecutive channels.
Device damage could result from the current flow through the
forward biased substrate-channel junction, exceeding the
aluminum current handling capacity (i.e. 20 mA). Analog signal dc
biasing or offsetting the device power supplies can prevent this
problem. These methods are discussed in the applications
section of this paper (Figure 7 and Figure 8).
Source/Body
Gate
Gate
Drain
— Aluminum
n+
n+
— Gate Oxide
— Polysilicon
— Field Oxide
Source
Drain
p+
Symbol
p-Substrate
FIGURE 3. Cross-Section of an N-Channel, Silicon-Gate DMOS Transistor
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DG535/536 DC Characteristics
On-Resistance
Power Supply Current Consumption
Until now, most available video multiplexers or digital crosspoint
switches relied on high-level supply currents for operation. The
DG535/536 requires a total supply current of only 5 mA, typical.
This feature makes the DG535/536 ideal for systems with high
channel density, such as 32-channel crosspoint matrices used in
video mixing consoles or as ECL digital crosspoint replacements
in large data transmission systems.
On-resistance must be low to ensure low insertion loss, especially
when the switch drives low load resistances. As shown in
Figure 4, the on-resistance remains low and fairly constant over
the usable analog signal range. This makes the DG535/536
useful for audio applications that require low harmonic distortion.
The total supply current for a 32-channel crosspoint system using
the DG535/536 is approximately 320 mA, much lower than other
video multiplexers.
r
vs. V and Temperature
D
DS(on)
400
360
320
V+ = +15 V
GND = 0 V
DG536 AC Characteristics
280
240
200
160
125_C
(Refer to the DG535 data sheet for the 28-pin DIP performance.)
Bandwidth
120
80
40
0
25_C
The “on” frequency response is expressed as the frequency
at which the insertion loss (at dc) increases by 3 dB. The
measured bandwidth of the DG536 is greater than 300 MHz.
–55_C
0
2
4
6
8
10
Crosstalk
V
D
(V)
Crosstalk is the amount of unwanted signal apparent at a
particular node due to the parasitic capacitance of the device. As
the most important parameter for many applications, crosstalk is
specified in a number of ways.
FIGURE 4. On-Resistance vs. Analog Signal Characteristics
Nominal r
= 50 W
DS(on)
V
OUT
1. Single-channel crosstalk is the ratio of the signal seen at
the drain (output) to the signal applied to a single off-channel
input. This is expressed by
Dr
DS(on)
v 2 W
R
IN
600 W
R
L
600 W
VOUT
V
IN
1 V
p-p
XTALK(SC)(dB) + 20 log10
VIN
Most conventional multiplexers specify this parameter on the
data sheet as off-isolation. This value for the DG536 is more
than twice as good as other 16-channel analog multiplexer
ICs, proving the effectiveness of the T switch.
V
OUT
Insertion Loss + 20 LOG
10
V
IN
FIGURE 5. 600-W Audio System
2. All hostile crosstalk is the ratio of the signal measured at
the drain to the signal applied simultaneously to all
15 channels (i.e., with one channel on).
In a 600-W audio system, such as the one represented in
Figure 5, the percentage of on-resistance change relative to the
load resistance is only 0.33%. The insertion loss due to the switch
on-resistance is 0.7dB.
3. Chip-disabled crosstalk is the drain output to signal input
ratio. The input signal is applied to all 16 off channels simulta-
neously.
4. Adjacent input crosstalk is the ratio of the signal applied
to a source (input) to the signal measured at any adjacent
source. A low adjacent input crosstalk is required for video
applications to avoid ghosting effects that may appear on
video monitors or TV screens.
Leakage Current
The DG535/536 features low off and on leakage currents,
reducing switching errors.
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TABLE 1. CAPACITANCE VALUE FOR 16ĆCHANNEL MULTIPLEXERS
Parameter
DG526
DG506A
DG508A
CD4051/2/3
DG536
CS
(pF)
(pF)
10
65
6
5
10
60
2
8
(off)
(off)
CD
46
26
Note: These are typical values taken from data sheets
Switching Time
S Coaxial interconnect of leads, plugs, and sockets.
S Sockets should be avoided
The DG535/536 switching time enables use of the device at high
multiplexing rates. The low transition times (tON = 300 ns
maximum and tOFF = 150 ns maximum) make it ideal for fast
multi-channel analog or digital multiplexing.
True break-before-make (BBM) switching action is guaranteed by
design. This prevents shorting (crosstalk) of time adjacent input
channels during transition.
Capacitance
Capacitance determines the loading effect of the multiplexer on
signal sources and affects transition times, as well as system
bandwidth.
1. Off-state input capacitance gives the loading of the
device (in the off-state) to a signal source. With a typical value
of2pF,thisallowsefficientparallelingofmanydevicechannels
in multi-channel crosspoint matrices with negligible loading
effects.
SMB-PCB Mounting sockets
2. On-state input capacitance also determines the loading
effectsofthedeviceon-signalsourcesandlimitsthenumberof
parallelonchannelsallowedinalargematrix. Inlargematrixes
buffering of the input signals is recommended.
Top Side (Ground Plane)
PCB
Bottom Side
DG536 Mounted on Underside of PCB
3. Off-state output capacitance affects the transition speed
of the multiplexer. The output capacitance must be charged
and discharged in turning on and off a device; thus, a low value
of capacitance enables rapid transition times. Table 1 shows a
comparison of DG536 capacitance to comparable 16-channel
multiplexers.
FIGURE 6. Circuit Board Layout for Optimal
Performance (DG536)
Applications
Circuit Board Layout
Many applications for the DG535/536 will be in video related
systems. Some examples of circuit configurations are included in
this section.
To optimize the high-frequency characteristics of the DG536, care
must be taken in circuit board layout and interconnections.
Parasitic stray capacitances caused by poor layout could
degrade performance significantly. As shown in Figure 6, use of
guard planes and traces between signal paths is a good layout
practice. Other layout considerations include:
Video
The DG536 was designed primarily for handling broadcast quality
video signals. Optimum performance is achieved with a bias
between +2.5 V and +3 V. Differential phase linearity is best at this
bias level.
S Short signal paths
S Sufficient power supply decoupling
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A general-purpose 16-channel wideband multiplexer is shown in
Figure 7. Dc biasing is achieved with the divider network R1 and
R2. A wideband op-amp (CLC410) is configured to give an
inverting unity gain, while removing the +3 V dc by setting the
voltage on the non-inverting input to +1.5 V dc. The use of trimpot
R7 and precision resistors allows accurate elimination of any dc
bias. This arrangement results in faster multiplexing rates than
capacitive decoupling while providing black-level clamping,
impedance matching for 75 W loads, and greater drive for
transmission stages, with no major compromise on signal quality
(distortion, frequency response, etc.)
in Figure 8, could be used in a security system or in a remote
industrial monitoring system. The DG535/536 positive supply and
ground pins (at –3 V) should be heavily decoupled to the video
camera ground connections.
The switching threshold of the device at a supply voltage of +15 V
is approximately between +6 V and +8.5 V above the substrate
potential (Figure 9). Since the substrate is held at –3 V, the
effective switching threshold referenced to ground is between
+3 V and +5.5 V. Thus, the device can still be controlled from
CMOS logic signals (provided that the logic 0 (VAL) is less than
3 V and logic 1 (VAH) is greater than +5.5 V).
Alternatively, the device supplies can be offset to eliminate the
need for 16 separate bias circuits. Such an arrangement, shown
+15 V
R
470 W
5
+
R
1
39 kW
R
3
0.1 mF
470 W
Video
Output
CS
V+
Video
Input
S
1
–
R
4
75 W
D
18 kW
S
2
CLC410
+
+15 V
R
2
DG535/536
10 kW
CS
S
16
R
6
1.2 kW
All GNDs
EN ST
R (1 kW l )
7 in
A , A ,
A , A
2
0
1
3
Address Bus
Control Logic
FIGURE 7. General-Purpose 16-Channel Wideband Multiplexer
+12 V
1
2
EN CS ST V+
S
1
S
2
S
3
S
4
75 W
3
4
Video
Monitor
D
CLC111
1 kW
DG535/536
Video Cameras
CS
All
–3 V
S
16
GND
A , A , A , A
3
pins
0
1
2
16
Address
Logic
FIGURE 8. A Closed-Circuit Monitoring System
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V+
Logic Input Switching Threshold
vs. Supply Voltage (V+)
+5 V
13
11
9
GND = 0 V
T
= 25_C
V
CC
V
DD
A
V+
DG535/536
TTL 4-Bit
Binary Address
ST
EN
MC14504
Bus
7
A
3
A
2
A
1
A
0
5
V–
3
8
10
12
14
16
18
V+ – Positive Supply Voltage (V)
FIGURE 9. Logic Input Switching Threshold
FIGURE 10. Using the MC14504 for Address Logic
vs. Supply Voltage
Level Shifting
In applications involving reduced supply voltages and offset
conditions, the input switching threshold (VT) may be reduced
below the CMOS logic “0”. This may cause the address inputs
to appear permanently as logic “1” regardless of the control
logic states. Therefore, control logic level shifting may be
needed.
the address inputs (A0 to A3) and applying the appropriate logic
level to output select simultaneously.
The circuit in Figure 11 also illustrates how the chip select
inputs can be used. As shown in Figure 12, a 32-channel
single-ended multiplexer can be configured without external
chip select circuits. This circuit makes use of the CS and CS
inputs which allow device selection from a single control line.
TTL to CMOS level shifting can be easily accomplished using
inexpensive CMOS level shifters such as the MC14504 or
CD40109.
The basic circuit shown in Figure 11 can be extended and
elaborated to give a 16 x 16 matrix for video crosspoint
applicationssuchascentralroutersusedinvideostudios. This
circuit, shown in Figure 13, allows source (or video input) to be
connected to any video output (or any number of outputs). The
strobe input (ST) on each device is used to latch the
appropriate address into that particular device. By strobing the
requiredaddress into each device sequentially, any crosspoint
connection can be made.
Crosspoint Switching
Manyanaloganddigitalsystems, suchasacentralrouterused
in a video studio console (Figure 8), require crosspoint
switching functions. In this application, many channels route
signalstomanydifferentoutputs. DuetoitssmalloutlinePLCC
package and low power consumption, the DG536 leads itself
easily to multi-channel crosspoint functions.
The DG535/536 makes an excellent digital switch due to its
low channel-to-channel crosstalk, high off-isolation, and wide
bandwidthspecifications. Indigitaldatatransmissionsystems,
the DG535/536 can easily handle data rates in excess of
100 Mb/s.
Figure 11 illustrates how the DIS (disable) pin can be used to
indicate which output is selected. When logic 1 is applied to
output select, device 1 is enabled and device 2 is disabled.
With device 1 enabled, the DIS pin is connected to signal
ground, thus turning LED 1 on. With device 2 disabled (due to
CSbeing1), itsDISpinrepresentsahighimpedancetoground
and LED 2 is off.
The circuit shown in Figure 13 can be used as a digital
cross-point to replace expensive, power consuming ECL
crosspoint ICs. Besides handling raw digital data, the
DG535/536 can also be used for other forms of data
transmission, such as FSK and PCM systems.
Any one of sixteen inputs can be connected to either output. This
is achieved by applying the appropriate CMOS logic address to
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+5 V
4
Si584 Buffers
LED
LED
2
1
S
1
V+ EN ST
R
1
R
2
OUTPUT
D
1
DG535/
16 Signal
Inputs
DG536 #1
DIS
CS
CS
S
16
to A
A
0
GND
3
S
1
V+ EN CS
ST
OUTPUT
D
2
DG535/
DG536 #2
DIS
CS
OUTPUT SELECT
“1” = 0/P Selected
S
A
16
1
GND
to A
0
3
“0” = 0/P Selected
2
Address Logic
FIGURE 11. The DG535/536 as a 16 2 Matrix Switch
+15 V
Si584s
CH
1
S
S
S
STV–
GNDS
1
2
3
S
1
DG535/
DG536
D
D
1
Video
Input
Channels
75 W
1
Video
Input
DG535/
DG536
ST
D
S
16
Channels
CH
16
EN
to A
CS
A
0
3
75 W
DG535/
DG536
2
Video
Outputs
Enable
Device Select
2
ST
Video
Output
Address Bus
+15 V
Video
Output
Select
CH
17
ST CSV+
EN
CS
1
S
D
16
DG535/
DG536
75 W
Video
Input
Channels
DG535/
DG536
16
ST
D
Address Bus
(Video Input Select)
CH
22
GNDS
to A
S
16
A
0
3
75 W
FIGURE 12. 32-Channel Multiplexer
FIGURE 13. 16 16 Video Crosspoint Circuit
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FSK
distribution frame. Similarly, code converters are required to
reconvert the binary PCM into ternary PCM for transmission.
Frequency shift keying (FSK), commonly used in data
transmission networks, relies on representing the digital code
with frequency sine wave bursts. An FSK multiplexing system
block diagram is shown in Figure 14. Each digital level has a
specific signal frequency. The DG535/536 can be used to
Unlike digital switches which require specific digital signals,
using the DG535/536 in the distribution frame (Figure 17)
eliminates the need for code conversion and meticulous
regeneration because it can handle analog signals.
multiplex 16 different digital channels into
a single
transmission line or into a transmitter. Similarly, a DG535/536
may be used to demultiplex the data at the receiving end.
Since the device canmanipulatehigherfrequencysinewaves,
data can be transmitted at a higher rate than with a
conventional multiplexer.
Programmable Gain Video Amplifier
The circuit shown in Figure 19 uses the DG536 as a binary
gain select for a video/wideband op-amp (CLC410).
The gain of the Si582 is set by:
PCM
Rf
AV + 1 )
Rg
A more commonly used and faster form of digital data
transmission is known as PCM (pulse coded modulation).
Used in telecommunications systems, PCM converts analog
speech signals into 8-bit digital words for serial transmission.
Thedatatransfer rate used (for 4 kHz bandwidth voice signals)
is up to 274.176 Mbps.
For example, listed below in Table 2 are the results when Rf
= 470 W.
TABLE 2.
The DG535/536 can be used to route PCM signals in main
telephone exchanges, replacing bulky hard-wired distribution
frames. PCM highways can thus be rerouted remotely, under
computer control, rather than manually.
Gains For The Circuit of Figure 19
Logic Input
0000
Rg
Gain (AV)
47 kW
4.7 kW
2.4 kW
1.6 kW
1.0
1.1
1.2
1.3
0001
RZ (returns to zero) PCM data consists of three discrete
(ternary) levels to overcome long periods of zeroes (Figure
13). Digital signals can degrade beyond legibility after only a
few hundred yards of travel down a transmission line.
Therefore, the PCM signals must be regenerated at regular
distances to avoid excessive distortion.
0010
0011
The low on-resistance of the DG535/536 gives good gain
stability, and the resistor tolerances mainly determine the gain
error of the circuit.
Figure 16 shows the architecture of a conventional binary
distribution frame in
a
telephone exchange. Signal
regeneration is applied to handle degradation during
transmission and routing. Code converters are required to
change the ternary PCM into binary PCM for routing within the
The wideband qualities of the CLC410 allows this circuit to be
employed for digital level correction in any video systems
including broadest quality specifications.
FSK Output
FSK
e.g. 1011
Generator
S
S
S
1
2
3
FSK
Generator
Binary
PCM
DG535/
DG536
Output
to Transmission
Line or
Transmitter
Input
a) Analog voice signal converted to digital signal using
8 bits per sample
FSK
Generator
D
Digital
Input
Stage
Channels
Ternary
PCM
S
16
A
0
to A
3
FSK
Generator
b) Digital signal transmitted and clock regenerated
from digital signal to get synchronization
Frequency
Synthesizer
(f )
0
Address
Bus
(f )
1
FIGURE 14. FSK Multiplexing System Block Diagram
FIGURE 15.
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PCM Highway from codecs
within main exchange
Central office or main telephone
exchange
PCM Highway
Remote
Exchange/
Switch
Remote
Exchange/
Switch
Regen
-erator
(1)
Regen
-erator
(2)
Binary
Distribution
Frame
Code
Converter
(2)
Regen
-erator
(3)
Code
Converter
or
or
Digital PBX
or
Concentrator
Digital PBX
or
Concentrator
Couple hundred yards/different floor
FIGURE 16. Binary PCM Routing Network
PCM Highway
PCM Highway from codecs
within main exchange
Central office or main telephone
exchange
Remote
Exchange/
Switch
Remote
Exchange/
Switch
DG535/536
Crosspoint
or
or
Digital PBX or
Concentrator
Digital PBX or
Concentrator
FIGURE 17. DG536 PCM Distribution Frame
Video In
Digital Signal
Processing Board Under Test
+
75 W
DG535/536
75 W
CLC410
–
S
1
S
2
470 W
Video Out
R
f
D
S
1
2
3
4
5
R
A
S
S
S
S
R
B
R
C
R
D
R
E
S
16
A
0
to A
3
Address Bus
D
Micro-
Processor
Data
Logging
S
16
16-Bit Data Bus
R
P
DG536
to A
A
0
3
Logic
Input
Gain Set
FIGURE 19. Programmable Gain Video Amplifier
FIGURE 18. ATE Applications
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ATE
The data latches are activated by the DG535/536 strobe input
(ST). The latch is transparent when ST= logic 1, thus the
device responds to changes of data at the address inputs.
When ST = logic 0, the previous data is latched into the device,
regardless of new data appearing at the address inputs.
AsimplebutaccurateATE system, as shown in Figure 18, can
be designed for testing digital processing boards.
The propagation delay time for each of the 16 digital signal
paths can be tested individually, with negligible errors due to
the very small propagation delay through the DG535/536.
Also, the variation of delay times from channel to channel is
less than 0.25 ns.
The DG535/536 timing arrangements meet the requirements
of popular microprocessors, such as the 8085A, 6800, and
Z80. The 8085A to DG535/536 interface is shown in
Figure 20,andTable3illustratesthetimingcompatibilityofthe
DG535/536 with the 8085A and the faster 8085A-2 devices.
TABLE 3.
Microprocessor Interface
Timing—DG538/536 With Popular Microprocessors
8085A
8085A-2 DG536
On-chip data latches in the DG535/536 simplify interface with
a microprocessor data bus. This eliminates the need for
peripheral memory devices (such as I/O ports or D-type latch
ICs)tomaintainswitchaddressingwhiletheprocessorusesits
data bus for other functions.
Specification
(strobe pulse width)
(data valid to strobe)
(data valid after strobe)
ns/min. ns/min. ns/min.
t
t
t
400
420
100
230
230
60
200
100
50
SW
DW
WD
+15 V
+15 V
5 V
V+ CS
A
0
A
1
A
2
A
3
S
S
1
Data Bus
MC14504
EN
WR
ST
8085A
mP
System
Bus
16
DG535/536
D
D
CS
GNDs
CS
Address
Decoder
Address Bus
FIGURE 20. 8085A to DG535/536 Interface
+15 V
R
1
R
2
R
3
R
4
R
5
V+ CS
A
0
A
1
A
2
A
3
S
1
Data Bus
EN
+15 V
CD7407
DG535/536
S
16
R
6
F2 = DBE
6800 mP
System
Bus
ST
GNDs
D
D
CS
Control Bus
Address Bus
R/W
R
1
to R = 100 kW
6
CS
Address
Decoder
FIGURE 21. 6800 to DG535/536 Interface
Document Number: 70608
03-Aug-99
www.vishay.com S FaxBack 408-970-5600
6-10
AN501
Vishay Siliconix
Figure 21 shows the complete 6800 to DG536 interface
circuit. In order to have a data valid signal, it is necessary to
nand the R /W/CS gate output with the F2 clock (usually
connected to the DBE pin). This makes the interface circuit
functionally compatible with the 8085A interface shown in
Figure 20.
moelectric offset voltage. For the DG535/536, the thermal
EMFs produced on chip are small since the device exhibits a
low power consumption (75 mW), producing a low temperature
on the die.
2. Leakage current offset is caused by leakage current flow-
ing through the rDS of an on-switch and/or the load resis-
tance.The offset voltage developed due to leakage current is
negligible since the device has very low leakage currents (a
benefitincurred by the two-level system) coupled with very low
on-resistance.
Note that open collector gates and buffers could be used to
level shift the TTL logic levels from the microprocessor to the
CMOS levels required by the DG535/536 logic inputs.
To achieve the correct ST signal in a Z80 processor system,
theWRandMREQsignalsmustbegatedwiththestandardCS
signal, as shown in Figure 22.
For example:
V (offset) = ID(on) x rDS(on)
= "100 pA (typical @ 25_C) 55 W (typical)
= "5.5 nV (typically)
Low Analog Signal Switching/Multiplexing
The circuit shown in Figure 23 can be used to remotely
monitor up to 16 different thermocouples with high accuracy.
The output of the thermocouples is in the form of a small dc
voltage, on the order of millivolts, with typical voltage changes
on the order of tens of microvolts per _C. Thus, voltage offset
developed by the switching devices can frequently limit
system accuracy.
The DG535/536 has several uses in handling low-level analog
signals (such as in medical equipment or ultrasound
transducer multiplexing) because the device exhibits
inherently low noise and offset voltages. Two factors affect
offset voltage:
1. Thermoelectric offset voltage is produced by the incidental
thermocouples that exist within the integrated circuit. There
are many intermetallic junctions within an IC. These junctions
act as an individual thermocouple and has an identical
reversed counterpart. That is, from source to drain, we have
gold-aluminum/aluminum-silicon and silicon-aluminum/ alumi-
num-gold. Therefore, if the temperature surrounding each
junction is constant and equal, the thermal EMFs cancel each
other, giving a zero net offset voltage. Since a thermal gradient
always exists across the chip, then there is always a net ther-
Using the differential multiplexing technique shown in
Figure 23, high resolution can be achieved since the thermal
EMFs produced by each DG535/536 are canceled as
common mode voltages at the instrumentation amplifier
inputs. To minimize pick-up and noise effects, the same PC
board layout rules apply for this type of circuit. Best accuracy
is achieved by ensuring that the multiplexers are kept close
together in a thermally stable environment.
+15 V
DG535/
DG536
Differential
Instrumentation
Amplifier
S
S
1
2
D
R
1
R
2
R
3
R
4
R
5
Thermo–
Couples
(X 16)
V+ CS
A
0
A
1
A
2
A
3
+
–
S
1
S
16
Data Bus
A
to A
3
0
EN
+15 V
DG535/
DG536
CD7407
S
16
R
6
DG535/
DG536
WR
Z80 mP
System
Bus
S
S
D
ST
GNDs
D
1
2
MREQ
D
CS
Address
Bus
S
16
CS
Address
Decoder
A
to A
0
3
Channel
Select
FIGURE 22. Z80 to DG536 Interface
FIGURE 23. Thermocouple Multiplexing System
Document Number: 70608
03-Aug-99
www.vishay.com S FaxBack 408-970-5600
6-11
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