PI3749 [VICOR]
16V to 34VIN, 12V to 28VOUT, 240W Cool-Power ZVS Buck-Boost;
| 型号： | PI3749 |
| 厂家： | 
VICOR CORPORATION |
| 描述： | 16V to 34VIN, 12V to 28VOUT, 240W Cool-Power ZVS Buck-Boost |
| 文件： | 总27页 (文件大小：827K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Cool-Power®
ZVS Switching Regulators
PI3749-x0
16V to 34VIN, 12V to 28VOUT, 240W Cool-Power ZVS Buck-Boost
Product Description
Features & Benefits
• Up to 98.5% efficiency at 800kHz FSW
The PI3749-x0 is high efficiency, wide range DC-DC ZVS
Buck-Boost regulator. This high density System-in-Package (SiP)
integrates controller, power switches, and support components.
The integration of a high performance Zero-Voltage Switching
(ZVS) topology, within the PI3749-x0, increases point of load
performance providing best in class power efficiency. The
PI3749-x0 requires an external inductor, resistive feedback divider
and minimal capacitors to form a complete DC-DC switching
mode buck-boost regulator.
• Up to 240W of continuous output power
(for specific conditions)
• Fast transient response
• Parallel capable with single wire current sharing
• External frequency synchronization / interleaving
• High Side Current Sense Amplifier
• General Purpose Amplifier
The ZVS architecture also enables high frequency operation while
minimizing switching losses and maximizing efficiency. The high
switching frequency operation reduces the size of the external
filtering components, improves power density, and enables very
fast dynamic response to line and load transients.
• Input Over/Undervoltage Lockout (OVLO/UVLO)
• Output Overvoltage Protection (OVP)
• Overtemperature Protection (OTP)
• Fast and slow current limits
• -40°C to 115°C operating range (TJ)
• Excellent light load efficiency
• Optional I2C™ * functionality & programmability:
■■VOUT margining
■■Fault reporting
■■Enable and SYNCI pin polarity
Applications
• Computing, Communications, Industrial
• Variable output step up/down voltage regulation
Package Information
• 10mm x 14mm x 2.56mm LGA SiP
Typical Application
L1
99
98
97
96
95
94
93
92
91
5
VIN
VIN
VS1
VS2
VOUT
VOUT
4.5
4
CIN
COUT
PGND
ISP
PGND
3.5
3
ISN
PI3749-00
VDR
IMON
VSN
2.5
2
PGD
EN
R1
R2
VSP
SYNCO
VDIFF
EAIN
EAO
1.5
1
SYNCI
TRK
15
20
25
30
35
COMP
SGND
VIN (V)
Efficiency
Power Dissipation
* I2C™ is a trademark of NXP semiconductor
Cool-Power® ZVS Switching Regulators
Page 1 of 27
Rev 2.1
09/2017
PI3749-x0
Contents
Order Information
3
3
Applications Information
Input / Output Range Limitation
Output Voltage Trim
Soft-Start Adjustment and Tracking
Inductor Pairing
17
17
17
17
17
17
18
19
19
19
21
21
22
22
Absolute Maximum Ratings
Pin Description
4
Package Pin-Out
5
Large Pin Blocks
5
Storage and Handling Information
Block Diagram
6
Thermal De-rating
6
Filter Considerations
Parallel Operation
Electrical Characteristics
Performance Characteristics
Efficiency & Power Loss
Safe Operating Area
7
10
12
12
13
14
15
15
15
15
15
15
15
15
15
15
16
16
16
16
Synchronization
Interleaving
I2C Addressing
Thermal De-Rating
I2C Command Structure
I2C Parameter Readback
Fault Monitoring
MTBF
Functional Description
Enable
I2C Volatile Addresses for Parameter Programming
MRGN: Margin Control
22
23
24
25
26
27
Switching Frequency Synchronization
Soft-Start and Tracking
Remote Sensing Differential Amplifier
Power Good
Package Drawings
Receiving PCB Pattern Design Recommendations
Revision History
Output Current Limit Protection
Input Undervoltage Lockout
Input Overvoltage Lockout
Output Overvoltage Protection
Overtemperature Protection
Pulse Skip Mode (PSM)
Variable Frequency Operation
I2C Interface Operation
Product Warranty
Cool-Power® ZVS Switching Regulators
Page 2 of 27
Rev 2.1
09/2017
PI3749-x0
Order Information
Part Number
Description
Package
Transport Media
MFG
PI3749-00-LGIZ
16VIN to 34VIN SiP
10mm x 14mm 108-pin LGA
TRAY
Vicor
16VIN to 34VIN SiP
I2C™ compatible
PI3749-20-LGIZ
10mm x 14mm 108-pin LGA
TRAY
Vicor
Absolute Maximum Ratings
Note: Stresses beyond these limits may cause permanent damage to the device. Operation at these conditions or conditions beyond those listed in the
Electrical Specifications table is not guaranteed. All voltage nodes are referenced to PGND unless otherwise noted.
Location
Name
VIN
VMAX
36V
VMIN
-0.7V
-0.7VDC
-0.7VDC
-0.7VDC
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-0.3V
-1.5V
-1.5V
-0.5V
-0.3V
-0.3V
-0.3V
-2VDC
-2VDC
-0.3V
N/A
ISOURCE
40A [1]
40A [1]
40A [1]
40A [1]
30mA
20mA
5mA
ISINK
40A [1]
18A [1]
18A [1]
40A [1]
200mA
20mA
5mA
1-2,G-K
4-5,G-K
VS1
36V
10-11,G-K
VS2
36V
13-14,G-K
VOUT
VDR
36V
1E
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
5.5V
40V
1D
PGD
1C
SYNCO
SYNCI
ADR1
ADR0
SCL
1B
5mA
5mA
1A
5mA
5mA
2A
5mA
5mA
3A
5mA
5mA
4A
SDA
10mA
5mA
10mA
5mA
5A
EN
6A
TRK
50mA
5mA
50mA
5mA
7A
LGH
8A
COMP
VSN
5mA
5mA
9A
5mA
5mA
10A
VSP
5mA
5mA
11A
VDIFF
EAIN
EAO
5mA
5mA
12A
5mA
5mA
13A
5mA
5mA
14A
IMON
ISN [2]
ISP [2]
SGND
PGND
5mA
5mA
14D
5mA
5mA
14E
40V
5mA
5mA
10-14,B + 10-12,C-E
2-9,B-E + 7-8,F-K
[1] Non-Operating Test Mode Limits.
0.3V
N/A
200mA
18A [1]
200mA
18A [1]
[2] The ISP pin to ISN pin has a maximum differential limit of +5.5VDC and -0.5VDC
.
Cool-Power® ZVS Switching Regulators
Page 3 of 27
Rev 2.1
09/2017
PI3749-x0
Pin Description
Pin Number
1-2,G-K
Pin Name
VIN
Description
Input voltage and sense node for UVLO, OVLO and feed forward compensation.
Input side switching node and ZVS sense node for power switches.
Output side switching node and ZVS sense node for power switches.
4-5,G-K
VS1
10-11,G-K
VS2
Output voltage and sense node for power switches, VOUT feed forward compensation, VOUT_OV
and internal signals.
13-14,G-K
VOUT
VDR
1E
Internal 5.1V supply for gate drivers and internal logic; not for external use.
Fault & Power Good indicator. PGD pulls low when the regulator is not operating or if EAIN is less
than 1.4V.
1D
PGD
Synchronization output. Outputs a high signal for ½ of the programmed switching period at the beginning
of each switching cycle, for synchronization of other regulators.
1C
1B
SYNCO
SYNCI
Synchronization input. When a falling edge synchronization pulse is detected, the PI3749-x0 will delay
the start of the next switching cycle until the next falling edge sync pulse arrives, up to a maximum delay
of two times the programmed switching period. If the next pulse does not arrive within two times the
programmed switching period, the controller will leave sync mode and start a switching cycle automatically.
Connect to SGND when not in use.
1A
2A
3A
4A
ADR1
ADR0
SCL
I2C™ Addressing Pin, for use with PI3749-20 only. No connect for the PI3749-00.
I2C Addressing Pin, for use with PI3749-20 only. No connect for the PI3749-00.
I2C Clock, for use with the PI3749-20 only. Connect to SGND for PI3749-00.
I2C Clock, for use with the PI3749-20 only. Connect to SGND for PI3749-00.
SDA
Regulator Enable control. Asserted high or left floating = regulator enabled;
asserted low, regulator output disabled.
5A
EN
Soft-start and track input. An external capacitor may be connected between TRK pin and SGND to decrease
the rate of output rise during soft-start.
6A
7A
8A
TRK
LGH
For factory use only. Connect to SGND in application.
Error amp compensation dominant pole. Connect a capacitor between COMP and SGND to set the control
loop dominant pole.
COMP
9A
VSN
VSP
General purpose amplifier inverting input
10A
11A
12A
General purpose amplifier non-inverting input
VDIFF
EAIN
General Purpose amplifier output. When unused connect VDIFF to VSN and VSP to SGND.
Error amplifier inverting input and sense for PGD. Connect by resistive divider to the output.
Transconductance error amplifier output, PWM input and external connection for load sharing.
Connect a capacitor between EAO and SGND to set the control loop high frequency pole.
13A
EAO
14A
14D
14E
IMON
ISN
High side current sense amplifier output
High side current sense amplifier negative input
High side current sense amplifier positive input
ISP
Signal ground. Internal logic and analog ground for the regulator. SGND and PGND are star connected
within the regulator package.
10-14,B + 10-12,C-E
2-9,B-E + 7-8,F-K
SGND
PGND
Power ground. VIN, VOUT, VS1 and VS2 power returns. SGND and PGND are star connected within the
regulator package.
Cool-Power® ZVS Switching Regulators
Page 4 of 27
Rev 2.1
09/2017
PI3749-x0
Package Pin-Out
1
2
FT1
FT2
SYNCI
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
SGND
SGND
SGND
SGND
SGND
SYNC0
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
SGND
SGND
SGND
PGD
VDR
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
SGND
SGND
SGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
SGND
SGND
SGND
3
FT3
4
FT4
VS1
VS1
VS1
VS1
VS1
VS1
VS1
VS1
EN
5
TRK
6
LGH
COMP
VSN
VSP
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
7
8
9
VS2
VS2
VS2
VS2
VS2
VS2
VS2
VS2
10
11
12
13
14
VDIFF
EAIN
EAO
IMON
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
ISN
ISP
Large Pin Blocks
Pin Block Name
Group of pins
VIN
K1-2, J1-2, H1-2, G1-2
K4-5, J4-5, H4-5, G4-5
VS1
PGND
VS2
K7-8, J7-8, H7-8, G7-8, F7-8, E2-9, D2-9, C2-9, B2-9
K10-11, J10-11, H10-11, G10-11
VOUT
SGND
K13-14, J13-14, H13-14, G13-14
E10-12, D10-12, C10-12, B10-14
Cool-Power® ZVS Switching Regulators
Page 5 of 27
Rev 2.1
09/2017
PI3749-x0
Storage and Handling Information
Maximum Storage Temperature Range
Maximum Operating Junction Temperature Range
Soldering Temperature for 20 seconds
MSL Rating
-65°C to 150°C
-40°C to 115°C
245°C
3
ESD Rating [3]
500V HBM; 1.0kV CDM
[3] JESD22-C101F, JESD22-A114F.
Block Diagram
VS1 VS2
VIN
VOUT
Q1
Q3
ISN
ISP
IMON
-
+
VS1
Q2
VS2
Q4
VSN
VSP
-
+
LDO
VDIFF
VDR
EAIN
EAO
ZVS Buck Boost Control
and
Digital Parametric Trim
-
+
SYNCO
SYNCI
PGD
VREF
EN
FT1 - FT5
COMP
TRK
CLAMP
0Ω
PGND
*Simplified Block Diagram (I2C pins SCL, SDA, ADRO, ADR1, only active for PI3749-20 device version)
Cool-Power® ZVS Switching Regulators
Page 6 of 27
Rev 2.1
09/2017
PI3749-x0
Electrical Characteristics
Specifications apply for the conditions -40°C < TJ < 115°C, VIN = 16V – 34V, VOUT = 24V, LEXT = 480nH [4], external CIN = COUT = 20µF,
unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Input Specifications
Input Voltage
Input Current
Input Current
VIN_DC
IIN_DC
IIN_DC
16
24
34
V
A
A
IOUT = 4A, VIN = 24V, VOUT = 24V, TCASE = 25°C
IOUT = 7.0A, VIN = 16V, VOUT = 24V, TCASE = 25°C
4.06
10.8
Input Current During Output Short
(Fault Condition Duty Cycle)
[5]
IIN_SHORT
2.5
6.6
mA
Input Quiescent Current
Input Voltage Slew Rate
Internal Input Capacitance
VIN UVLO Threshold Rising
VIN UVLO Hysteresis
IQ_VIN
VIN_SR
Enabled (no load)
mA
V/µs
µF
V
[5]
1
CIN
50V, X7R type 25°C, VOUT = 0V
2
VIN_UVLO_START
VIN_UVLO_HYS
VIN_OVLO_START
VIN_OVLO_HYS
13.0
35.2
14.1
0.7
15.0
39.5
V
VIN OVLO Threshold Rising
VIN OVLO Hysteresis
37.4
0.75
V
V
Output Specifications
VIN = 16V to 34V
12
12
29
34
Output Voltage Range
VOUT_DC
V
A
VIN = 24V to 34V
VIN =24V, VOUT = 24V, TCASE = 25°C [6]
VIN = 16V, VOUT = 24V, TCASE = 25°C [6]
VIN = 24V, VOUT = 12V, TCASE = 25°C [6]
VIN = 24V, VOUT = 24V, TCASE = 25°C [6]
VIN = 16V, VOUT = 24V, TCASE = 25°C [6]
VIN = 24V, VOUT = 12V, TCASE = 25°C [6]
6.8
Output Current Steady State
IOUT_DC
7.2
10
163.2
172.8
120
Output Power Steady State
Output Ripple
POUT_DC
W
IOUT = 4A, VIN = 24V, VOUT = 16V, Tcase = 25°C
COUT_EX = 8 x 10µF, 50V, X7S, 20MHz BW
VOUT_AC
137
mVp-p
Internal Output Capacitance
VOUT Over Voltage Threshold
V Drive
COUT
VOUT_OVT
VDR
50V, X7R type 25°C, VOUT = 0V
1
µF
V
Rising VOUT threshold to detect open loop
Internal drive supply, internal use only
35.2
4.84
37.4
5.10
39.5
5.36
V
Current Sense Amplifier (Dedicated to Monitor Input or Output Current)
ISP Pin Bias Current (Sink)
ISN Pin Bias Current
Common Mode Input Range
IMON Source Current
IMON Sink Current
VOUT = 10V, Flows to SGND
VOUT = 10V
90
150
0
260
µA
µA
V
8
1
36
3
1.8
1.6
10
mA
mA
mV
%
1
2.6
20
4
IMON Output At No Load
Full Scale Error
0
40mV input
-4
[5]
Bandwidth
40
20
20
kHz
µs
Settling Time for Full Scale Step
Gain
1%
AV_CS
V/V
[4] See Inductor Pairing section.
[5] Assured to meet performance specification by design, test correlation, characterization, and/or statistical process control.
[6] Output current capability varies with input & output voltage. See performance curves in Figures 15 – 17.
Cool-Power® ZVS Switching Regulators
Page 7 of 27
Rev 2.1
09/2017
PI3749-x0
Electrical Characteristics (Cont.)
Specifications apply for the conditions -40°C < TJ < 115°C, VIN = 16V – 34V, VOUT = 24V, LEXT = 480nH[4], external CIN = COUT = 20µF,
unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
General Purpose Amplifier
[5]
[5]
Open Loop Gain
96
5
120
7
140
dB
MHz
mV
V
Small Signal Gain-Bandwidth
Offset
12
-1
0.2
1
2.5
Common Mode Input Range
Differential Mode Input Range
Maximum Output Voltage
Minimum Output Voltage
-0.1
2
V
IDIFF = -1mA
No Load
VDR - 0.2V
20
V
mV
Capacitive Load
for Stable Operation
[5]
0
100
pF
Slew Rate
10
V/µs
mA
Output Current
-1
1
Transconductance Error Amplifier
Reference
VREF
EAIN = EAO
1.667
0
1.7
1.734
VDR
V
V
Input Range
VEAIN
Note VEAIN_OV below
Maximum Output Voltage
Minimum Output Voltage
Transconductance
3.45
4.0
V
0
0.1
V
Factory Set
7.6
7.0
400
400
80
mS
kΩ
µA
µA
dB
Zero Resistor
Factory Set
EAO Output Current Sourcing
EAO Output Current Sinking
Open Loop Gain
VEAO = 50mV, VEAIN = 0V
VEAO = 2V, VEAIN = 5V
ROUT > 1MΩ [5]
70
Control and Protection
Switching Frequency
FSW
FSW
VIN = VOUT = 24V, IOUT = 2A
VIN = 16V, VOUT = 12V, IOUT = 7A
VEAO to SGND
800
480
0.6
kHz
kHz
V
Switching Frequency
VEAO Pulse Skip Threshold
Control Node Range
VEAO_PST
VRAMP
VEAO_OL
TOL
0
3.3
3.4
V
VEAO Overload Threshold
Overload Timeout
VEAO to SGND
3.2
V
VEAO > VEAO_OL
10µs time constant
1
ms
A
VOUT Slow Current Limit
VOUT_SCL
VEAIN_OV
TOTP
18
VEAIN Output Overvoltage Threshold
Overtemperature Fault Threshold
Overtemperature Restart Hysteresis
VOUT Negative Fault Threshold
[4] See Inductor Pairing section.
VEAIN > VEAIN_OV
2.04
129
30
V
[5]
125
°C
°C
V
[5]
TOPT_HYS
-0.35
-0.25
-0.15
[5] Assured to meet performance specification by design, test correlation, characterization, and/or statistical process control.
[6] Output current capability varies with input & output voltage. See performance curves in Figures 15 – 17.
Cool-Power® ZVS Switching Regulators
Page 8 of 27
Rev 2.1
09/2017
PI3749-x0
Electrical Characteristics (Cont.)
Specifications apply for the conditions -40°C < TJ < 115°C, VIN = 16V - 34V, VOUT = 24V, LEXT = 480nH[4], external CIN = COUT = 20µF,
unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Soft Start and Tracking Function
TRK Active Range
Nominal
0
1.7
70
V
TRK Disable Threshold
TRK Internal Capacitance
Soft Start Charge Current
Soft Start Discharge Current
Soft Start Time
20
40
0.047
50
mV
µF
30
70
µA
mA
ms
VTRK = 0.5V
8.5
tSS
Ext CSS = 0µF
1.6
Enable
Enable High Threshold
Enable Low Threshold
Enable Threshold Hysteresis
Enable Pin Bias Current
Enable Pull-Up Voltage
Fault Restart Delay Time
ENIH
ENIL
0.9
0.7
100
1
1.1
0.9
300
V
V
0.8
200
-50
2.0
30
ENHYS
mV
µA
V
VEN = 0V or VEN = 2V
Floating
tFR_DLY
ms
Digital Signals
SYNCI Threshold Rising
SYNCI Threshold Falling
SYNCO High
VDR = 5.1V
VDR = 5.1V
3.1
2.2
V
V
SYNCOOH
SYNCOOL
PGDILH
VDR - 0.5
VDR
0.5
V
SYNCO Low
ISYNCOUT = 1mA
VPGD = VDR
V
PGD High Leakage
PGD Output Low
10
µA
V
PGDOL
IPGD = 4mA
0.4
PGD EAIN Low Rise
PGD EAIN Low Fall
PGD EAIN Threshold Hysteresis
PGD EAIN High
1.41
1.36
1.45
1.41
35
1.48
1.46
V
V
mV
V
1.94
2.04
2.14
I2C Digital Signals (PI3749-20 only)
I2C™ Address High Threshold
I2C Address Mid Threshold
I2C Address Low Threshold
VADRx-HI
VADRx-MID
VADRx-LOW
3.872
1.452
4.59
V
V
V
3.752
1.072
0.51
10
I2C Address Resistance,
Within Mid Thresholds
I2C Address Resistance,
Outside Mid Thresholds
Resistance to 2.5V, when ADRx pin voltage
within VADRx_MID
RADRx-MID
RADRx-MID
V
V
Resistance to 2.5V, when ADRx pin voltage
outside range of VADRx_MID
200
SCL, SDA In High
VSER_IH
VSER_IL
VSER_OL
ISER_I
2.1
V
V
V
V
SCL, SDA In Low
1.5
0.4
10
SDA Out Low
Sinking up to 3mA
SCL, SDA Pull-Down Current
[4] See Inductor Pairing section.
Weak pull-down current to SGND
[5] Assured to meet performance specification by design, test correlation, characterization, and/or statistical process control.
[6] Output current capability varies with input & output voltage. See performance curves in Figures 15 – 17.
Cool-Power® ZVS Switching Regulators
Page 9 of 27
Rev 2.1
09/2017
PI3749-x0
Performance Characteristics TA = 25°C
100
95
90
85
80
0
1
2
3
4
5
6
7
Output Current (A)
16VIN
24VIN
34VIN
Figure 1 — 24VOUT Efficiency
Figure 4 — 34VIN to 12VOUT, COUT = 8 x 10µF Ceramic
5.0A Load Step at 5A/µs
100
95
90
85
80
0
1
2
3
4
5
6
7
8
9
10 11
Output Current (A)
16VIN 24VIN
34VIN
Figure 2 — 12VOUT Efficiency
Figure 5 — 24VIN to 24VOUT, COUT = 8 x 10µF Ceramic
3.0A Load Step at 5A/µs
100
95
90
85
80
0
1
2
3
4
5
6
7
8
Output Current (A)
16VIN 24VIN
34VIN
Figure 3 — 28VOUT Efficiency
Figure 6 — 16VIN to 28VOUT, COUT = 8 x 10µF Ceramic
3.0A Load Step at 5A/µs
Cool-Power® ZVS Switching Regulators
Page 10 of 27
Rev 2.1
09/2017
PI3749-x0
Performance Characteristics TA = 25°C (Cont.)
900
800
700
600
500
400
300
200
100
0
0
1
2
3
4
5
6
7
8
9
10 11
Output Current (A)
16VIN 24VIN
34VIN
Figure 7 — Switching Frequency vs. Output Current @ 12VOUT
Figure 10 — Start-up with 24VIN to 24VOUT at 5A
900
800
700
600
500
400
300
200
100
0
0
1
2
3
4
5
6
7
Output Current (A)
16VIN 24VIN
34VIN
Figure 8 — Switching Frequency vs. Output Current @ 24VOUT
Figure 11 — Short Circuit with 24VIN to 24VOUT at 5A
900
800
700
600
500
400
300
200
100
0
0
1
2
3
4
5
6
7
8
Output Current (A)
20VIN
18VIN
16VIN
24VIN
34VIN
Figure 9 — Switching Frequency vs. Output Current @ 28VOUT
Cool-Power® ZVS Switching Regulators
Page 11 of 27
Rev 2.1
09/2017
PI3749-x0
Efficiency & Power Loss TA = 25°C [7]
Safe Operating Area TA = 25°C [7]
14
13
12
11
10
9
200
180
160
140
120
100
80
98
97.5
97
4.5
4
3.5
3
96.5
96
8
2.5
2
7
60
6
40
95.5
95
5
20
4
0
1.5
12 14 16 18 20 22 24 26 28 30 32 34
15
20
25
30
35
VOUT (V)
VIN (V)
IOUT
Current Limit
POUT
Efficiency
Power Dissipation
Figure 12 — 12VOUT Efficiency and Power Dissipation at 7A over
Figure 15 — Power and current output at 34VIN
Input Voltage Range
12
11
10
9
300
250
200
150
100
50
99
98
97
96
95
94
93
92
91
5
4.5
4
3.5
3
2.5
2
8
7
1.5
1
6
0
12 14 16 18 20 22 24 26 28 30 32 34
15
20
25
30
35
VOUT (V)
VIN (V)
IOUT
Current Limit
POUT
Efficiency
Power Dissipation
Figure 13 — 24VOUT Efficiency and Power Dissipation at 7A over
Figure 16 — Power and current output at 24VIN
Input Voltage Range
10
250
200
150
100
50
6
98.6
98.4
98.2
98
Safe Operating Area (SOA)
5.5
5
9
8
7
6
4.5
4
97.8
97.6
97.4
97.2
97
3.5
3
2.5
2
1.5
5
0
96.8
12 14 16 18 20 22 24 26 28 30 32 34
15
20
25
30
35
VOUT (V)
VIN (V)
IOUT
Current Limit
POUT
Efficiency
Power Dissipation
Figure 14 — 28VOUT Efficiency and Power Dissipation at 6A over
Figure 17 — Power and current output at VIN less than 24V
Input Voltage Range
[7] Note: Testing was performed using a 3 in. x 3 in., four 2 oz. copper layers, FR4 evaluation board platform.
Cool-Power® ZVS Switching Regulators
Page 12 of 27
Rev 2.1
09/2017
PI3749-x0
Thermal De-Rating [7]
12
11
10
9
8
7
6
5
4
3
8
7
6
5
4
3
2
1
0
2
1
0
25
35
45
55
65
75
85
95
105
20
30
40
50
Ambient Temperature (°C)
24VIN 28VIN 34VIN
60
70
80
90
100 110
Ambient Temperature (°C)
16VIN
24VIN
34VIN
Figure 18 — Thermal de-rating @ VOUT = 12V
Figure 21 — Thermal de-rating @ VOUT = 30V with Limited
Input Range (24VIN to 34VIN)
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
20
30
40
50
60
70
80
90
100 110
20
30
40
50
Ambient Temperature (°C)
24VIN 30VIN 34VIN
60
70
80
90
100 110
Ambient Temperature (°C)
16VIN
24VIN
34VIN
Figure 19 — Thermal de-rating @ VOUT = 24V
Figure 22 — Thermal de-rating @ VOUT = 34V with Limited
Input Range (24VIN to 34VIN)
9
8
7
6
5
4
3
2
1
0
20
30
40
50
60
70
80
90
100
Ambient Temperature (°C)
16VIN 24VIN 34VIN
Figure 20 — Thermal de-rating @ VOUT = 28V
[7] Note: Testing was performed using a 3 in. x 3 in., four 2 oz. copper layers, FR4 evaluation board platform.
Cool-Power® ZVS Switching Regulators
Page 13 of 27
Rev 2.1
09/2017
PI3749-x0
MTBF
PI3749-00-LGIZ vs. Temperature, Assuming 50% Derating and GB
10000
1000
100
10
1
0
-60
-40
-20
20
40
60
80
100
120
140
Temperature (°C)
MTBF Calculations Over Temperature Using Telcordia SR-332
Figure 23 — PI3749-x0 calculated MTBF Telcordia SR-332 GB
Cool-Power® ZVS Switching Regulators
Page 14 of 27
Rev 2.1
09/2017
PI3749-x0
Soft-Start and Tracking
Functional Description
The PI3749-x0 provides a soft start and tracking feature using the
TRK pin. Programmable Soft Start requires an external capacitor
from the TRK pin to SGND in addition to the internal 47nF
soft-start capacitor to set the start-up ramp period greater then
tSS. The PI3749-x0 output will proportionately follow the TRK pin
when it is below 1.7VDC. If the TRK pin is goes below the disable
threshold, the regulator will finish the current switching cycle and
then stop switching.
The PI3749-x0 is part of a family of highly integrated ZVS
Buck-Boost regulators. The PI3749-x0 has a variable output
voltage that is set with a resistive divider. Performance and
maximum output current are characterized with a specific external
power inductor as defined in electrical specifications, with
Inductor Pairing section.
L1
Remote Sensing Differential Amplifier
VIN
VIN
VS1
VS2
VOUT
VOUT
A general purpose operational amplifier is provided to assist with
differential remote sensing and or level shifting of the output
voltage. The VDIFF pin can be connected to the transconductance
error amplifier input EAIN pin, or with proper configuration can
also be connected to the EAO pin to drive the modulator directly.
CIN
COUT
PGND
ISP
PGND
ISN
PI3749-00
VDR
IMON
VSN
PGD
EN
R1
R2
Power Good
VSP
SYNCO
VDIFF
EAIN
EAO
The PI3749-x0 PGD pin functions as a power good indicator
and pulls low when the regulator is not operating or if EAIN is
less than 1.4V.
SYNCI
TRK
COMP
SGND
Output Current Limit Protection
PI3749-x0 has three methods implemented to protect from
output short circuit or over current condition.
Figure 24 — ZVS Buck-Boost with required components
For basic operation, Figure 24 shows the minimum connections
and components required.
Slow Current Limit protection: prevents the output load from
sourcing current higher than the maximum rated regulator
current. If the output current exceeds the VOUT Slow Current
Limit (VOUT_SCL) a slow current limit fault is initiated and the
regulator is shutdown which eliminates output current flow.
After Fault Restart Delay (tFR_DLY), a soft-start cycle is initiated.
This restart cycle will be repeated indefinitely until the excessive
load is removed.
Enable
The EN pin of the regulator is referenced to SGND and permits the
user to turn the regulator on or off. The EN polarity is a positive
logic assertion. If the EN pin is left floating or asserted high, the
regulator output is enabled. Pulling the EN pin below 0.8VDC with
respect to SGND will discharge the SS/TRK pin until the output
reaches zero or the EN pin is released. When the converter is
disabled via the EN pin or due to a fault mode, the internal gate
driver high side charge pumps are enabled as long as there is
enough input voltage for the internal VDR supply voltage to be
available. The return path for this charge pump supply is through
the output. If the output load is disconnected or high impedance,
the output capacitors will float up to about 3.4V maximum,
sourced by 960µA of leakage current. This pre-biased condition
poses no issue for the converter. The 960µA leakage current
may be safely bypassed to SGND. A simple application circuit is
available to bypass this current in a non-dissipative manner. Please
contact Applications Engineering for details.
Fast Current Limit protection: monitors the regulator inductor
current pulse-by-pulse to prevent the output from supplying very
high current. If the regulator senses a high inductor current pulse,
it will initiate a fault and stop switching. After Fault Restart Delay
(tFR_DLY), a soft-start cycle is initiated. This restart cycle will be
repeated indefinitely until the excessive load is removed.
Overload Timeout protection: If the regulator is providing
maximum output power for longer than the Overload Timeout
Delay (TOL), it will initiate a fault and stop switching. After
Fault Restart Delay (tFR_DLY), a soft-start cycle is initiated. This
restart cycle will be repeated indefinitely until the overload
load is removed.
Input Undervoltage Lockout
Switching Frequency Synchronization
If VIN falls below the input Under Voltage Lockout (UVLO)
threshold, the PI3749-x0 will complete the current cycle and
stop switching. The system will restart once the input voltage is
reestablished and after the Fault Restart Delay.
The SYNCI input allows the user to synchronize the controller
switching frequency to the falling edge of an external clock
referenced to SGND. The external clock can synchronize the unit
between 50% and 110% of the preset switching frequency (FSW).
The SYNCI pin should be connected to SGND when not in use,
and should never be left floating.
Input Overvoltage Lockout
If VIN rises above the input Overvoltage Lockout (OVLO) threshold,
the PI3749-x0 will complete the current cycle and stop switching.
The system will restart once the input voltage is reestablished and
after the Fault Restart Delay.
Cool-Power® ZVS Switching Regulators
Page 15 of 27
Rev 2.1
09/2017
PI3749-x0
Output Overvoltage Protection
IMON Amplifier
The PI3749-x0 provides a differential amplifier with a level
shifted, SGND referenced output, the IMON Pin, which is useful
for sensing input or output current on high voltage rails. A fixed
gain of 20:1 is provided over a large common mode range.
When using the amplifier, the ISN pin must be referenced to the
common mode voltage of the ISP pin for proper operation. See
Absolute Maximum Ratings for more information. If not in use,
the ISN and ISP pins should be connected to SGND and the IMON
pin left floating.
The PI3749-x0 family is equipped with two methods of detecting
an output overvoltage condition. Output Overvoltage Protection
(OVP) to prevent damage to input voltage sensitive devices. If
the output voltage exceeds 20% of its set regulated value as
measured by the EAIN pin (VEAIN_OV), the regulator will complete
the current cycle, stop switching and issue an OVP fault. Also if
the output voltage of the regulator exceeds the VOUT Overvoltage
Threshold (VOUT_OVT) then the regulator will complete the current
cycle, stop switching and issue an OVP fault. The system will
resume operation once the output voltage falls below the OVP
threshold and after Fault Restart Delay.
I2C Interface Operation
PI3749-20 devices provide an I2C digital interface that
enables the user to:
Overtemperature Protection
The internal package temperature is monitored to prevent
internal components from reaching their thermal maximum. If
the Overtemperature Protection Threshold is exceeded (TOTP), the
regulator will complete the current switching cycle, enter a low
power mode, set a fault flag, and will soft-start when the internal
temperature decreases by more than the Overtemperature Restart
Hysteresis (TOTP_HYS).
Device Configuration Options:
n■Dynamic VOUT margining
n■Programmable Sync Phase Delay
Fault telemetry including:
n■Input and Output Overvoltage
n■Input and Output Undervoltage
n■Internal Bias Supply Undervoltage
n■Overtemperature Protection
Pulse Skip Mode (PSM)
PI3749-x0 features a hysteretic Pulse Skip Mode to achieve high
efficiency at light loads. The regulator is setup to skip pulses if
VEAO falls below the Pulse Skip Threshold (VEAO_PST). Depending
on conditions and component values, this may result in single
pulses or several consecutive pulses followed by skipped pulses.
Skipping cycles significantly reduces gate drive power and
improves light load efficiency. The regulator will leave Pulse Skip
Mode once the control node rises above the Pulse Skip Mode
Threshold (VEAO_PST).
n■Multi Tiered Current Limit reporting
Variable Frequency Operation
The PI3749-x0 is preprogrammed to a fixed, maximum, base
operating frequency. The frequency is selected with respect to
the required power stage inductor to operate at peak efficiency
across line and load variations. The switching frequency period
will stretch as needed during each cycle to accommodate low
line and or high load conditions. By stretching the switching
frequency period, thus decreasing the switching frequency, the
ZVS operation is preserved throughout the input line voltage
range maintaining optimum efficiency.
Cool-Power® ZVS Switching Regulators
Page 16 of 27
Rev 2.1
09/2017
PI3749-x0
to startup and reach regulation at the same time (see Figure
25 (a)). To implement proportional tracking, simply connect all
devices TRK pins together.
Applications Information
Input / Output Range Limitation
For Direct Tracking, choose the regulator with the highest output
voltage as the master and connect the master to the TRK pin of
the other regulators through a divider (Figure 26) with the same
ratio as the slave’s feedback divider (see Output Voltage Trim).
The PI3749-x0 is capable of wide step-up and step-down
conversions, but high boosting ratios place thermal stress on the
external inductor that may not be fully protected by the controller
overtemperature shut down. For this reason boosting above 29V
out when the input voltage is less than 24V is not supported.
Master VOUT
Output Voltage Trim
The output voltage can be adjusted by feeding back a portion
of the desired output through a voltage divider to the error
amplifier’s input (see Figure 24). Equation 1 can be used to
determine resistor values needed for the voltage divider.
R1
PI3749
TRK
VOUT
Slave
R2
(1)
R1 = R2 •
-1
1.7
SGND
The R2 value is selected by the user; a 1.07kΩ resistor value
is recommended.
Figure 26 — Voltage divider connections for direct tracking
If, for example, a 24V output is needed, the user can select a
1.07kΩ (1%) resistor for R2 and use equation (1) to calculate R1.
Once R1 value is calculated, the user should select the nearest
resistor value available. In this example, R1 is 14.03kΩ so a
14.0kΩ should be selected.
All connected regulators’ soft-start slopes will track with this
method. Direct tracking timing is demonstrated in Figure 25 (b).
All tracking regulators should have their Enable (EN) pins
connected together for proper operation.
Soft-Start Adjustment and Tracking
Inductor Pairing
The TRK pin offers a means to increase the regulator’s soft-start
time or to track with additional regulators. The soft-start slope
is controlled by an internal 47nF and a fixed charge current to
provide a minimum startup time of 1.6ms (typical). By adding
an external capacitor to the TRK pin, the soft-start time can be
increased further. The following equation can be used to calculate
the proper capacitor for a desired soft-start times:
Operations and characterization of the PI3749-x0 was performed
using a 480nH inductor, Part # HCV1206-R48-R, manufactured
by Eaton. This Inductor has a form factor of 12.5mm x 10mm
x 5mm. No other inductor is recommended for use with the
PI3749-x0. For additional inductor information and sourcing,
please contact Eaton directly.
Where, tTRK is the desired soft-start time and ISS is the TRK pin
source current (see Electrical Characteristics for limits).
Thermal De-rating
Thermal de-rating curves are provided (page 13) that are based
on component temperature changes versus load current, input
voltage and no air flow. It is recommended to use these curves
as a guideline for proper thermal de-rating. These curves
represent the entire system and are inclusive to both the SiP and
the external inductor. Maximum thermal operation is limited
by either the MOSFETs or inductor depending upon line and
load conditions.
(tTRK • ISS )
-9
(2)
CTRK
=
– 47 • 10
1.7
The PI3749-x0 allows the tracking of multiple like regulators.
Two methods of tracking can be chosen: proportional or direct
tracking. Proportional tracking will force all connected regulators
All thermal testing was performed using a 3in. x 3in., four
2oz. copper layers, FR4 evaluation board platform. Thermal
measurements were made on the five main power devices; the
four internal MOSFETS and the external inductor.
VOUT
VOUT
1
2
(a)
Master VOUT
VOUT
2
(b)
t
Figure 25 — PI3749-x0 tracking methods
Cool-Power® ZVS Switching Regulators
Page 17 of 27
Rev 2.1
09/2017
PI3749-x0
Input Filter Case 2; Inductive source and local, external input
Filter Considerations
decoupling capacitance with significant RCIN_EXT ESR
(i.e.: electrolytic type)
The PI3749-x0 requires low impedance ceramic input capacitors
(X7R/X5R or equivalent) to ensure proper start up and high
frequency decoupling for the power stage. The PI3749-x0
will draw nearly all of the high frequency current from the
low impedance ceramic capacitors when the main high side
MOSFET(s) are conducting. During the time the MOSFET(s) are off,
the input capacitors are replenished from the source.
In order to simplify the analysis in this case, the voltage source
impedance can be modeled as a simple inductor Lline. Notice
that, the high performance ceramic capacitors CIN_INT within
the PI3749-x0 should be included in the external electrolytic
capacitance value for this purpose. The stability criteria will be:
Table 1 shows the recommended input and output capacitors to
be used for the PI3749-x0 as well as total RMS current, and input
and output ripple voltages. Divide the total RMS current by the
number of ceramic capacitors used to calculate the individual
capacitor’s RMS current. Table 2 includes the recommended input
and output ceramic capacitor. It is very important to verify that
the voltage supply source as well as the interconnecting line are
stable and do not oscillate.
(5)
rEQ_IN > RC
IN_EXT
Lline
(6)
< rEQ_IN
CIN_INT • RC
IN_EXT
Equation (6) shows that if the aggregate ESR is too small – for
example by using very high quality input capacitors (CIN_EXT) – the
system will be under-damped and may even become destabilized.
Again, an octave of design margin in satisfying Equation (5)
should be considered the minimum.
Input Filter Case 1; Inductive source and local, external, input
decoupling capacitance with negligible ESR (i.e.: ceramic type)
The voltage source impedance can be modeled as a series Rline
Lline circuit. The high performance ceramic decoupling capacitors
will not significantly damp the network because of their low ESR;
therefore in order to guarantee stability the following conditions
must be verified:
Note: When applying an electrolytic capacitor for input filter
damping the ESR value must be chosen to avoid loss of
converter efficiency and excessive power dissipation in the
electrolytic capacitor.
Lline
(3)
Rline
>
CIN_INT + CIN_EXT • rEQ_IN
(4)
Rline << rEQ_IN
Where, rEQ_IN can be calculated by dividing the lowest line voltage
by the full load input current. It is critical that the line source
impedance be at least an octave lower than the converter’s
dynamic input resistance, Equation (4). However, Rline cannot
be made arbitrarily low otherwise Equation (3) is violated
and the system will show instability, due to under-damped
RLC input network.
Cool-Power® ZVS Switching Regulators
Page 18 of 27
Rev 2.1
09/2017
PI3749-x0
Parallel Operation
Synchronization
PI3749-x0 can be connected in parallel to increase the output
capability of a single output rail. When connecting modules
in parallel, each EAO, TRK, and EN pin should be connected
together. Current sharing will occur automatically in this manner
so long as each inductor is the same value. EAIN pins should
remain separated, each with an REA1 and REA2, to reject
noise differences between different modules’ SGND pins. Up
to three modules may be connected in parallel. The modules
current sharing accuracy is determined by the inductor tolerance
( 10%) and to a lesser extent, timing variation ( 1.5%). Current
sharing may be considered independent of synchronization
and/or interleaving. Modules do not have to be interleaved
or synchronized to share current. The following equation
determines the output capability of N modules (up to three)
to be determined:
PI3749-x0 units may be synchronized to an external clock by
driving the SYNCI pin. The synchronization frequency must not
be higher than 110% of the programmed maximum value FSW
.
This is the switching frequency during DCM of operation. The
minimum synchronization frequency is FSW / 2. In order to ensure
proper power delivery during synchronization, the user should
refer to the switching frequency vs. output current curves for the
load current, output voltage and input voltage operating point.
The synchronization frequency should not be lower than that
determined by the curve or reduced output power will result.
The power reduction is approximately the ratio between required
frequency and synchronizing frequency. If the required frequency
is 1MHz and the sync frequency is 600kHz, the user should
expect a 40% reduction in output capability.
Interleaving
Iarray = Imod + I • (N – 1) • 0.77
(7)
(
)
mod
Interleaving is primarily done to reduce output ripple and the
required number of output capacitors by introducing phase
current cancellation. The PI3749-x0 has a fixed delay that is
proportional to to the maximum value of FSW shown in the
datasheet. When connecting two units as showin in
Where:
Iarray is the maximum output current of the array
Imod is the maximum output per module
Figure 58, they will operate at 180 degrees out of phase when the
converters switching frequency is equal to FSW. If the converter
enters CrCM and the switching frequency is lower than FSW, the
phase delay will no longer be 180 degrees and ripple cancellation
will begin to decay. Interleaving when the switching frequency is
reduced to lower than 80% of the programmed maximum value
is not recommended. Operation over high boost ratios such as
8V in to 36V out or narrow buck ratios like 28V in to 24V is not
recommended for interleaving.
N
is the number of modules
L1
VOUT
PGND
VS1
VS2
VIN
CIN_1
COUT_1
REA1_1
REA2_1
PGND
ISP
ISN
VDR
IMON
VSN
VSP
PI3749-x0
PGD
EN
VDIFF
LGH
EN
SYNCO
SYNCI
TRK
EAIN
EAO
COMP
CHF_1
2.5kΩ
TRK
SGND
CCOMP_1
CTRK_1
L2
VOUT
PGND
VS1
VS2
VIN
CIN_2
COUT_2
REA1_2
REA2_2
PGND
ISP
ISN
VDR
IMON
VSN
PI3749-x0
VSP
PGD
EN
VDIFF
LGH
EN
SYNCO
SYNCI
TRK
EAIN
EAO
COMP
CHF_2
SGND
TRK
CCOMP_2
CTRK_2
Figure 27 — PI3749-x0 parallel operation
Cool-Power® ZVS Switching Regulators
Page 19 of 27
Rev 2.1
09/2017
PI3749-x0
CINPUT
Ripple Current
COUTPUT
Ripple Current
Output
Ripple
(mVpp)
Input
Ripple
(mVpp)
VOUT
(V)
VIN
(V)
ILOAD
(A)
CINPUT
(see table 2)
COUTPUT
(see table 2)
(IRMS
)
(IRMS)
5
7
6
9
6
10
6
11
7
11
5
7
5
7
5
7
5
7
5
7
6
9
5
7
5
6
5
7
4
6
5
7
4
6
3
5
3.55
4.59
4.45
6.08
4.68
6.93
5.06
7.66
5.78
7.8
3.65
4.89
4.43
6.32
4.36
6.84
4.34
7.21
4.64
6.76
4.49
6.07
3.91
4.6
37.1
60.6
44
67.5
113
84.3
162
81
12
12
12
12
12
24
24
24
24
24
28
28
28
28
28
34
34
34
16
20
24
28
34
16
20
24
28
34
16
20
24
28
34
24
29
34
6 X 10µF
6 X 10µF
6 X 10µF
6 X 10µF
6 X 10µF
6 X 10µF
6 X 10µF
6 X 10µF
6 X 10µF
6 X 10µF
6 X 10µF
6 X 10µF
6 X 10µF
6 X 10µF
6 X 10µF
6 X 10µF
6 X 10µF
6 X 10µF
8 X 10µF
8 X 10µF
8 X 10µF
8 X 10µF
8 X 10µF
8 X 10µF
8 X 10µF
8 X 10µF
8 X 10µF
8 X 10µF
8 X 10µF
8 X 10µF
8 X 10µF
8 X 10µF
8 X 10µF
8 X 10µF
8 X 10µF
8 X 10µF
80.5
40.2
88
184
90.1
217
125
240
63.5
114
56
43.4
95
50
87
5.13
7.08
4.28
5.3
75.4
138
61.6
85
75
4.24
4.7
4.13
4.5
64
82
68
88
4.55
5.1
4.4
68
105
121
142
176
108
223
70
5.1
74
5.1
4.66
5.67
6.5
72.5
83
5.93
7.18
10.62
5.09
6.49
4.68
5.06
4.66
5.31
4.5
143.5
301
84
9.37
4.65
5.51
4.46
4.68
4.54
5.16
4.18
5.26
5.39
5.76
4.5
122
82
95
83
87
83.5
107.5
119
130.6
168
95
83
93
77.4
95
5.49
5.6
124
148
107
133
90.4
124
6.66
4.5
100
107
122
118
160
5.6
5.33
3.7
3.87
5.12
4.95
Table 1 — Recommended input and output capacitance
Part Number
Description
MFG Description
C3225X7S1H106M250AB
10µF Capacitor, X7S 20% 50V, 1210
TDK
Table 2 — Capacitor manufacturer part numbers
Cool-Power® ZVS Switching Regulators
Page 20 of 27
Rev 2.1
09/2017
PI3749-x0
I2C Addressing
The PI3749-20 is hardware compatible with the NXP I2C™ Bus Specification Version 2.1, January 2000, in Standard Mode (100kHz) for all
bus timing and voltage levels up to 5.5V. It operates as a slave on the I2C bus.
The PI3749-20 I2C interface responds to the address programmed by the two I2C Address pins, ADR1 and ADR0. The address pins are
three level inputs, providing nine possible combination pairs, although only eight of these combinations are unique, as shown in table 3.
Considering only the 7 bit address sub-field, the high-order address bits <6> through <4> are hardcoded to 4’b1001, while the lower order
address bits <3> through <0> are modified by the ADRx pins.
Resultant I2C address sub-field
Fully formed address write word
ADDRx state
(including lsb of the transfer set for a write)
Sub-field bit positions <7.1>
ADR1
ADR0
Hexadecimal
Decimal
72
Binary
Binary
L
L
L
M
H
L
7’h48
7’h49
7’h4A
7’h4B
7’h4C
7’h4D
7’h4E
7’h4F
7’h4F
7’b100_1000 8’b1001_0001
73
7’b100_1001 8’b1001_0011
7’b100_1010 8’b1001_0101
7’b100_1011 8’b1001_0111
7’b100_1100 8’b1001_1001
7’b100_1101 8’b1001_1011
7’b100_1110 8’b1001_1101
7’b100_1111 8’b1001_1111
7’b100_1111 8’b1001_1111
L
74
M
M
M
H
H
H
75
M
H
L
76
77
78
M
H
79
79
Table 3 — I2C Address selection
Note that the state of the ADRx pins is resolved on each I2C address transfer. Therefore the PI3749-20 address can be changed while the
regulator is powered up and in operation.
I2C Command Structure
Depending on the state of the read/write bit, two types of transfers are possible:
a. Write: Data transferred from the I2C master to the PI3749-20 slave
The first byte is transmitted by the master and includes the slave address and the R/W bit set to write (as shown in the last column of
Table 3.) The second byte is also transmitted by the master and is the write data. The slave responds between each byte with an
acknowledge bit.
b. Read: Data returned from the PI3749-20 slave to the master
The first byte is transmitted by the master and includes the slave address but the R/W bit is set to read. The slave responds to the
first byte (the address transmitted by the master) with an acknowledge bit. The second byte is transmitted by the slave back to the
master and is the read data. The master responds after the read data byte with a not-acknowledge bit (since the PI3749-20 read
data are all single byte registers).
Figure 28 — Data transfer on the I2C bus
Per the I2C standard, the master generates all serial clock pulses, and all data is transferred MSB first.
Cool-Power® ZVS Switching Regulators
Page 21 of 27
Rev 2.1
09/2017
PI3749-x0
I2C™ Parameter Readback
Fault Monitoring
Register
Name
Register
Address
Bit <7>
Bit <6>
Bit <5>
Bit <4>
Bit <3>
Bit <2>
Bit <1>
Bit <0>
FLT2
FLT3
2
3
4
TRISE
0
OTP
0
VOUT_NEG
0
VOUT_OV
0
EAIN_HI
Q1_FIL
VIN_OV
Q3_SIL
VIN_UV
Q3_FIL
VCC_UV
SLOW_IL
FLTREG_CLR
Write only, data ignored
Table 4 — PI3749-20 Fault Readback/Clear Registers
The fault bits in the FLT2 and FLT3 registers are only latched when the regulator first stops operating due to a given fault type. If the
regulator is already not operating (perhaps due to a fault protection or being disabled) then should a new fault condition occur, the fault bit
associated with the new fault will not be registered.
Both versions of the PI3749-x0 will auto recover from any fault protection mechanism, once the fault is corrected. However in order to aid in
monitoring of the regulator via the I2C fault monitoring registers, when a fault occurs, the associated fault bit(s) will set and latch until they
are explicitly cleared by the I2C host using the FLTREG_CLR register.
A write to the FLTREG_CLR register address will clear all latched fault register bits.
Fault Bit
Location
Fault Bit
Name
Fault Destination
Overtemperature Protection: The predicted maximum hot-spot temperature, based on measured temperature and loading,
exceeded the maximum safe operating temperature.
TRISE
FLT2, Bit<7>
OTP
FLT2, Bit<6> Overtemperature Protection: The internal measured temperature exceeded the maximum safe operating temperature.
FLT2, Bit<5> VOUT negative fault. The output voltage was below ground.
FLT2, Bit<4> Output Overvoltage protection.
VOUT_NEG
VOUT_OV
EAIN_HI
VIN_OV
FLT2, Bit<3> Current Limit: Overload Timeout.
FLT2, Bit<2> Input Overvoltage Lockout.
VIN_UV
FLT2, Bit<1> Input Undervoltage Lockout.
VCC_UV
FLT2, Bit<0> VCC undervoltage. The internal bias supply faulted due to undervoltage.
Current Limit: Fast current limit (Q1) The peak current through Q1 and the inductor was higher than
the maximum current allowed.
Q1_FIL
Q3_SIL
Q3_FIL
FLT3, Bit<3>
FLT3, Bit<2> Current Limit: Slow current limit (Q3)
Current Limit: Fast current limit (Q3) The peak current through Q3 and the inductor was higher than
the maximum current allowed.
FLT3, Bit<1>
SLOW_IL
FLT3, Bit<0> Current Limit: Slow current limit.
Table 5 — Fault register bit summary
I2C Volatile Addresses for Parameter Programming
Register
Name
Register
Address
Readback
capable?
Bit <3>
Bit <2>
Bit <1>
Bit <0>
MRGN
5
Yes
MRGN_ENA
MRGN<2>
MRGN<1>
MRGN<0>
Table 6 — PI3749-20 Parameter Programming Volatile Registers
Cool-Power® ZVS Switching Regulators
Page 22 of 27
Rev 2.1
09/2017
PI3749-x0
MRGN: Margin Control
By default, output voltage margining is disabled, corresponding to B3 being cleared. In this case, the reference to the error amplifier is at its
nominal value of 1.700V. When margining is enabled, the reference can be modified in 85mV steps according to Table 7.
MRGN state
MRGN data
Resultant Margin Function
Reference Voltage (V)
MRGN_ENA<3>
MRGN<2..0>
100
Margin active?
1
1
1
1
0
1
1
1
1
Yes
1.360
1.445
1.530
1.615
1.700
1.785
1.870
1.955
2.040
101
Yes
110
Yes
111
Yes
xxx
No (data ignored), default
Yes
000
001
Yes
Yes
010
011
Yes
Table 7 — Margin control register programming
The MRGN state is always controlled by four bit wide volatile register. At power up, the register always resets to 4’b0000. The MRGN
address can be freely read and written, as there are no one-time programmable fuses involved.
Cool-Power® ZVS Switching Regulators
Page 23 of 27
Rev 2.1
09/2017
PI3749-x0
Package Drawings
DETAIL A
(SECTION VIEW)
E
PIN 1 INDEX
M
M
ddd
eee
C
C
A B
D
b
SEE NOTE 2
L
PAD OPENING (b)
b
SEE NOTE 2
aaa
C
(4)PL
TOP VIEW
M
M
ddd
eee
C
C
A B
DETAIL B
BB 10x14mm SiP
DIMENSIONAL REFERENCES
REF.
A
A1
A2
b
MIN.
2.49
--
--
0.50
NOM.
2.56
--
--
0.55
MAX.
2.63
0.04
2.59
0.60
DETAIL A
E1
e SEE NOTE 1
D
E
14.00 BSC
10.00 BSC
13.00 BSC
9.00 BSC
1.00 BSC
0.225
e
SEE NOTE 1
D1
E1
e
14
13
12
11
10
9
L
.175
.275
BB 10x14mm SiP
DIMENSIONAL REFERENCES
TOLERANCE OF FORM AND
POSITION
REF.
aaa
bbb
ccc
ddd
eee
0.10
0.10
0.08
0.10
0.08
8
D1
7
6
5
NOTES:
1. 'e' REPRESENTS THE BASIC TERMINAL PITCH.
SPECIFIES THE TRUE GEOMETRIC POSITION OF THE TERMINAL AXIS.
4
2. DIMENSION 'b' APPLIES TO METALLIZED TERMINAL AND IS MEASURED
BETWEEN 0.00mm AND 0.25mm FROM TERMINAL TIP.
3
2
3. DIMENSION 'A' INCLUDES PACKAGE WARPAGE
1
4. EXPOSED METALLIZED PADS ARE Cu PADS WITH SURFACE FINISH
PROTECTION.
DETAIL B
A
B
C
D
E
F
G
H
J
K
PIN 1 INDEX
5. RoHS COMPLIANT PER CST-0001 LATEST REVISION.
6. ALL DIMENSIONS ARE IN MM UNLESS OTHERWISE SPECIFIED.
BOTTOM VIEW
bbb
C
A2
A
SEE NOTE 3
ccc
C
SEATING PLANE
A1
b
C
Cool-Power® ZVS Switching Regulators
Page 24 of 27
Rev 2.1
09/2017
PI3749-x0
Receiving PCB Pattern Design Recommendations
E1
PIN 1
e
e
D1
b
b
PCB LAND PATTERN
BB 10x14mm SiP
DIMENSIONAL REFERENCES
REF.
b
MIN.
0.50
NOM.
0.55
MAX.
0.60
D1
E1
e
13.00 BSC
9.00 BSC
1.00 BSC
Recommended receiving footprint for PI3749-x0 10mm x 14mm package. All pads should have a final copper size of 0.55mm x 0.55mm,
whether they are solder-mask defined or copper defined, on a 1mm x 1mm grid. All stencil openings are 0.45mm when using either a 5mil
or 6mil stencil.
Cool-Power® ZVS Switching Regulators
Page 25 of 27
Rev 2.1
09/2017
PI3749-x0
Revision History
Revision
Date
Description
Page Number(s)
1.0
04/13/15
Initial Release
n/a
Updated conditions column
Added additional specifications
7
8
Clarified parameters and updated typical
Corrected labels
Corrected labels
9
1.1
07/14/15
10
15
18
Inductor Pairing updated
1.2
1.3
08/03/15
09/03/15
Inductor value corrected
7-9
all
Added I2C capability throughout
Added documentation for I2C capability
Changed frequency units for readability
Reformatted for readability
1, 4, 6, 7, 8, 9 & 20
1.4
10/12/15
11
19
1.5
1.6
04/08/16
09/27/16
Updated VDIFF description
Power level updated
4
ALL
Corrections to Typical Application, Figure 24
Package drawings updated
1, 15
5, 23, 24
1.7
1.8
02/14/17
03/31/17
Correct LGH pin name
Parallel Operation section updated
Include additional PCB Pattern information
3-5
18
24
Update Absolute Maximum Ratings
Update IMON Output voltage
3
7
1.9
2.0
2.1
05/31/17
06/14/17
09/15/17
Parallel Operation update
18-19
15
Updated functional description of enable
Please note: Page added in Rev 2.0.
Cool-Power® ZVS Switching Regulators
Page 26 of 27
Rev 2.1
09/2017
PI3749-x0
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Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor
makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves
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Cool-Power® ZVS Switching Regulators
Page 27 of 27
Rev 2.1
09/2017
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