BCM3814V60E10A5T06 [VICOR]
Isolated Fixed-Ratio DC-DC Converter;
| 型号： | BCM3814V60E10A5T06 |
| 厂家： | 
VICOR CORPORATION |
| 描述： | Isolated Fixed-Ratio DC-DC Converter |
| 文件： | 总39页 (文件大小：1258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
BCM® in a VIA Package
Bus Converter
BCM3814x60E10A5yzz
Isolated Fixed-Ratio DC-DC Converter
Features & Benefits
Product Ratings
• Up to 150A continuous low voltage side current
• Fixed transformation ratio(K) of 1/6
• Up to 769W/in3 power density
• 97.2% peak efficiency
VHI = 54V (36 – 60V)
ILO = up to 150A
K = 1/6
VLO = 9V (6 – 10V)
(no load)
Product Description
• Integrated ceramic capacitance filtering
• Parallel operation for multi-kW arrays
• OV, OC, UV, short circuit and thermal protection
• 3814 package
The BCM in a VIA package is a high efficiency Bus Converter,
operating from a 36 to 60VDC high voltage bus to deliver an
isolated 6 to 10VDC unregulated, low voltage.
This unique ultra-low profile module incorporates DC-DC
conversion, integrated filtering and PMBus™ commands and
controls in a chassis or PCB mount form factor.
• High MTBF
• Thermally enhanced VIA™ package
• PMBusTM management interface
The BCM offers low noise, fast transient response and industry
leading efficiency and power density. A low voltage side referenced
PMBus™ compatible telemetry and control interface provides
access to the BCM’s internal controller configuration, fault
monitoring, and other telemetry functions.
Typical Applications
Leveraging the thermal and density benefits of Vicor’s VIA
packaging technology, the BCM module offers flexible thermal
management options with very low top and bottom side thermal
impedances.
• DC Power Distribution
• Information and Communication
Technology (ICT) Equipment
When combined with downstream Vicor DC-DC conversion
components and regulators, the BCM allows the Power Design
Engineer to employ a simple, low-profile design which will
differentiate the end system without compromising on cost or
performance metrics.
• High End Computing Systems
• Automated Test Equipment
• Industrial Systems
• High Density Energy Systems
• Transportation
Size:
3.76 x 1.40 x 0.37 in
95.59 x 35.54 x 9.40 mm
Part Ordering Information
High
Side
Voltage
Range
Ratio
Max
High
Side
Max
Low
Side
Max
Low
Side
Product
Function
Package
Length
Package
Width
Package
Type
Product Grade
(Case Temperature)
Option Field
Voltage
Voltage Current
BCM
38
14
x
60
E
10 A5
y
zz
BCM =
Bus Converter
Module
02 = Chassis/PMBus
06 = Short Pin/PMBus
10 = Long Pin/PMBus
Length in
Width in
B = Board VIA
C = -20 to 100°C[1]
T = -40 to 100°C[1]
Internal Reference
Inches x 10 Inches x 10 V = Chassis VIA
[1] High Temperature Current Derating may apply; See Figure 1, specified thermal operating area.
BCM® in a VIA Package
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Typical Application
Host µC
PMBus
+
–
V
EXT
SGND
BCA_SGND
BCM in a VIA Package
µc_SGND
EXT_BIAS
SCL
3
SDA
}
SGND
ADDR
BCA_SGND
FUSE
+HI
–HI
+LO
–LO
Non-Isolated
Point of Load
Regulators
V
C
LOAD
HI
HI
HV
LV
ISOLATION BOUNDRY
SOURCE_RTN
BCM3814x60E10A5yzz at point of load
Host µC
PMBus
+
–
V
EXT
SGND
BCA_SGND
µc_SGND
BCM in a VIA Package
EXT_BIAS
SCL
3
SDA
}
BCA_SGND
SGND
ADDR
FUSE
+HI
–HI
+LO
–LO
C
LOAD
V
HI
HI
HV
LV
ISOLATION BOUNDRY
SOURCE_RTN
BCM3814x60E10A5yzz direct to load
BCM® in a VIA Package
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Pin Configuration
10
1
TOP VIEW
3
12
+HI
–HI
–LO
–LO
+LO
5
6
7
8
9
EXT BIAS
SCL
PMBus™
SDA
SGND
ADDR
–LO
–LO
+LO
11
2
4
13
BCM in a 3814 VIA Package - Chassis (Lug) Mount
11
13
2
TOP VIEW
4
–HI
+HI
–LO
–LO
+LO
9
8
7
6
5
ADDR
SGND
SDA
PMBus™
SCL
EXT BIAS
+LO
–LO
–LO
10
1
3
12
BCM in a 3814 VIA Package - Board (PCB) Mount
Note: The dot on the VIA housing indicates the location of the signal pin 9.
Pin Descriptions
Pin Number
Signal Name
Type
Function
1
2
+HI
–HI
HIGH SIDE POWER
Positive transformer power terminal on high voltage side
Negative transformer power terminal on high voltage side
HIGH SIDE POWER
RETURN
LOW SIDE
POWER
3, 4
+LO
Positive transformer power terminal on low voltage side
5
6
7
EXT BIAS
SCL
INPUT
INPUT
5V supply input
I2C Clock, PMBus™ Compatible
I2C Data, PMBus™ Compatible
SDA
INPUT/OUTPUT
LOW SIDE
SIGNAL RETURN
8
SGND
ADDR
–LO
Signal Ground
9
INPUT
Address assignment - Resistor based
Negative transformer power terminal on low voltage side
LOW SIDE
POWER RETURN
10, 11, 12, 13
Notes: All signal pins (5, 6, 7, 8, 9) are referenced to low voltage side and isolated from the high voltage side.
Keep SGND Signal of the BCM in a VIA package separated from the low voltage side power return terminal (–LO) in electrical design.
BCM® in a VIA Package
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Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.
Parameter
Comments
Min
Max
80
Unit
V
+HI to –HI
-1
HI_DC or LO_DC slew rate
+LO to –LO
1
V/µs
V
-1
15
-0.3
10
V
EXT BIAS to SGND
0.15
5.5
5.5
3.6
A
SCL to SGND
-0.3
-0.3
-0.3
V
SDA to SGND
V
ADDR to SGND
V
Dielectric Withstand*
High Voltage Side to Case
See note below
Basic Insulation
1500
1500
N/A
VDC
VDC
VDC
High Voltage Side to
Low voltage Side
Basic Insulation
Low Voltage Side to Case
Functional Insulation
* The SELV side (-LO) is directly connected to the case of the BCM in a VIA package.
BCM® in a VIA Package
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Electrical Specifications
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
General Powertrain High Voltage Side to Low Voltage Side Specification (Forward Direction)
High Side Input Voltage range,
continuous
VHI_DC
36
60
V
V
VHI_DC voltage where µC is initialized,
(powertrain inactive)
VHI µController
VµC_ACTIVE
14
Disabled, VHI_DC = 54V
5
HI to LO Input Quiescent Current
IHI_Q
mA
T
CASE ≤ 100ºC
10
9
VHI_DC = 54V, TCASE = 25ºC
VHI_DC = 54V
7.2
5
14
12
17
HI to LO No Load Power Dissipation
PHI_NL
W
VHI_DC = 36V to 60V, TCASE = 25 ºC
VHI_DC = 36V to 60V
VHI_DC = 60V, CLO_EXT = 4000 µF, RLOAD_LO = 20% of full
load current
30
HI to LO Inrush Current Peak
IHI_INR_PK
A
T
CASE ≤ 100ºC
35
DC High Side Input Current
Transformation Ratio
IHI_IN_DC
K
At ILO_OUT_DC = 150A, TCASE ≤ 85ºC
25.5
A
High voltage to low voltage, K = VLO_DC / VHI_DC, at no
load
1/6
V/V
Low Side Output Current
(continuous)
ILO_OUT_DC
T
CASE ≤ 85°C
150
180
A
A
10 ms pulse, 25% Duty cycle, ILO_OUT_AVG ≤ 50% rated
ILO_OUT_DC
Low Side Output Current (pulsed)
ILO_OUT_PULSE
VHI_DC = 54V, ILO_OUT_DC = 150A
95.2
93.6
96.7
95.4
95.8
HI to LO Efficiency (ambient)
HI to LO Efficiency (hot)
hAMB
VHI_DC = 36V to 60V, ILO_OUT_DC = 150A
VHI_DC = 54V, ILO_OUT_DC = 75A
%
97.2
95.6
hHOT
h20%
VHI_DC = 54V, ILO_OUT_DC = 150A, TCASE = 85°C
%
%
HI to LO Efficiency
(over load range)
30A < ILO_OUT_DC < 150A
93
RLO_COLD
RLO_AMB
RLO_HOT
FSW
VHI_DC = 54V, ILO_OUT_DC = 150A, TCASE = -40°C
VHI_DC = 54V, ILO_OUT_DC = 150A
0.9
2
1.7
2.1
2.1
2.4
HI to LO Output Resistance
mΩ
VHI_DC = 54V, ILO_OUT_DC = 150A, TCASE = 85°C
Frequency of the LO Side Voltage Ripple = 2x FSW
1.6
0.85
2.3
2.6
Switching Frequency
0.90
0.95
MHz
mV
CLO_EXT = 0µF, ILO_OUT_DC = 150A, VHI_DC = 54V,
20MHz BW
120
Low Side Output Voltage Ripple
VLO_OUT_PP
T
CASE ≤ 100ºC
200
BCM® in a VIA Package
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Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
General Powertrain High Voltage Side to Low Voltage Side Specification (Forward Direction) Cont.
Effective HI Side Capacitance
(Internal)
CHI_INT
CLO_INT
CLO_OUT_EXT
CLO_OUT_AEXT
Effective Value at 54VHI_DC
Effective Value at 9VLO_DC
11.2
202
µF
µF
µF
Effective LO Side Capacitance
(Internal)
Effective LO Side Output Capacitance
(External)
Excessive capacitance may drive module into SC
protection
6000
Effective LO Side Output Capacitance
(External)
CLO_OUT_AEXT Max = N * 0.5 * CLO_OUT_EXT MAX, where N
= the number of units in parallel
Powertrain Protection High Voltage Side to Low Voltage Side (Forward Direction)
Startup into a persistent fault condition. Non-Latching
fault detection given VHI_DC > VHI_UVLO+
Auto Restart Time
tAUTO_RESTART
VHI_OVLO+
VHI_OVLO-
490
63
560
71
ms
V
HI Side Overvoltage Lockout
Threshold
67
65
2
HI Side Overvoltage Recovery
Threshold
61
69
V
HI Side Overvoltage Lockout
Hysteresis
VHI_OVLO_HYST
tHI_OVLO
V
HI Side Overvoltage Lockout
Response Time
100
1
µs
ms
A
From powertrain active. Fast Current limit protection
disabled during Soft-Start
HI Side Soft-Start Time
tHI_SOFT-START
ILO_OUT_OCP
tLO_OUT_OCP
ILO_OUT_SCP
tLO_OUT_SCP
tOTP+
LO Side Output Overcurrent Trip
Threshold
180
195
125
204
3
240
LO Side Output Overcurrent
Response Time Constant
Effective internal RC filter
ms
A
LO Side Output Short Circuit
Protection Trip Threshold
LO Side Output Short Circuit
Protection Response Time
1
µs
°C
Overtemperature Shutdown
Threshold
Temperature sensor located inside controller IC
(Internal Temperature)
BCM® in a VIA Package
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Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
Powertrain Supervisory Limits HIGH VOLTAGE SIDE to LOW VOLTAGE SIDE (Forward Direction)
HI Side Overvoltage Lockout
Threshold
VHI_OVLO+
VHI_OVLO-
VHI_OVLO_HYST
tHI_OVLO
64
60
66
64
2
68
66
V
V
HI Side Overvoltage Recovery
Threshold
HI Side Overvoltage Lockout
Hysteresis
V
HI Side Overvoltage Lockout
Response Time
100
28
30
2
µs
V
HI Side Undervoltage Lockout
Threshold
VHI_UVLO-
26
28
30
32
HI Side Undervoltage Recovery
Threshold
VHI_UVLO+
VHI_UVLO_HYST
tHI_UVLO
V
HI Side Undervoltage Lockout
Hysteresis
V
HI Side Undervoltage Lockout
Response Time
100
µs
From VHI_DC = VHI_UVLO+ to powertrain active, (i.e One
time Startup delay form application of VHI_DC to VLO_DC
HI Side Undervoltage Startup Delay
tHI_UVLO+_DELAY
20
ms
)
LO Side Output Overcurrent Trip
Threshold
ILO_OUT_OCP
tLO_OUT_OCP
tOTP+
193
204
3
215
A
ms
°C
°C
°C
s
LO Side Output Overcurrent
Response Time Constant
Effective internal RC filter
Overtemperature Shutdown
Threshold
Temperature sensor located inside controller IC
(Internal Temperature)
125
Overtemperature Recovery
Threshold
Temperature sensor located inside controller IC
(Internal Temperature)
tOTP–
105
110
3
115
-45
Undertemperature Shutdown
Threshold
Temperature sensor located inside controller IC;
Protection not available for M-Grade units.
tUTP
Startup into a persistent fault condition. Non-Latching
fault detection given VHI_DC > VHI_UVLO+
Undertemperature Restart Time
tUTP_RESTART
BCM® in a VIA Package
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200
180
160
140
120
100
80
60
40
20
0
-60
-40
-20
0
20
40
60
80
100
120
Case Temperature ( °C)
36 – 60V
Figure 1 — Specified thermal operating area
1. The BCM in a VIA Package is cooled through bottom case (bottom housing).
2. The thermal rating of the BCM in a VIA Package is based on typical measured device efficiency.
3. The case temperature in the graph is the measured temperature of the bottom housing, such that operating internal junction temperature of the BCM in a
VIA Package does not exceed 125°C.
2000
1750
1500
1250
1000
750
200
175
150
125
100
75
500
50
250
25
0
0
36 38 40 42 44 46 48 50 52 54 56 58 60
36 38 40 42 44 46 48 50 52 54 56 58 60
HI Side Voltage (V)
HI Side Voltage (V)
ILO_OUT_DC
ILO_OUT_PULSE
PLO_OUT_DC
PLO_OUT_PULSE
Figure 2 — Specified electrical operating area using rated RLO_HOT
110
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80
100
LO Side Current (% ILO_DC
)
Figure 3 — Specified HI side start-up into load current and external capacitance
BCM® in a VIA Package
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PMBus™ Reported Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted.
Monitored Telemetry
• The BCM communication version is not intended to be used without a Digital Supervisor.
DIGITAL SUPERVISOR
ACCURACY
(RATED RANGE)
FUNCTIONAL
REPORTING RANGE
UPDATE
RATE
ATTRIBUTE
REPORTED UNITS
PMBusTM READ COMMAND
HI Side Voltage
HI Side Current
LO Side Voltage[1]
LO Side Current
LO Side Resistance
Temperature[2]
(88h) READ_VIN
(89h) READ_IIN
5%(LL - HL)
28V to 66V
-1A to 34A
100µs
100µs
100µs
100µs
100ms
100ms
VACTUAL = VREPORTED x 10-1
IACTUAL = IREPORTED x 10-2
VACTUAL = VREPORTED x 10-1
IACTUAL = IREPORTED x 10-2
RACTUAL = RREPORTED x 10-5
TACTUAL = TREPORTED
20%(10 - 20% of FL)
5%(20 - 133% of FL)
(8Bh) READ_VOUT
5%(LL - HL)
4.7V to 11V
20%(10 - 20% of FL)
5%(20 - 133% of FL)
(8Ch) READ_IOUT
-6A to 204A
500u to 3000u
- 55ºC to 130ºC
5%(50 - 100% of FL) at NL
10%(50 - 100% of FL)(LL - HL)
(D4h) READ_ROUT
(8Dh) READ_TEMPERATURE_1
7°C(Full Range)
[1] Default READ LO Side Voltage returned when unit is disabled = -300V.
[2] Default READ Temperature returned when unit is disabled = -273°C.
Variable Parameter
• Factory setting of all below Thresholds and Warning limits are 100% of listed protection values.
• Variables can be written only when module is disabled either EN pulled low or VHI < VHI_UVLO-
.
• Module must remain in a disabled mode for 3ms after any changes to the below variables allowing ample time to commit changes to EEPROM.
FUNCTIONAL
REPORTING
RANGE
DIGITAL SUPERVISOR
ACCURACY
(RATED RANGE)
DEFAULT
VALUE
ATTRIBUTE
CONDITIONS / NOTES
PMBusTM COMMAND [3]
HI Side Overvoltage
Protection Limit
VHI_OVLO- is automatically 3%
lower than this set point
(55h) VIN_OV_FAULT_LIMIT
(57h) VIN_OV_WARN_LIMIT
(D7h) DISABLE_FAULTS
(5Bh) IIN_OC_FAULT_LIMIT
(5Dh) IIN_OC_WARN_LIMIT
(4Fh) OT_FAULT_LIMIT
5%(LL - HL)
5%(LL - HL)
5%(LL - HL)
28V to 66V
28V to 66V
28V or 66V
0 to 34A
100%
100%
100%
100%
100%
100%
100%
0ms
HI Side Overvoltage
Warning Limit
HI Side Undervoltage
Protection Limit
Can only be disabled to a preset
default value
HI Side Overcurrent
Protection Limit
20%(10 - 20% of FL)
5%(20 - 133% of FL)
HI Side Overcurrent
Warning Limit
20%(10 - 20% of FL)
5%(20 - 133% of FL)
0 to 34A
Overtemperature
Protection Limit
Internal Temperature
Internal Temperature
7°C(Full Range)
7°C( Full Range)
50µs
0 to 125°C
0 to 125°C
0 to 100ms
Overtemperature
Warning Limit
(51h) OT_WARN_LIMIT
(60h) TON_DELAY
Additional time delay to the
Undervoltage Startup Delay
Turn on Delay
[3] Refer to internal µc datasheet for complete list of supported commands.
BCM® in a VIA Package
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Signal Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤100°C (T-Grade); all other specifications are at TCASE = 25ºC unless otherwise noted. Please note: For chassis mount model, Vicor part number 42550 will be
needed for applications requiring the use of the signal pins. Signal cable 42550 is rated up to five insertions and extractions. To avoid unnecessary stress on the
connector, the cable should be tied to the chassis.
EXT. BIAS (VDDB) Pin
• 5V supply input, required to power the circuitry internal to the BCM in a VIA package for communication signals such as SCL, SDA, ADDR etc
• Voltage to EXT BIAS pin is needed for PMBus™ enable and disable control. It is not needed for PMBus monitoring voltage, current, power or temperature.
Lower voltage is better. It will help to lower the power dissapation in the internal regulator that is generating 3.3V voltage for communication circuits.
• Apply voltage to this pin between 4.5V and 9V. The nominal voltage is 5V.
SIGNAL TYPE
STATE
ATTRIBUTE
VDDB Voltage
SYMBOL
VVDDB
CONDITIONS / NOTES
MIN
TYP MAX UNIT
4.5
5
9
V
mA
A
Regular
Operation
VDDB Current consumption
Inrush Current Peak
Turn on time
IVDDB
50
INPUT
IVDDB_INR
tVDDB_ON
VVDDB Slew Rate = 1V/µs
3.5
1.5
Startup
From VVDDB_MIN to PMBus active
ms
SGND Pin
• This pin is supply return pin for Ext. Bias (VDDB) pin.
• All input and output signals (SCL, SDA, ADDR) are referenced to SGND pin.
Note: Keep SGND Signal of the BCM in a VIA package separated from the low voltage side power return terminal (–LO) in electrical design.
Address (ADDR) Pin
• This pin programs only a Fixed and Persistent slave address for BCM in a VIA package.
• This pin programs the address using a resistor between ADDR pin and signal ground.
• The address is sampled during startup and is used until power is reset.
• This pin has 10kΩ pullup resistor internally between ADDR pin and internal VDD.
• 16 addresses are available. Relative to nominal value of internal VDD (VVDD_NOM = 3.3V), a 206.25mV range per address.
SIGNAL TYPE
STATE
ATTRIBUTE
ADDR Input Voltage
ADDR leakage current
ADDR registration time
SYMBOL
VSADDR
ISADDR
CONDITIONS / NOTES
See address section
MIN
TYP MAX UNIT
0
3.3
1
V
Regular
Operation
MULTI LEVEL
INPUT
Leakage current
From VVDD_IN_MIN
µA
ms
Startup
tSADDR
1
BCM® in a VIA Package
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Serial Clock input (SCL) AND Serial Data (SDA) Pins
• High power SMBus specification and SMBus physical layer compatible. Note that optional SMBALERT# is signal not supported.
• PMBusTM command compatible.
• The internal µC requires the use of a flip flop to drive SSTOP. See system diagram section for more details.
SIGNAL TYPE
STATE
ATTRIBUTE
SYMBOL
CONDITIONS / NOTES
MIN
TYP MAX UNIT
Electrical Parameters
VIH
VIL
VVDD_IN = 3.3V
2.1
3
V
Input Voltage Threshold
Output Voltage Threshold
VVDD_IN = 3.3V
VVDD_IN = 3.3V
VVDD_IN = 3.3V
Unpowered device
VOL = 0.4V
0.8
V
V
VOH
VOL
0.4
10
V
Leakage current
ILEAK PIN
ILOAD
µA
mA
Signal Sink Current
4
Total capacitive load of
one device pin
Signal Capacitive Load
CI
10
pF
Signal Noise Immunity
Timing Parameters
Operating Frequency
VNOISE_PP
10MHz to 100MHz
300
mV
FSMB
tBUF
tHD:STA
tSU:STA
Idle state = 0Hz
10
400
KHz
µs
Free time between
Stop and Start Condition
1.3
DIGITAL
Regular
Hold time after Start or
Repeated Start condition
First clock is generated
after this hold time
INPUT/OUTPUT
Operation
0.6
0.6
µs
µs
Repeat Start Condition
Setup time
Stop Condition setup time
Data Hold time
tSU:STO
tHD:DAT
tSU:DAT
tTIMEOUT
tLOW
0.6
300
100
25
µs
ns
ns
ms
µs
µs
Data Setup time
Clock low time out
Clock low period
Clock high period
35
1.3
0.6
tHIGH
50
25
Cumulative clock low
extend time
tLOW:SEXT
ms
ns
ns
Measured from
(VIL_MAX 0.15) to (VIH_MIN + 0.15)
Clock or Data Fall time
Clock or Data Rise time
tF
20
20
300
300
tR
0.9 • VVDD_IN_MAX to (VIL_MAX 0.15)
tLOW tR
tF
SCL
VIH
VIL
tHIGH
tSU,DAT
tHD,STA
tHD,DAT
tSU,STA
tSU,STO
SDA
VIH
VIL
tBUF
P
S
S
P
BCM® in a VIA Package
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Timing diagram (Foward Direction)
BCM® in a VIA Package
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Application Characteristics
Product is mounted and temperature controlled via top side cold plate, unless otherwise noted. All data presented in this section are collected data from high
voltage side sourced units processing power in forward direction.See associated figures for general trend data.
16
14
12
10
8
97.0
96.0
95.0
6
94.0
93.0
4
2
0
-40
-20
0
20
40
60
80
100
36 38 40 42 44 46 48 50 52 54 56 58 60
Case Temperature (ºC)
HI Side Input Voltage (V)
VHI_DC
:
36V
54V
60V
TCASE
:
-40°C
25°C
70°C
Figure 4 — No load power dissipation vs. VHI_DC
Figure 5 — Full load efficiency vs. temperature; VHI_DC
100
90
80
70
60
50
40
30
20
10
0
99
97
95
93
91
89
87
85
83
81
79
0
15
30
45
60
75
90 105 120 135 150
0
15
30
45
60
75
90 105 120 135 150
LO Side Output Current (A)
LO Side Output Current (A)
VHI_DC
:
36V
54V
60V
VHI_DC:
36V
54V
60V
Figure 6 — Efficiency at TCASE = -40°C
Figure 7 — Power dissipation at TCASE = -40°C
100
90
80
70
60
50
40
30
20
10
0
99
97
95
93
91
89
87
85
83
81
79
0
15
30
45
60
75
90 105 120 135 150
0
15
30
45
60
75
90 105 120 135 150
LO Side Output Current (A)
LO Side Output Current (A)
VHI_DC
:
VHI_DC:
36V
54V
60V
36V
54V
60V
Figure 8 — Efficiency at TCASE = 25°C
Figure 9 — Power dissipation at TCASE = 25°C
BCM® in a VIA Package
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99
97
95
93
91
89
87
85
83
81
79
100
90
80
70
60
50
40
30
20
10
0
0
15
30
45
60
75
90 105 120 135 150
0
15
30
45
60
75
90 105 120 135 150
LO Side Output Current (A)
LO Side Output Current (A)
VHI_DC
:
36V
54V
60V
VHI_DC
:
36V
54V
60V
Figure 10 — Efficiency at TCASE = 70°C
Figure 11 — Power dissipation at TCASE = 70°C
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
250
225
200
175
150
125
100
75
50
25
0
0
15
30
45
60
75
90 105 120 135 150
-40
-20
0
20
40
60
80
100
LO Side Output Current (A)
Case Temperature°C()
VHI_DC
:
54V
ILO_DC
:
150A
Figure 12 — RLO vs. temperature; Nominal VHI_DC
Figure 13 — VLO_OUT_PP vs. ILO_DC ; No external CLO_OUT_EXT Board
.
ILO_DC = 150A at TCASE = 70°C
mounted module, scope setting : 20MHz analog BW
BCM® in a VIA Package
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Figure 14 — Full load ripple, 300µF CHI_IN_EXT; No external
Figure 15 — 0 A– 150A transient response:
CHI_IN_EXT = 300µF, no external CLO_OUT_EXT
CLO_OUT_EXT Board mounted module, scope setting :
.
20MHz analog BW
Figure 17 — Start up from application of VHI_DC = 54V, 20% ILO_DC
,
Figure 16 — 150A – 0A transient response:
100% CLO_OUT_EXT
CHI_IN_EXT = 300µF, no external CLO_OUT_EXT
Figure 18 — Start up from application of EN with pre-applied
VHI_DC = 54V, 20% ILO_DC, 100% CLO_OUT_EXT
BCM® in a VIA Package
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General Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤100°C (T-Grade); All other specifications are at TCASE = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
Mechanical
mm / [in]
mm / [in]
mm / [in]
mm / [in]
cm3/ [in3]
Length
L
L
Lug (Chassis) Mount
95.34 / [3.75] 95.59 / [3.76] 95.84 / [3.77]
97.55 / [3.84] 97.80 / [3.85] 98.05 / [3.86]
35.29 / [1.39] 35.54 / [1.40] 35.79 / [1.41]
9.019 / [0.355] 9.40 / [0.37] 9.781 / [0.385]
31.93 / [1.95]
Length
PCB (Board) Mount
Width
W
H
Height
Volume
Weight
Vol
W
Without heatsink
130.4 / [4.6]
g / [oz]
Pin Material
Underplate
C145 copper, 1/2 hard
Low stress ductile Nickel
Palladium
50
0.8
100
6
µin
µin
Pin Finish
Soft Gold
0.12
2
Thermal
BCM3814x60E10A5yzz (T-Grade)
BCM3814x60E10A5yzz (C-Grade)
-40
-20
125
125
Operating junction temperature
Operating case temperature
TINTERNAL
BCM3814x60E10A5yzz (T-Grade),
derating applied, see safe thermal
operating area
-40
-20
100
100
°C
TCASE
BCM3814x60E10A5yzz (C-Grade),
derating applied, see safe thermal
operating area
Estimated thermal resistance to
maximum temperature internal
component from isothermal top
Thermal resistance top side
RJC_TOP
1.33
0.49
°C/W
°C/W
Estimated thermal resistance of thermal
coupling between the top and bottom
case surfaces
Thermal Resistance Coupling between
top case and bottom case
RHOU
Estimated thermal resistance to
maximum temperature internal
component from isothermal bottom
Thermal resistance bottom side
Thermal capacity
RJC_BOT
0.71
52
°C/W
Ws/°C
Assembly
BCM3814x60E10A5yzz (T-Grade)
BCM3814x60E10A5yzz (C-Grade)
-40
-40
125
125
°C
°C
Storage
Temperature
TST
Human Body Model,
ESDHBM
“ESDA / JEDEC JDS-001-2012” Class I-C
(1kV to < 2 kV)
1000
200
ESD Withstand
Charge Device Model,
“JESD 22-C101-E” Class II (200V to <
500V)
ESDCDM
BCM® in a VIA Package
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General Characteristics (Cont.)
Specifications apply over all line, load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40°C ≤ TCASE
≤ 125°C (T-Grade); All other specifications are at TCASE = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Safety
Min
Typ
Max
Unit
Isolation capacitance
CHI_lo
RHI_lo
Unpowered unit
620
10
780
940
pF
Isolation resistance
At 500VDC
MΩ
MIL-HDBK-217Plus Parts Count - 25°C
Ground Benign, Stationary, Indoors /
Computer
2.2
3.6
MHrs
MHrs
MTBF
Telcordia Issue 2 - Method I Case III;
25°C Ground Benign, Controlled
Agency approvals / standards
CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable
BCM® in a VIA Package
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BCM in a VIA Package
IHI
ILO
RLO
+
+
V•I
K
K • ILO
K • VHI
+
–
+
–
VHI
VLO
IHI_Q
–
–
Figure 19 — BCM DC model (Forward Direction)
The BCM in a VIA package uses a high frequency resonant tank
to move energy from high voltage side to low voltage side and
vice versa. The resonant LC tank, operated at high frequency, is
amplitude modulated as a function of HI side voltage and LO side
current. A small amount of capacitance embedded in the high
voltage side and low voltage side stages of the module is sufficient
for full functionality and is key to achieving high power density.
The use of DC voltage transformation provides additional
interesting attributes. Assuming that RLO = 0Ω and IHI_Q = 0A,
Eq. (3) now becomes Eq. (3) and is essentially load independent,
resistor R is now placed in series with VHI.
The BCM3814x60E10A5yzz can be simplified into the preceeding
model.
R
BCM
V
LO
+
–
K = 1/6
At no load:
VHI
VLO = VHI • K
(1)
K represents the “turns ratio” of the BCM.
Rearranging Eq (1):
Figure 20 — K = 1/6 BCM with series HI side resistor
VLO
K =
(2)
(3)
(4)
The relationship between VHI and VLO becomes:
VHI
In the presence of load, VLO is represented by:
•
•
K
VLO = (VHI – IHI R)
(5)
VLO = VHI • K – ILO • RLO
and ILO is represented by:
IHI – IHI_Q
Substituting the simplified version of Eq. (4)
(IHI_Q is assumed = 0A) into Eq. (5) yields:
2
•
•
•
R K
VLO = VHI K – ILO
(6)
ILO
=
K
This is similar in form to Eq. (3), where RLO is used to represent the
characteristic impedance of the BCM. However, in this case a real R
on the high voltage side of the BCM is effectively scaled by K2 with
respect to the low voltage side.
RLO represents the impedance of the BCM, and is a function of the
RDS_ON of the HI side and LO side MOSFETs, PC board resistance of
HI side and LO side boards and the winding resistance of the power
transformer. IHI_Q represents the HI side quiescent current of the
BCM control, gate drive circuitry, and core losses.
Assuming that R = 1Ω, the effective R as seen from the low voltage
side is 28mΩ, with K = 1/6.
BCM® in a VIA Package
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A similar exercise should be performed with the additon of a
capacitor or shunt impedance at the high voltage side of the BCM.
A switch in series with VHI is added to the circuit. This is depicted in
Figure 21.
Low impedance is a key requirement for powering a high-
current, low-voltage load efficiently. A switching regulation stage
should have minimal impedance while simultaneously providing
appropriate filtering for any switched current. The use of a BCM
between the regulation stage and the point of load provides a
dual benefit of scaling down series impedance leading back to
the source and scaling up shunt capacitance or energy storage
as a function of its K factor squared. However, the benefits are
not useful if the series impedance of the BCM is too high. The
impedance of the BCM must be low, i.e. well beyond the
crossover frequency of the system.
S
BCM
V
LO
+
–
K = 1/6
C
C
V
HI
A solution for keeping the impedance of the BCM low involves
switching at a high frequency. This enables small magnetic
components because magnetizing currents remain low. Small
magnetics mean small path lengths for turns. Use of low loss
core material at high frequencies also reduces core losses.
Figure 21 — BCM with HI side capacitor
The two main terms of power loss in the BCM module are:
n No load power dissipation (PHI_NL): defined as the power
used to power up the module with an enabled powertrain
at no load.
A change in VHI with the switch closed would result in a change in
capacitor current according to the following equation:
n Resistive loss (PRLO): refers to the power loss across
the BCM module modeled as pure resistive impedance.
dVHI
(7)
Ic(t) = C
dt
Pdissipated = PHI_NL + PRLO
(10)
(11)
Assume that with the capacitor charged to VHI, the switch is
opened and the capacitor is discharged through the idealized BCM.
In this case,
Therefore,
PLO_OUT = PHI_IN – Pdissipated = PHI_IN – PHI_NL – PRLO
•
Ic= ILO
K
(8)
The above relations can be combined to calculate the overall
module efficiency:
substituting Eq. (1) and (8) into Eq. (7) reveals:
C
K2
dVLO
dt
(9)
ILO
=
•
ꢀꢀ
h
pLO_OUt
pHi_iN
pHi_iN – pHi_NL – pRLO
pHi_iN
=
=
(12)
The equation in terms of the LO side has yielded a K2 scaling factor
for C, specified in the denominator of the equation.
A K factor less than unity results in an effectively larger capacitance
on the low voltage side when expressed in terms of the high
voltage side. With a K = 1/6 as shown in Figure 21,
2
VHI
i
HI – pHI_NL – (iLO
)
R
•
LO
•
=
VHi iHi
•
C = 1µF would appear as C = 36µF when viewed from the low
voltage side.
2
pHI_NL + (iLO
)
R
•
LO
=
1
–
(
)
VHI • iHI
BCM® in a VIA Package
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Filter Design
Thermal Considerations
A major advantage of BCM systems versus conventional PWM
converters is that the transformer based BCM does not require
external filtering to function properly. The resonant LC tank,
operated at extreme high frequency, is amplitude modulated as
a function of HI side voltage and LO side current and efficiently
transfers charge through the isolation transformer. A small amount
of capacitance embedded in the high voltage side and low voltage
side stages of the module is sufficient for full functionality and is
key to achieving power density.
The VIA™ package provides effective conduction cooling from
either of the two module surfaces. Heat may be removed from the
top surface, the bottom surface or both. The extent to which these
two surfaces are cooled is a key component for determining the
maximum power that can be processed by a VIA, as can be seen
from specified thermal operating area in Figure 1. Since the VIA has
a maximum internal temperature rating, it is necessary to estimate
this internal temperature based on a system-level thermal solution.
To this purpose, it is helpful to simplify the thermal solution into a
roughly equivalent circuit where power dissipation is modeled as
a current source, isothermal surface temperatures are represented
as voltage sources and the thermal resistances are represented as
resistors. Figure 22 shows the “thermal circuit” for the VIA module.
This paradigm shift requires system design to carefully evaluate
external filters in order to:
n Guarantee low source impedance:
To take full advantage of the BCM module’s dynamic
response, the impedance presented to its HI side terminals
must be low from DC to approximately 5MHz. The
connection of the bus converter module to its power
source should be implemented with minimal distribution
inductance. If the interconnect inductance exceeds
100nH, the HI side should be bypassed with a RC damper
to retain low source impedance and stable operation. With
an interconnect inductance of 200nH, the RC damper
may be as high as 1µF in series with 0.3Ω. A single
electrolytic or equivalent low-Q capacitor may be used in
place of the series RC bypass.
+
RJC_TOP
TC_TOP
–
RHOU
s
–
TC_BOT
RJC_BOT
+
PDISS
s
n Further reduce HI side and/or LO side voltage ripple without
sacrificing dynamic response:
Figure 22 — Double sided cooling VIA thermal model
Given the wide bandwidth of the module, the source
response is generally the limiting factor in the overall
system response. Anomalies in the response of the source
will appear at the LO side of the module multiplied by its
K factor.
In this case, the internal power dissipation is PDISS, RJC_TOP and
RJC_BOT are thermal resistance characteristics of the VIA module and
the top and bottom surface temperatures are represented as TC_TOP
,
and TC_BOT. It is interesting to notice that the package itself provides
a high degree of thermal coupling between the top and bottom
case surfaces (represented in the model by the resistor RHOU). This
feature enables two main options regarding thermal designs:
n Protect the module from overvoltage transients imposed
by the system that would exceed maximum ratings and
induce stresses:
The module high side/low side voltage ranges shall not be
exceeded. An internal overvoltage lockout function
prevents operation outside of the normal operating HI side
range. Even when disabled, the powertrain is exposed
to the applied voltage and power MOSFETs must
withstand it.
n Single side cooling: the model of Figure 22 can be simplified by
calculating the parallel resistor network and using one simple
thermal resistance number and the internal power dissipation
curves; an example for bottom side cooling only is shown in
Figure 23.
In this case, RJC can be derived as following:
Total load capacitance at the LO side of the BCM module shall not
exceed the specified maximum. Owing to the wide bandwidth
and small LO side impedance of the module, low-frequency bypass
capacitance and significant energy storage may be more densely
and efficiently provided by adding capacitance at the HI side of
the module. At frequencies <500kHz the module appears as an
impedance of RLO between the source and load.
(RJC_TOP + RHOU) • RJC_BOT
R
=
(14)
JC
RJC_TOP + RHOU + RJC_BOT
Within this frequency range, capacitance at the HI side appears as
effective capacitance on the LO side per the relationship
defined in Eq. (13).
CHI_EXT
K2
(13)
CLO_EXT
=
This enables a reduction in the size and number of capacitors used
in a typical system.
BCM® in a VIA Package
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ZIN_EQ1
ZOUT_EQ1
BCM®1
R0_1
VLO
VHI
RJC
+ TC_BOT
s
ZOUT_EQ2
ZIN_EQ2
BCM®2
R0_2
PDISS
+
Load
DC
s
ZOUT_EQn
BCM®n
R0_n
ZIN_EQn
Figure 23 – Single-sided cooling VIA thermal model
n Double side cooling: while this option might bring limited
advantage to the module internal components (given the
surface-to-surface coupling provided), it might be appealing
in cases where the external thermal system requires allocating
power to two different elements, like for example heatsinks with
independent airflows or a combination of chassis/air cooling.
Figure 24 — BCM module array
Fuse Selection
Current Sharing
In order to provide flexibility in configuring power systems, BCM in
a VIA package modules are not internally fused. Input line fusing of
BCM in a VIA package products is recommended at system level to
provide thermal protection in case of catastrophic failure.
The performance of the BCM in a VIA package is based on efficient
transfer of energy through a transformer without the need of
closed loop control. For this reason, the transfer characteristic
can be approximated by an ideal transformer with a positive
temperature coefficient series resistance.
The fuse shall be selected by closely matching system
requirements with the following characteristics:
This type of characteristic is close to the impedance characteristic
of a DC power distribution system both in dynamic (AC) behavior
and for steady state (DC) operation.
n Current rating
(usually greater than maximum current of BCM module)
n Maximum voltage rating
(usually greater than the maximum possible input voltage)
When multiple BCM modules of a given part number are
connected in an array they will inherently share the load current
according to the equivalent impedance divider that the system
implements from the power source to the point of load.
n Ambient temperature
n Nominal melting I2t
Some general recommendations to achieve matched array
impedances include:
n Recommend fuse: ≤40A Littlefuse 456 Series (HI side)
n Dedicate common copper planes/wires within the PCB/Chassis
to deliver and return the current to the VIA modules.
Reverse Operation
n Provide as symmetric a PCB/Wiring layout as possible among
VIA™ modules
BCM modules are capable of reverse power operation. Once the
unit is started, energy will be transferred from low voltage side
back to the high voltage side whenever the low side voltage
exceeds VHI • K. The module will continue operation in this fashion
for as long as no faults occur.
For further details see AN:016 Using BCM Bus Converters
in High Power Arrays.
The BCM3814x60E10A5yzz has not been qualified for continuous
operation in a reverse power condition. Furthermore fault
protections which help protect the module in forward operation
will not fully protect the module in reverse operation.
Transient operation in reverse is expected in cases where there is
significant energy storage on the low voltage side and transient
voltages appear on the high voltage side.
BCM® in a VIA Package
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System Diagram for PMBus™ Interface
5 V
EXT_BIAS
SCL
SDA
SCL
BCM in a VIA
Package
Host
PMBus™
SDA
SGND
ADDR
SGND
The BCM in a VIA package provides accurate telemetry monitoring and reporting, threshold and warning limits adjustment, in
addition to corresponding status flags.
The BCM’s internal µC is referenced to low voltage side signal ground.
The BCM provides the host system µC with access to standalone BCM. The standalone BCM is constantly polled for status by the
internal µC. Direct communication to BCM is enabled by a page command. For example, the page (0x00) prior to a telemetry inquiry
points to the internal µC data and pages (0x01) prior to a telemetry inquiry points to the BCM connected data. The BCM constantly
polls it’s data through the PMBus.
The BCM enables the PMBus compatible host interface with an operating bus speed of up to 400kHz. The BCM follows the PMBus
command structure and specification.
BCM® in a VIA Package
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Where:
PMBus™ Interface
X, is a “real world” value in units (A, V, °C, s)
Refer to “PMBus Power System Management Protocol Specification
Revision 1.2, Part I and II” for complete PMBus specifications details
visit http://pmbus.org.
Y, is a two’s complement integer received from the internal µC
m, b and R are two’s complement integers defined as follows:
Device Address
Command
TON_DELAY
Code
60h
88h
89h
8Bh
8Ch
8Dh
96h
A0h
A1h
A4h
A5h
A6h
A7h
D1h
D4h
m
R
3
1
2
1
2
0
0
0
0
0
0
0
0
0
5
b
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The PMBus address (ADDR Pin) should be set to one of a
predetermined 16 possible addresses shown in the table below
using a resistor between ADDR pin and SGND pin.
1
READ_VIN
1
READ_IIN
1
The BCM accepts only a fixed and persistent address and does not
support SMBus address resolution protocol. At initial power up, the
BCM internal µC will sample the address pin voltage, and will hold
this address until device power is removed.
READ_VOUT
1
READ_IOUT
1
READ_TEMPERATURE_1
READ_POUT
1
Slave
Address
Recommended
Resistor RADDR (Ω)
1
ID
HEX
MFR_VIN_MIN
MFR_VIN_MAX
MFR_VOUT_MIN
MFR_VOUT_MAX
MFR_IOUT_MAX
MFR_POUT_MAX
READ_K_FACTOR
READ_BCM_ROUT
1
1
2
1010 000b
1010 001b
1010 010b
1010 011b
1010 100b
1010 101b
1010 110b
1010 111b
1011 000b
1011 001b
1011 010b
1011 011b
1011 100b
1011 101b
1011 110b
1011 111b
50h
51h
52h
53h
54h
55h
56h
57h
58h
59h
5Ah
5Bh
5Ch
5Dh
5Eh
5Fh
487
1050
1
1
3
1870
1
4
2800
1
5
3920
1
65536
1
6
5230
7
6810
8
8870
9
11300
14700
19100
25500
35700
53600
97600
316000
[1] Default READ LO side voltage returned when BCM unit is disabled = -300V.
[2] Default READ Temperature returned when BCM unit is disabled = -273°C.
10
11
12
13
14
15
16
No special formatting is required when lowering the supervisory
limits and warnings.
Reported DATA Formats
The BCM internal µC employs a direct data format where all
reported internal µC measurements are in Volts, Amperes,
Degrees Celsius, or Seconds. The host uses the following PMBus
specification to interpret received values metric prefixes. Note that
the Coefficients command is not supported:
1
m
X =
(
• (Y • 10-R - b)
)
BCM® in a VIA Package
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Supported Command List
Command
Code
Function
Default Data Content
Data Bytes
Access BCM stored information for all connected
devices
PAGE
00h
01h
02h
00h
80h
1Dh
1
1
1
OPERATION
ON_OFF_CONFIG
Turn BCMs on or off
Defines startup when power is applied as well
as immediate on/off control over the BCMs
CLEAR_FAULTS
03h
19h
Clear all BCM and all internal µC faults
Internal µC PMBusTM key capabilities set by factory
BCM over temperature protection
BCM over temperature warning
N/A
20h
64h
64h
64h
64h
64h
64h
00h
00h
00h
00h
00h
None
CAPABILITY
1
2
2
2
2
2
2
2
1
2
1
1
OT_FAULT_LIMIT
OT_WARN_LIMIT
VIN_OV_FAULT_LIMIT
VIN_OV_WARN_LIMIT
IIN_OC_FAULT_LIMIT
IIN_OC_WARN_LIMIT
TON_DELAY
4Fh[1]
51h[1]
55h[1]
57h[1]
5Bh[1]
5Dh[1]
60h[1]
78h
BCM VHI overvoltage warning
BCM VHI overvoltage protection
BCM ILO overcurrent protection
BCM ILO overcurrent warning
Startup delay additional to any BCM fixed delays
Summary of BCM faults
STATUS_BYTE
STATUS_WORD
STATUS_IOUT
79h
Summary of BCM fault conditions
BCM overcurrent fault status
7Bh
STATUS_INPUT
7Ch
BCM overvoltage and under voltage fault status
BCM over temperature and under temperature
fault status
STATUS_TEMPERATURE
7Dh
00h
1
STATUS_CML
7Eh
80h
88h
89h
8Bh
8Ch
8Dh
96h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
Internal µC PMBus Communication fault
Other BCM status indicator
Reads HI side voltage
00h
00h
1
1
STATUS_MFR_SPECIFIC
READ_VIN
FFFFh
2
READ_IIN
Reads HI side current
FFFFh
2
READ_VOUT
Reads LO side voltage
FFFFh
2
READ_IOUT
Reads LO side current
FFFFh
2
READ_TEMPERATURE_1
READ_POUT
BCM temperature
FFFFh
2
Reads LO side power
FFFFh
2
PMBUS_REVISION
MFR_ID
Internal µC PMBus compatible revision
Internal µC ID
22h
1
“VI”
2
MFR_MODEL
Internal µC or BCM model
Internal µC or BCM revision
Internal µC or BCM factory location
Internal µC or BCM manufacturing date
Internal µC or BCM serial number
BCM Minimum rated VHI
BCM Maximum rated VHI
BCM Minimum rated VLO
BCM Maximum rated VLO
BCM Maximum rated ILO
BCM Maximum rated PLO
Set BCM EN pin polarity
BCM K factor
Part Number
FW and HW revision
“AP”
18
18
2
MFR_REVISION
MFR_LOCATION
MFR_DATE
“YYWW”
Serial Number
Varies per BCM
Varies per BCM
Varies per BCM
Varies per BCM
Varies per BCM
Varies per BCM
02h
4
MFR_SERIAL
16
2
MFR_VIN_MIN
MFR_VIN_MAX
MFR_VOUT_MIN
MFR_VOUT_MAX
MFR_IOUT_MAX
MFR_POUT_MAX
BCM_EN_POLARITY
READ_K_FACTOR
READ_BCM_ROUT
SET_ALL_THRESHOLDS
A0h
A1h
A4h
A5h
A6h
A7h
D0h[1]
D1h
D4h
D5h[1]
2
2
2
2
2
1
Varies per BCM
Varies per BCM
646464646464h
2
BCM RLO
2
Set BCM supervisory warning and protection thresholds
6
Disable BCM overvoltage, overcurrent or
under voltage supervisory faults
DISABLE_FAULT
D7h[1]
00h
2
[1] The BCM must be in a disabled state during a write message.
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Command Structure Overview
Write Byte protocol:
The Host always initiates PMBus™ communication with a START bit. All messages are terminated by the Host with a STOP bit. In a write
message, the master sends the slave device address followed by a write bit. Once the slave acknowledges, the master proceeds with the
command code and then similarly the data byte.
1
7
1
1
8
1
8
1
1
S
Slave Address Wr
A
Command Code
A
x = 0
Data Byte
A
x = 0
P
x = 0 x = 0
S
Start Condition
Repeated start Condition
Sr
Rd Read
Wr Write
X
A
P
Indicated that field is required to have the value of x
Acknowledge (bit may be 0 for an ACK or 1 for a NACK)
Stop Condition
From Master to Slave
From Slave to Master
…
Continued next line
Figure 1 — PAGE COMMAND (00h), WRITE BYTE PROTOCOL
Read Byte protocol:
A Read message begins by first sending a Write Command, followed by a REPEATED START Bit and a slave Address. After receiving the
READ bit, the internal µC begins transmission of the Data responding to the Command. Once the Host receives the requested Data, it
terminates the message with a NACK preceding a stop condition signifying the end of a read transfer.
1
7
1
1
8
1
1
7
1
1
8
1
1
S
Slave Address Wr
A
Command Code
A
x = 0
Sr Slave Address Rd
A
Data Byte
A
x = 1
P
x = 0 x = 0
x = 1 x = 0
Figure 2 — ON_OFF_CONFIG COMMAND (02h), READ BYTE PROTOCOL
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Write Word protocol:
When transmitting a word, the lowest order byte leads the highest order byte. Furthermore, when transmitting a Byte, the least significant
bit (LSB) is sent last. Refer to System Management Bus (SMBus) specification version 2.0 for more details.
Note: Extended command and Packet Error Checking Protocols are not supported.
1
7
1
1
8
1
8
1
8
1
1
S
Slave Address Wr
A
Command Code
A
x = 0
Data Byte Low
A
x = 0
Data Byte High
A
x = 0
P
x = 0 x = 0
Figure 3 — TON_DELAY COMMAND (60h)_WRITE WORD PROTOCOL
Read Word protocol:
1
7
1
1
8
1
1
7
1
1
8
1
8
1
1
S
Slave Address Wr
A
Command Code
A
x = 0
Sr Slave Address Rd
A
Data Byte Low
A
x = 0
Data Byte High
A
x = 1
P
x = 0 x = 0
x = 1 x = 0
Figure 4 — MFR_VIN_MIN COMMAND (A0h)_READ WORD PROTOCOL
Write Block protocol:
1
7
1
1
8
1
8
1
8
1
S
Slave Address Wr
A
Command Code
A
x = 0
Byte Count = N
A
x = 0
Data Byte 1
A
x = 0
...
x = 0 x = 0
...
8
1
8
1
1
Data Byte 2
A
x = 0
...
...
Data Byte N
A
x = 0
P
Figure 5 — SET_ALL_THRESHOLDS COMMAND (D5h)_WRITE BLOCK PROTOCOL
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Read Block protocol:
1
7
1
1
8
1
1
7
1
1
8
1
S
Slave Address Wr
A
Command Code
A
x = 0
Sr Slave Address Rd
A
Data Byte = N
A
x = 0
...
x = 0 x = 0
x = 1 x = 0
...
8
1
8
1
8
1
1
Data Byte 1
A
x = 0
Data Byte 2
A
x = 0
...
...
Data Byte N
A
x = 1
P
Figure 6 — SET_ALL_THRESHOLDS COMMAND (D5h)_READ BLOCK PROTOCOL
Write Group Command protocol:
Note that only one command per device is allowed in a group command.
1
7
1
1
8
1
8
1
8
1
S
Slave Address Wr
A
Command Code
A
x = 0
Data Byte Low
A
x = 0
Data Byte High
One or more Data Bytes
A
x = 0
...
First Device
x = 0 x = 0
First Command
1
7
1
1
8
1
8
1
8
1
Sr Slave Address Wr
A
Command Code
A
Data Byte Low
A
x = 0
Data Byte High
A
...
P
Second Device
x = 0 x = 0
Second Command
x = 0
One or more Data Bytes
x = 0
1
7
1
1
8
1
8
1
8
1
Sr Slave Address Wr
A
Command Code
A
x = 0
Data Byte Low
A
x = 0
Data Byte High
One or more Data Bytes
A
x = 0
Nth Device
x = 0 x = 0
Nth Command
Figure 7 — DISABLE_FAULT COMMAND (D7h)_WRITE
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Supported Commands Transaction Type
Page Command (00h)
A direct communication to the BCM internal µC and a simulated
communication to non-PMBus™ devices is enabled by a page
command. Supported command access privileges with a pre-
selected PAGE are defined in the following table. Deviation from
this table generates a communication error in
The page command data byte of 00h prior to a command call will
address the internal µC specific data and a page data byte of FFh
would broadcast to all of the connected BCMs. The value of the
Data Byte corresponds to the pin name trailing number with the
exception of 00h and FFh.
STATUS_CML register.
Data Byte
Description
PAGE Data Byte
Access Type
00h
01h
µC
Command
Code
BCM
00h
01h
PAGE
00h
01h
02h
03h
19h
4Fh
R/W
R
R/W
R/W
R
OPERATION Command (01h)
OPERATION
ON_OFF_CONFIG
CLEAR_FAULTS
CAPABILITY
The Operation command can be used to turn on and off the
connected BCM. Note that the host OPERATION command will not
enable the BCM if the BCM EN pin is disabled in hardware with
respect to the pre set pin polarity. Only with the EN pin active, will
the OPERATION command provide ON/OFF control.
W
R
W
OT_FAULT_LIMIT
OT_WARN_LIMIT
VIN_OV_FAULT_LIMIT
VIN_OV_WARN_LIMIT
IIN_OC_FAULT_LIMIT
IIN_OC_WARN_LIMIT
TON_DELAY
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
51h
55h
57h
5Bh
5Dh
60h
78h
79h
7Bh
7Ch
7Dh
7Eh
80h
88h
89h
8Bh
8Ch
8Dh
96h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
A0h
A1h
A4h
A5h
A6h
A7h
D0h
D1h
D4h
D5h
D7h
If synchronous startup is required in the system, it is recommended
to use the command from host PMBus in order to achieve
simultaneous array startup.
STATUS_BYTE
R/W
R
STATUS_WORD
STATUS_IOUT
R
Unit is On when asserted (default)
Reserved
R
R/W
R/W
R/W
STATUS_INPUT
STATUS_TEMPERATURE
STATUS_CML
R
R
R/W
R
7
6
5
4
3
2
1
0
STATUS_MFR_SPECIFIC
READ_VIN
R/W
R
b
1
0
0
0
0
0
0
0
READ_IIN
R
R
READ_VOUT
R
This command accepts only two data values: 00h and 80h. If any
other value is sent the command will be rejected and a CML Data
error will result.
READ_IOUT
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
READ_TEMPERATURE_1
READ_POUT
R
R
PMBUS_REVISION
MFR_ID
MFR_MODEL
R
R
MFR_REVISION
MFR_LOCATION
MFR_DATE
R
R
MFR_SERIAL
R
MFR_VIN_MIN
R
MFR_VIN_MAX
MFR_VOUT_MIN
MFR_VOUT_MAX
MFR_IOUT_MAX
MFR_POUT_MAX
BCM_EN_POLARITY
READ_K_FACTOR
READ_BCM_ROUT
SET_ALL_THRESHOLDS
DISABLE_FAULT
R
R
R
R
R
R/W
R
R
R/W
R/W
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ON_OFF_CONFIG Command (02h)
OT_FAULT_LIMIT Command (4Fh),
OT_WARN_ LIMIT Command (51h),
VIN_OV_FAULT_ LIMIT Command (55h),
VIN_OV_WARN_ LIMIT Command (57h),
IIN_OC_FAULT_ LIMIT Command (5Bh),
IIN_OC_WARN_ LIMIT Command (5Dh)
Reserved for Future Use
Unit does not power up until commanded by the
CONTROL pin and operation command
Unit requires that the on/off portion of the
OPERATION command is instructing the unit to run[1]
Unit requires the CONTROL pin to be asserted
to start the unit[2]
The values of these registers are set in non volatile memory and
can only be written when the BCMs are disabled.
Not supported: Polarity of the CONTROL pin[3]
Turn off the output and stop transferring
energy to the output as fast as possible[4]
The values of the above mentioned fault and warning are set by
default to a 100% of the respective BCM model supervisory limits.
However these limits can be set to a lower value. For example: In
order for a limit percentage to be set to 80% one would send a
write command with a (50h) Data Word.
7
6
5
4
3
2
1
0
b
0
0
0
1
1
1
0
1
Any values outside the range of (00h – 64h) sent by a host will be
rejected, will not override the currently stored value and will set the
Unsupported Data bit in STATUS_CML.
[1] The BCM Enable pin is ALWAYS to be asserted for powerup. The
BCM_EN_POLARITY command (D0h) bit[(1) defines the logic level
required for the control pin (i.e BCM Enable pin) to be asserted.
[2] With respect to the BCM EN Control Pin if used in system
[3] See MFR_SPECIFIC_00 / BCM_EN_POLARITY to change the Polarity
of the BCM Enable Pin
The SET_ALL_THRESHOLDS COMMAND (D5h) combines in one
block over temperature fault and warning limits, VHI overvoltage
fault and warning limits as well as ILO overcurrent fault and warning
limits. A delay prior to a read command of up to 200ms following a
write of new value is required.
[4] The BCM powertrain once disabled cannot sink current
The VIN_UV_WARN_LIMIT (58h) and VIN_UV_FAULT_LIMIT
(59h) are set by the factory and cannot be changed by the host.
However, a host can disable the under voltage setting using the
DISABLE_FAULT COMMAND (D7h).
CLEAR_FAULTS Command (03h)
This command clears all status bits that have been previously set.
Persistent or active faults are re asserted again once cleared. All
faults are latched once asserted in the internal µC. Registered faults
will not be cleared when shutting down the BCM powertrain by
recycling the BCM high side voltage, or toggling the BCM EN pin,
or sending the OPERATION command.
All FAULT_RESPONSE commands are unsupported. The BCM
powertrain supervisory limits and powertrain protection will behave
as described in the BCM datasheet. In general, once a fault is
detected, the BCM powertrain will shut down and attempt to auto
restart after a predetermined delay.
CAPABILITY Command (19h)
TON_DELAY Command (60h)
Packet Error Checking is not supported
Maximum supported bus speed is 400 KHz
The value of this register word is set in non volatile memory and
can only be written when the BCMs are disabled.
The maximum possible delay is 100ms. Default value is set to (00h).
Follow this equation below to interpret the reported value.
The Device does not have SMBALERT# pin and does
not support the SMBus Alert Response protocol
Reserved
TON_DELAYACTUAL = tREPORTED • 10-3(s)
Staggering startup in an array is possible with TON_DELAY
Command. This delay will be in addition to any startup delay
inherent in the BCM module. For example: startup delay from
application of VHI is typically 20ms whereas startup with EN pin is
typically 250µs. When TON_DELAY is greater than zero, the set
delay will be added to both.
7
6
5
4
3
2
1
0
b
0
0
1
0
0
0
0
0
The internal µC returns a default value of 20h. This value indicates
that the PMBus™ frequency supported is up to 400KHz and that
both Packet Error Checking (PEC) and SMBALERT# are
not supported.
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STATUS_BYTE (78h) and STATUS_WORD (79h)
STATUS_WORD
High Byte
Low Byte
STATUS_BYTE
Not Supported: UNKNOWN FAULT OR WARNING
Not Supported: OTHER
UNIT IS BUSY
UNIT IS OFF
Not Supported: FAN FAULT OR WARNING
Not Supported: VOUT_OV_FAULT
POWER_GOOD Negated*
IOUT_OC_FAULT
VIN_UV_FAULT
STATUS_MFR_SPECIFIC
INPUT FAULT OR WARNING
TEMPERATURE FAULT OR WARNING
IOUT/POUT FAULT OR WARNING
PMBusTM COMMUNCATION EVENT
NONE OF THE ABOVE
Not Supported: VOUT FAULT OR WARNING
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
1
1
1
0
0
0
1
1
0
1
1
1
1
0
b
* equal to POWER_GOOD#
If the internal µC is still powered, it will retain the last status it
received from the BCM and this information will be available to
the user via a PMBus Status request. This is in agreement with the
PMBus standard which requires that status bits remain set until
specifically cleared. Note that in this case where the BCM VHI is lost,
the status will always indicate an under voltage fault, in addition to
any other fault
All fault or warning flags, if set, will remain asserted until
cleared by the host or once the internal µC power is removed.
This includes under voltage fault, overvoltage fault, overvoltage
warning, overcurrent warning, over temperature fault, over
temperature warning, under temperature fault, reverse operation,
communication faults and analog controller shutdown fault.
that occurred.
Asserted status bits in all status registers, with the exception of
STATUS_WORD and STATUS_BYTE, can be individually cleared.
This is done by sending a data byte with one in the bit position
corresponding to the intended warning or fault to be cleared. Refer
to the PMBus™ Power System Management Protocol Specification
– Part II – Revision 1.2 for details.
NONE OF THE ABOVE bit will be asserted if either the STATUS_
MFR_SPECIFIC (80h) or the High Byte of the STATUS WORD
is set.
STATUS_IOUT (7Bh)
The POWER_GOOD# bit reflects the state of the device and does
not reflect the state of the POWER_GOOD# signal limits. The
POWER_GOOD_ON COMMAND (5Eh) and POWER_GOOD_OFF
COMMAND (5Fh) are not supported. The POWER_GOOD# bit is
set anytime the BCM is not in the enabled state, to indicate that
the powertrain is inactive and not switching. The POWER_GOOD#
bit is cleared when the BCM completes the enabling state, 5 ms
after the powertrain is activated allowing for soft start to elapse.
POWER_GOOD# and OFF bits cannot be cleared as they always
reflect the current state of the device.
IOUT_OC_FAULT
Not Supported: IOUT_OC_LV_FAULT
IOUT_OC_WARNING
Not Supported: IOUT_UC_FAULT
Not Supported: Current Share Fault
Not Supported: In Power Limiting Mode
Not Supported: POUT_OP_FAULT
Not Supported: POUT_OP_WARNING
When Page (00h) is used the POWER_GOOD# bit reflects the OR-
ing of all active BCMs’ POWER_GOOD# bits. When Page
(01h – 04h) is used POWER_GOOD# is clear only when the
BCM is active.
7
6
5
4
3
2
1
0
When Page (00h) is used UNIT IS OFF is SET when all BCMs are
not active. When Page (01h – 04h) is used UNIT IS OFF is clear only
when the BCM is active.
b
1
0
0
1
0
0
0
0
Unsupported bits are indicated above. A one indicates a fault.
The Busy bit can be cleared using CLEAR_ALL Command (03h) or
by writing either data value (40h, 80h) to PAGE (00h) using the
STATUS_BYTE (78h).
Fault reporting, such as SMBALERT# signal output, and host
notification by temporarily acquiring bus master status is
not supported.
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The STATUS_CML data byte will be asserted when an unsupported
PMBus™ command or data or other communication fault occured.
STATUS_INPUT (7Ch)
VIN_OV_FAULT
STATUS_MFR_SPECIFIC (80h)
VIN_OV_WARNING
Not Supported: VIN_UV_WARNING
Reserved
Reserved
Reserved
Reserved
PAGE Data Byte = (01h - 04h)
VIN_UV_FAULT
Not Supported: Unit Off For Insufficient
Input Voltage
Not Supported: IIN_OC_FAULT
Not Supported: IIN_OC_WARNING
Not Supported: PIN_OP_WARNING
Reserved
BCM UART CML
Analog Controller Shutdown Fault
BCM Reverse Operation
7
6
5
4
3
2
1
0
b
1
1
0
1
0
0
0
0
7
6
5
4
3
2
1
0
Unsupported bits are indicated above. A one indicates a fault.
b
0
0
0
0
0
1
1
1
The reverse operation bit, if asserted, indicates that the BCM is
processing current in reverse. Reverse current reported value is
not supported.
STATUS_TEMPERATURE (7Dh)
OT_FAULT
The BCM has analog protections and internal µC protections. The
analog controller provides an additional layer of protection and
has the fastest response time. The analog controller shutdown
fault, when asserted, indicates that at least one of the powertrain
protection faults is triggered. This fault will also be asserted if
a disabled fault event occurs after asserting any bit using the
DISABLE_FAULTS COMMAND.
OT_WARNING
Not Supported: UT_WARNING
UT_FAULT
Reserved
Reserved
Reserved
Reserved
The BCM UART is designed to operate with the internal µC UART.
If the BCM UART CML is asserted, it may indicate a hardware or
connection issue between both devices.
7
6
5
4
3
2
1
0
b
Reserved
Reserved
Reserved
1
1
0
1
0
0
0
0
Unsupported bits are indicated above. A one indicates a fault.
Reserved
Reserved
Reserved
Reserved
Reserved
STATUS_CML (7Eh)
Invalid Or Unsupported Command Received
Invalid Or Unsupported Data Received
Not Supported: Packet Error Check Failed
Not Supported: Memory Fault Detected
Not Supported: Processor Fault Detected
Reserved
7
6
5
4
3
2
1
0
b
0
0
0
0
0
0
0
0
When PAGE COMMAND (00h) data byte is equal to (00h), the
BCM Reverse operation, Analog Controller Shutdown Fault, and
BCM UART CML bit will return OR-ing result of active BCMs. The
BCM UART CML will also be asserted if any of the active BCMs
stops responding. The BCM must communicate at least once to
the internal µC in order to trigger this FAULT. The BCM UART CML
can be cleared from the culprit BCM once the internal µC is able
to communicate with it once again or can be cleared using PAGE
(00h) CLEAR_FAULTS (03h) Command.
Other Communication Faults
Not Supported: Other Memory Or Logic
Fault
7
6
5
4
3
2
1
0
b
1
1
0
0
0
0
1
0
Unsupported bits are indicated above. A one indicates a fault.
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READ_VIN Command (88h)
READ_POUT Command (96h)
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual BCM’s HI side voltage in the following format:
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual BCM’s LO side power in the following format:
VHI_ACTUAL = VHI_REPORTED • 10-1(V)
PLO_ACTUAL = PLO_REPORTED (W)
READ_IIN Command (89h)
If PAGE data byte is equal to (00h) command will return the sum of
active BCM’s LO side power.
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual BCM’s HI side current in the following format:
MFR_VIN_MIN Command (A0h),
MFR_VIN_MAX Command (A1h),
MFR_VOUT_MIN Command (A4h),
MFR_VOUT_MAX Command (A5h),
MFR_IOUT_MAX Command (A6h),
MFR_POUT_MAX Command (A7h)
IHI_ACTUAL = IHI_REPORTED • 10-2(A)
If PAGE data byte is equal (00h) command will return the sum of
active BCM’s HI side current.
READ_VOUT Command (8Bh)
These values are set by the factory and indicate the device HI side/
LO side voltage and LO side current range and LO side power
capacity.
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual BCM’s LO side voltage in the following format:
The internal µC will report rated BCM HI side voltage minimum
and maximum in Volts, LO side voltage minimum and maximum
in Volts, LO side current maximum in Amperes and LO side power
maximum in Watts.
VLO_ACTUAL = VLO_REPORTED • 10-1(V)
READ_IOUT Command (8Ch)
If PAGE data byte is equal to (00h) then:
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual BCM’s LO side current in the following format:
n MFR_VIN_MIN COMMAND (A0h) will return the highest
MFR_VIN_MIN of all active BCMs
n MFR_VIN_MAX COMMAND (A1h) will return the lowest
MFR_VIN_MAX of all active BCMs
ILO_ACTUAL = ILO_REPORTED • 10-2(A)
n MFR_VOUT_MIN COMMAND (A4h) will return the highest
If PAGE data byte is equal (00h) command will return the sum of
active BCM’s LO side current.
MFR_VOUT_MIN of all active BCMs
n MFR_VOUT_MAX COMMAND (A5h) will return the lowest
MFR_VOUT_MAX of all active BCMs
READ_TEMPERATURE_1 Command (8Dh)
n MFR_IOUT_MAX COMMAND (A6h) will return the SUM of
MFR_IOUT_MAX of all active BCMs
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual BCM’s temperature in the following format:
n MFR_POUT_MAX COMMAND (A7h) will return the SUM of
MFR_POUT_MAX of all active BCMs
TACTUAL = TREPORTED (°C)
If PAGE data byte is equal (00h) command will return the maximum
temperature of active BCM’s.
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BCM_EN_POLARITY Command (D0h)
SET_ALL_THRESHOLDS Command (D5h)
Reserved
Reserved
Reserved
SET_ALL_THRESHOLDS_BLOCK (6 Bytes)
IOUT_OC_WARN_ LIMIT
IOUT_OC_FAULT_ LIMIT
Reserved
VIN_OV_WARN_ LIMIT
Reserved
VIN_OV_FAULT_ LIMIT
OT_WARN_LIMIT
Reserved
BCM EN Pin Polarity
Reserved
OT_FAULT_LIMIT
5
4
3
2
1
0
7
6
5
4
3
2
1
0
h
64 64 64 64 64 64
b
0
0
0
0
0
0
1
0
Values of this register block is set in non volatile memory and can
only be written when the BCMs are disabled.
The value of this register is set in non volatile memory and can only
be written when the BCMs are disabled.
This command provides a convenient way to configure all the
limits, or any combination of limits described previously using one
command.
When PAGE COMMAND (00h) data byte is equal to (01h – 04h),
this command defines the polarity of the EN pin. If BCM_EN_
POLARITY is set, the BCM will startup once VHI is greater than the
under voltage threshold.
VHI Overvoltage, Overcurrent and Overtemperature values are all
set to 100% of the BCM datasheet supervisory limits by default
and can only be set to a lower percentage.
The BCM EN PIN is internally pulled-up to 3.3V. If the BCM_EN_
POLARITY is cleared, an external pull-down is then required.
Applying VHI greater than the under voltage threshold will not
suffice to start the BCM.
To leave a particular threshold unchanged, set the corresponding
threshold data byte to a value greater than (64h).
READ_K_FACTOR Command (D1h)
DISABLE_FAULT Command (D7h)
If PAGE data byte is equal to (01h - 04h) command will return a
reported individual BCMs K factor in the following format:
DISABLE_FAULT
MSB
LSB
K_FACTORACTUAL = K_FACTORREPORTED • 2-16(V/V)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
IOUT_OC_FAULT
Reserved
The K factor is defined in a BCM to represent the ratio of the
transformer winding and hence is equal to VLO / VHI.
VIN_OV_FAULT
Reserved
Reserved
Reserved
Reserved
Reserved
VIN_UV_FAULT
Reserved
READ_BCM_ROUT Command (D4h)
If PAGE data byte is equal to (01h - 04h) command will return
a reported individual BCM’s LO side resistance in the following
format:
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
b
BCM_RLO_ACTUAL = BCM_RLO_REPORTED • 10-5(Ω)
Unsupported bits are indicated above. A one indicates that the
supervisory fault associated with the asserted bit is disabled.
The value of these registers is set in non volatile memory and can
only be written when the BCMs are disabled.
This command allows the host to disable the supervisory faults
and respective statuses. It does not disable the powertrain analog
protections or warnings with respect to the set limits in the SET_
ALL_THRESHOLDS Command.
The HI side undervoltage can only be disabled to a pre set low limit
as shown in the functional reporting range in the BCM data sheet.
BCM® in a VIA Package
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3. The internal µC unsupported PMBus command code response as
described in the Fault Management and Reporting:
The internal µC Implementation vs.
PMBus™ Specification Rev 1.2
ꢀnꢀDeviations from the PMBus specification:
a. PMBus section 10.2.5.3, exceptions
The internal µC is an I2C compliant, SMBus™ compatible device
and PMBus command compliant device. This section denotes some
deviation, perceived as differences from the PMBus Part I and Part II
specification Rev 1.2.
• The busy bit of the STATUS_BYTE as implemented can
be cleared (80h). In order to maintain compatibility with
the specification (40h) can also be used.
1. The internal µC meets all Part I and II PMBus specification
requirements with the following differences to the
transport requirement.
nꢀManufacturer Implementation of the PMBus Spec
a. PMBus section 10.5, setting the response to a detected
fault condition
Unmet DC parameter Implementation vs SMBus™ spec
• All powertrain responses are pre-set and cannot be
changed. Refer to the BCM datasheet for details.
SMBus™
Rev 2.0
D44TL1A0
Symbol
Parameter
Units
Min Max Min Max
b. PMBus section 10.6, reporting faults and warnings
[a]
to the Host
VIL
Input Low Voltage
Input High Voltage
Input Leakage per Pin
-
0.99
-
-
0.8
V
V
[a]
• SMBALERT# signal and Direct PMBus Device to Host
Communication are not supported. However, the Digital
Supervisor will set the corresponding fault status bits and
will wait for the host to poll.
VIH
2.31
10
2.1 VVDD_IN
[b]
ILEAK_PIN
22
-
5
µA
[a]
V
= 3.3V
VDD_IN
[b]
c. PMBus section 10.7, clearing a shutdown due to a fault
V
= 5V
BUS
• There is no RESET pin or EN pin in the internal µC.
Cycling power to the internal µC will not clear a
BCM Shutdown. The BCM will clear itself once the fault
condition is removed. Refer to the BCM datasheet
for details.
2.The internal µC accepts 38 PMBus command codes.
Implemented commands execute functions as described in the
PMBus specification.
nꢀDeviations from the PMBus specification:
a. Section 15, fault related commands
d. PMBus Section 10.8.1, corrupted data transmission faults:
• Packet error checking is not supported.
• The limits and Warnings unit implemented is percentage
(%) a range from decimal (0-100) of the factory set limits.
Data Transmission Faults Implementation
This section describes data transmission faults as implemented in the internal µC.
Response to Host
STATUS_BYTE
STATUS_CML
Section
Description
Notes
Unsupported
NAK
FFh
CML
Other Fault
Data
10.8.1
10.8.2
10.8.3
Corrupted data
No response; PEC not supported
Sending too few bits
Reading too few bits
X
X
X
X
Host sends or reads too
few bytes
10.8.4
X
X
Host sends too many
bytes
10.8.5
10.8.6
X
X
X
X
X
Reading too many bytes
X
X
X
Device will ACK own address
BUSY bit in STATUS_BYTE even if
STATUS_WORD is set
10.8.7
Device busy
BCM® in a VIA Package
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Data Content Faults Implementation
This section describes data content fault as implemented in the internal µC.
Response
STATUS_BYTE
to Host
STATUS_CML
Section
Description
Notes
Other
Fault
Unsupported
Command
Unsupported
Data
NAK
X
CML
X
Improperly Set Read Bit In
The Address Byte
10.9.1
10.9.2
10.9.3
X
Unsupported Command
Code
X
X
X
Invalid or Unsupported
Data
X
X
X
X
10.9.4
10.9.5
Data Out of Range
Reserved Bits
No response; not a fault
BCM® in a VIA Package
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BCM in VIA Package Chassis (Lug) Mount Package Mechanical Drawing
BCM® in a VIA Package
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BCM in VIA Package PCB (Board) Mount Package Mechanical Drawing and Recommended Hole Pattern
9
8
7
6
5
1
EDITAL
CSALE8:
5
6
7
8
9
3
4
4
3
N
SDETIAL
1
3
12
31
W
OTPVIEW
1
10
TBMOEV
1
CMNDHOLPATER
01
2
1
1
2
BCM® in a VIA Package
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Revision History
Revision
1.0
Date
Description
Page Number(s)
03/3/16
05/2/16
06/17/16
08/01/16
09/26/16
Initial release
n/a
All
1.1
New Power Pin Nomenclature
Notes update
1.2
2, 3, 10
13, 14, 15
23
1.3
Charts format update
1.4
Value of R correction for READ_BCM_ROUT
BCM® in a VIA Package
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Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and ac-
cessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power
systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor makes no
representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves the right to make
changes to any products, specifications, and product descriptions at any time without notice. Information published by Vicor has been checked and
is believed to be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies. Testing and other quality controls
are used to the extent Vicor deems necessary to support Vicor’s product warranty. Except where mandated by government requirements, testing of
all parameters of each product is not necessarily performed.
Specifications are subject to change without notice.
Vicor’s Standard Terms and Conditions
All sales are subject to Vicor’s Standard Terms and Conditions of Sale, which are available on Vicor’s webpage or upon request.
Product Warranty
In Vicor’s standard terms and conditions of sale, Vicor warrants that its products are free from non-conformity to its Standard Specifications (the
“Express Limited Warranty”). This warranty is extended only to the original Buyer for the period expiring two (2) years after the date of shipment
and is not transferable.
UNLESS OTHERWISE EXPRESSLY STATED IN A WRITTEN SALES AGREEMENT SIGNED BY A DULY AUTHORIZED VICOR SIGNATORY, VICOR DIS-
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FITNESS FOR PARTICULAR PURPOSE, INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT, OR ANY OTHER
MATTER.
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for collateral or consequential damage. Vicor disclaims any and all liability arising out of the application or use of any product or circuit and assumes
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ing safeguards.
Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact
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VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS
PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used herein, life support
devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform
when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the
user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
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and components in life support applications assumes all risks of such use and indemnifies Vicor against all liability and damages.
Intellectual Property Notice
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products described in this data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is
granted by this document. Interested parties should contact Vicor’s Intellectual Property Department.
The products described on this data sheet are protected by the following U.S. Patents Pending
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25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
email
Customer Service: custserv@vicorpower.com
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