U74AC74 [UTC]
POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET; 正边沿触发的D型触发器具有清零和预设
| 型号： | U74AC74 |
| 厂家： | 
Unisonic Technologies |
| 描述： | POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET |
| 文件： | 总6页 (文件大小：170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UNISONIC TECHNOLOGIES CO., LTD
U74AC74
CMOS IC
DUAL
POSITIVE-EDGE-TRIGGERED
D-TYPE FLIP-FLOP WITH
CLEAR AND PRESET
DESCRIPTION
The U74AC74 is a dual positive-edge-triggered D-type flip-flop.
The preset (
) and clear (
) input can set or reset the
CLR
PRE
output at a low level ,regardless of the level of others inputs .when
the and are inactive(high), data at the data D input
PRE
CLR
meeting the set-up time requirements is transferred to the outputs
on the positive-going edge of the clock pulse. Following the
hold-time interval, data D can be changed without affecting the
levels at the outputs.
FEATURES
* Operating voltage rauge: VCC(OPR)=2V to 6V.
* Inputs accept voltages to 6V
* Max tpd at 10ns of 5V
ORDERING INFORMATION
Ordering Number
Lead Free
Package
SOP-14
Packing
Tape Reel
Halogen Free
U74AC74L-S14-R
U74AC74G-S14-R
www.unisonic.com.tw
Copyright © 2012 Unisonic Technologies Co., Ltd
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U74AC74
CMOS IC
PIN CONFIGURATION
FUNCTION TABLE (each gate)
INPUT
OUTPUT
Q
L
CLR
H
CLK
X
D
X
X
X
H
L
Q
H
L
PRE
L
H
L
L
X
H
L
X
H
H
H
L
H
H
H
H
↑
H
↑
L
H
H
L
X
Q0
Q0
LOGIC DIAGRAM (positive logic)
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U74AC74
CMOS IC
ABSOLUTE MAXIMUM RATING (TA=25°C, unless otherwise specified)(Note 1)
PARAMETER
SYMBOL
VCC
RATINGS
-0.5~7
UNIT
V
Supply Voltage
Input Voltage
VIN
-0.5~ VCC+0.5
-0.5~VCC+0.5
-20(MIN)
±20
V
Output Voltage(active mode)
VOUT
IIK
V
Input Clamp Current(VIN<0)
Output Clamp Current(VOUT<0)
Output Current
mA
mA
mA
mA
°C
IOK
IOUT
ICC
±50
VCC or GND Current
±200
Storage Temperature
TSTG
-65 ~ +150
Note 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Absolute maximum ratings are those values beyond which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and functional device operation is not implied.
RECOMMENDED OPERATING COMDITIONS
PARAMETER
SYMBOL
VCC
TEST CONDITIONS
MIN
2
TYP
MAX UNIT
Supply Voltage
Input Voltage
Output Voltage
6
V
V
V
VIN
0
5.5
VCC
VOUT
0
V
CC =3V
2.1
3.15
3.85
High-level input voltage
Low-level input voltage
High-level Output Current
Low-level Output Current
VIH
VIL
IOH
IOL
VCC=4.5V
VCC =5.5V
V
V
V
CC=3V
0.9
1.35
1.65
-12
-24
-24
12
VCC =4.5V
VCC=5.5V
VCC =3V
VCC=4.5V
VCC =5.5V
VCC=3V
mA
mA
VCC =4.5V
VCC=5.5V
24
24
8
ns/V
°C
Input Transition Rise or Fall Rate
Operating Temperature
Δt/Δv
TA
-40
+85
STATIC CHARACTERISTICS (TA=25°C, unless otherwise specified)
PARAMETER
SYMBOL
TEST CONDITIONS
CC=3V
MIN
2.9
TYP
MAX UNIT
V
IOH=-50uA
VCC=4.5V
VCC=5.5V
VCC=3V
4.4
5.4
High-Level Output Voltage
Low-Level Output Voltage
VOH
V
IOH=-12mA
IOH=-24mA
2.56
3.86
4.86
VCC=4.5V
VCC=5.5V
V
CC=3V
0.1
0.1
IOL=-50uA
VCC=4.5V
VCC=5.5V
VCC=3V
0.1
V
VOL
IOL=12mA
IOL=24mA
0.36
VCC=4.5V
VCC=5.5V
0.36
0.36
±0.1
Input Leakage Current
Quiescent Supply Current
Input Capacitance
II(LEAK)
ICC
VCC =0V ~ 5.5V, VIN=VCC or GND
CC = 5.5V, VIN=5.5V or GND
OUT=0
VCC =3.3V, VIN=VCC or GND
μA
V
I
2
CIN
3
pF
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U74AC74
CMOS IC
DYNAMIC CHARACTERISTICS
TA=25°C, unless otherwise specified, Input: tR, tF≤2.5ns; PRR≤1MHz
PARAMETER
Clock frequency
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
100 MHZ
FCLOCK VCC=3V±0.3V
VCC=3V±0.3V，
or
or
in Low
PRE
CLR
CLR
5.5
Pulse duration
tw
ns
ns
VCC=3V±0.3V, CLK
5.5
VCC=3V±0.3V,
inactive
PRE
0
Setup time before CLK↑
tsu
th
Data
4
Hold time ,data after CLK↑
VCC=3V±0.3V
0.5
ns
Clock frequency
FCLOCK VCC=5V±0.5V
140 MHz
VCC=5V±0.5V，
or
or
in Low
PRE
CLR
CLR
4.5
4.5
0
Pulse duration
tw
ns
VCC=3V±0.3V, CLK
CC=5V±0.5V,
V
inactive
PRE
Setup time before CLK↑
tsu
th
ns
ns
Data
3
Hold time ,data after CLK↑
VCC=5V±0.5V
0.5
DYNAMIC CHARACTERISTICS (See Fig. 1 and Fig. 2 for test circuit and waveforms.)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Maximum clock
FMAX VCC=3V±0.3V, CL=50pF, RL=500Ω
100
3.5
4
125
8
MHz
tPLH
12
12
Propagation delay from input
V
CC=3V±0.3V, CL=50pF, RL=500Ω
CC=3V±0.3V, CL=50pF, RL=500Ω
ns
(
or
) to output(Q or Q)
CLR
PRE
tPHL
tPLH
tPHL
10.5
8
4.5
3.5
140
2.5
3
13.5
14
Propagation delay from input
(CLK) to output(Q or Q)
Maximum clock
V
ns
MHz
ns
8
FMAX VCC=5V±0.5V
tPLH
160
6
Propagation delay from input
9
V
CC=5V±0.5V, CL=50pF, RL=500Ω
(
or
) to output(Q or Q)
CLR
PRE
tPHL
tPLH
tPHL
8
9.5
10
10
Propagation delay from input
(CLK) to output(Q or Q)
3.5
2.5
6
VCC=5V±0.5V, CL=50pF, RL=500Ω
ns
6
OPERATING CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN TYP MAX UNIT
Power Dissipation Capacitance
Cpd CL=50p, f=1MHz, VCC=3.3V
45
pF
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U74AC74
CMOS IC
TEST CIRCUIT AND WAVEFORMS
From Output
CL
RL
TEST CIRCUIT
Note: CL includes probe and jig capacitance.
Fig. 1 Load circuitry for switching times.
Fig. 2 Propagation delay from input to output and input voltage waveforms.
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U74AC74
CMOS IC
UTC assumes no responsibility for equipment failures that result from using products at values that
exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or
other parameters) listed in products specifications of any and all UTC products described or contained
herein. UTC products are not designed for use in life support appliances, devices or systems where
malfunction of these products can be reasonably expected to result in personal injury. Reproduction in
whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate
and reliable and may be changed without notice.
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